Universal interposer with diagonal vias for testing integrated circuit devices

Abstract

The invention relates to a universal interposer with diagonal vias for testing integrated circuit devices. High density packaging of multiple semiconductor devices results in a very large package that is highly required for reliable testing. Due to the differential coefficient of thermal expansion of the attached parts, the manufacturing process may result in defects such as deformation. The loss of flatness causes a problem to reliable connection in a test environment, resulting in frequent wear of a test socket. A new mode for reducing the connection uncertainty provides higher reliability, and the downtime of maintenance is greatly reduced.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims the benefit of and priority to U.S. Provisional Application No. 63 / 633,671, filed on April 12, 2024, entitled “VERSATILE INTERPOSER WITH DIAGONAL VIAS FOR TESTING OF INTEGRATED CIRCUIT DEVICES,” the contents of which are incorporated herein by reference in their entirety. Technical Field

[0003] The present invention relates to systems and methods for reliable or trustworthy test tools for packaged integrated circuit (IC) devices. In particular, an improved interconnect structure for IC device test tools is provided that is tolerant to mechanical irregularities in multi-chip devices. Background Art

[0004] As semiconductor components continue to be integrated on a larger scale, yield begins to suffer as individual substrate semiconductors approach sizes that encompass defects (e.g., crystal discontinuities in the material itself). Performance (especially speed) is significantly affected by the proximity of interconnected components, so alleviating the size limitations of individual components has led to multi-chip devices. This involves juxtaposing components into a single component, which increases the capabilities of the device and also allows for improvements in volumetric efficiency, where semiconductor components can be stacked vertically on top of other semiconductor components. Increasing the number of components within a device inevitably impacts the contact area or region, and can lead to mechanical failures when multiple semiconductor components are assembled side by side on a relatively large substrate.

[0005] When multiple components are attached to a substrate to create a single device, typically by welding or possibly brazing, the different rates of thermal expansion and contraction between the components and the substrate material generate significant stress as the components cool. This stress inevitably deforms the substrate, often resulting in complex warping, meaning that the bottom of the substrate is no longer flat and the external contact fields typically introduced into the bottom of the substrate now vary in height. While this variation can be managed in commercial applications of devices (which are composites of multiple individual integrated circuits, as encompassed herein) by using cantilevered contact springs, it is impractical to use such contact spring fields in a test environment. Such contact springs have a limited lifespan and wear out quickly. If the device is simply installed in a consumer application and may be changed or replaced, the risk of contact spring failure is minimal, but the repeated insertion and release of such devices in a test system results in a very low lifespan or cycle time before these contact springs fail.

[0006] In many cases, pogo pins (contact pins with variable height based on a center pin held against it by a spring) used in a "bed of nails" test fixture are employed to address vertical position uncertainty caused by poor flatness of the contact surface of the device under test, but these pogo pins are expensive, easily damaged, and can be difficult to service and repair.

[0007] Another challenge is that new developments often produce repackaged components in new form factors, and if possible, it's desirable to use existing, proven test fixtures. New versions of existing products are often reduced-size versions, and this can result in contact points on the new product being closer together than in the original version for which the test fixture was designed. In this case, it can be helpful to build adapters in addition to addressing the mechanical deficiencies caused by such packaging changes. This allows the use of existing test systems that incorporate conversion capabilities to match different connection point geometries, as well as translation capabilities.

[0008] Clearly, there is a pressing need for an improved contactor or interposer assembly that achieves superior electrical performance when connecting between large subassemblies with poor mechanical planarity and contact points on existing test fixture components. This improved interposer accommodates DUTs with poor planarity while mirroring the contact geometry between the DUT and the test fixture. The manufacturing process creates a versatile and durable interposer while reducing the impact of manufacturing process defects on test performance, resulting in more reliable and cost-effective test performance. Summary of the Invention

[0009] To achieve the foregoing and in accordance with the present invention, systems and methods are provided for reliably testing packaged high-speed integrated circuit (IC) devices.

[0010] In one embodiment, contact areas on one surface of the interposer are arranged to align with corresponding contact areas associated with the device under test. On the other surface of the interposer, second contact areas are arranged so that they correspond to contact areas provided on a test board that is connected to a set of test equipment so that power and signals can be connected to the device under test. This allows the contact geography of the device under test to be translated or converted to match the contact geography present on the test board.

[0011] In particular, the contact layout on the DUT is typically different from that on the test board. Economic advantages are gained by using adapters that fit between the DUT and the board, which is then used to connect to the test equipment used for testing. Given the cost of new wiring and the complexity involved in switching between test setups, redesigning the test board could negate the economic benefits of enhanced device packaging and improved DUT performance. Therefore, reusing a reliable and proven test fixture that includes an existing test board is recommended.

[0012] This advantage is achieved by providing connections between contact points on the device under test and contact points on the test board using connecting vias, which are routed between corresponding contact points on the adapter or interposer and drilled at an angle to the plane of the interposer substrate. This angle can be chosen to suit the required displacement and can lie in the same reference plane as the original contacts, for example, the plane established by a row of contacts.

[0013] In some embodiments, the area of ​​the contacts can be linearly shifted so that if the device under test has contacts at a given distance from a reference plane set by the position of the test board, the converted contacts can simply be moved or translated to a different position relative to that reference without changing the geometry of the contact area. In another embodiment, the contacts can be moved so that the distance between them is larger in order to fit a small contact pitch device onto a larger pitch on an existing test board. This conversion repositions and resizes the original geometry of the contacts on the device under test.

[0014] Drilling vias at an angle to the normal vertical plane of the substrate reduces complexity and minimizes the distance between contact points on the device under test, thereby improving the performance of the device testing process. Reducing series resistance and minimizing phase shift by using angled drilled and plated vias are significant advantages of the most direct connection path possible.

[0015] By using anisotropic individual conductive elastomer pillars, connections are created when the pillars are compressed by inserting the device under test into the test fixture. As opposed to using elastomeric connection strips or sheets where pressure is applied uniformly, the use of individual conductive pillars allows for targeted application of pressure. This approach facilitates testing of large devices (e.g., multi-chip modules) by overcoming the challenges posed by the inherent lack of flatness in large devices. Large modules often exhibit surface irregularities that can affect the effectiveness of single layers or single sheets, but the use of individual pillars can address these irregularities, ensuring more reliable testing.

[0016] When multi-chip devices experience forces generated by differential thermal expansion during fabrication, the introduction of complex curvatures requires care to ensure the interposer is shaped accordingly to match the deformation. Therefore, using individual deformable conductive elements, rather than a group of elements in a single sheet, provides predictability, reliability, and durability. The interconnecting elastomeric conductor components then require less compliance to simultaneously establish contact with the entire complex curvature.

[0017] It should be noted that the above-mentioned various features of the present invention can be practiced individually or in combination. These and other features of the present invention will be described in more detail below in the detailed description of the invention and in conjunction with the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] In order to more clearly define the present invention, some embodiments will now be described by way of example with reference to the accompanying drawings, in which:

[0019] Figure 1A shows a top view of an interposer having angled conductive vias and separate anisotropic conductive pads attached to one end of the vias, the vias having contact area spacing suitable for a device under test, according to one or more aspects of various embodiments;

[0020] Figure 1B According to one or more aspects of various embodiments Figure 1A a bottom view of the interposer showing the contact areas laterally shifted to correspond to the contact pitch on the test fixture;

[0021] Figure 1C FIG. 1 is a diagram illustrating a circuit having angled vias to provide lateral displacement according to one or more aspects of various embodiments. Figure 1A A cross-sectional view showing an outline of a typical internal structure of an interposer;

[0022] Figure 2 shows a close-up profile view of an angled via structure with a displaced contact area having a deformable anisotropic connection button or post according to one or more aspects of various embodiments;

[0023] Figure 3 A transition structure is shown in accordance with one or more aspects of various embodiments, wherein vias having different angles are used to transition a connection from one pitch at an upper connection point to a different pitch at a lower connection point;

[0024] Figure 4 is an outline diagram of a device under test connected to a test board through upper and lower elastomeric strips and an interposer having angled conductive vias according to one or more aspects of various embodiments;

[0025] Figure 5An interposer structure for a twisted or deformed device under test using anisotropic conductive buttons or pillars to create contact points between the device and a test fixture board is shown according to one or more aspects of various embodiments; and

[0026] Figure 6 One or more aspects of various embodiments are shown. Figure 5 A version of a typical elastomeric conductive interconnect is used in both the upper and lower connection regions. DETAILED DESCRIPTION

[0027] The present invention will now be described in detail with reference to several embodiments of the invention as illustrated in the accompanying drawings. In the following description, numerous specific details are set forth to provide a thorough understanding of the embodiments of the present invention. However, it will be apparent to those skilled in the art that the embodiments may be practiced without some or all of these specific details. In other instances, well-known process steps and / or structures are not described in particular detail to avoid unnecessarily obscuring the present invention. The features and advantages of the embodiments may be better understood with reference to the following drawings and discussion.

[0028] With reference to the following description in conjunction with (one or more) accompanying drawings, each aspect, feature and advantage of the exemplary embodiments of the present invention will be better understood. It should be clear to those skilled in the art that the described embodiments of the present invention provided herein are merely illustrative, not restrictive, and are provided by way of example only. All features disclosed in this specification may be replaced by alternative features for the same or similar purposes, unless otherwise expressly stated. Therefore, many other modified embodiments thereof are considered to fall within the scope of the present invention defined herein and its equivalents. Therefore, the use of absolute and / or sequential terms (such as "will", "will not", "should", "should not", "must", "must not", "first", "initially", "next", "subsequently", "before", "after", "last" and "ultimate") is not meant to limit the scope of the present invention, as the embodiments disclosed herein are merely exemplary.

[0029] With reference to the accompanying drawings, Figure 1A and Figure 1BThe top and bottom views of an example interposer 100 are shown, respectively. This converts a specific device contact geometry on the top side (as shown in 1A) to a different geometry on the bottom side (as shown in 1B). The bottom side corresponds to the contact spacing on a test board. The test board connects the test signals transmitted using cables from the measurement equipment to the device being tested via the interposer. Such interposers are useful because they allow connections to be made to packaged semiconductor devices of various sizes of the same functional family. Therefore, the wear caused by repeated insertion and removal of the test device is mainly limited to the interposer, which can be changed economically and efficiently when wear is observed. The contact points on the interposer are individual contact buttons or posts made of an anisotropic elastomeric material with well-controlled properties, chief among these properties being the operating compliance range of these buttons. Such conductive elastomeric buttons can be used as The product is commercially available from R&D Interconnect Solutions, Inc. located in Allentown, Pennsylvania.

[0030] The interposer substrate material can be any suitable material with good electrical insulation properties and suitable mechanical properties, for example, glass-reinforced polyester, such as FR4. Printed circuit boards, such as test boards that interface between test equipment kits and test systems designed to accept components for testing, can be easily manufactured using this material, and it can be arranged to include multiple layers of conductors to achieve extremely wide distribution of signals and power to connection points around the board.

[0031] Now go to Figure 1C , the exemplary interposer 100 is formed along Figure 1A The outline as seen from the section line AA1-AA2 is shown. Figure 1C In FIG, the upper portion of the interposer houses the device under test (DUT) (not shown), while the lower portion is mounted on a test board (not shown) that interfaces with test equipment. The figure shows a substrate 120 with diagonal vias 121a...121m and 122a...122m drilled into the substrate 120 at an angle to the substrate plane. For illustrative purposes, four angled vias are shown on either side of the center portion of the illustrated assembly. As can be seen, the angled vias result in a linear shift in contact area relative to the contact area on the opposite side of the interposer. Vias 121a...121m and 122a...122m are first drilled and then plated through with a conductive material, either by electroplating or using an electroless plating solution, such that electrical continuity exists between the upper and lower ends of each via. The increase in conductor volume in the vias is achieved through "plating-up," or "filling the vias with a conductive filler," where plating-up involves thickening the initial coating using an electroplating process.

[0032] Vias 121a...121m and 122a...122m are drilled at an angle consistent with the material used for the substrate. Precision, multi-axis, CNC drilling equipment allows this operation to be performed in a very precise and repeatable manner, and drilling fixtures are generally not required. If the substrate is delaminated, it is important to limit the angle to a value that will not cause delamination. Delamination is the separation of the layers of the substrate and is often the cause of substrate failure, indicated by unreliable or intermittent operation. Failure typically occurs due to intermittent operation caused by a via cracking somewhere along its length. If this critical angle is required to be greater than the angle the substrate can withstand, a different substrate material can be selected. In some cases, a number of different engineering plastic materials may be more suitable, but economic factors are generally considered when selecting such a material. The vias can be left plated or can be filled with a suitable filler material. In one embodiment, a conductive epoxy is used to fill the vias to reduce resistance and provide further mechanical toughness that can mitigate any delamination tendencies in some materials. In some embodiments, epoxy filling of these vias is performed solely to improve mechanical toughness.

[0033] The substrate material is further plated on the upper and lower surfaces to provide contact pads at the upper and lower ends of each via; Figure 1C In FIG, the contact pad is shown as 125m on the upper surface and as 126m on the lower surface. For clarity, two contact pads 125m and 126m are identified in the figure, but these pads are provided at any point where the vias terminate and a conductive support is to be provided.

[0034] The anisotropic conductive pillars (131a...131m and 132a...132m on the upper surface, and conductive pillars 111a...111m and 112a...112m on the lower surface) are soldered to their respective contact pads, for example, pads 125a...125m and 126a...126m and other terminal points of the vias, which attachment provides a secure mounting at one end of each pillar.

[0035] In some embodiments, insulating films 110 and 130 are provided to act as hard stops to limit compression of the pillars once they are assembled in place. It is a suitable membrane material that is freely available in a certain range of thicknesses, so that the geometry of the pillars can be controlled very accurately. The membrane can be provided with an adhesive layer for easy application and fixing. The membranes 110 and 130 are separated from the pillars by small air gaps (e.g., gaps 133a...133m), so that the compression of the pillars is achieved without excessive strain. When these anisotropic conductive pillars are squeezed vertically by pushing the device under test down on the top of the anisotropic conductive pillars or applying corresponding pressure when the interposer is pressed on the test board on which it rests, they may tend to expand radially and should accommodate this change in radial size; the tight fit of the membrane will constrain the pillars and force the material of the pillars to move upward so that it can overflow above the membrane. This movement is undesirable, destructive, and tears the elastomeric material, making the quality of the contact unrepeatable.

[0036] In some embodiments, solder mask is used instead of Kapton film. Although slightly less durable than Kapton, this provides a relatively simple short-term solution for short-term production test runs. Abrasive wear on the solder mask is mitigated by more frequent replacement of worn components before damage occurs during testing. Because solder mask application is a standard process in production, including it reduces the complexity of interposer manufacturing at the expense of durability.

[0037] Figure 2 A close-up of another embodiment of an interposer 200 is shown without a hard stop film. Each elastomeric pillar 231a...231n and 211a...211n has a corresponding flange 233a...233n and 214a...214n that are soldered to contact pads 222a...222n and 223a...223n. It should be noted that pairs of contact pads 222a and 223a...222n and 223n terminate with vias 221a...221n located on the top and bottom surfaces, respectively, of the interposer substrate 220. In some embodiments, the anisotropic pillars are slightly conical so that the resulting draft angle allows for easy release from their manufacturing molds.

[0038] Each pillar 231a...231n and 211a...211n is bonded at its respective base to a metal flange having a diameter slightly larger than the base of the pillar. These flanges (e.g., flange 233a) can be 50-60 μm larger than the pillar, and in some embodiments, for a pillar diameter of 500 μm, the flange diameter can be approximately 560 μm. These flanges are made of a weldable material to allow for secure mounting and attachment to their respective contact pads on the substrate 220. An elastomeric pillar suitable for an 800 μm contact pad spacing can have a vertical height of 500 μm set on a flange height of 38 μm and can have a working compression range of 200 μm. In the example above, The membrane can be approximately 330-340 μm thick so that further compression of the elastomeric pillars by devices pressing down on top of the interposer will be prevented. For tighter spacing between these conductive elastomeric pillars, spacing as low as 400 μm is possible, but the vertical compliance of these parts can be limited to about 90 μm.

[0039] Figure 3 Another embodiment of an interposer structure 300 is shown, wherein upper contact pads 322a ... 322n terminate with vias 321a ... 321n and lower contact pads 323a ... 323n terminate with vias 321a ... 321n. Each elastomeric pillar 331a ... 331n and 311a ... 311n has a corresponding flange 333a ... 333n and 314a ... 314n, which are welded to the contact pads 322a ... 322n and 323a ... 323n.

[0040] The vias 321a...321n are drilled at increasingly steeper angles relative to the plane of the substrate, causing the contact pitch (the distance between contact pads) to not only be translated, but also to be increased. Simply changing the interposer structure allows the very small pitch on the device under test to be mapped to a much larger pitch on the test board that is terminated to the test equipment. In the extreme case, the elastomeric posts 331a...331n on the top surface of the substrate 320 can be set to a pitch of 400μm and a usable compression range of approximately 90μm, while the elastomeric posts 311a...311n on the bottom layer can still have a compression range of 200μm. Although the extreme compression for the hard stop posts is not shown in this figure, film, but the thickness of the film should be different on the two surfaces.

[0041] In such Figure 4In another embodiment shown in a cross-sectional view of FIG, a packaged device under test 450 is connected to a test board 470 via an interposer 420 through elastomeric sheets 440 and 460, which interfaces with test equipment using a cable connection. The packaged device under test (DUT) 450 is connected to contact pads 451a...451r on the connection surface of the package containing the device. The elastomeric sheet 440 has alternating conductive and non-conductive elastomeric elements arranged in a vertical direction so that the connection is from top to bottom and there are no conductive channels extending from side to side. It should be clear that the spacing of the elastomeric sheets should be such that at least one conductive element should be available for each intended contact pad.

[0042] exist Figure 4 In the diagram, a close inspection reveals that each contact pad has two or three available conductive paths, even though the lateral positioning of the device under test may vary slightly. The width of the conductive strip is such that it is generally smaller than the inter-pad spacing between the contact pads, preventing any conductive paths between nominally coplanar and adjacent contact pads, such as 431a...431r or 451a...451r. Signals and power flow to and from contact pads 451a...451r on the device under test through conductive channels in elastomeric strip 440 to corresponding contact pads 431a...431r on the top surface of interposer 420. From there, the signals and power flow through angled vias 421a...421r to contact pads 411a...411r ​​on the bottom surface of the interposer, shifting these contact pads in pitch so that they are then positioned relative to matching contact pads on test board 470. Elastomeric strips 460 then connect the contact pads 411a...411r ​​to their corresponding contact pads 471a...471r on the test board.

[0043] When the device under test is a large package (for example, a multi-chip device), Figure 4 The elastomeric connectors shown, arranged as sheets, have a considerable surface area and relatively high forces may be required to achieve the required connection quality. This can be disadvantageous. Similarly, while deformed device packages (which warp during the manufacturing process through the effects of differential expansion and contraction) can be successfully handled using elastomeric sheets, this becomes problematic when deformations exhibiting compound curvature are encountered. Elastomeric strips can undergo creep and deformation under repeated application of considerable forces, particularly when used as a sheet or layer over wide areas of contact points or pads. The inherent design of the strip allows the width of the conductive element to expand and contract and facilitates this creep and introduces strain differences in the event of asymmetric loading. This problem is often observed in packages that are bent or deformed, highlighting the vulnerability of using elastomeric strips in such applications.

[0044] Figure 5 The curved deformation of a device under test 550 is shown. Anisotropic elastomeric contact pillars 531a…531u are attached by soldering their flanges 535a…535u to contact pads 522a…522u on the top surface of the interposer 520, whose curvature matches the curvature of the device under test. Fortunately, during a stable manufacturing process, the package deformation of the device under test is quite consistent from project to project, so surface irregularities can be accurately mapped and used to create a very closely matching curvature for the top surface of the interposer. This can be extended to complex bending deformations in the package, and once the interposer is formed to a matching shape, connection details can be generated. These contact pads 522a…522u terminate with vias 521a…521u cut at an angle and terminated by contact pads 523a…523u on the bottom surface of the interposer 520. The bottom surface of the interposer is nominally flat to match the flatness of a test board 570 that is attached to the test equipment using cables. The contact pads 523a...523u on the lower surface of the interposer 520 are positioned to mate with the contact pads 571a...571u on the test board 570. The anisotropic elastomeric pillars 511a...511u are attached by soldering their flanges 513a...513u to the pads 523a...523u and, when the interposer is properly positioned, contact the matching contact pads on the test board 570. It should be noted that, for clarity, the hard stop film used to limit the compressive displacement of the pillars is not shown in this figure.

[0045] By combining this structure of individual struts, forces are applied to the struts, and no excess residual force is applied to any elastomeric parts not involved in signal or power transmission. This minimizes the stress applied to the interposer 520, which helps reduce wear and improve repeatability and reliability. It also almost completely eliminates any detrimental effects associated with single elastomeric strip contacts (e.g., creep or aggregation), especially when the curvature is complex.

[0046] refer to Figure 6 , with Figure 5The curved interposer is shown in the same manner as in Figure 1. The device under test 650 is connected to the test board 670 via the interposer 620 through the elastomeric sheets 640 and 660. Instead of individual posts for contact, the conductive strip array is typically used as a single sheet or layer to minimize issues when assembling the test device. All contact pads (e.g., pad 625a) protrude slightly from the surface. This is also true for the contact pads on the packaged device under test 650 and the test board 670. Upon contact with the elastomeric strip, sheet, or layer, the contact pads on both the device under test 650 and the test board 670 compress the elastomeric strip directly adjacent to it. This causes the strip to expand as the material is compressed over each pad, leading to localized buckling in the strip. Any unevenness in the applied force can cause the strip to creep and increase wear, resulting in hot spots (areas of sustained, repetitive movement) that wear away the strip and, to some extent, the contact pads themselves. When all the strips are compressed in their vertical plane and force is applied to the entire surface area of ​​the strips, ultimate compression is reached. Furthermore, the angled vias 621 a ... 621 w convert the pitch of the contact pads 625 a ... 625 w on the top surface of the interposer corresponding to the contact pitch spacing on the device under test 650 to the pitch of the contact pads 626 a ... 626 w on the bottom of the interposer to align with the corresponding contact pads 671 a ... 671 w on the test board 670.

[0047] In summary, the disclosed technology overcomes the limitations of conventional approaches by providing diagonal vias to enable conversion and translation between different geometries of device contact arrangements and contact points on a test board setup. This is achieved by using an offset interposer having upper compressible conductive pillars, lower compressible conductive pillars, and a substrate having diagonal vias oriented at an angle toward the plane of the substrate. The upper pillars are electrically coupled to contact pads of a device under test (DUT). The lower pillars are electrically coupled to corresponding contact pads on a test circuit board. A subset of the upper pillars are offset relative to a corresponding subset of the lower pillars. The substrate is located between the upper pillars and the lower pillars. Each of the diagonal vias electrically couples a subset of the subset of the upper pillars to a subset of the subset of the lower pillars. Technical advantages of the disclosed technology include fewer manufacturing steps in forming the interposer and the ability to accommodate a range of devices with different contact pad geometries while maintaining an existing test board setup by simply replacing the interposer.

[0048] 1. In some embodiments, an offset interposer for electrically coupling a device under test (DUT) to a test circuit board, the interposer comprising: a plurality of upper compressible conductive pillars configured to be electrically coupled to a corresponding plurality of contact pads of the DUT; a plurality of lower compressible conductive pillars configured to be electrically coupled to a corresponding plurality of contact pads of the test circuit board, and wherein a subset of the plurality of upper pillars is offset relative to a corresponding subset of the plurality of lower pillars; and a substrate having a plurality of diagonal vias oriented at an angle toward a plane of the substrate, wherein the substrate is located between the plurality of upper pillars and the plurality of lower pillars, and wherein each of the plurality of diagonal vias is configured to electrically couple a corresponding one of the subset of the plurality of upper pillars with a corresponding one of the subset of the plurality of lower pillars.

[0049] 2. The interposer of clause 1, wherein each diagonal via of the plurality of diagonal vias is constructed by forming a diagonal through-hole and plating the through-hole with a conductive material.

[0050] 3. The interposer according to clause 1 or 2, wherein the diagonal vias are constructed by diagonal drilling or machining.

[0051] 4. The interposer of clauses 1 to 3, wherein the plated diagonal vias are reinforced with epoxy.

[0052] 5. The interposer of clauses 1 to 4, wherein each upper leg of the plurality of upper legs and each lower leg of the plurality of lower legs is cylindrical.

[0053] 6. The interposer of clauses 1 to 5, wherein each upper leg of the plurality of upper legs and each lower leg of the plurality of lower legs is tapered.

[0054] 7. The interposer of clauses 1 to 6, wherein at least one of the upper and lower surfaces of the substrate is flat.

[0055] 8. The interposer of clauses 1 to 7, wherein at least one of the upper and lower surfaces of the substrate is curved to accommodate a correspondingly curved surface of the DUT.

[0056] 9. The interposer of clauses 1 to 8, wherein each diagonal via of the plurality of diagonal vias is angled between 15 degrees and 60 degrees relative to a normal to the substrate.

[0057] 10. The interposer of clauses 1 to 9, wherein a first diagonal via of the plurality of diagonal vias is angled relative to a second diagonal via of the plurality of diagonal vias.

[0058] 11. In some embodiments, a method for manufacturing an interposer having a substrate, the substrate having a plurality of diagonal vias for electrically interconnecting a device under test (DUT) to a test circuit, the method comprising: forming a plurality of diagonal vias in the substrate of the interposer; depositing a conductive material into the plurality of diagonal vias to form a plurality of conductive diagonal vias; and electrically coupling the plurality of conductive diagonal vias to a corresponding plurality of upper elastomeric pillars and a corresponding plurality of lower elastomeric pillars, wherein the plurality of upper elastomeric pillars are located on an upper surface of the substrate, and wherein the plurality of lower elastomeric pillars are located on a lower surface of the substrate, and wherein the plurality of upper elastomeric pillars and the plurality of lower elastomeric pillars are configured to provide corresponding interconnections between the DUT and the test circuit, respectively.

[0059] 12. The method according to clause 11, wherein the processing comprises ultrasonic machining or laser machining.

[0060] 13. The method of clause 11 or 12, wherein the electrically conductive material is metallic.

[0061] 14. The method according to clauses 11 to 13, wherein the conductive material is embedded in an adhesive.

[0062] 15. The method according to clauses 11 to 14, wherein the adhesive is an epoxy resin material.

[0063] 16. The method of clauses 11 to 15, wherein each upper strut of the plurality of upper struts and each lower strut of the plurality of lower struts is cylindrical.

[0064] 17. The method of clauses 11 to 16, wherein each upper strut of the plurality of upper struts and each lower strut of the plurality of lower struts is tapered.

[0065] 18. The method of clauses 11 to 17, wherein at least one of the upper and lower surfaces of the substrate is curved to accommodate a correspondingly curved surface of the DUT.

[0066] 19. The method of clauses 11 to 18, wherein each diagonal via of the plurality of diagonal vias is angled between 15 degrees and 60 degrees relative to a normal to the substrate.

[0067] 20. The method of clauses 11 to 19, a first diagonal via of the plurality of diagonal vias being angled relative to a second diagonal via of the plurality of diagonal vias.

[0068] Many modifications and permutations of the above embodiments are possible and contemplated in accordance with the present invention. For example, to shift the contact pads on the bottom of the interposer, the contact pads can be asymmetrically placed at the ends of the vias so that the vias connect to one edge of the contact pads rather than the center area.

[0069] Although the present invention has been described in terms of several embodiments, there are variations, modifications, reorderings, and substitutions of equivalents that fall within the scope of the present invention. For example, many modifications are possible, and the above-described features from the various embodiments may be used individually or in combination. Although section headings are provided to aid in describing the present invention, these headings are illustrative only and are not intended to limit the scope of the present invention.

[0070] It should also be noted that there are many alternative ways of implementing the methods and apparatus of the present invention. Therefore, the appended claims should be interpreted to include all such changes, modifications, arrangements and substitute equivalents that fall within the true spirit and scope of the present invention.

Claims

1. An offset interposer for electrically coupling a device under test (DUT) to a test circuit board, the interposer comprising: a plurality of upper compressible conductive pillars configured to be electrically coupled to a corresponding plurality of contact pads of the DUT; a plurality of lower compressible conductive pillars configured to be electrically coupled to a corresponding plurality of contact pads of the test circuit board, and wherein a subset of the plurality of upper pillars are offset relative to a corresponding subset of the plurality of lower pillars; and A substrate having a plurality of diagonal vias oriented at an angle toward a plane of the substrate, wherein the substrate is located between the plurality of upper pillars and the plurality of lower pillars, and wherein each of the plurality of diagonal vias is configured to electrically couple a corresponding one of the subset of the plurality of upper pillars with a corresponding one of the subset of the plurality of lower pillars.

2. The interposer according to claim 1, wherein: Each diagonal via of the plurality of diagonal vias is constructed by forming a diagonal through-hole and plating the through-hole with a conductive material.

3. The interposer according to claim 2, wherein: The diagonal through holes are formed by diagonal drilling or machining.

4. The interposer according to claim 2, wherein: The plated diagonal through holes are reinforced with epoxy.

5. The interposer according to claim 1, wherein: Each of the plurality of upper struts and each of the plurality of lower struts is cylindrical.

6. The interposer according to claim 1, wherein: Each upper strut of the plurality of upper struts and each lower strut of the plurality of lower struts is tapered.

7. The interposer according to claim 1, wherein: At least one of the upper surface and the lower surface of the substrate is flat.

8. The interposer according to claim 1, wherein: At least one of the upper and lower surfaces of the substrate is curved to accommodate a corresponding curved surface of the DUT.

9. The interposer according to claim 1, wherein: Each diagonal via of the plurality of diagonal vias is angled between 15 degrees and 60 degrees relative to a normal to the substrate.

10. The interposer according to claim 1, wherein: A first diagonal via of the plurality of diagonal vias is angled relative to a second diagonal via of the plurality of diagonal vias.

11. A method for fabricating an interposer having a substrate with a plurality of diagonal vias for electrically interconnecting a device under test (DUT) to a test circuit, the method comprising: forming a plurality of diagonal vias in the substrate of the interposer; depositing a conductive material into the plurality of diagonal through holes to form a plurality of conductive diagonal vias; as well as The plurality of conductive diagonal vias are electrically coupled to a corresponding plurality of upper elastomeric pillars and a corresponding plurality of lower elastomeric pillars, wherein the plurality of upper elastomeric pillars are located on an upper surface of the substrate, and wherein the plurality of lower elastomeric pillars are located on a lower surface of the substrate, and wherein the plurality of upper elastomeric pillars and the plurality of lower elastomeric pillars are configured to provide corresponding interconnections between the DUT and the test circuit, respectively.

12. The method according to claim 11, wherein The diagonal through holes are formed by one or more of drilling, ultrasonic machining, or laser machining.

13. The method according to claim 11, wherein The conductive material is metallic.

14. The method according to claim 11, wherein The conductive material is embedded in an adhesive. The method according to claim 14 , wherein the adhesive is an epoxy resin material.

16. The method according to claim 11, wherein Each of the plurality of upper struts and each of the plurality of lower struts is cylindrical.

17. The method according to claim 11, wherein Each upper strut of the plurality of upper struts and each lower strut of the plurality of lower struts is tapered.

18. The method according to claim 11, wherein At least one of the upper and lower surfaces of the substrate is curved to accommodate a corresponding curved surface of the DUT.

19. The method according to claim 11, wherein Each diagonal via of the plurality of diagonal vias is angled between 15 degrees and 60 degrees relative to a normal to the substrate.

20. The method according to claim 11, wherein A first diagonal via of the plurality of diagonal vias is angled relative to a second diagonal via of the plurality of diagonal vias.

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