Differential signal generator and calibration method thereof

Abstract

The invention provides a differential signal generator and a calibration method thereof, and the differential signal generator comprises a control processing unit which is used for obtaining a common-mode bias voltage set value and a differential-mode bias voltage set value, determining a common-mode bias voltage code word according to a first mapping relation, determining a differential-mode bias voltage code word according to a second mapping relation, and setting the common-mode bias voltage set value and the differential-mode bias voltage set value; the common-mode bias voltage code word and the differential-mode bias voltage code word are output to the output amplification unit; the waveform generation unit is connected with the output amplification unit and is used for providing a positive-end alternating-current signal and a negative-end alternating-current signal for the output amplification unit under the control of the control processing unit; the output amplification unit is used for obtaining a positive-end bias intermediate voltage and a negative-end bias intermediate voltage according to the common-mode bias voltage code word and the differential-mode bias voltage code word so as to output a positive-end output signal and a negative-end output signal; the differential signal generator solves the problem that an existing differential signal generator cannot adjust common-mode bias output voltage and differential-mode bias output voltage.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of instruments, in particular to a differential signal generator and a calibration method thereof. BACKGROUND

[0002] A signal generator is an electronic measuring instrument capable of generating various different frequencies, amplitudes and waveforms according to user requirements, for example, it can be used to generate clock signals, modulation signals, or simulate various test signals, etc., and is commonly used to evaluate whether electronic circuits and devices are running normally or to optimize performance, wherein the differential signal is an important signal output form of the signal generator; the differential signal has the advantages of strong anti-interference ability, effective suppression of electromagnetic interference, improved signal-to-noise ratio, suppression of even harmonics, etc., and has a wide range of applications in the electronic field, for example, common LVDS, LVPECL, USB3.0, etc. are in the form of differential signals, and the input and output ends of high-speed ADCs (analog-to-digital converters), DACs (digital-to-analog converters) and VGAs basically adopt differential ports.

[0003] When the signal generator outputs a differential signal and is directly coupled with the device under test, the signal generator usually needs to provide an output bias voltage signal to meet the requirements of the device under test; for example, high-performance ADCs usually require the input common-mode voltage to be within a certain range, otherwise the ADC will have a reduced input signal dynamic range and a serious distortion problem; full-differential operation may deteriorate the harmonic and bandwidth performance when the input and output bias voltages deviate from the center of the power supply rail; for the output port of the differential signal generator, the bias voltage includes both the output common-mode bias and the output differential-mode bias, and different devices under test have different requirements for the bias voltage. Therefore, the common-mode bias output voltage and the differential-mode bias output voltage of the differential signal generator need to have the ability to be adjusted within a certain range and meet certain accuracy requirements, which is a deficiency of the current differential signal generator. SUMMARY

[0004] In view of the above problems, the present application provides a differential signal generator and a calibration method thereof, which have the function of adjustable common-mode bias output voltage and differential-mode bias output voltage.

[0005] In a first aspect, an embodiment provides the following technical solutions: The differential signal generator comprises a control processing unit, a waveform generating unit and an output amplifying unit connected to the control processing unit; the control processing unit is used to acquire a common-mode bias voltage setting value and a differential-mode bias voltage setting value, determine a common-mode bias voltage code word according to a first mapping relationship and determine a differential-mode bias voltage code word according to a second mapping relationship, and output the common-mode bias voltage code word and the differential-mode bias voltage code word to the output amplifying unit; the first mapping relationship is a mapping relationship between the common-mode bias voltage code word and the common-mode bias voltage setting value and the differential-mode bias voltage setting value, and the second mapping relationship is a mapping relationship between the differential-mode bias voltage code word and the common-mode bias voltage setting value and the differential-mode bias voltage setting value; the waveform generating unit is connected to the output amplifying unit and used to provide a positive end alternating current signal and a negative end alternating current signal for the output amplifying unit under the control of the control processing unit; and the output amplifying unit is used to obtain a positive end bias intermediate voltage and a negative end bias intermediate voltage according to the common-mode bias voltage code word and the differential-mode bias voltage code word, output a positive end output signal according to the positive end alternating current signal and the positive end bias intermediate voltage, and output a negative end output signal according to the negative end alternating current signal and the negative end bias intermediate voltage.

[0006] In some embodiments, the first mapping relationship is: DAC _code_cm = a 1 ×V cm_set + a 2 ×V diff_set + a 3 ; the second mapping relationship is: DAC _code_diff = b 1 ×V cm_set + b 2 ×V diff_set + b 3 ; wherein, DAC _code_cm is the common-mode bias voltage code word, DAC _code_diff is the differential-mode bias voltage code word, V cm_set is the common-mode bias voltage setting value, V diff_set is the differential-mode bias voltage setting value, a 1 , a2 and a 3 is a coefficient term, b 1 , b 2 and b 3 is a coefficient term.

[0007] In some embodiments, the output amplification unit comprises a first radio frequency amplifier, a second radio frequency amplifier and a bias voltage circuit, an input end of the first radio frequency amplifier is connected to an output end of the waveform generation unit, for amplifying and outputting the positive end alternating current signal, an input end of the second radio frequency amplifier is connected to an output end of the waveform generation unit, for amplifying and outputting the negative end alternating current signal; an input end of the bias voltage circuit is connected to the control processing unit to obtain the common mode bias voltage code word and the differential mode bias voltage code word, the bias voltage circuit comprises a first bias output end and a second bias output end, the first bias output end is connected to an output end of the first radio frequency amplifier, the second bias output end is connected to an output end of the second radio frequency amplifier; the bias voltage circuit is used for determining the positive end bias intermediate voltage and the negative end bias intermediate voltage according to the common mode bias voltage code word and the differential mode bias voltage code word, superimposing the positive end bias intermediate voltage to the output end of the first radio frequency amplifier through the first bias output end to obtain the positive end output signal, and superimposing the negative end bias intermediate voltage to the output end of the second radio frequency amplifier through the second bias output end to obtain the negative end output signal.

[0008] In some embodiments, the bias voltage circuit comprises a bias digital-to-analog converter, a first operational amplifier sub-circuit and a second operational amplifier sub-circuit; an input terminal of the bias digital-to-analog converter is connected to an output terminal of the control processing unit, and output terminals of the bias digital-to-analog converter are respectively connected to input terminals of the first operational amplifier sub-circuit and the second operational amplifier sub-circuit; the bias digital-to-analog converter is configured to convert the common-mode bias voltage code word into a common-mode bias analog voltage and output the common-mode bias analog voltage to the first operational amplifier sub-circuit and the second operational amplifier sub-circuit, and convert the differential-mode bias voltage code word into a differential-mode bias analog voltage and output the differential-mode bias analog voltage to the first operational amplifier sub-circuit; an output terminal of the first operational amplifier sub-circuit is connected to an input terminal of the second operational amplifier sub-circuit and the first bias output terminal, and the first operational amplifier sub-circuit is configured to obtain the positive terminal bias intermediate voltage according to the common-mode bias analog voltage and the differential-mode bias analog voltage, and output the positive terminal bias intermediate voltage to the first bias output terminal and the second operational amplifier sub-circuit; and an output terminal of the second operational amplifier sub-circuit is connected to the second bias output terminal, and the second operational amplifier sub-circuit is configured to obtain the negative terminal bias intermediate voltage according to the positive terminal bias intermediate voltage and the common-mode bias analog voltage, and output the negative terminal bias intermediate voltage to the second bias output terminal.

[0009] In some embodiments, the first operational amplifier sub-circuit comprises a first resistor, a second resistor, a third resistor and a first operational amplifier; a non-inverting input terminal of the first operational amplifier is connected to an output terminal of the bias digital-to-analog converter through the first resistor to obtain the differential-mode bias analog voltage, an inverting input terminal of the first operational amplifier is connected to the output terminal of the bias digital-to-analog converter through the second resistor to obtain the common-mode bias analog voltage, and an output terminal of the first operational amplifier is connected to the first bias output terminal and an input terminal of the second operational amplifier sub-circuit, and the first operational amplifier is configured to obtain the positive terminal bias intermediate voltage according to the common-mode bias analog voltage and the differential-mode bias analog voltage, and output the positive terminal bias intermediate voltage to the first bias output terminal and the second operational amplifier sub-circuit; one end of the third resistor is connected to the inverting input terminal of the first operational amplifier, and the other end of the third resistor is connected to the output terminal of the first operational amplifier.

[0010] In some embodiments, the second op-amp sub-circuit comprises a fourth resistor, a fifth resistor, a sixth resistor and a second operational amplifier; the non-inverting input terminal of the second operational amplifier is grounded, the inverting input terminal of the second operational amplifier is connected to the output terminal of the biasing digital-to-analog converter through the fourth resistor and to the output terminal of the first op-amp sub-circuit through the fifth resistor to obtain a superimposed voltage of the common-mode biasing analog voltage and the positive end biasing intermediate voltage, the output terminal of the second operational amplifier is connected to the second biasing output terminal for outputting the negative end biasing intermediate voltage according to the superimposed voltage; one end of the sixth resistor is connected to the inverting input terminal of the second operational amplifier and the other end is connected to the output terminal of the second operational amplifier.

[0011] In some embodiments, the output amplifying unit further comprises a first two-way switch, a second two-way switch, a first output stage amplifier, a third two-way switch, a fourth two-way switch, a second output stage amplifier, a positive output terminal and a negative output terminal; the input terminal of the first two-way switch is connected to the output terminal of the first radio frequency amplifier, the first output terminal of the first two-way switch is connected to the input terminal of the first output stage amplifier, the output terminal of the first output stage amplifier is connected to the first input terminal of the second two-way switch, the second output terminal of the first two-way switch is connected to the second input terminal of the second two-way switch, and the output terminal of the second two-way switch is connected to the positive output terminal; the first two-way switch and the second two-way switch are configured to directly connect the output terminal of the first radio frequency amplifier and the positive output terminal, or connect the output terminal of the first radio frequency amplifier, the first output stage amplifier and the positive output terminal; the input terminal of the third two-way switch is connected to the output terminal of the second radio frequency amplifier, the first output terminal of the third two-way switch is connected to the input terminal of the second output stage amplifier, the output terminal of the second output stage amplifier is connected to the first input terminal of the fourth two-way switch, the second output terminal of the third two-way switch is connected to the second input terminal of the fourth two-way switch, and the output terminal of the fourth two-way switch is connected to the output terminal of the output amplifying unit; the third two-way switch and the fourth two-way switch are configured to directly connect the output terminal of the second radio frequency amplifier and the negative output terminal, or connect the output terminal of the second radio frequency amplifier, the second output stage amplifier and the negative output terminal.

[0012] In some embodiments, the differential signal generator further comprises an output attenuation unit, the waveform generating unit connects the output amplification unit through the output attenuation unit; the output attenuation unit is configured to filter the positive end alternating current signal and the negative end alternating current signal, attenuate the positive end alternating current signal to the input signal range of the first radio frequency amplifier, and output the positive end alternating current signal to the first radio frequency amplifier, and attenuate the negative end alternating current signal to the input signal range of the second radio frequency amplifier, and output the negative end alternating current signal to the second radio frequency amplifier.

[0013] In some embodiments, the differential signal generator further comprises an output control unit, the output control unit comprises a fifth two-way switch, a sixth two-way switch, a P differential output end and an N differential output end, and the output amplification unit comprises a positive output end and a negative output end; the P differential output end is connected to the positive output end through the fifth two-way switch, and is configured to output or prohibit output of the positive end output signal under the control of the fifth two-way switch; the N differential output end is connected to the negative output end through the sixth two-way switch, and is configured to output or prohibit output of the negative end output signal under the control of the sixth two-way switch.

[0014] In a second aspect, based on the same inventive concept, an embodiment provides the following technical solution: A calibration method applied to the differential signal generator provided in the first aspect, the calibration method comprising: obtaining at least three groups of common mode bias voltage code words and differential mode bias voltage code words; inputting each group of the common mode bias voltage code words and the differential mode bias voltage code words into the output amplification unit in sequence through the control processing unit, measuring positive end bias output voltage and negative end bias output voltage output by the output amplification unit, calculating common mode bias output voltage and differential mode bias output voltage according to the positive end bias output voltage and the negative end bias output voltage; setting the common mode bias output voltage as a common mode bias voltage set value, and setting the differential mode bias output voltage as a differential mode bias voltage set value, and calibrating the first mapping relationship and the second mapping relationship according to the at least three groups of common mode bias voltage code words, differential mode bias voltage code words, common mode bias voltage set value and differential mode bias voltage set value.

[0015] According to the technical solution in one of the above embodiments, the following beneficial effects or advantages are achieved: The application provides a differential signal generator which can receive a common-mode bias voltage setting value and a differential-mode bias voltage setting value set by a user, calculate a common-mode bias voltage code word and a differential-mode bias voltage code word through a first mapping relationship and a second mapping relationship prepared in advance, obtain a positive terminal bias intermediate voltage and a negative terminal bias intermediate voltage according to the code words, and superimpose the positive terminal bias intermediate voltage and the negative terminal bias intermediate voltage on a positive terminal alternating current signal and a negative terminal alternating current signal respectively, so as to generate a positive terminal output signal containing a common-mode bias output voltage and a negative terminal output signal containing a differential-mode bias output voltage. Therefore, the differential signal generator provided by the application can support the user to adjust the common-mode bias voltage setting value and the differential-mode bias voltage setting value, obtain the corresponding common-mode bias voltage code word and the differential-mode bias voltage code word through the first mapping relationship and the second mapping relationship prepared or calibrated in advance, so as to realize the adjustment of the positive terminal bias intermediate voltage and the negative terminal bias intermediate voltage, and further realize the function of adjusting the common-mode bias output voltage and the differential-mode bias output voltage, and meanwhile, the output precision of the bias voltage is improved.

[0016] The above description is only a summary of the technical scheme of the application, in order to enable the technical means of the application to be more clearly understood and implemented according to the content of the description, and in order to enable the above and other purposes, characteristics and advantages of the application to be more apparent and easy to understand, the following specific embodiments of the application are described. BRIEF DESCRIPTION OF DRAWINGS

[0017] Various other advantages and benefits will become apparent to those of ordinary skill in the art upon reading the following detailed description of the preferred embodiments. The accompanying drawings are included to provide a description of the preferred embodiments and are not intended to limit the scope of the application. Moreover, the same reference numerals in different drawings represent the same or similar components; in the drawings.

[0018] Figure 1 A framework diagram of the differential signal generator according to one embodiment of the application is shown.

[0019] Figure 2 A detailed framework diagram of the differential signal generator according to one embodiment of the application is shown.

[0020] Figure 3 A structure and connection relationship diagram of an output amplification unit according to one embodiment of the application is shown.

[0021] Figure 4 A framework diagram of a bias voltage circuit according to one embodiment of the application is shown.

[0022] Figure 5 A circuit structure diagram of the bias voltage circuit according to one embodiment of the application is shown.

[0023] Figure 6A flowchart showing a calibration method according to an embodiment of the present application is shown.

[0024] BRIEF DESCRIPTION OF DRAWINGS 10, control processing unit; 20, waveform generation unit; 21, waveform digital-to-analog converter; 30, output amplification unit; 31, first radio frequency amplifier; 32, second radio frequency amplifier; 33, bias voltage circuit; Op, first bias output terminal; On, second bias output terminal; Ro_P, first output resistor; Ro_N, second output resistor; 331, bias digital-to-analog converter; 332, first operational amplifier sub-circuit; 333, second operational amplifier sub-circuit; R1, first resistor; R2, second resistor; R3, third resistor; U1, first operational amplifier; R4, fourth resistor; R5, fifth resistor; R6, sixth resistor; U2, second operational amplifier; 34, first two-way switch; 35, first output stage amplifier; 36, second two-way switch; 37, third two-way switch; 38, second output stage amplifier; 39, fourth two-way switch; O1, positive output terminal; O2, negative output terminal; 40, output attenuation unit; 41, first filter; 42, second filter; 43, first attenuator; 44, second attenuator; 50, output control unit; 51, fifth two-way switch; 52, sixth two-way switch; 53, P differential output terminal; 54, N differential output terminal; 60, input unit; 70, display unit; 80, storage unit. DETAILED DESCRIPTION

[0025] Hereinafter, embodiments of the present application will be described with reference to the accompanying drawings. It should be understood, however, that the description is merely exemplary of the present application, but not intended to limit the scope of the present application. Furthermore, in the following description, description of well-known functions and constructions will be omitted so as not to obscure the concept of the present application.

[0026] In the drawings, various structural diagrams according to embodiments of the present application are shown. These diagrams are not drawn to scale, in which certain details are exaggerated for the purpose of clarity and precision, and certain details can be omitted. The shapes of various regions, layers, and their relative sizes and positional relationships shown in the drawings are merely exemplary, and in actuality can be deviated due to manufacturing tolerances or technical limitations, and regions / layers having different shapes, sizes, and relative positions can be additionally designed by those skilled in the art as needed.

[0027] Unless otherwise defined, technical terms or scientific terms used in the present application shall have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. Unless otherwise defined, the technical terms or scientific terms used in the present application shall have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terms "first", "second", and similar terms are used herein merely to distinguish one element from another, and are not intended to imply any order or importance. Similarly, the terms "one", "another", or "the" are not limited to one element, but rather are used to indicate that at least one of the elements can be present. The terms "comprises", "comprising", "includes", "including" and the like can be used herein to indicate the presence of one or more elements or the like. The term "connected" or "coupled" can be used herein to indicate either a direct connection or an indirect connection or an indirect connection through one or more intervening elements or intervening components, whether mechanical, electrical, or otherwise. The terms "upper", "lower", "left", "right", and the like are used herein only to represent relative positions, and can change accordingly when the absolute positions of the described objects change.

[0028] Part of the Chinese terms and corresponding English abbreviations involved in the embodiments of the present application are as follows.

[0029] V p_out , positive end (P end) output signal.

[0030] V n_out , negative end (N end) output signal.

[0031] V cm_out , common mode bias output voltage.

[0032] V diff_out , differential mode bias output voltage.

[0033] V cm_set , common mode bias voltage setting value.

[0034] V diff_set , differential mode bias voltage setting value.

[0035] V cm_dac , common mode bias analog voltage.

[0036] V diff_dac , differential mode bias analog voltage.

[0037] DAC _code_cm , common mode bias voltage code word.

[0038] DAC _code_diff , differential mode bias voltage code word.

[0039] V p_ac , positive end (P end) AC signal.

[0040] V n_ac , negative end (N end) AC signal.

[0041] V p_offset0 , biasing the intermediate voltage at the positive end.

[0042] V n_offset0 , biasing the intermediate voltage at the negative end.

[0043] V p_offset_out , biasing the output voltage at the positive end (P end).

[0044] V n_offset_out , biasing the output voltage at the negative end (N end).

[0045] Most of the existing signal generators are single-port output, which cannot meet the test requirements of differential signal interface. A few differential signal generators on the market have differential output ends, but the output bias voltage precision is usually about ± (2% x set value + 10mV), which cannot reach the precision level of ± (1% x set value + 2mV) of single-port signal source. In addition, the existing few differential signal generators usually only focus on the common-mode bias output voltage, and ignore the adjustment function of the differential-mode bias output voltage, or the adjustable range is relatively small, only about ± 20mV, which cannot meet the actual application requirements.

[0046] For example, one of the current solutions is to provide an implementation method of a differential signal generator, but the function of the differential signal generator is relatively simple, the bandwidth is only about 10M, and more importantly, the adjustment function of the output common-mode bias and the output differential-mode bias is not mentioned, which cannot meet the most test requirements in the field of electronic measurement.

[0047] To solve the above problems, the embodiments of the present application provide a structure or implementation method of a differential signal generator with independently adjustable output common-mode and output differential-mode bias voltages, analyze the reasons that may cause low output bias precision of the differential signal generator, and provide a corresponding calibration scheme to improve the precision of the output bias voltage without increasing the hardware cost.

[0048] In a first aspect, to solve the problem that the common-mode bias output voltage and the differential-mode bias output voltage can be adjusted within a certain range, in an optional embodiment, please refer to Figure 1 The differential signal generator provided by the present application comprises a control processing unit 10, a waveform generation unit 20 connected to the control processing unit 10, and an output amplification unit 30 connected to the control processing unit 10; the control processing unit 10 is used to obtain a common-mode bias voltage set value V cm_set and a differential-mode bias voltage set value V diff_set , determine a common-mode bias voltage code word DAC _code_cm according to a first mapping relationship, determine a differential-mode bias voltage code word DAC _code_diff according to a second mapping relationship, and output the common-mode bias voltage code word DAC and the differential-mode bias voltage code word DAC ._code_cm and differential mode bias voltage code word DAC _code_diff to the output amplification unit 30; the first mapping relationship is the mapping relationship between the common mode bias voltage code word DAC _code_cm and the common mode bias voltage setting value V cm_set , the differential mode bias voltage setting value V diff_set ; the second mapping relationship is the mapping relationship between the differential mode bias voltage code word DAC _code_diff and the common mode bias voltage setting value V cm_set , the differential mode bias voltage setting value V diff_set ; the waveform generation unit 20 is connected to the output amplification unit 30, and is configured to provide the positive end alternating current signal V p_ac and the negative end alternating current signal V n_ac to the output amplification unit 30 under the control of the control processing unit 10; the output amplification unit 30 is configured to obtain the positive end bias intermediate voltage V _code_cm and the negative end bias intermediate voltage V _code_diff according to the common mode bias voltage code word DAC p_offset0 and the differential mode bias voltage code word DAC n_offset0 , and output the positive end output signal according to the positive end alternating current signal V p_ac and the positive end bias intermediate voltage V p_offset0 , and output the negative end output signal according to the negative end alternating current signal V n_ac and the negative end bias intermediate voltage V n_offset0 .

[0049] Specifically, the output signal of the differential signal generator can be divided into two parts, one is the alternating current part provided by the waveform generation unit 20 and amplified by the output amplification unit 30, i.e. the positive end alternating current signal V p_ac and the negative end alternating current signal V n_ac , and the other is the direct current bias part provided by the output amplification unit 30, i.e. the positive end bias intermediate voltage V p_offset0 and the negative end bias intermediate voltage V n_offset0 ; the positive end output signal V p_offset0 is obtained by superimposing the positive end bias intermediate voltage V p_ac on the positive end alternating current signal V p_out , and the negative end output signal V n_offset0 is obtained by superimposing the negative end bias intermediate voltage V n_ac on the negative end alternating current signal V n_out .

[0050] In the above signal output process, the control processing unit 10 is configured to, on the one hand, realize the configuration and monitoring of other units such as the waveform generation unit 20 and the output amplification unit 30, and on the other hand, obtain the common mode bias voltage setting value V cm_set and the differential mode bias voltage setting value Vcm_diff , and the common-mode bias voltage code word DAC _code_cm and the differential-mode bias voltage code word DAC _code_diff are converted into corresponding digital quantity codes respectively through the first mapping relationship and the second mapping relationship.

[0051] The waveform generating unit 20 realizes the generation of the differential signal waveform under the monitoring of the control processing unit 10, and is mainly responsible for generating a wideband differential alternating current signal, i.e., the positive end alternating current signal V p_ac and the negative end alternating current signal V n_ac and outputting them to the output amplification unit 30. The positive end alternating current signal V p_ac and the negative end alternating current signal V n_ac are a pair of strictly related core signals that jointly construct the differential alternating current signal, and correspond to the alternating current signal peak values of the differential signal positive end (i.e., the P end) and the differential signal negative end (i.e., the N end) respectively, and have the key characteristics of “equal amplitude and opposite phase”. The V p_ac and V n_ac output by the waveform generating unit 20 only contain alternating current components under normal circumstances, and do not generate bias at the output end, or generate fixed bias in some cases, which can be eliminated through subsequent calibration steps.

[0052] The output amplification unit 30 outputs the positive end output signal V p_ac and the negative end output signal V _code_cm under the monitoring of the control processing unit 10 according to the input signals: the positive end alternating current signal V n_ac , the common-mode bias voltage code word DAC _code_diff , the negative end alternating current signal V p_out and the differential-mode bias voltage code word DAC n_out ; the direct current bias part in the positive end output signal V p_out can be recorded as the positive end bias output voltage V p_offset_out , and the direct current bias part in the negative end output signal V n_out can be recorded as the negative end bias output voltage V n_offset_out .

[0053] The output amplification unit 30 can have a signal amplification function to improve the bandwidth of the output signal. For example, the alternating current signals V p_ac and V n_ac may be further amplified, then the positive end bias intermediate voltage V p_offset0 is superimposed on the amplified positive end alternating current signal V p_ac to obtain the preliminary positive end output signal V p_out , and the negative end bias intermediate voltage V n_offset0 is superimposed on the amplified negative end alternating current signal V n_ac to obtain the preliminary negative end output signal Vn_out ; the output amplification unit 30 can directly output V p_out and V n_out , or can output them after further amplification. When the output amplification unit 30 does not consider the further gain variation and zero offset variation of the output signal, and the output end of the differential signal generator is suspended or connected to a high-impedance load, V p_offset_out and V p_offset0 are the same, V n_offset_out and V n_offset0 are the same, and if the gain variation and zero offset variation are considered, V n_offset_out and V n_offset0 are different, V n_offset_out and V n_offset0 are different.

[0054] According to the direct current bias components in the output signal: V p_offset_out and V n_offset_out , the differential signal generator can output a common-mode bias output voltage V cm_out and a differential-mode bias output voltage V diff_out . According to the definition of the differential signal, the common-mode bias output voltage V cm_out and the differential-mode bias output voltage V diff_out output by the differential signal generator should satisfy the following formula: V cm_out = (V p_offset_out + V n_offset_out ) / 2 (1) V diff_out = V p_offset_out – V n_offset_out (2).

[0055] In an ideal case or in the case of accurate calibration, the common-mode bias output voltage V cm_out output by the differential signal generator should be consistent with the common-mode bias voltage set value V cm_set set or input by the user, and the differential-mode bias output voltage V diff_out should be consistent with the differential-mode bias voltage set value V diff_set set or input by the user; therefore, the first mapping relationship, as a mathematical conversion relationship determined in advance and stored in the control processing unit 10, can be regarded as a mapping relationship between the common-mode bias voltage code word DAC _code_cm and the common-mode bias voltage set value V cm_set , the differential-mode bias voltage set value V diff_set , or as a mapping relationship between the common-mode bias voltage code word DAC _code_cm and the common-mode bias output voltage V cm_out , the differential-mode bias output voltage V diff_out ; the second mapping relationship is the same.

[0056] The first and second mapping relationships can be constructed and adjusted during the calibration phase of the differential signal generator, using the user-input common-mode bias voltage setting V as much as possible. cm_set The common-mode bias output voltage V of the differential signal generator cm_out To maintain consistency, the differential bias voltage setting value V diff_set The differential bias output voltage V of the differential signal generator diff_out To maintain consistency and minimize the error between the two; it is understandable that the mathematical expressions corresponding to the first and second mapping relationships may have different forms depending on the application environment or requirements.

[0057] As can be seen, the differential signal generator provided in this application can receive the common-mode bias voltage setting value and the differential-mode bias voltage setting value set by the user. It calculates the common-mode bias voltage codeword and the differential-mode bias voltage codeword through a pre-prepared first mapping relationship and a second mapping relationship. Then, based on the codeword, it obtains the positive terminal bias intermediate voltage and the negative terminal bias intermediate voltage, respectively, and superimposes them onto the positive terminal AC signal and the negative terminal AC signal, thus generating a positive terminal output signal containing the common-mode bias output voltage and a negative terminal output signal containing the differential-mode bias output voltage. Therefore, the differential signal generator provided in this application can support users in obtaining the corresponding common-mode bias voltage codeword (DAC) by adjusting the common-mode bias voltage setting value and the differential-mode bias voltage setting value through a pre-prepared or calibrated first mapping relationship and a second mapping relationship. _code_cm Sum and difference mode bias voltage codeword DAC _code_diff This allows for adjustment of the positive terminal bias intermediate voltage V. p_offset0 and the negative terminal bias intermediate voltage V n_offset0 This enables the adjustment of common-mode bias output voltage and differential-mode bias output voltage, while also improving the output accuracy of the bias voltage. The first and second mapping relationships are also continuously adjusted according to different application scenarios and requirements to further improve the adjustment accuracy of the bias voltage.

[0058] It should be noted that the solution in this application focuses on the regulation of DC bias voltage. Therefore, the main consideration in the solution introduction is the impact of the structure and function of each unit on the DC bias section.

[0059] In some embodiments, the first mapping relationship can be a common-mode bias voltage codeword DAC. _code_cm With common-mode bias voltage setting value V cm_set Differential bias voltage setting value V diff_set The binary polynomial relationship between them, the second mapping relationship can be the differential bias voltage codeword DAC. _code_diff With common-mode bias voltage setting value V diff_set Differential bias voltage setting value V diff_seta second mapping relationship can well output the bias output voltage matched with the bias voltage setting value input by the user according to the mathematical relationship, and can realize the independent adjustment of the common-mode bias output voltage V cm_out and the differential-mode bias voltage setting value V diff_set , without affecting each other, and eliminates the requirement for the consistency of the two-end bias circuit of the differential signal generator, further improving the adjustment accuracy.

[0060] In some embodiments, the common-mode bias voltage code word DAC _code_cm and the differential-mode bias voltage code word DAC _code_diff have a binomial polynomial relationship in the form of: DAC _code_cm = a 1 ×V cm_set + a 2 ×V diff_set + a 3 (3) DAC _code_diff = b 1 ×V cm_set + b 2 ×V diff_set + b 3 (4) wherein, a 1 , a 2 and a 3 are coefficient terms, b 1 , b 2 and b 3 are coefficient terms, which can be determined by pre-calibration.

[0061] Without the need for signal filtering and conditioning of the positive-end alternating current signal V p_ac and the negative-end alternating current signal V n_ac , in some embodiments, the output end of the waveform generation unit 20 can be directly connected to the input end of the output amplification unit 30; if there is a filtering and conditioning requirement, in some embodiments, please refer to Figure 2, the differential signal generator further comprises an output attenuation unit 40, the waveform generating unit 20 is connected to the output amplification unit 30 through the output attenuation unit 40; the output attenuation unit 40 is used for conditioning and filtering the differential alternating current signal: positive end alternating current signal V p_ac and negative end alternating current signal V n_ac , and attenuating the differential alternating current signal to the input signal range suitable for the output amplification unit 30, preventing it from entering the saturation state; in some embodiments, the output amplification unit 30 can include multi-stage amplifiers and can be switched by electronic switches, and the output attenuation unit 40 can switch different gears, cooperating with the output amplification unit 30 to realize a larger differential signal dynamic range.

[0062] In some embodiments, referring to Figure 2 , the differential signal generator further comprises an output control unit 50, the output control unit 50 is connected to the output end of the output amplification unit 30, and is used for responsible for controlling the switching of the switches on the signal link, providing protection for the signal link and the like.

[0063] In some embodiments, referring to Figure 2 , the differential signal generator further comprises an input unit 60 and a display unit 70, the input unit 60 and the display unit 70 are used for providing various input and output interaction functions for users under the monitoring of the control processing unit 10.

[0064] In some embodiments, referring to Figure 2 , the differential signal generator further comprises a storage unit 80, the storage unit 80 can be used to store various data and configuration information, and can cooperate with the control processing unit 10 to complete the configuration and monitoring of other units.

[0065] All the above units can be communicatively connected with the control processing unit 10, and realize their respective functions under the configuration and monitoring of the control processing unit 10; for the common mode bias output and the differential mode bias output of the differential signal generator, the main points mainly concentrate in two aspects, one aspect is the common mode bias voltage code word DAC _code_cm and the differential mode bias voltage code word DAC _code_diff output by the control processing unit 10, and the other aspect is the output amplification unit 30 of the output signal including the positive end bias output voltage V p_offset_out , the positive end output signal V p_out , and the negative end output signal V n_offset_out including the negative end bias output voltage V n_out .

[0066] For the output amplification unit 30, in some embodiments, the output amplification unit 30 includes a first radio frequency amplifier and a second radio frequency amplifier, the input end of the first radio frequency amplifier is connected to the output end of the waveform generating unit 20, and is used for amplifying and outputting the positive end alternating current signal Vp_ac The input of the second RF amplifier is connected to the output of the waveform generation unit 20, and is used to amplify and output the negative AC signal V. n_ac .

[0067] AC signal V at the positive terminal p_ac AC signal V at the negative terminal n_ac When conditioning and filtering are not required, the first and second RF amplifiers can be directly connected to the waveform generation unit 20, while the positive terminal AC signal V... p_ac AC signal V at the negative terminal n_ac For conditioning and filtering, please refer to [link / reference]. Figure 3 The input terminal of the first RF amplifier 31 can be connected to the output terminal of the waveform generation unit 20 through the output attenuation unit 40, and the input terminal of the second RF amplifier 32 can be connected to the output terminal of the waveform generation unit 20 through the output attenuation unit 40. The output attenuation unit 40 includes a first filter 41, a second filter 42, a first attenuator 43, and a second attenuator 44. The input terminal of the first filter 41 is connected to the waveform digital-to-analog converter 21 of the waveform generation unit 20, and its output terminal is connected to the input terminal of the first attenuator 43. The output terminal of the first attenuator 43 is connected to the input terminal of the first RF amplifier 31. The input terminal of the second filter 42 is connected to the waveform digital-to-analog converter 21, and its output terminal is connected to the input terminal of the second attenuator 44. The output terminal of the second attenuator 44 is connected to the input terminal of the second RF amplifier 32.

[0068] The waveform digital-to-analog converter 21, or waveform DAC for short, is mainly responsible for generating wideband differential AC signals: positive terminal AC signal V p_ac AC signal V at the negative terminal n_ac It has two output terminals, one of which is used to output the positive AC signal V. p_ac The positive terminal AC signal V is filtered out by the first filter 41. p_ac The image frequency and out-of-band spurious signals are then input to the first attenuator 43, and the other output is used to output the negative AC signal V. n_ac The negative terminal AC signal V is filtered out by the second filter 42. n_ac The image frequency and out-of-band spurious signals are input to the second attenuator 44. The first attenuator 43 and the second attenuator 44 are responsible for switching between different levels, that is, achieving a larger dynamic range, and attenuating the signal to a range suitable for the input signals of the first RF amplifier 31 and the second RF amplifier 32, preventing the RF amplifier from entering saturation. The first RF amplifier 31 and the second RF amplifier 32 are respectively used to amplify their respective differential AC signals and increase the signal bandwidth.

[0069] In some embodiments, please refer to Figure 3The output amplification unit 30 also includes a bias voltage circuit 33, the input of which is connected to the control processing unit 10 to obtain a common-mode bias voltage codeword DAC. _code_cm Sum and difference mode bias voltage codeword DAC _code_diff The bias voltage circuit 33 includes a first bias output terminal and a second bias output terminal. Figure 3 (Not shown) The first bias output terminal is connected to the output terminal of the first RF amplifier 31, and the second bias output terminal is connected to the output terminal of the second RF amplifier 32; the bias voltage circuit 33 is used to determine the codeword DAC based on the common-mode bias voltage. _code_cm Sum and difference mode bias voltage codeword DAC _code_diff Determine the positive terminal bias intermediate voltage V p_offset0 and the negative terminal bias intermediate voltage V n_offset0 The positive terminal is biased by the intermediate voltage V through the first bias output terminal. p_offset0 The positive output signal V is obtained by superimposing it onto the output terminal of the first RF amplifier 31. p_out The negative terminal is biased to the intermediate voltage V through the second bias output terminal. n_offset0 The negative output signal V is obtained by superimposing it onto the output of the second RF amplifier 32. n_out .

[0070] For the differential signal generator in this embodiment, the DC bias portion of its output signal (including output common mode and output differential mode) is generated by the bias voltage circuit 33. The bias voltage circuit 33 processes the received common mode bias voltage codeword and differential mode bias voltage codeword through circuit operations and outputs: positive terminal bias intermediate voltage V. p_offset0 and the negative terminal bias intermediate voltage V n_offset0 The initial positive and negative output signals can be obtained by superimposing them onto the output terminals of the first RF amplifier 31 and the second RF amplifier 32, respectively.

[0071] The output amplification unit 30 can directly output the initial positive terminal output signal and the negative terminal output voltage as the final output signal, or it can further amplify them before outputting. To achieve selective amplification of the output signal, in some embodiments, please refer to... Figure 3The output amplification unit 30 further comprises a first two-way switch 34, a second two-way switch 36, a first output stage amplifier 35, a third two-way switch 37, a fourth two-way switch 39, a second output stage amplifier 38, a positive output terminal O1 and a negative output terminal O2. The input terminal of the first two-way switch 34 is connected to the output terminal of the first radio frequency amplifier 31. The first output terminal of the first two-way switch 34 is connected to the input terminal of the first output stage amplifier 35. The output terminal of the first output stage amplifier 35 is connected to the first input terminal of the second two-way switch 36. The second output terminal of the first two-way switch 34 is connected to the second input terminal of the second two-way switch 36. The output terminal of the second two-way switch 36 is connected to the positive output terminal O1. The first two-way switch 34 and the second two-way switch 36 are configured to directly connect the output terminal of the first radio frequency amplifier 31 to the positive output terminal O1, or to connect the output terminal of the first radio frequency amplifier 31, the first output stage amplifier 35 and the positive output terminal O1. The input terminal of the third two-way switch 37 is connected to the output terminal of the second radio frequency amplifier 32. The first output terminal of the third two-way switch 37 is connected to the input terminal of the second output stage amplifier 38. The output terminal of the second output stage amplifier 38 is connected to the first input terminal of the fourth two-way switch 39. The second output terminal of the third two-way switch 37 is connected to the second input terminal of the fourth two-way switch 39. The output terminal of the fourth two-way switch 39 is connected to the output terminal of the output amplification unit 30. The third two-way switch 37 and the fourth two-way switch 39 are configured to directly connect the output terminal of the second radio frequency amplifier 32 to the negative output terminal O2, or to connect the output terminal of the second radio frequency amplifier 32, the second output stage amplifier 38 and the negative output terminal O2.

[0072] According to the above circuit design, when the user wants the output signal to have greater power and bias voltage, and can accept the bandwidth, harmonic and noise to be deteriorated, the two-way switch can be switched to the output stage amplifier, i.e. the signal paths of the first two-way switch 34, the first output stage amplifier 35 and the second two-way switch 36 are turned on to further amplify the positive terminal output signal V p_out , and the signal paths of the third two-way switch 37, the second output stage amplifier 38 and the fourth two-way switch 39 are turned on to further amplify the negative terminal output signal V n_out .

[0073] When the user wants the output signal to have better high frequency performance, including higher bandwidth, lower noise floor and better harmonic performance, the output stage amplifier can be bypassed, i.e. the first two-way switch 34 and the second two-way switch 36 are directly turned on, and the third two-way switch 37 and the fourth two-way switch 39 are directly turned on, without further amplifying the output signal through the output stage amplifier.

[0074] Therefore, the output amplification unit 30 comprises multi-stage (at least two stages) amplifiers, the first stage amplifier is a radio frequency amplifier for amplifying the alternating current signal, and the second stage amplifier is a selectively used output stage amplifier, which provides the function of further amplifying the output signal; the output stage amplifier is switched by the two-way switch, which can adapt to different requirements and realize a larger signal dynamic range.

[0075] In some embodiments, referring to Figure 3 , the output control unit 50 comprises a fifth two-way switch 51, a sixth two-way switch 52, a P differential output end 53 and an N differential output end 54, the P differential output end 53 is connected to the positive output end O1 through the fifth two-way switch 51, and is used for outputting or inhibiting the output of the positive end output signal V p_out under the control of the fifth two-way switch 51; the N differential output end 54 is connected to the negative output end O2 through the sixth two-way switch 52, and is used for outputting or inhibiting the output of the negative end output signal V n_out .

[0076] Specifically, the fifth two-way switch 51 and the sixth two-way switch 52 of the output control unit 50 are respectively responsible for realizing the closing and opening of the P differential output end 53 and the N differential output end 54, that is, the output state of the control signal; the two-way switch is selected because when the external output signal is not needed, the two-way switch is switched to the internal load of the differential signal generator to absorb power, so as to avoid external radiation; the on-off control of the fifth two-way switch 51 and the sixth two-way switch 52 can be monitored and realized by the control processing unit 10.

[0077] All the two-way switches above can use electronic switches.

[0078] In some embodiments, the structure of the bias voltage circuit 33 is as shown in Figure 4 , comprising a bias digital-to-analog converter 331, a first operational amplifier sub-circuit 332 and a second operational amplifier sub-circuit 333; the input end of the bias digital-to-analog converter 331 is connected to the output end of the control processing unit 10, and the output end of the bias digital-to-analog converter 331 is respectively connected to the input end of the first operational amplifier sub-circuit 332 and the second operational amplifier sub-circuit 333; the bias digital-to-analog converter 331 is used for converting the common-mode bias voltage code word DAC _code_cm into a common-mode bias analog voltage V cm_dac , and then outputting to the first operational amplifier sub-circuit 332 and the second operational amplifier sub-circuit 333, and converting the differential-mode bias voltage code word DAC _code_diff into a differential-mode bias analog voltage V diff_dacThe output is then sent to the first operational amplifier sub-circuit 332; the output terminal of the first operational amplifier sub-circuit 332 is connected to the input terminal of the second operational amplifier sub-circuit 333 and the first bias output terminal Op. The first operational amplifier sub-circuit 332 is used to adjust the common-mode bias analog voltage V. cm_dac Sum and difference mode bias analog voltage V diff_dac The positive terminal biased intermediate voltage V is obtained p_offset0 And bias the positive terminal with the intermediate voltage V p_offset0 The output is connected to the first bias output terminal Op and the second operational amplifier sub-circuit 333; the output terminal of the second operational amplifier sub-circuit 333 is connected to the second bias output terminal On, and is used to bias the intermediate voltage V based on the positive terminal. p_offset0 and common-mode bias analog voltage V cm_dac Obtain the negative terminal bias intermediate voltage V n_offset0 And bias the negative terminal with the intermediate voltage V n_offset0 Output to the second bias output terminal On.

[0079] Specifically, the CPU in the control processing unit 10 converts the codeword: DAC _code_cm and DAC _code_diff The output is sent to the bias voltage circuit 33, which is responsible for generating the bias intermediate voltage across the differential link: positive terminal bias intermediate voltage V. p_offset0 and the negative terminal bias intermediate voltage V n_offset0 The bias digital-to-analog converter 331, or bias DAC for short, is used to convert the input digital bias voltage codeword into a corresponding bias analog voltage and then output it to the corresponding operational amplifier sub-circuit; the common-mode bias analog voltage V cm_dac Sum and difference mode bias analog voltage V diff_dac After the first operational amplifier sub-circuit 332 and the second operational amplifier sub-circuit 333 are superimposed and driven to enhance the voltage, the positive terminal bias intermediate voltage V is obtained. p_offset0 and the negative terminal bias intermediate voltage V n_offset0 Then, the bias intermediate voltage is superimposed onto the corresponding RF amplifier through the corresponding bias output terminal to obtain the positive terminal output signal V. p_out and negative terminal output signal V n_out .

[0080] In some embodiments, please refer to Figure 3The first bias output end Op is connected to the output end of the first radio frequency amplifier 31 through the first output resistance Ro_P, and the second bias output end On is connected to the output end of the second radio frequency amplifier 32 through the second output resistance Ro_N; the first output resistance Ro_P and the second output resistance Ro_N are used to realize the single-end output impedance and the differential output impedance of the differential signal generator; the resistance values of the first output resistance Ro_P and the second output resistance Ro_N are set according to actual requirements, for example, both are 50±1 ohm, which are used to realize the single-end 50 ohm and the differential 100 ohm output impedance.

[0081] The first operational amplifier sub-circuit 332 and the second operational amplifier sub-circuit 333 are used as the circuit structure of signal superposition and driving enhancement, and can adopt an operational amplifier circuit; in some embodiments, please refer to Figure 5 The first operational amplifier sub-circuit 332 includes a first resistance R1, a second resistance R2, a third resistance R3 and a first operational amplifier U1; the non-inverting input end of the first operational amplifier U1 is connected to the output end of the bias digital-to-analog converter 331 through the first resistance R1 to obtain a differential mode bias analog voltage V diff_dac The inverting input end of the first operational amplifier U1 is connected to the output end of the bias digital-to-analog converter 331 through the second resistance R2 to obtain a common mode bias analog voltage V cm_dac The output end of the first operational amplifier U1 is connected to the first bias output end Op and the input end of the second operational amplifier sub-circuit 333, which is used to obtain a positive end bias intermediate voltage V cm_dac from the common mode bias analog voltage V diff_dac and the differential mode bias analog voltage V p_offset0 and output the positive end bias intermediate voltage V p_offset0 to the first bias output end Op and the second operational amplifier sub-circuit 333; one end of the third resistance R3 is connected to the inverting input end of the first operational amplifier U1, and the other end is connected to the output end of the first operational amplifier U1.

[0082] The first operational amplifier U1 cooperates with the first resistance R1, the second resistance R2 and the third resistance R3 to form a hybrid / modulation circuit of differential signals and common mode signals; the first operational amplifier U1 performs weighted processing on the common mode bias analog voltage V cm_dac and the differential mode bias analog voltage V diff_dac in a manner of “differential amplification + common mode superposition”, and outputs a positive end bias intermediate voltage V p_offset0 .

[0083] In some embodiments, please refer to Figure 5, the second op-amp sub-circuit 333 comprises a fourth resistor R4, a fifth resistor R5, a sixth resistor R6 and a second operational amplifier U2; the non-inverting input terminal of the second operational amplifier U2 is grounded, the inverting input terminal of the second operational amplifier U2 is connected to the output terminal of the biasing digital-to-analog converter 331 through the fourth resistor R4 and to the output terminal of the first op-amp sub-circuit 332 through the fifth resistor R5, so as to obtain a superimposed voltage of the common-mode biasing intermediate voltage V cm_dac and the positive-end biasing intermediate voltage V p_offset0 ; the output terminal of the second operational amplifier U2 is connected to the second biasing output terminal On, for outputting the negative-end biasing intermediate voltage V n_offset0 according to the superimposed voltage; one end of the sixth resistor R6 is connected to the inverting input terminal of the second operational amplifier U2, and the other end is connected to the output terminal of the second operational amplifier U2.

[0084] The second operational amplifier U2 cooperates with the fourth resistor R4, the fifth resistor R5 and the sixth resistor R6 (feedback resistor) to carry out voltage division and feedback amplification on a superimposed signal of the common-mode biasing intermediate voltage V cm_dac and the positive-end biasing intermediate voltage V p_offset0 output by the first op-amp sub-circuit 332, wherein the common-mode biasing intermediate voltage V cm_dac is input to the inverting input terminal of the second operational amplifier U2 through the fourth resistor R4, and the output signal of the first operational amplifier U1, i.e. the positive-end biasing intermediate voltage V p_offset0 is input to the inverting input terminal of the second operational amplifier U2 through the fifth resistor R5, and the two are superimposed at the inverting input terminal and jointly serve as the input signal of the second operational amplifier U2 to participate in the subsequent feedback amplification process, so as to output the negative-end biasing intermediate voltage V n_offset0 .

[0085] The above embodiment introduces the hardware composition of the differential signal generator. In the following embodiment, the complete generation process of the biasing voltage is introduced by taking the differential signal generator of V Figure 3 and V Figure 5 as an example, and the specific process is as follows.

[0086] 1) The user sets the common-mode biasing voltage setting value V cm_set and the differential-mode biasing voltage setting value V diff_set according to the expected output common-mode and output differential-mode biasing voltage through the input unit 60.

[0087] 2) The control processing unit 10 substitutes V cm_set and V diff_set into the first mapping relationship and the second mapping relationship prepared in advance or obtained after calibration through the processor CPU, so as to obtain the corresponding common-mode biasing voltage code word DAC _code_cm and the differential-mode biasing voltage code word DAC _code_diffand transmit it to the biasing digital-to-analog converter 331 (biasing DAC).

[0088] 3) The biasing digital-to-analog converter 331 converts the input code word: DAC _code_cm and DAC _code_diff into corresponding common-mode biasing analog voltage V cm_dac and differential-mode biasing analog voltage V diff_dac .

[0089] 4) After the analog voltage V cm_dac and V diff_dac are superimposed and driven by the first operational amplifier U1 and the second operational amplifier U2, the positive-end biasing intermediate voltage V p_offset0 and the negative-end biasing intermediate voltage V n_offset0 are generated, which are superimposed to the output end of the first radio frequency amplifier 31 at the P end and the second radio frequency amplifier 32 at the N end, respectively, to obtain the initial positive-end output signal V p_out and the negative-end output signal V n_out .

[0090] 5) Due to the insertion loss of the two-way switch and the gain and zero offset of the output stage amplifier, the gain and zero offset will change during the superimposition of the voltage at the output end of the radio frequency amplifier, and finally V p_offset_out represents the measured positive-end biasing output voltage V p_out at the P differential output end 53 of the differential signal generator, and V n_offset_out represents the measured negative-end biasing output voltage V n_out at the N differential output end 54.

[0091] 6) According to V p_offset_out and V n_offset_out , the common-mode biasing output voltage V cm_out and the differential-mode biasing output voltage V diff_out of the signal generator are defined, as shown in formula (1) and formula (2).

[0092] Through the above circuit design of the differential signal generator, the user can set the values of V cm_set and V diff_set to realize the adjustment and control of the common-mode biasing output voltage V cm_out and the differential-mode biasing output voltage V diff_out of the differential signal generator; in the ideal case, the actual output common-mode biasing voltage and differential-mode biasing voltage should be consistent with the user settings, or within a certain accuracy range, i.e. V cm_out = V cm_set , V diff_out = V diff_set .

[0093] To achieve this, a quantitative relationship between the common-mode bias output voltage, the differential-mode bias output voltage and the DAC code word, i.e., V cm_out and V diff_out , can be obtained through calibration, and the mapping relationship between V _code_cm and V code_diff , the first mapping relationship after V cm_out is replaced by V cm_set , and the second mapping relationship after V diff_out is replaced by V diff_set , is obtained. The calibration principle and calibration method are described in the second aspect embodiment.

[0094] The differential signal generator provided by the first aspect embodiment has the following advantages: 1) It has the function of independently adjusting the common-mode bias output voltage and the differential-mode bias output voltage, respectively, without affecting each other, and also improves the output accuracy of the bias voltage and enhances the user experience.

[0095] 2) Through the generation process of each component unit and the above bias voltage, a differential signal generator with a bandwidth of about 2.6 GHz, wide signal dynamic range, output bias voltage, and single-ended output impedance equal to 50 ohms (the resistance value of the first output resistor Ro_P and the second output resistor Ro_N) can be provided.

[0096] 3) No additional hardware design cost and complexity is added.

[0097] As described in the first aspect embodiment, the first mapping relationship and the second mapping relationship can be constructed and adjusted through calibration. At present, the calibration method for the output bias voltage is commonly used for the calibration of the bias output voltage of a single-port output signal source, which cannot be directly applied to the differential signal generator. The main reason is that the definitions of the bias output voltage are inconsistent between the two, and the output bias of the differential signal generator includes the output common mode and the output differential mode, not just the bias output voltage of a single port. Secondly, there is a difference in gain between the two ends of the differential link, which will cause the same DC voltage to generate common-mode and differential-mode components after passing through the two ends of the differential, and the algorithm needs to be modified for this problem. If this is ignored, the calibrated common-mode bias output voltage and the differential-mode bias output voltage will affect each other, reducing the calibration accuracy and user experience.

[0098] The solution to the above problem is to construct reasonable first and second mapping relationships and to provide corresponding calibration methods. Therefore, in the second aspect, based on the same inventive concept, a calibration method is provided for the differential signal generator provided in the first aspect embodiment. Please refer to Figure 6 , the calibration method includes steps S601-S603, which are as follows: S601: Obtain at least three sets of common-mode bias voltage code words and differential-mode bias voltage code words.

[0099] S602: Input each set of common-mode bias voltage code words and differential-mode bias voltage code words into the output amplification unit in sequence by controlling the processing unit, measure the positive end bias output voltage and the negative end bias output voltage output by the output amplification unit, and calculate the common-mode bias output voltage and the differential-mode bias output voltage according to the positive end bias output voltage and the negative end bias output voltage.

[0100] S603: Set the common-mode bias output voltage as the common-mode bias voltage setting value, and set the differential-mode bias output voltage as the differential-mode bias voltage setting value, and calibrate the first mapping relationship and the second mapping relationship according to the at least three sets of common-mode bias voltage code words, differential-mode bias voltage code words, common-mode bias voltage setting value and differential-mode bias voltage setting value.

[0101] In some embodiments, when calibration is performed, the waveform output unit can be controlled to make the differential alternating current signal output by the waveform output unit zero, so as to simplify the entire calibration process and facilitate the measurement of the positive end bias output voltage V p_ac and the negative end bias output voltage V n_ac . p_offset_out n_offset_out .

[0102] The calibration principle of the above scheme is as follows.

[0103] When the bias digital-to-analog converter 331 works in the linear region, the bias analog voltage and the bias voltage code word satisfy the following relationship: V cm_dac k1 x DAC _code_cm + d1 (5) V diff_dac k1 x DAC _code_diff + d1 (6) In the above formula, k1 represents the gain relationship between the input code word of the bias DAC and the output voltage, and d1 represents the zero offset of the bias DAC.

[0104] When the first operational amplifier U1 and the second operational amplifier U2 work in the linear region, the output of the bias voltage circuit 33 satisfies: V p_offset0 k5 x V cm_dac + k6 x V diff_dac (7) V ​​​​n_offset0 = k7 x V cm_dac + k8 x V diff_dac (8) wherein k5 and k6, k7 and k8, respectively, represent the coefficients of the first operational amplifier sub-circuit 332 of the positive terminal (P) and the second operational amplifier sub-circuit 333 of the negative terminal (N), and can be expressed by the following relational expression according to the resistance values of R2~R6 in Figure 5

[0105] k 5 =- R3 / R2 (9) k 6 =( R3 + R2 ) / R2 (10) k 7 =- R3 / R2× (- R6 / R5 )– R6 / R4 (11) k 8 =( R3 + R2 ) / R2 ) × (- R6 / R5 ) (12) The resistance values of R1~R6 are set according to actual requirements, and according to the definitions of the common-mode bias output voltage and the differential-mode bias output voltage, when setting the resistance values of R1~R6, it is only necessary to satisfy k5=k7, k 6= -k8.

[0106] When other elements, such as the output stage amplifier and the two-way switch, are working in the linear region, the relationship between the bias output voltage and the bias intermediate voltage satisfies: V p_offset_out = k3 x V p_offset0 + d3 (13) V n_offset_out = k4 x V n_offset0 + d4 (14) k3 and d3 represent the positive terminal bias intermediate voltage V p_offset0 ​The gain variation coefficient and zero offset variation coefficient generated in the process of reaching the P differential output end 53 (P port) of the differential signal generator; similarly, k4 and d4 represent the negative end offset middle voltage V p_offset0 The gain variation coefficient and zero offset variation coefficient generated in the process of reaching the N differential output end 54 (N port) of the differential signal generator.

[0107] In some embodiments, according to product design, the resistance values of the first to sixth resistances R1 to R6 are respectively: R1=R2=R3=R5=R6=10kΩ, R4=5kΩ, so it can be concluded that k5=k7=-1, k6=2, k8=-2, and equations (7) and (8) are: V p_offset0 = -V cm_dac +2 ×V diff_dac (15) V n_offset0 = -V cm_dac -2 ×V diff_dac (16)。

[0108] For the convenience of derivation, the following will be calculated and derived according to equations (15) and (16).

[0109] Further calculation of equations (13) and (14) has: V p_offset_out = k3 x V p_offset0 + d3 = (-k1 x k3) x DAC _code_cm +(2 x k1 x k3) x DAC _code_diff +(k3 x d1 + d3) (17) V n_offset_out = k4 x V n_offset0 + d4 = (-k1 x k4) x DAC _code_cm -(2 x k1 x k4) x DAC _code_diff +(-3 x k4 x d1 + d4) (18)。

[0110] Substituting equations (17) and (18) into equations (1) and (2), we can get: V cm_out =( V p_offset_out+ V n_offset_out ) / 2 = ((-k1) x (k3 + k4) x DAC _code_cm + 2 x k1 x (k3 - k4) x DAC _code_diff ) / 2 + (d3 + d4 + k3 x d1 - 3 x k4 x d1) / 2 = A1 x DAC _code_cm + A2 x DAC _code_diff + A3 (19) V diff_out = V p_offset_out -V n_offset_out = ((-k1) x (k3 - k4) x DAC _code_cm + 2 x k1 x (k3 + k4) x DAC _code_diff ) / 1 + (d3 - d4 + k3 x d1 + 3 x k4 x d1) / 1 = B1 x DAC _code_cm + B2 x DAC _code_diff + B3 (20) wherein: A1 = (-k1) x (k3 + k4) / 2 A2 = k1 x (k3 - k4) A3 = (d3 + d4 + k3 x d1 - 3 x k4 x d1) / 2 B1 = (-k1) x (k3 - k4) B2 = 2 x k1 x (k3 + k4) B3 = d3 - d4 + k3 x d1 + 3 x k4 x d1 .

[0111] In ideal case, the output resistors, the electronic switches, the output stage amplifiers used on both sides of the positive terminal (P) and the negative terminal (N) are all the same devices, the insertion loss of the electronic switches are all the same, the gain of the output stage amplifiers are all the same, i.e. k3=k4, substituting into the above formula, we can get: A2=B1=0, i.e. V cm_out = A1 x DAC _code_cm +A3 (21) V diff_out = B2 x DAC _code_diff +B3 (22)

[0112] That is, in an ideal case, the common-mode bias output voltage V cm_out only and the differential-mode bias voltage code word DAC _code_cm is linearly related to the differential-mode bias output voltage V diff_out only and the differential-mode bias voltage code word DAC _code_diff is linearly related to each other and independent of each other.

[0113] However, in reality, there are inevitable differences between the devices at both ends of the differential link. For example, Figure 3 The first output resistance Ro_P and the second output resistance Ro_N in the 50 ohm in the differential link are usually large in size and need to meet the requirements of high frequency performance, and the resistors that meet such requirements usually have low precision; for example, a 50 ohm RF resistor provided by a certain company on the market usually has a precision of only ±2% or even ±5%; in addition, the insertion loss of the electronic switch and the gain of the output stage amplifier also differ; therefore, k3≠k4, and thus A2≠0 and B1≠0; therefore, the following two formulas are more consistent with the actual circuit model.

[0114] V cm_out = A1 x DAC _code_cm + A2 x DAC _code_diff +A3 (23) V diff_out = B1 x DAC _code_cm + B2 x DAC _code_diff +B3 (24).

[0115] This means that when the link gains at the P end and the N end are inconsistent, the common-mode bias voltage code word DAC _code_cm will generate a part of the differential-mode voltage at the output end; the differential-mode bias voltage code word DAC _code_diff will generate a part of the common-mode voltage at the output end, and if this is ignored and calibration is performed based on formulas (21) and (22), the output common-mode bias and the output differential-mode bias will be affected by each other, for example, when V cm_set is adjusted, not only V cm_out ≈V cm_set , but also V diff_out is also changing, that is, the output common-mode and the output differential-mode cannot be independently adjusted.

[0116] Since A1, A2, A3, B1, B2, and B3 are constants, formulas (23) and (24) can be simply linearly transformed to obtain: DAC _code_cm =a 1 ×V cm_out +a 2 ×V diff_out +a 3 (25) DAC _code_diff =b 1 ×V cm_out +b 2 ×V diff_out +b 3 (26).

[0117] wherein a 1 、a 2 、a 3 、b 1 、b 2 、b 3 are unknown constants, the process of calibration is to solve these unknown constants; after calibration is completed, the user sets the common-mode bias voltage setting value V cm_set and the differential-mode bias voltage setting value V diff_set through the UI of the input unit 60, the processor CPU of the control processing unit 10 substitutes V cm_set for V cm_out of the equations (25) and (26), and substitutes V diff_set for V diff_out of the equations (25) and (26), that is, the common-mode bias voltage code word DAC _code_cm is calculated through the first mapping relationship shown in equation (3), and the differential-mode bias voltage code word DAC _code_diff is calculated through the second mapping relationship shown in equation (4), and then transmitted to the bias digital-to-analog converter 331 of the bias voltage circuit 33, and the expected common-mode bias output voltage V cm_out and the differential-mode bias output voltage V diff_out can be generated through the processing of the bias voltage circuit 33.

[0118] From the above discussion of the calibration principle, it can be known that the purpose of calibration is to obtain the mapping relationship between the DAC code word and the output common-mode and output differential-mode bias, that is, DAC _code_cm and V cm_out , Vdiff_out The polynomial relationship between them, DAC _code_diff With V cm_out V diff_out The polynomial relationship between them is obtained by solving equations (25) and (26). After solving the constant terms in equations (25) and (26), the first mapping relationship and the second mapping relationship are obtained simultaneously.

[0119] The equipment required for calibration includes a multimeter and a computer. Set the output of waveform generation unit 20 to zero, so the multimeter can be used to directly measure the bias voltage V at the differential output terminals (i.e., P and N terminals). p_offset_out and V n_offset_out The computer is used to calculate the corresponding common-mode bias output voltage V. cm_out Sum and difference mode bias output voltage V diff_out It also controls the signal source and multimeter to achieve automated calibration.

[0120] For polynomial relations of the form (25) and (26), solve for the constant term. a 1 、a 2 、a 3 、b 1 、b 2 、b 3 At least three sets of data are required, therefore the calibration steps are as follows.

[0121] 1) Set the signal source to be tested, and set the first set of bias voltage DAC codewords: DAC _code_cm1 and DAC _code_diff1 The bias output voltage V at the P differential output terminal 53 was measured using a multimeter. p_offset_out1 The bias output voltage V of the N differential output terminal 54 n_offset_out1 Based on this, the common-mode bias output voltage V is calculated. cm_out1 Sum and difference mode bias output voltage V diff_out1 The first set of test data (DAC) was obtained. _code_cm1 DAC _code_diff1 V cm_out1 , and V diff_out1 ).

[0122] 2) Set the signal source to be tested, and set the second set of bias voltage DAC codewords: DAC _code_cm2 and DAC _code_diff2 Repeat step 1) to obtain the second set of test data (DAC). _code_cm2 DAC _code_diff2 V cm_out2 , and V diff_out2).

[0123] 3) Set the signal source to be measured, set the third group of bias voltage DAC code word: DAC _code_cm3 and DAC _code_diff3 , repeat step 1), get the third group of test data (DAC _code_cm3 , DAC _code_diff3 , V cm_out3 , and V diff_out3 ).

[0124] 4) Substitute the above three groups of test data into equations (25) and (26) to solve a 1 ~a 3 ,b 1 ~b 3 , and synchronously get the first mapping relationship corresponding to equation (3) and the second mapping relationship corresponding to equation (4).

[0125] 5) Save the function relationship after calibration.

[0126] At this point, the calibration step is completed, and according to the above steps, the V cm_set ≈V cm_out , V diff_set ≈V diff_out mentioned in the foregoing can be realized, that is, the set value and the actual output value of the bias voltage are basically consistent, so the control processing unit 10 only needs to calculate the corresponding DAC cm_set and DAC diff_set according to the first mapping relationship and the second mapping relationship according to the user-set V _code_cm and V _code_diff , that is, the output differential mode bias of the expected output common mode bias can be generated.

[0127] Use the calibrated differential signal generator for testing and verification, set multiple different V cm_set and V diff_set , measure the output voltage V p_out and V n_out of the output port of the link, considering that the AC part can be set to zero when measuring, so V p_out and V n_out actually correspond to the DC bias output voltage: V p_offset_out and V n_offset_out , and the common mode bias output voltage V cm_out and the differential mode bias output voltage V diff_out are calculated according to the deviation between the set value and the actual value, and the precision of the bias output voltage is obtained.

[0128] Table 1: Test data after calibration. Test No. V cm_set / mV]]> V diff_set / mV]]> V p_out / mV]]> V n_out / mV]]> V cm_out / mV]]> V diff_out / mV]]> 1 2000 0 2000 2000 2000 0 2 1000 0 999.97 999.99 999.98 -0.02 3 100 0 100 100 100 0 4 10 0 10.01 10 10.005 0.01 5 0 0 0.00619 0.00070864 0.00344932 0.00548136 6 -10 0 -9.99 -10 -9.995 0.01 7 -100 0 -99.99 -100 -99.995 0.01 8 -1000 0 -999.96 -999.98 -999.97 0.02 9 -2000 0 -2000 -2000 -2000 0 10 0 2000 1000 -1000 0 2000 11 0 1000 500 -500 0 1000 12 0 100 50.01 -50 0.005 100.01 13 0 10 5.01 -5 0.005 10.01 15 0 -10 -4.99 5 0.005 -9.99 16 0 -100 -49.99 50 0.005 -99.99 17 0 -1000 -499.99 500 0.005 -999.99 18 0 -2000 -999.99 1000 0.005 -1999.99 According to Table 1, the differential signal generator and the calibration method provided by the application can improve the precision of the common-mode bias output voltage and the differential-mode bias output voltage to the level of ± (1% x set value + 3mV); at the same time, when the user adjusts the common-mode bias voltage set value V cm_set , the differential-mode bias output voltage V diff_out is basically unchanged; when the differential-mode bias voltage set value V diff_set is adjusted, the common-mode bias output voltage V cm_out is basically unchanged, that is, the independent adjustment of the common-mode bias output voltage V cm_out and the differential-mode bias output voltage V diff_out is realized, and they do not affect each other.

[0129] In summary, the scheme provided by one or more embodiments has the following advantages: The differential signal generator and the corresponding calibration method provided by the application fully verify that due to the link gain difference of the differential two-end link, DAC _code_cm and V cm_out , V diff_out all have a linear relationship, DAC _code_diff and V cm_out , V diff_out all have a linear relationship, and explains why the current differential signal generator has the problem of low output bias voltage precision, and the possible problem of "adjusting the common-mode voltage will cause the output differential-mode voltage to change, adjusting the differential-mode voltage will cause the output common-mode voltage to change, affecting the user experience", and proposes a differential signal generator that can solve this problem and a calibration method suitable for the output bias of the differential signal generator.

[0130] The differential signal generator and the corresponding calibration method provided by the application fully consider the difference between the two ends of the differential link, construct the polynomial relationship between the common-mode bias voltage code word obtained according to the user setting and the common-mode bias output voltage and the differential-mode bias output voltage, and the polynomial relationship between the differential-mode bias voltage code word and the common-mode bias output voltage and the differential-mode bias output voltage, realize the independent adjustment of the output common-mode voltage and the output differential-mode voltage without affecting each other, and improve the adjustment precision.

[0131] The calibration method for the differential signal generator provided by the application has the advantage of easy implementation, eliminates the requirement for high consistency of the differential two-end bias circuit, such as the electronic switch and the output stage amplifier of the P and N end links, and also reduces the requirement for the device and the difficulty of hardware design. Under the premise, the precision of the final output bias voltage can reach about ± (1% + 3mV), which is obviously better than the existing product indicators on the market: ± (2% + 10mV).

[0132] From the perspective of the user, the differential signal generator provided by the application can independently adjust the output common-mode bias and the output differential-mode bias, and the precision is improved, thereby improving the user experience.

[0133] Although the preferred embodiments of the application have been described, those skilled in the art who have the benefit of the present disclosure can make additional changes and modifications to these embodiments without departing from the spirit and scope of the application. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments and all changes and modifications falling within the scope of the application.

[0134] Obviously, those skilled in the art can make various modifications and variations to the present application without departing from the spirit and scope of the present application. Thus, if these modifications and variations of the present application fall within the scope of the claims of the present application and their equivalent technologies, the present application also intends to include these modifications and variations.

Claims

1. A differential signal generator, characterized by, The control processing unit is configured to obtain a common-mode bias voltage setting value and a differential-mode bias voltage setting value, determine a common-mode bias voltage code word according to a first mapping relationship and a differential-mode bias voltage code word according to a second mapping relationship, and output the common-mode bias voltage code word and the differential-mode bias voltage code word to the output amplification unit. The first mapping relationship is a mapping relationship between the common-mode bias voltage code word and the common-mode bias voltage setting value and the differential-mode bias voltage setting value, and the second mapping relationship is a mapping relationship between the differential-mode bias voltage code word and the common-mode bias voltage setting value and the differential-mode bias voltage setting value. The waveform generation unit is connected to the output amplification unit and configured to provide a positive-end alternating-current signal and a negative-end alternating-current signal for the output amplification unit under control of the control processing unit. The output amplification unit is configured to obtain a positive-end bias intermediate voltage and a negative-end bias intermediate voltage according to the common-mode bias voltage code word and the differential-mode bias voltage code word, and output a positive-end output signal according to the positive-end alternating-current signal and the positive-end bias intermediate voltage and a negative-end output signal according to the negative-end alternating-current signal and the negative-end bias intermediate voltage. The first mapping relationship is:

2. The differential signal generator of claim 1, wherein, DAC The second mapping relationship is: _code_cm = a 1 ×V cm_set + a 2 ×V diff_set + a 3 ； DAC DAC _code_diff = b 1 ×V cm_set + b 2 ×V diff_set + b 3 ； wherein, DAC _code_cm is the common mode bias voltage code word, The output amplification unit includes a first radio frequency amplifier, a second radio frequency amplifier and a bias voltage circuit, an input end of the first radio frequency amplifier is connected to an output end of the waveform generation unit, configured to amplify and output the positive-end alternating-current signal, an input end of the second radio frequency amplifier is connected to an output end of the waveform generation unit, configured to amplify and output the negative-end alternating-current signal. _code_diff is the differential mode bias voltage code word, V cm_set is the common mode bias voltage set point, V diff_set is the differential mode bias voltage set point, a 1 , a 2 and a 3 is a coefficient term, b 1 , b 2 and b 3 is a coefficient term.

3. The differential signal generator of claim 1, wherein, An input end of the bias voltage circuit is connected to the control processing unit to obtain the common-mode bias voltage code word and the differential-mode bias voltage code word, the bias voltage circuit includes a first bias output end and a second bias output end, the first bias output end is connected to an output end of the first radio frequency amplifier, and the second bias output end is connected to an output end of the second radio frequency amplifier. The bias voltage circuit is configured to determine the positive-end bias intermediate voltage and the negative-end bias intermediate voltage according to the common-mode bias voltage code word and the differential-mode bias voltage code word, superimpose the positive-end bias intermediate voltage to the output end of the first radio frequency amplifier through the first bias output end to obtain the positive-end output signal, and superimpose the negative-end bias intermediate voltage to the output end of the second radio frequency amplifier through the second bias output end to obtain the negative-end output signal. The bias voltage circuit includes a bias digital-to-analog converter, a first operational amplifier sub-circuit and a second operational amplifier sub-circuit.

4. The differential signal generator of claim 3, wherein, ​ The input end of the biasing digital-to-analog converter is connected to the output end of the control processing unit, and the output end of the biasing digital-to-analog converter is connected to the input end of the first operational amplifier sub-circuit and the second operational amplifier sub-circuit respectively; the biasing digital-to-analog converter is used to convert the common-mode bias voltage code word into a common-mode bias analog voltage and then output to the first operational amplifier sub-circuit and the second operational amplifier sub-circuit, and convert the differential-mode bias voltage code word into a differential-mode bias analog voltage and then output to the first operational amplifier sub-circuit; The output end of the first operational amplifier sub-circuit is connected to the input end of the second operational amplifier sub-circuit and the first biasing output end, and the first operational amplifier sub-circuit is used to obtain the positive terminal biasing intermediate voltage according to the common-mode bias analog voltage and the differential-mode bias analog voltage and then output to the first biasing output end and the second operational amplifier sub-circuit; The output end of the second operational amplifier sub-circuit is connected to the second biasing output end, and the second operational amplifier sub-circuit is used to obtain the negative terminal biasing intermediate voltage according to the positive terminal biasing intermediate voltage and the common-mode bias analog voltage and then output to the second biasing output end.

5. The differential signal generator of claim 4, wherein, The first operational amplifier sub-circuit comprises a first resistor, a second resistor, a third resistor and a first operational amplifier; The non-inverting input end of the first operational amplifier is connected to the output end of the biasing digital-to-analog converter through the first resistor to obtain the differential-mode bias analog voltage, the inverting input end of the first operational amplifier is connected to the output end of the biasing digital-to-analog converter through the second resistor to obtain the common-mode bias analog voltage, and the output end of the first operational amplifier is connected to the first biasing output end and the input end of the second operational amplifier sub-circuit, and the first operational amplifier is used to obtain the positive terminal biasing intermediate voltage according to the common-mode bias analog voltage and the differential-mode bias analog voltage and then output to the first biasing output end and the second operational amplifier sub-circuit; One end of the third resistor is connected to the inverting input end of the first operational amplifier, and the other end is connected to the output end of the first operational amplifier.

6. The differential signal generator of claim 4, wherein, The second operational amplifier sub-circuit comprises a fourth resistor, a fifth resistor, a sixth resistor and a second operational amplifier; The non-inverting input end of the second operational amplifier is grounded, the inverting input end of the second operational amplifier is connected to the output end of the biasing digital-to-analog converter through the fourth resistor and connected to the output end of the first operational amplifier sub-circuit through the fifth resistor to obtain the superimposed voltage of the common-mode bias analog voltage and the positive terminal biasing intermediate voltage, and the output end of the second operational amplifier is connected to the second biasing output end, and the second operational amplifier is used to output the negative terminal biasing intermediate voltage according to the superimposed voltage; One end of the sixth resistor is connected to the inverting input end of the second operational amplifier, and the other end is connected to the output end of the second operational amplifier.

7. The differential signal generator of claim 3, wherein, The output amplifying unit further comprises a first two-way switch, a second two-way switch, a first output stage amplifier, a third two-way switch, a fourth two-way switch, a second output stage amplifier, a positive output end and a negative output end; The input end of the first two-way switch is connected to the output end of the first radio frequency amplifier, the first output end of the first two-way switch is connected to the input end of the first output stage amplifier, the output end of the first output stage amplifier is connected to the first input end of the second two-way switch, the second output end of the first two-way switch is connected to the second input end of the second two-way switch, and the output end of the second two-way switch is connected to the positive output end; the first two-way switch and the second two-way switch are configured to directly connect the output end of the first radio frequency amplifier and the positive output end, or connect the output end of the first radio frequency amplifier, the first output stage amplifier and the positive output end; The input end of the third two-way switch is connected to the output end of the second radio frequency amplifier, the first output end of the third two-way switch is connected to the input end of the second output stage amplifier, the output end of the second output stage amplifier is connected to the first input end of the fourth two-way switch, the second output end of the third two-way switch is connected to the second input end of the fourth two-way switch, and the output end of the fourth two-way switch is connected to the output end of the output amplifying unit; the third two-way switch and the fourth two-way switch are configured to directly connect the output end of the second radio frequency amplifier and the negative output end, or connect the output end of the second radio frequency amplifier, the second output stage amplifier and the negative output end.

8. The differential signal generator of claim 3, wherein, Further comprising an output attenuation unit, the waveform generating unit is connected to the output amplifying unit through the output attenuation unit; The output attenuation unit is used for filtering the positive end alternating current signal and the negative end alternating current signal, attenuating the positive end alternating current signal to the input signal range of the first radio frequency amplifier, and then outputting the positive end alternating current signal to the first radio frequency amplifier, and attenuating the negative end alternating current signal to the input signal range of the second radio frequency amplifier, and then outputting the negative end alternating current signal to the second radio frequency amplifier.

9. The differential signal generator of claim 1, wherein, Further comprising an output control unit, the output control unit comprises a fifth two-way switch, a sixth two-way switch, a P differential output end and an N differential output end, and the output amplifying unit comprises a positive output end and a negative output end; The P differential output end is connected to the positive output end through the fifth two-way switch, and is used for outputting or inhibiting outputting the positive end output signal under the control of the fifth two-way switch; The N differential output end is connected to the negative output end through the sixth two-way switch, and is used for outputting or inhibiting outputting the negative end output signal under the control of the sixth two-way switch.

10. A calibration method, characterized by, The calibration method is applied to the differential signal generator of any one of claims 1-9, and the calibration method comprises: At least three groups of common mode bias voltage code words and differential mode bias voltage code words are obtained; Each group of common mode bias voltage code words and differential mode bias voltage code words is input into the output amplifying unit in sequence by the control processing unit, the positive end bias output voltage and the negative end bias output voltage output by the output amplifying unit are measured, and the common mode bias output voltage and the differential mode bias output voltage are calculated according to the positive end bias output voltage and the negative end bias output voltage; The common-mode bias output voltage is set as a common-mode bias voltage setting value, and the differential-mode bias output voltage is set as a differential-mode bias voltage setting value. The first mapping relationship and the second mapping relationship are calibrated according to at least three groups of common-mode bias voltage code words, differential-mode bias voltage code words, common-mode bias voltage setting values and differential-mode bias voltage setting values.

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