Processor chip with adjustable power consumption and clock frequency dynamic adjustment method

Abstract

The invention provides a processor chip with adjustable power consumption, which is integrated with a plurality of functional cores and a plurality of routers, all the routers are mutually connected to form an on-chip network, all the functional cores are mounted on the on-chip network to realize mutual communication, and the chip further comprises a power consumption management module, all the functional cores and all the routers are configured to be subjected to clock frequency adjustment by a power consumption management module, and the power consumption management module is used for adjusting the clock frequency of the processor chip based on a received frequency raising request from the functional cores and / or the routers; the clock frequency of the processor chip is adjusted based on a self-configured adjusting mechanism; wherein the power consumption management module is configured to support unified adjustment of clock frequencies of all the functional cores and / or all the routers, and independently adjust the clock frequencies of each functional core and each router; and the power consumption management module is mounted on the network-on-chip to realize communication with each router and each functional core.

Description

Technical Field

[0001] This invention relates to integrated chips, more specifically to low-power integrated chips, and more specifically to a power-adjustable processor chip and a method for dynamically adjusting the clock frequency. Background Technology

[0002] With the continuous development of integrated circuit technology, integrating multiple functional cores (CPU, GPU, I / O, PICE, etc.) into a single chip to build a large-scale System-on-Chip (SoC) has become a mainstream trend. In such multi-core systems, the Network-on-Chip (NoC) serves as the core interconnect infrastructure, undertaking the critical task of meeting the communication needs between the functional cores. Functional cores are mounted to the NoC as master / slave devices, transmitting data packets to routers within the network to achieve data transmission with the target device (functional core). The NoC typically consists of multiple routers and links, and can flexibly adopt different network topologies to adapt to diverse application scenarios.

[0003] However, while pursuing high performance, current processor chips face severe power consumption challenges. The continuous expansion of on-chip network scale, the sustained increase in operating frequency, and the large-scale configuration of cache resources have all led to a sharp increase in processor chip power consumption. This high power consumption has a variety of negative impacts on the chip. From a performance perspective, high power consumption limits the overall performance of the chip, preventing it from reaching its theoretically optimal operating state. More seriously, high power consumption can cause chip overheating. Excessive chip temperature not only reduces its operational stability, leading to frequent data transmission errors and calculation result deviations, but also, in the long run, damages the chip's physical structure and shortens its lifespan.

[0004] To reduce the power consumption of processor chips, researchers have focused on on-chip networks (CNNs), proposing to optimize overall chip power consumption by reducing CNN power consumption. Currently, there are two main approaches to reducing CNN power consumption. The first involves collecting information from all devices and CNN components on the processor chip for power management. This method attempts to achieve fine-grained power control by comprehensively understanding the operating status of each part of the system. The second approach manages power consumption by adjusting the CNN's operating frequency. By dynamically adjusting the frequency, the CNN can operate at appropriate power under different workloads, thereby reducing power consumption.

[0005] While both approaches can reduce the power consumption of on-chip networks to some extent, they both have significant drawbacks. For the global information collection and power management approach, the core problem lies in the fact that collecting global information from all devices and all on-chip network components for power management leads to extremely complex control logic. The large amount of information processing and analysis requires complex algorithms and hardware support, which not only increases the design difficulty of the chip but also introduces excessive management overhead, including the consumption of computing and storage resources, thus offsetting some of the benefits of power reduction. For the operating frequency adjustment approach, the main drawback is that to achieve effective power reduction, overly fine-grained frequency adjustments are often required. These fine-grained frequency adjustments make clock switching control exceptionally complex, requiring precise clock generation and switching circuits, which also leads to high control overhead.

[0006] In summary, while existing technologies offer a solution to reduce processor chip power consumption by lowering on-chip network power consumption, their complexity in control and high management overhead make it difficult to achieve efficient and practical power management in real-world applications.

[0007] It should be noted that the background information presented here is only for illustrating relevant information about the present invention to aid in understanding the technical solutions of the present invention, and does not imply that the relevant information is necessarily prior art. In the absence of evidence indicating that the relevant information was disclosed before the filing date of this invention, the relevant information should not be considered prior art. Summary of the Invention

[0008] Therefore, the purpose of this invention is to overcome the shortcomings of the prior art and provide a processor chip with adjustable power consumption and a method for dynamically adjusting clock frequency.

[0009] The objective of this invention is achieved through the following technical solutions.

[0010] According to a first aspect of the present invention, a power-adjustable processor chip is provided. The processor chip integrates multiple functional cores and multiple routers, all routers are interconnected to form an on-chip network, and all functional cores are mounted on the on-chip network to achieve mutual communication. The processor chip further includes a power management module, and all functional cores and all routers are configured to have their clock frequencies adjusted by the power management module. Specifically: the power management module is used to adjust the clock frequency of the processor chip based on received upsampling requests from the functional cores and / or routers, and to adjust the clock frequency of the processor chip based on its own configured adjustment mechanism; the power management module is configured to support unified adjustment of the clock frequencies of all functional cores and / or all routers, and individual adjustment of the clock frequencies of each functional core and each router; and the power management module is mounted on the on-chip network to achieve communication with each router and each functional core.

[0011] In some embodiments of the present invention, the power management module is configured to adjust the clock frequency of the processor chip in the following manner: the power management module detects at fixed time intervals whether it has received a frequency upsampling request from the router and / or functional core; if a frequency upsampling request is received from the router and / or functional core, the current clock frequency of the corresponding router and / or functional core is doubled; if no frequency upsampling request is received from the router and / or functional core, the current clock frequency of all routers and functional cores is halved; wherein, each router and each functional core has a set clock frequency range, and the power management module adjusts the clock frequency based on the clock frequency range of each router and each functional core, so that the clock frequency of each router and each functional core does not exceed its own clock frequency range after frequency upsampling or frequency downsampling.

[0012] In some embodiments of the present invention, the adjustment mechanism includes an energy-saving adjustment mode, a balanced adjustment mode, and a full-power adjustment mode.

[0013] In some embodiments of the present invention, the energy-saving adjustment mode is as follows: when the processor chip is configured to energy-saving mode, the clock frequency of all routers and all functional cores is reduced by half at fixed time intervals until the clock frequency of all routers and functional cores is kept at the minimum value of their own clock frequency range.

[0014] In some embodiments of the present invention, the equalization adjustment mode is as follows: when the processor chip is configured in equalization mode, for routers and functional cores whose clock frequencies exceed the midpoint of their own clock frequency range, the clock frequencies of these routers and functional cores are reduced by half at fixed time intervals until the clock frequencies of these routers and functional cores are all maintained at the midpoint of their own clock frequency range; for routers and functional cores whose clock frequencies do not exceed the midpoint of their own clock frequency range, the clock frequencies of these routers and functional cores are increased by half at fixed time intervals until the clock frequencies of these routers and functional cores are all maintained at the midpoint of their own clock frequency range.

[0015] In some embodiments of the present invention, the full power adjustment mode is as follows: when the processor chip is configured to full power mode, the clock frequency of all routers and all functional cores is doubled at fixed time intervals until the clock frequency of all routers and all functional cores is maintained at the maximum value of their own clock frequency range.

[0016] In some embodiments of the present invention, the network topology of the on-chip network is a Mesh network topology, a Ring network topology, a Torus network topology, or a Butterfly network topology.

[0017] According to a second aspect of the present invention, a method for dynamically adjusting the clock frequency of a processor chip as described in the first aspect of the present invention is provided. The method involves configuring the processor chip to adjust its clock frequency at each fixed time interval according to the following steps: Step S1: Detecting whether it has received an upclocking request from a router and / or a functional core; Step S2: If an upclocking request is received from a router and / or a functional core, doubling the current clock frequency of the corresponding router and / or functional core; If no upclocking request is received from a router and / or a functional core, halving the current clock frequency of all routers and functional cores.

[0018] Compared with the prior art, the advantages of the present invention are: (1) a power management module is introduced and the power management module is configured to adjust the clock frequency of the processor chip based on the received up-frequency request from the functional core and / or router, and to adjust the clock frequency of the processor chip based on its own configured adjustment mechanism, thereby realizing power management through a combination of hardware and software; (2) when performing up-frequency or down-frequency processing, the power management module adjusts the clock frequency of the processor chip by multiplicative frequency division, which reduces the complexity of design and implementation, and can realize efficient and practical power management in practical applications. Attached Figure Description

[0019] The embodiments of the present invention will be further described below with reference to the accompanying drawings, wherein:

[0020] Figure 1 This is a schematic diagram of the composition of a processor chip according to an embodiment of the present invention;

[0021] Figure 2 This is a schematic diagram illustrating a Mesh network topology example according to an embodiment of the present invention;

[0022] Figure 3 This is a schematic diagram illustrating a Ring network topology example according to an embodiment of the present invention;

[0023] Figure 4 This is a schematic diagram illustrating an example of a Torus network topology according to an embodiment of the present invention;

[0024] Figure 5 This is a schematic diagram illustrating a Butterfly network topology example according to an embodiment of the present invention;

[0025] Figure 6 This is a schematic flowchart of a clock frequency dynamic adjustment method according to an embodiment of the present invention. Detailed Implementation

[0026] To make the objectives, technical solutions, and advantages of this invention clearer, the invention will be further described in detail below with reference to the accompanying drawings and specific embodiments. It should be understood that the specific embodiments described herein are merely illustrative and are not intended to limit the invention.

[0027] Before describing the present invention, let me first introduce some existing methods for reducing the power consumption overhead of on-chip networks.

[0028] Chinese patent application CN202011135266.9 proposes a method, apparatus, CPU chip, and server for reducing on-chip network (NoC) power consumption. The method involves acquiring the operating status data of the NoC, including one or more of the following: the number of unresponsive requests initiated by the NIU within a time window, the number of requests and responses cached in the RU within a time window, and historical bandwidth statistics of the NoC. Based on this data, the method calculates the expected operating frequency of the NoC and adjusts its operating frequency accordingly, ultimately reducing the power consumption overhead of the NoC. While this method can reduce the power consumption overhead of the NoC, it requires overly fine-grained frequency adjustments, which makes clock switching control exceptionally complex and introduces high control overhead.

[0029] Chinese patent application CN202011135779.X discloses a method, apparatus, CPU chip, and server for reducing the power consumption of an on-chip network (NoC). The method includes: acquiring the operating status data of the NoC, which includes one or more of the following: the maximum number of caches used by the NIU and the maximum number of caches used by the RU in a recent period; calculating the number of caches that need to be enabled in the NIU and RU respectively based on the operating status data; and disabling the remaining caches in the NIU and RU based on the number of caches that need to be enabled. While this method can reduce the power consumption of the NoC, collecting global information from all devices and all NoC components for power management leads to extremely complex control logic and introduces excessive management overhead.

[0030] Chinese patent application CN202011135270.5 discloses a method, apparatus, CPU chip, and server for reducing the power consumption of an on-chip network (NoC). The method includes: acquiring operating status data of the on-chip NoC's mounted devices within a time window, the operating status data including one or more of the following: the frequency of bandwidth-sensitive events occurring in the device, cache utilization in the device, and the bandwidth of the device's interface bus; calculating the expected operating frequency of the NoC based on the operating status data; and adjusting the operating frequency of the NoC based on the expected operating frequency. While this method can reduce the power consumption of the on-chip network, it requires overly fine-grained frequency adjustments, which makes clock switching control exceptionally complex and introduces high control overhead.

[0031] Chinese patent application CN202011284050.9 discloses a method, apparatus, CPU chip, and server for reducing the power consumption of an on-chip network (NoC). The method includes: dividing the NoC into two or more non-overlapping regions, each region using its own independent operating clock; acquiring the operating status data of the routing units (RUs) of the NoC; calculating the expected operating frequency of each region of the NoC based on the operating status data; and adjusting the operating frequency of each region of the NoC to the expected operating frequency. While this method can reduce the power consumption of the NoC, it requires overly fine-grained frequency adjustments, which makes clock switching control exceptionally complex and introduces high control overhead.

[0032] As can be seen from the background technology and the above-mentioned methods for reducing on-chip network power consumption, although the existing technology provides a way to reduce processor chip power consumption by reducing on-chip network power consumption, it is difficult to achieve efficient and practical power management in actual applications due to problems such as control complexity and high management overhead.

[0033] To address the aforementioned problems, the inventors studied processor chips and discovered that their power consumption primarily consists of dynamic power consumption and static power consumption. Dynamic power consumption is mainly caused by the current consumption generated during the charging and discharging of load capacitors when internal transistors switch logic states (0->1 or 1->0) during chip operation. Its magnitude is related to the operating frequency (…). ), the square of the working voltage ( ), load capacitor ( ) and switching activity factor ( Proportional (i.e.) Static power consumption is mainly caused by the minute current consumption of transistors even when they are not switching states (static), due to the non-ideal characteristics resulting from miniaturization of the manufacturing process. Analysis shows that dynamic power consumption is related to the operating frequency (…). The power consumption of a processor exhibits a linear proportional relationship with its operating frequency. Therefore, by reducing the processor's operating frequency (downclocking), the number of transistor state switches per unit time can be directly reduced, thereby significantly reducing the dynamic power consumption and ultimately lowering the processor chip's power consumption. Based on this, the inventors propose a processor chip capable of dynamically adjusting power consumption. This processor chip incorporates a power management module for clock frequency adjustment. Specifically, the power management module is configured to adjust the processor chip's clock frequency based on received upclocking requests from functional cores and / or routers, as well as based on its own configured adjustment mechanism. This allows for the management of the processor chip's power consumption, enabling it to operate at appropriate power levels and thus reducing power consumption.

[0034] In summary, such as Figure 1 As shown, this invention provides a power-adjustable processor chip. The processor chip integrates multiple functional cores and multiple routers. All routers are interconnected to form an on-chip network. All functional cores are mounted on the on-chip network to achieve mutual communication. The processor chip also includes a power management module, and all functional cores and all routers are configured to have their clock frequencies adjusted by the power management module. Specifically: the power management module adjusts the processor chip's clock frequency based on received upsampling requests from the functional cores and / or routers, and adjusts the processor chip's clock frequency based on its own configured adjustment mechanism; the power management module is configured to support unified adjustment of the clock frequencies of all functional cores and / or all routers, as well as individual adjustment of the clock frequencies of each functional core and each router; the power management module is mounted on the on-chip network to achieve communication with each router and each functional core.

[0035] To better understand the present invention, the working principle of the power management module in the processor chip will be described in detail below with reference to specific embodiments.

[0036] In one embodiment of the present invention, the power management module is configured to adjust the clock frequency of the processor chip as follows: the power management module detects at fixed time intervals whether it has received a frequency upsampling request from a router and / or a functional core; if a frequency upsampling request is received from a router and / or a functional core, the current clock frequency of the corresponding router and / or functional core is doubled; if no frequency upsampling request is received from a router and / or a functional core, the current clock frequency of all routers and functional cores is halved; wherein each router and each functional core has a set clock frequency range, and the power management module adjusts the clock frequency based on the clock frequency range of each router and each functional core, such that the clock frequency of each router and each functional core, after frequency upsampling or downsampling, does not exceed its own clock frequency range. Through this adjustment method, the power management module can support unified adjustment of the clock frequency of all functional cores and / or all routers, unified adjustment of the clock frequency of some functional cores and / or some routers, and individual adjustment of the clock frequency of each functional core and each router.

[0037] It's important to note that each router and each functional core must not exceed its own clock frequency range during frequency upscaling or downscaling. For example, if a router's clock frequency range is 600-1500MHz, and the frequency is upscaled when it's at 1200MHz, the theoretical clock frequency should be 2400MHz, which far exceeds the router's clock frequency range. In this case, due to the router's own clock frequency range limitation, the actual clock frequency after the upscaling is 1500MHz. Conversely, if the frequency is downscaled when it's at 900MHz, the theoretical clock frequency should be 450MHz, which also exceeds the router's clock frequency range. In this case, due to the router's own clock frequency range limitation, the actual clock frequency after the downscaling is 600MHz.

[0038] In one embodiment of the present invention, the adjustment mechanism includes an energy-saving adjustment mode, a balanced adjustment mode, and a full-power adjustment mode. The adjustment mechanism can be written and configured into the processor chip in the form of code, causing the processor chip to follow the adjustment mechanism to adjust the clock frequency. It should be noted that the adjustment mechanism can also be set according to actual needs, and the present invention does not impose any special limitations.

[0039] In one embodiment of the present invention, the energy-saving adjustment mode is as follows: when the processor chip is configured to energy-saving mode, the clock frequency of all routers and all functional cores is reduced by half at fixed time intervals until the clock frequency of all routers and functional cores is kept at the minimum value of their own clock frequency range.

[0040] In one embodiment of the present invention, the equalization adjustment mode is as follows: when the processor chip is configured in equalization mode, for routers and functional cores whose clock frequencies exceed the midpoint of their own clock frequency range, the clock frequencies of these routers and functional cores are reduced by half at fixed time intervals until the clock frequencies of these routers and functional cores are all maintained at the midpoint of their own clock frequency range; for routers and functional cores whose clock frequencies do not exceed the midpoint of their own clock frequency range, the clock frequencies of these routers and functional cores are increased by half at fixed time intervals until the clock frequencies of these routers and functional cores are all maintained at the midpoint of their own clock frequency range.

[0041] In one embodiment of the present invention, the full power adjustment mode is as follows: when the processor chip is configured to full power mode, the clock frequency of all routers and all functional cores is doubled at fixed time intervals until the clock frequency of all routers and all functional cores is maintained at the maximum value of their own clock frequency range.

[0042] In one embodiment of the present invention, the network topology of the on-chip network is a Mesh network topology, a Ring network topology, a Torus network topology, or a Butterfly network topology.

[0043] Mesh network topology as follows Figure 2 As shown. Figure 2 The image shows a mesh network topology consisting of 16 routers (hollow circles in the image represent routers). The 16 routers are arranged in a 4x4 two-dimensional grid. Each router is only connected to its directly adjacent routers (i.e., its upper, lower, left, and right neighbors, excluding diagonals). The interconnected routers can communicate with each other.

[0044] Ring network topology as follows Figure 3 As shown. Figure 3 The diagram illustrates a Ring network topology consisting of four routers (the hollow circles in the diagram represent routers). All routers are connected in series to form a physical or logical ring. Each router is directly connected to only two neighboring routers, and the interconnected routers can communicate with each other.

[0045] Torus network topology as follows Figure 4 As shown. Figure 4The diagram shows a Torus network topology consisting of 16 routers (represented by hollow circles in the diagram). All routers are arranged in a 4x4 two-dimensional grid, and interconnection between them is achieved by connecting the grid boundaries end to end to form a toroidal structure. The interconnected routers can communicate with each other.

[0046] Butterfly network topology as follows: Figure 5 As shown. Figure 5 The Butterfly network topology, consisting of 32 routers, is shown. Hollow circles represent functional cores (numbered 0-15), and rectangles represent routers (numbered 0.0-3.7). In the Butterfly network topology, each router communicates with other routers through hierarchical connections.

[0047] As can be seen from the foregoing embodiments, unlike the prior art, the present invention introduces a power management module into the processor chip, and configures the power management module to adjust the clock frequency of the processor chip based on the received upclocking request from the functional core and / or router, and to adjust the clock frequency of the processor chip based on its own configured adjustment mechanism. Power management is achieved through a combination of hardware and software. Furthermore, when performing upclocking or downclocking, the power management module adjusts the clock frequency of the processor chip by multiplicative division, reducing the complexity of design and implementation, and enabling efficient and practical power management in real-world applications.

[0048] Based on the foregoing embodiments, such as Figure 6 As shown, the present invention also proposes a method for dynamically adjusting the clock frequency of a processor chip as described in the foregoing embodiments. The method involves configuring the processor chip to adjust its clock frequency at each fixed time interval according to the following steps: Step S1: Detect whether it has received an upclocking request from a router and / or a functional core; Step S2: If an upclocking request is received from a router and / or a functional core, double the current clock frequency of the corresponding router and / or functional core; if no upclocking request is received from a router and / or a functional core, halve the current clock frequency of all routers and functional cores.

[0049] The beneficial effects of the present invention are as follows: (1) A power management module is introduced and configured to adjust the clock frequency of the processor chip based on the received up-frequency request from the functional core and / or router, and to adjust the clock frequency of the processor chip based on its own configured adjustment mechanism, thereby realizing power management through a combination of hardware and software; (2) When performing up-frequency or down-frequency processing, the power management module adjusts the clock frequency of the processor chip by multiplicative frequency division, which reduces the complexity of design and implementation, and can realize efficient and practical power management in practical applications.

[0050] It should be noted that although the steps are described in a specific order above, it does not mean that the steps must be executed in the above specific order. In fact, some of these steps can be executed concurrently or even in a different order, as long as the required function can be achieved.

[0051] This invention can be a system, method, and / or computer program product. A computer program product may include a computer-readable storage medium having computer-readable program instructions loaded thereon for causing a processor to implement various aspects of the invention.

[0052] Computer-readable storage media can be tangible devices that hold and store instructions for use by an instruction execution device. Computer-readable storage media can include, for example, but not limited to, electrical storage devices, magnetic storage devices, optical storage devices, electromagnetic storage devices, semiconductor storage devices, or any suitable combination thereof. More specific examples (a non-exhaustive list) of computer-readable storage media include: portable computer disks, hard disks, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), static random access memory (SRAM), portable compact disc read-only memory (CD-ROM), digital multifunction disc (DVD), memory sticks, floppy disks, mechanical encoding devices, such as punch cards or recessed protrusions storing instructions thereon, and any suitable combination thereof.

[0053] The various embodiments of the present invention have been described above. These descriptions are exemplary and not exhaustive, nor are they limited to the disclosed embodiments. Many modifications and variations will be apparent to those skilled in the art without departing from the scope and spirit of the described embodiments. The terminology used herein is chosen to best explain the principles, practical application, or technical improvements to the embodiments in the market, or to enable others skilled in the art to understand the embodiments disclosed herein.

Claims

1. A power-adjustable processor chip, wherein the processor chip integrates multiple functional cores and multiple routers, all routers are interconnected to form an on-chip network, and all functional cores are mounted on the on-chip network to achieve mutual communication, characterized in that, The processor chip also includes a power management module, and all functional cores and all routers are configured to have their clock frequencies adjusted by the power management module, wherein: The power management module is used to adjust the clock frequency of the processor chip based on the received upclocking requests from the functional cores and / or routers, and to adjust the clock frequency of the processor chip based on its own configured adjustment mechanism; wherein, the power management module is configured to support unified adjustment of the clock frequency of all functional cores and / or all routers, as well as individual adjustment of the clock frequency of each functional core and each router. The power management module is mounted on the on-chip network to enable communication with various routers and functional cores.

2. The processor chip according to claim 1, characterized in that, The power management module is configured to adjust the clock frequency of the processor chip in the following manner: The power management module checks at fixed time intervals whether it has received an upsampling request from the router and / or the functional core. If an upclocking request is received from a router and / or functional core, the current clock frequency of the corresponding router and / or functional core will be doubled. If no upclocking request is received from the routers and / or functional cores, the current clock frequency of all routers and functional cores will be halved. Each router and each functional core has a set clock frequency range. The power management module adjusts the clock frequency based on the clock frequency range of each router and each functional core, so that the clock frequency of each router and each functional core does not exceed its own clock frequency range after being up- or down-clocked.

3. The processor chip according to claim 2, characterized in that, The regulation mechanism includes energy-saving regulation mode, balanced regulation mode and full-power regulation mode.

4. The processor chip according to claim 3, characterized in that, The energy-saving adjustment mode is as follows: When the processor chip is configured to power-saving mode, the clock frequency of all routers and all functional cores is reduced by half at fixed time intervals until the clock frequency of all routers and functional cores is kept at the minimum value of their own clock frequency range.

5. The processor chip according to claim 4, characterized in that, The equilibrium adjustment mode is as follows: When the processor chip is configured in balanced mode, for routers and functional cores whose clock frequency exceeds the midpoint of their own clock frequency range, the clock frequency of these routers and functional cores is reduced by half at fixed time intervals until the clock frequency of these routers and functional cores is kept at the midpoint of their own clock frequency range. For routers and functional cores whose clock frequencies do not exceed the midpoint of their own clock frequency range, the clock frequencies of these routers and functional cores are doubled at fixed time intervals until the clock frequencies of these routers and functional cores are all maintained at the midpoint of their own clock frequency range.

6. The processor chip according to claim 5, characterized in that, The full power adjustment mode is as follows: When the processor chip is configured to full power mode, the clock frequency of all routers and all functional cores is doubled at fixed time intervals until the clock frequency of all routers and all functional cores remains at the maximum value of their own clock frequency range.

7. The processor chip according to claim 6, characterized in that, The network topology of the on-chip network can be a Mesh network topology, a Ring network topology, a Torus network topology, or a Butterfly network topology.

8. A method for dynamically adjusting the clock frequency of a processor chip as described in any one of claims 1-7, characterized in that, The method involves configuring the processor chip to adjust its clock frequency at fixed time intervals according to the following steps: Step S1: Check whether you have received an upsampling request from the router and / or the functional core; Step S2: If an upclocking request is received from the router and / or functional core, the current clock frequency of the corresponding router and / or functional core is doubled. If no upclocking request is received from the routers and / or functional cores, the current clock frequency of all routers and functional cores will be halved.

9. A computer-readable storage medium, characterized in that, It stores a computer program that can be executed by a processor to implement the steps of the method of claim 8.

10. An electronic device, characterized in that, include: One or more processor chips as described in any one of claims 1-7, and a memory.

Images