LDO (Low Dropout Regulator) grounding short circuit protection device

Abstract

The invention provides an LDO (Low Dropout Regulator) ground short circuit protection device, which comprises a first LDO, a second LDO, a third LDO and a fourth LDO, the voltage sampling module is used for sampling the high-voltage domain power supply voltage and generating sampling voltage; the band-gap reference source is used for generating reference voltage; the ground short circuit detection and control module is used for judging whether the first LDO generates a ground short circuit or not according to the reference voltage and the sampling voltage and generating a control signal, and the control signal is used for controlling the output of the first LDO to be turned off or turned on. The circuit is realized in a pure analog circuit voltage detection mode, no auxiliary circuit such as a clock signal generation circuit, a delay circuit and a clock synchronization circuit is needed, and the circuit is simple in implementation mode, rapid in response, small in occupied area and low in power consumption.

Description

Technical Field

[0001] This invention relates to the field of electronic technology, and in particular to an LDO ground short-circuit protection device. Background Technology

[0002] With the widespread use of power management chips, the need for protection for these chips is becoming increasingly stringent. LDOs (Low-dropout regulators) are frequently used in power management chips. In board-level applications of power management chips, short circuits to ground at the LDO output pin often occur during testing or surface mount technology (SMT) assembly. When an LDO output pin is short-circuited to ground, a large current flows through the MOSFET between the LDO output pin and the chip's power supply, causing overheating. If the short circuit to ground persists for too long, the MOSFET may burn out, resulting in irreversible damage to the chip.

[0003] Most existing short-circuit protection systems use fuses, but fuses can only provide protection once and cannot be reset after an incident, resulting in high maintenance costs. Some solutions use analog circuit current sensing to achieve short-circuit protection, but this method is prone to false triggering during chip power-up, and after a short circuit occurs, the entire detection loop will lock the LDO in the off state, affecting normal operation and posing reliability issues. Furthermore, this solution requires auxiliary circuitry, such as an OSC clock circuit and digital logic control circuits or PWM module circuits, resulting in a large circuit size. Summary of the Invention

[0004] The purpose of this invention is to provide an LDO ground short-circuit protection device to solve the problems in the prior art.

[0005] The technical solution adopted in this invention is as follows: An LDO ground short-circuit protection device, comprising: The first LDO is used to convert the voltage output from the high-voltage domain power supply into a stable high-voltage domain supply voltage for output. The voltage sampling module is used to sample the supply voltage in the high-voltage domain and generate a sampled voltage. A bandgap reference source is used to generate a reference voltage; The ground short circuit detection and control module is used to determine whether the first LDO has a ground short circuit based on the reference voltage and the sampled voltage, and to generate a control signal, which is used to control the output of the first LDO to be turned off or on.

[0006] As a preferred embodiment, the LDO ground short-circuit protection device further includes a power supply detection module, used to detect whether the high-voltage power supply is operating stably and output a power supply detection signal; the power supply detection signal is used to control the ground short-circuit detection and control module to reset; the ground short-circuit detection and control module always outputs a control signal to control the activation of the first LDO in the reset state.

[0007] As a preferred embodiment, the ground short-circuit detection and control module includes a comparator and a D flip-flop, wherein, The comparator has a first input terminal, a second input terminal, and an output terminal. The first input terminal of the comparator receives the reference voltage, and the second input terminal of the comparator receives the sampled voltage. The comparator compares the magnitude of the reference voltage and the sampled voltage and outputs a short-circuit indication signal to ground through the output terminal. The D flip-flop has a data input terminal, a clock input terminal, a reset terminal, and a data output terminal. The data input terminal of the D flip-flop receives a high-level signal, the clock input terminal receives a short-circuit indication signal to ground, the reset terminal receives the power supply detection signal, and the data output terminal outputs a control signal.

[0008] As a preferred embodiment, the power detection module outputs a high-level power detection signal when it detects that the voltage output by the high-voltage power supply is greater than the power-on switching threshold; and outputs a low-level power detection signal when it detects that the voltage output by the high-voltage power supply is less than the power-off switching threshold; wherein the power-on switching threshold is greater than the power-off switching threshold.

[0009] As a preferred embodiment, in the short-circuit-to-ground detection and control module, when the sampled voltage received by the comparator is less than the reference voltage, it indicates that the first LDO has experienced a short circuit to ground, and the output terminal outputs a high-level short-circuit-to-ground indication signal; otherwise, it indicates that the first LDO is working normally, and the output terminal outputs a low-level short-circuit-to-ground indication signal.

[0010] As a preferred embodiment, in the short-circuit-to-ground detection and control module, when the reset terminal of the D flip-flop receives a low-level power detection signal, a reset occurs, and the data output terminal outputs a low-level control signal; when the reset terminal of the D flip-flop receives a high-level power detection signal, the received short-circuit-to-ground indication signal is monitored in real time, and when the short-circuit-to-ground indication signal changes from low to high, the data output terminal outputs a high-level control signal; otherwise, the previous state is maintained.

[0011] As a preferred embodiment, when the first LDO receives a low-level control signal, the first LDO normally outputs the high-voltage domain supply voltage; when it receives a high-level control signal, the first LDO stops outputting the high-voltage domain supply voltage.

[0012] As a preferred embodiment, the voltage sampling module includes a first resistor and a second resistor. The first terminal of the first resistor receives the high-voltage domain supply voltage output by the first LDO, the second terminal of the first resistor is grounded through the second resistor, and the common node of the first resistor and the second resistor outputs the sampling voltage.

[0013] As a preferred embodiment, the first LDO includes a current mirror bias circuit, a switch control circuit, and a power MOSFET. The current mirror bias circuit provides a level conversion function for the switch control circuit, converting the voltage domain of the control signal to the same voltage domain as the power MOSFET. The first terminal of the power MOSFET is connected to a high-voltage power supply, and the second terminal of the power MOSFET serves as the output terminal of the first LDO. The control terminal of the power MOSFET receives a switch signal output by the switch control circuit. The switch control circuit receives the control signal and outputs a corresponding switch signal according to the state of the control signal to control the power MOSFET to turn on or off. Specifically, when the control signal is high, the power MOSFET is off; when the control signal is low, the power MOSFET is on.

[0014] As a preferred embodiment, the LDO ground short-circuit protection device further includes a second LDO, which is used to convert the voltage output from the low-voltage domain power supply and supply power to the bandgap reference source and the ground short-circuit detection and control module, respectively.

[0015] Compared with existing technologies, the beneficial effects of adopting the above technical solution are as follows: 1. It can achieve multiple protections, and there is no problem of locking up after being triggered.

[0016] 2. It adopts a pure analog circuit voltage detection method, which does not require any auxiliary circuits such as clock signal generation circuit, delay circuit, or clock synchronization circuit. The implementation method is simple, the response is fast, the area occupied is small, and the power consumption is low. 3. After a short circuit occurs and the short circuit fault is eliminated, the circuit can be restarted by manually powering on and off. No additional reset control signal or reset pin is required. The operation is simple, safe and reliable. Attached Figure Description

[0017] Figure 1 This is a schematic diagram of an LDO ground short-circuit protection device according to an embodiment of the present invention.

[0018] Figure 2 This is a schematic diagram of the operation of an LDO ground short-circuit protection device in one embodiment of the present invention.

[0019] Figure 3 This is a schematic diagram of an LDO ground short-circuit protection device in one embodiment of the present invention. Detailed Implementation

[0020] The embodiments of this application are described in detail below, examples of which are illustrated in the accompanying drawings, wherein the same or similar reference numerals denote the same or similar modules or modules having the same or similar functions throughout. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain this application, and should not be construed as limiting this application. Rather, the embodiments of this application include all variations, modifications, and equivalents falling within the spirit and scope of the appended claims.

[0021] To address the problems in the background art, this invention proposes an LDO ground short-circuit protection device, which can detect and protect against LDO ground short circuits using a simple pure analog circuit structure.

[0022] Please refer to Figure 1 The LDO ground short-circuit protection device mainly includes a first LDO, a voltage sampling module, a bandgap reference source, and a ground short-circuit detection and control module. The first LDO is primarily used to convert the voltage output from the high-voltage domain power supply VDDH into a stable high-voltage domain supply voltage for output. The voltage sampling module is primarily used to sample the high-voltage domain supply voltage and generate a sampling voltage VSNS_VBIAS. The bandgap reference source is primarily used to generate a reference voltage VREF. The ground short-circuit detection and control module is primarily used to determine whether the first LDO has generated a ground short circuit based on the reference voltage VREF and the sampling voltage VSNS_VBIAS, and to generate a control signal VBIAS_PD. The control signal VBIAS_PD is used to control the output of the first LDO to be turned off or on.

[0023] In this embodiment, the LDO ground short-circuit protection device also includes a power supply detection module. This module primarily determines the operating state of the power supply and thus controls the ground short-circuit detection and control module. Specifically, the power supply detection module determines whether the high-voltage power supply is operating stably by detecting the voltage output of the high-voltage power supply and comparing it to a preset threshold, and then outputs a power supply detection signal VDDH_PG_H. The power supply detection signal VDDH_PG_H can be used to control the ground short-circuit detection and control module to reset. In the reset state, the ground short-circuit detection and control module continuously outputs a control signal VBIAS_PD to activate the first LDO.

[0024] Please continue to refer to this. Figure 1 This embodiment provides a specific implementation of a ground short circuit detection and control module, including a comparator CMP and a D flip-flop DFF. The ground short circuit detection and control module mainly includes two parts: a comparator CMP and a D flip-flop DFF.

[0025] Specifically, the comparator CMP has a first input terminal, a second output terminal, and an output terminal. The first input terminal of the comparator CMP receives a reference voltage VREF provided by a bandgap reference source. The second input terminal of the comparator CMP receives a sampled voltage VSNS_VBIAS provided by a voltage sampling module. The comparator CMP compares the magnitude of the reference voltage VREF with the sampled voltage VSNS_VBIAS and outputs a short-circuit-to-ground indication signal VBIAS_SCP through the output terminal. This short-circuit-to-ground indication signal VBIAS_SCP can characterize whether a short circuit to ground has occurred in the first LDO.

[0026] The D flip-flop (DFF) has a data input (D), a clock input (CLK), a reset input (RST_N), and a data output (Q). The data input (D) receives a high-level signal. The clock input (CLK) receives a short-circuit-to-ground indication signal (VBIAS_SCP). The reset input (RST_N) receives a power-on detection signal (VDDH_PG_H). The data output (Q) outputs a control signal (VBIAS_PD). ​​The DFF can adjust the output control signal (VBIAS_PD) based on the changes in the short-circuit-to-ground indication signal (VBIAS_SCP) input to the clock input (CLK), thereby controlling the on / off state of the first LDO.

[0027] Furthermore, the LDO short-circuit protection device proposed in this embodiment can be applied in the scenario of dual power supply chips. In this scenario, the LDO short-circuit protection device also includes a second LDO, which is used to convert the voltage output by the low voltage domain power supply VDDL into a lower voltage and more stable output voltage. The lower voltage and more stable output voltage are used to power the bandgap reference source and the short-circuit detection and control module, respectively.

[0028] Please refer to Figure 3 This embodiment also provides a specific implementation of a voltage sampling module. Specifically, the voltage sampling module includes a first resistor R1 and a second resistor R2. The first terminal of the first resistor R1 receives the high-voltage domain supply voltage output by the first LDO, and the second terminal of the first resistor R1 is grounded through the second resistor R2. The common node of the first resistor R1 and the second resistor R2 outputs a sampling voltage VSNS_VBIAS. By setting the first resistor R1 and the second resistor R2, the sampling voltage VSNS_VBIAS is proportional to the high-voltage domain supply voltage.

[0029] Please continue to refer to this. Figure 3This embodiment also provides a specific implementation of a first LDO, which includes a current mirror bias circuit, a switch control circuit, and a power MOSFET. The current mirror bias circuit provides a level conversion function for the switch control circuit, converting the voltage domain of the control signal to a voltage domain that can control the power MOSFET to turn on and off. The first terminal of the power MOSFET is connected to a high-voltage power supply, and the second terminal of the power MOSFET serves as the output terminal of the first LDO. The control terminal of the power MOSFET receives a switch signal output by the switch control circuit. The switch control circuit receives the control signal and outputs a corresponding switch signal according to the state of the control signal to control the power MOSFET to turn off or on. Specifically, when the control signal is high, the power MOSFET is off; when the control signal is low, the power MOSFET is on.

[0030] Normally, the control signal VBIAS_PD is in a low voltage domain (e.g., 1.5V), while the switching transistor Mn6 is in a high voltage source domain (normally around 12V). The voltage Vpbias is also generated in the high voltage domain during normal operation. Therefore, the control signal VBIAS_PD cannot directly turn on the switching transistor Mn6. Thus, this embodiment introduces a current mirror bias circuit and a switch control circuit. Specifically, the current mirror bias circuit includes switching transistors Mn0, Mn1, Mn2, resistor R0, Mn3, Mp0, and Mp1. The first terminals of switching transistors Mp0 and Mp1 are connected to the high voltage domain power supply VDDH. The control terminal of switching transistor Mp0 is connected to the control terminal of switching transistor Mp1. The second terminal of switching transistor Mp0 is connected to both the first terminal of switching transistor Mn3 and the control terminal of switching transistor Mp0. The second terminal of switching transistor Mp1 is connected to the switch control circuit. The control terminal of n3 is connected to the high-voltage domain power supply VDDH via resistor R0. The second terminal of switch Mn3 is connected to the first terminal of switch Mn1, and the second terminal of switch Mn1 is grounded. The first terminal of switch Mn2 is connected to the switch control circuit, and the second terminal of switch Mn2 is grounded. The first terminal of switch Mn0 receives the externally input bias current ibias, and the second terminal of switch Mn0 is grounded. The control terminal of switch Mn0 is connected to the first terminal of switch Mn0, the control terminal of switch Mn1, and the control terminal of switch Mn2, respectively. The bias current ibias is generated by the module in the low-voltage domain and can be implemented using existing methods, which will not be elaborated upon here.

[0031] The switching control circuit includes switching transistors Mn4, Mn5, and Mn6, resistors R3 and R4. The first terminal of switching transistor Mn4 is connected to the second terminal of switching transistor Mp1 in the current mirror bias circuit and the control terminal of switching transistor Mn5, respectively. The second terminal of switching transistor Mn4 is grounded, and its control terminal receives the control signal VBIAS_PD. The first terminal of switching transistor Mn5 is connected to the high-voltage domain power supply VDDH via resistor R3, and is also connected to the control terminal of switching transistor Mn6. The second terminal of switching transistor Mn5 is connected to the first terminal of switching transistor Mn2 in the current mirror bias circuit. The first terminal of switching transistor Mn6 is connected to the high-voltage domain power supply VDDH via resistor R4, and its second terminal is connected to the control terminal of the power MOSFET.

[0032] The first terminal of the power MOSFET is connected to the high-voltage domain power supply VDDH, and the second terminal of the power MOSFET serves as the output terminal of the first LDO, outputting a stable high-voltage domain supply voltage. This circuit also includes a voltage Vpbias, whose output terminal of operational amplifier EA is connected to the control terminal of the power MOSFET. This voltage Vpbias is used to provide the control terminal voltage Vpbias of the power MOSFET when the switching transistor Mn6 is off. The voltage Vpbias is determined by the loop feedback of the first LDO output voltage; this part is an existing circuit and is represented by ellipses in the attached diagram, so it will not be described in detail here. The ellipses at the power MOSFET in the diagram also include the resistor feedback network and compensation circuit in the loop; this part is also an existing circuit and will not be described in detail here.

[0033] With the above circuit structure, the switching transistor Mn6 is connected between the control terminal of the power MOSFET and the high-voltage power supply VDDH. It is opened or closed under the control signal VBIAS_PD, thereby realizing the switching control of the first LDO.

[0034] The following is combined with Figure 3 The control process of the first LDO is explained.

[0035] When the control signal VBIAS_PD=0, switch Mn4 is turned off, the voltage Vg5 at the control terminal of switch Mn5 is pulled up to VDDH, switch Mn5 is turned on, the voltage Vg6 at the control terminal of switch Mn6 is pulled down, switch Mn6 is turned off, the path between the control terminal of the power MOSFET and VDDH will be broken, the voltage Vpbias is determined by the op-amp output, the power MOSFET is turned on normally, at this time, the first LDO will work normally; When the control signal VBIAS_PD=1, switch Mn4 is turned on, the voltage Vg5 at the control terminal of switch Mn5 is pulled down, switch Mn5 is turned off, the voltage Vg6 at the control terminal of switch Mn6 is pulled up to VDDH, switch Mn6 is turned on, the path between the control terminal of the power MOSFET and VDDH will be opened, the voltage Vpbias is pulled up to VDDH, the power MOSFET is turned off, and at this time the first LDO will stop working.

[0036] Therefore, by using the control signal VBIAS_PD, the output of the first LDO can be cut off when a short circuit to ground occurs, thus preventing the MOSFET from burning out.

[0037] The following is combined with Figures 1-3 This section explains the operation of an LDO (Low Voltage Regulator) short-circuit protection device for ground faults in dual-power supply chip scenarios. Specifically, a dual-power supply chip scenario includes a high-voltage domain power supply VDDH (typically 12V) and a low-voltage domain power supply VDDL (typically 2.8V). The high-voltage domain power supply VDDH provides a stable high-voltage supply voltage to other internal modules (mainly the switching power supply drive circuit) through a first LDO. The low-voltage domain power supply VDDL provides a lower and more stable output voltage to other internal modules (mainly the analog circuit) through a second LDO. In practical operation, because the first LDO operates in the high-voltage domain, a very large current will flow directly from the high-voltage domain power supply VDDH through its internal power MOSFET to ground in the event of a ground fault. If this operation continues for an extended period, the power MOSFET is extremely prone to burnout. Based on the scenario where the first LDO suddenly short-circuits to ground during normal operation, the LDO ground protection device proposed in this embodiment can effectively detect the first LDO short-circuit to ground and disconnect the first LDO for protection when a ground short-circuit occurs. This method is simple, safe, and reliable, avoiding reliability problems caused by chip overheating due to short circuits.

[0038] exist Figure 1In the LDO ground short-circuit protection device shown, the voltage acquisition module samples the output voltage of the first LDO, and the comparator CMP compares the sampled voltage VSNS_VBIAS. When a ground short circuit occurs in the first LDO, the ground short-circuit indication signal VBIAS_SCP output by the comparator CMP will flip from 0 to 1, that is, from low level to high level. At this time, the rising edge of the D flip-flop DFF triggers the ground short-circuit indication signal VBIAS_SCP, generating a control signal VBIAS_PD to turn off the first LDO, thereby protecting the first LDO from ground short circuit. After manually troubleshooting and resolving the ground short-circuit fault of the first LDO, the high voltage domain power supply VDDH is powered on and off. This triggers the reset signal of the D flip-flop DFF, and then controls the first LDO to turn on again through its output control signal VBIAS_PD.

[0039] In this embodiment, the first LDO and the power detection module operate in the high voltage domain, receiving the voltage output from the high voltage domain; the bandgap reference source, comparator CMP, and D flip-flop DFF operate in the low voltage domain, receiving the low voltage domain power supply voltage output from the second LDO.

[0040] In the power detection module, a power-on switching threshold VTH and a power-off switching threshold VTT-1V are preset. When the voltage of the high-voltage domain power supply VDDH is detected to be greater than the power-on switching threshold, the power detection signal VDDH_PG_H=1, that is, a high-level power detection signal VDDH_PG_H is output; when the voltage of the high-voltage domain power supply VDDH is detected to be less than the power-off switching threshold, the power detection signal VDDH_PG_H=0, that is, a low-level power detection signal VDDH_PG_H is output.

[0041] In the voltage acquisition module, the high-voltage domain supply voltage output by the first LDO is sampled by setting the resistor to obtain the sampled voltage VSNS_VBIAS. In this embodiment, the magnitude of the sampled voltage VSNS_VBIAS is proportional to the magnitude of the high-voltage domain supply voltage.

[0042] In the bandgap reference source, the low-voltage domain supply voltage provided by the second LDO is received and a reference voltage VREF is generated as a voltage detection threshold, which is compared with the sampled voltage VSNS_VBIAS to determine whether the first LDO has a short circuit to ground.

[0043] In the comparator CMP, the sampled voltage VSNS_VBIAS is compared with the reference voltage VREF to generate a short-circuit-to-ground indication signal VBIAS_SCP. In this embodiment, the first input terminal of the comparator CMP is a positive input terminal, and the second input terminal is a negative input terminal. Specifically, when the first LDO is working normally, i.e., when no short circuit to ground occurs, the sampled voltage VSNS_VBIAS ≥ the reference signal, and the short-circuit-to-ground indication signal VBIAS_SCP = 0, thus generating a high-level short-circuit-to-ground indication signal VBIAS_SCP.

[0044] After a short circuit to ground occurs, and after manually checking for contact faults, the sampled voltage VSNS_VBIAS is greater than or equal to the reference voltage VREF. At this point, the short circuit to ground indication signal VBIAS_SCP goes low again.

[0045] In a D flip-flop (DFF), the DFF checks the information at the reset terminal RST_N. When the power detection signal VDDH_PG_H at the reset terminal RST_N is low, the DFF resets, and the data output terminal Q outputs a low-level control signal VBIAS_PD. When the power detection signal VDDH_PG_H at the reset terminal RST_N is high, the DFF triggers the data output terminal Q to output the data from the data input terminal D on the rising edge of the clock input terminal CLK. Since the data input terminal D continuously receives a high-level signal, the data output terminal Q will output a high-level control signal VBIAS_PD. If there is no rising edge at the clock input terminal CLK, the data output terminal Q will maintain its previous state.

[0046] The first LDO can be turned on and off using the control signal VBIAS_PD output from the D flip-flop (DFF). Specifically, when the first LDO experiences a short circuit to ground, the short circuit indication signal VBIAS_SCP transitions from 0 to 1, generating a rising edge. At this time, the control signal VBIAS_PD output from the data output terminal of the D flip-flop (DFF) transitions from low to high, thus turning off the first LDO. After the first LDO is turned off due to a short circuit to ground, and after manual troubleshooting and fault resolution, the high-voltage domain power supply VDDH is powered down. The power detection module will then output a low-level power detection signal VDDH_PG_H to reset the D flip-flop (DFF). The D flip-flop (DFF) will then reset the control signal VBIAS_PD from high to low, thus restoring the first LDO from its off state.

[0047] like Figure 2 As shown, the LDO ground short-circuit protection device mainly includes the following operating stages: (1) When the first LDO is working normally and there is no short circuit to ground, its output voltage is normal. At this time, the sampling voltage VSNS_VBIAS > the reference voltage VREF. The comparator CMP outputs the short circuit to ground indication signal VBIAS_SCP=0. The data output terminal of the D flip-flop DFF remains at the initial low level 0 established during the first power-on process of the high voltage domain power supply VDDH. During the initial power-on process of the high-voltage domain power supply VDDH: when the output voltage is less than the power-down switching threshold (VTH-1V), the power supply detection signal VDDH_PG_H = 0, the data output of the D flip-flop DFF is reset to 0, and the control signal VBIAS_PD = 0. During this period, the first LDO is turned on, and the high-voltage domain supply voltage rises with the rise of the high-voltage domain power supply VDDH. The sampling voltage VSNS_VBIAS rises proportionally with the high-voltage domain supply voltage. The short-circuit to ground indication signal VBIAS_SCP may always be 1 (if the sampling voltage VSNS_VBIAS < the reference voltage VREF), or it may be 1 first and then become 0 (if the initial sampling voltage VSNS_VBIAS < the reference voltage VREF, as the sampling voltage VSNS_VBIAS rises, the sampling voltage VSNS_VBIAS will exceed the reference voltage VREF). Even if the short-circuit to ground indication signal VBIAS_SCP transitions from 1 to 0, because it is a falling edge, it will not trigger a change in the state of the control signal VBIAS_PD at the data output terminal of the D flip-flop DFF. The control signal VBIAS_PD remains 0 during this period. When the output voltage is greater than the power-on toggle threshold VTH, the power supply detection signal VDDH_PG_H = 1, the D flip-flop DFF is released from reset and works normally. At this time, the output voltage of the first LDO has basically stabilized, the sampling voltage VSNS_VBIAS is greater than the reference voltage VREF, the short-circuit to ground indication signal VBIAS_SCP = 0, the clock input terminal of the D flip-flop DFF remains 0, and no rising edge occurs, so the data output terminal of the D flip-flop DFF remains 0, and the control signal VBIAS_PD remains 0.

[0048] 2. When the first LDO experiences a short circuit to ground: The output voltage drops instantaneously, the sampling voltage VSNS_VBIAS < the reference voltage VREF, and the short-circuit-to-ground indicator signal VBIAS_SCP jumps from 0 to 1. The D flip-flop (DFF) triggers a high-level signal 1P5V_TIEH at the sampling data input terminal via the rising edge of the short-circuit-to-ground indicator signal VBIAS_SCP, thereby causing the control signal VBIAS_PD = 1. This control signal will turn off the first LDO. After the first LDO is turned off, the sampling voltage VSNS_VBIAS of the voltage sampling module is less than the reference voltage VREF, and the short-circuit-to-ground indicator signal VBIAS_SCP will remain at 1 (since the clock input terminal of the D flip-flop (DFF) is always 1 at this time, there is no rising edge from 0 to 1). Therefore, the control signal VBIAS_PD will remain locked at 1, and the first LDO will remain locked in the off state. The control signal VBIAS_PD turns on the switching transistor Mn6 between the gate of the power MOSFET in the first LDO and the high-voltage power supply VDDH, and turns off the power MOSFET, thereby disconnecting the output current path to ground of the high-voltage power supply VDDH, thus protecting the power MOSFET of the first LDO when short-circuited to ground.

[0049] 3. After manually troubleshooting and clearing the short-circuit fault to ground, since the first LDO was previously turned off, the short-circuit indication signal VBIAS_SCP remains at 1, and the control signal VBIAS_PD also remains at 1. To ensure that the first LDO can resume operation after the short-circuit fault to ground is cleared, the high-voltage power supply VDDH needs to be powered off and then on. 4. The process of powering down the high-voltage domain power supply VDDH: VDDH begins to decrease. When the output voltage is less than the power-down threshold VTH-1V, the power supply monitoring signal VDDH_PG_H will jump from 1 to 0. At this time, the D flip-flop DFF will be reset, and its data output terminal will be reset to 0. The control signal VBIAS_PD will then jump from 1 to 0, and the first LDO will be turned on. However, since the high-voltage domain power supply VDDH has already been powered down, the output of the first LDO will gradually decrease to 0V following the power-down of the high-voltage domain power supply VDDH. 5. Subsequently, the high-voltage domain power supply VDDH is powered on: During this process, the high-voltage domain power supply VDDH will gradually increase. When the output voltage is less than the power-on switching threshold VTH, the power supply detection signal VDDH_PG_H = 0, the D flip-flop DFF is in the reset state, the control signal VBIAS_PD = 0, and the first LDO remains on. The first LDO follows the rise of the high-voltage domain power supply VDDH and establishes the output voltage. The high-voltage domain power supply VDDH continues to increase. When the output voltage is greater than the power-on switching threshold VTH, the voltage monitoring signal VDDH_PG_H jumps from 0 to 1. At this time, the D flip-flop DFF works normally. Since the ground short-circuit fault has been manually checked and resolved at this time, (if the sampling signal VSNS_VBIAS < the reference signal VREF, the ground short-circuit indicator signal VBIAS_SCP = 1, which is consistent with the previous state. There is no rising edge, and the state of the control signal VBIAS_PD at the data output terminal of the D flip-flop DFF will not change, that is, it will continue to remain at 0; if the sampling signal VSNS > the reference voltage VREF, the ground short-circuit indicator signal VBIAS_SCP changes from 1 to 0, which is a falling edge, and the state of the control signal VBIAS_PD at the data output terminal of the D flip-flop DFF will not change, that is, it will continue to remain at 0) therefore, during the power-on process of the high-voltage domain power supply VDDH, the control signal will continue to remain at 0, and the first LDO will start normally and stably establish the high-voltage domain power supply voltage during the power-on process.

[0050] The LDO ground short-circuit protection device proposed in this invention can effectively detect LDO ground short circuits and cut off the fault when a ground short circuit occurs. This device does not require any clock signal generation circuit, delay circuit, or clock synchronization digital circuit processing. It uses a D flip-flop to generate a shutdown signal triggered by the rising edge of the generated ground short-circuit indication signal. The sampling is implemented using a pure analog circuit, making it simple, practical, small in size, and low in power consumption. After a ground short circuit occurs, the fault can be manually cleared. By powering down and up the high-voltage power supply, the DFF is reset, restoring the first LDO to normal operation. No additional reset control signal or reset pin is required, resulting in high circuit reliability and safety.

[0051] For those skilled in the art, the specific meanings of the above terms in this invention can be understood according to the specific circumstances; the accompanying drawings in the embodiments are used to clearly and completely describe the technical solutions in the embodiments of this invention. Obviously, the described embodiments are some embodiments of this invention, but not all embodiments. Generally, the components of the embodiments of this invention described and shown in the accompanying drawings can be arranged and designed in various different configurations.

[0052] Although embodiments of this application have been shown and described above, it is understood that the above embodiments are exemplary and should not be construed as limiting this application. Those skilled in the art can make changes, modifications, substitutions and variations to the above embodiments within the scope of this application.

Claims

1. An LDO short-to-ground protection device, characterized by, The application relates to a power supply circuit, which comprises: a first LDO for converting the voltage output by a high-voltage domain power supply into a stable high-voltage domain supply voltage and outputting the same; a voltage sampling module for sampling the high-voltage domain supply voltage and generating a sampling voltage; a bandgap reference source for generating a reference voltage; a ground short circuit detection and control module for judging whether the first LDO generates a ground short circuit according to the reference voltage and the sampling voltage and generating a control signal for controlling the first LDO to be turned off or turned on.

2. The LDO short-to-ground protection device of claim 1, wherein, The application further comprises a power supply detection module for detecting whether the high-voltage power supply works stably and outputting a power supply detection signal; the power supply detection signal is used for controlling the ground short circuit detection and control module to be reset; the ground short circuit detection and control module always outputs the control signal for turning on the output of the first LDO in the reset state.

3. The LDO short-to-ground protection device of claim 2, wherein, The ground short circuit detection and control module comprises a comparator and a D flip-flop, wherein, the comparator has a first input end, a second input end and an output end; the first input end of the comparator receives the reference voltage; the second input end of the comparator receives the sampling voltage; the comparator compares the reference voltage and the sampling voltage and outputs a ground short circuit indication signal through the output end; the D flip-flop has a data input end, a clock input end, a reset end and a data output end; the data input end of the D flip-flop receives a high-level signal; the clock input end of the D flip-flop receives the ground short circuit indication signal; the reset end of the D flip-flop receives the power supply detection signal; and the data output end of the D flip-flop outputs the control signal.

4. The LDO short-to-ground protection device of claim 2, wherein, The power supply detection module outputs a high-level power supply detection signal when the voltage output by the high-voltage power supply is greater than a power-on flip threshold value; and outputs a low-level power supply detection signal when the voltage output by the high-voltage power supply is less than a power-off flip threshold value; the power-on flip threshold value is greater than the power-off flip threshold value.

5. The LDO short-to-ground protection device of claim 3, wherein, In the ground short circuit detection and control module, when the sampling voltage received by the comparator is less than the reference voltage, it indicates that the first LDO generates a ground short circuit, and the output end outputs a high-level ground short circuit indication signal; otherwise, it indicates that the first LDO works normally, and the output end outputs a low-level ground short circuit indication signal.

6. The LDO short-to-ground protection device according to claim 3 or 5, characterized in that In the ground short circuit detection and control module, when the reset end of the D flip-flop receives a low-level power supply detection signal, the D flip-flop is reset, and the data output end outputs a low-level control signal; when the reset end of the D flip-flop receives a high-level power supply detection signal, the D flip-flop monitors the received ground short circuit indication signal in real time, and when the ground short circuit indication signal changes from a low level to a high level, the data output end outputs a high-level control signal; otherwise, the previous state is maintained.

7. The LDO short-to-ground protection device of claim 1, wherein, The first LDO normally outputs the high-voltage domain supply voltage when the first LDO receives a low-level control signal; and stops outputting the high-voltage domain supply voltage when the first LDO receives a high-level control signal.

8. The LDO short-to-ground protection device of claim 1, wherein, The voltage sampling module comprises a first resistor and a second resistor; the first end of the first resistor receives the high-voltage domain supply voltage output by the first LDO; the second end of the first resistor is grounded through the second resistor; and the common node of the first resistor and the second resistor outputs the sampling voltage.

9. The LDO short-to-ground protection device of claim 1, wherein, The first LDO comprises a current mirror bias circuit, a switch control circuit and a power MOS tube, the current mirror bias circuit is used to provide a level conversion function for the switch control circuit, and convert a voltage domain of a control signal into a same voltage domain as the power MOS tube; a first end of the power MOS tube is connected with a high voltage domain power supply, a second end of the power MOS tube is used as an output end of the first LDO, a control end of the power MOS tube receives a switch signal output by the switch control circuit, the switch control circuit is used to receive a control signal and output a corresponding switch signal to control the power MOS tube to be turned off or turned on according to a state of the control signal, wherein when the control signal is at a high level, the power MOS tube is turned off; and when the control signal is at a low level, the power MOS tube is turned on.

10. The LDO short-to-ground protection device of claim 1, wherein, The second LDO is further included, and is used to convert a voltage output by a low voltage domain power supply and supply the converted voltage to a band gap reference source and a ground short circuit detection and control module respectively.

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