Driving circuit of lifting table motor

Abstract

The invention discloses a driving circuit of a lifting table motor. The driving circuit comprises an H-bridge motor driving unit, a left half-bridge driving unit, a right half-bridge driving unit, an enabling circuit and a PWM signal output unit. The left upper arm input end of the H-bridge motor driving unit is provided with a first bootstrap boost circuit, and the right upper arm input end of the H-bridge motor driving unit is provided with a second bootstrap boost circuit; one input end of the left bridge upper arm driving module is connected with the PWM signal output unit through a first signal reverse module, and one input end of the right bridge upper arm driving module is connected with the PWM signal output unit through a NOT gate circuit and a second signal reverse module. The output end of the second bootstrap boost circuit is connected with the right upper arm of the H-bridge motor driving unit through the second bootstrap boost circuit; the input end of the right bridge lower arm driving module is connected with the output end of the NOT gate circuit and the power supply VCC, and the output end of the right bridge lower arm driving module is connected with the right lower arm of the H bridge motor driving unit. The device has the characteristics of simple structure, small size, reliable performance, high applicability and the like.

Description

Technical Field

[0001] This invention relates to drive circuits, and more specifically to a drive circuit for a height-adjustable table motor. Background Technology

[0002] Height-adjustable desks, by adjusting their height to suit the needs of people of different heights and in different situations, are widely used in offices, homes, hospitals, and industries. The core mechanism of a height-adjustable desk is its motor control. Existing motor controllers for height-adjustable desks mainly employ relay bridge + MOSFET control and MOSFET bridge control methods. These methods use dead-time circuits and NAND gates to achieve motor speed control and forward / reverse rotation. Both of these control methods typically require multiple PWM signals to achieve motor speed control and forward / reverse rotation, resulting in a complex control circuit structure and a large motor size. Therefore, simplifying the structure of the motor drive control system for height-adjustable desks and effectively reducing its size has become an objective requirement. Summary of the Invention

[0003] This invention provides a drive circuit for a height-adjustable desk motor, which solves the problems of complex structure and large size of existing height-adjustable desk motor drive circuits.

[0004] The present invention provides a driving circuit for a height-adjustable desk motor. The driving circuit includes an H-bridge motor driving unit, a left half-bridge driving unit and a right half-bridge driving unit respectively connected to the H-bridge motor driving unit, an enable circuit and a PWM signal output unit respectively connected to the input terminals of the left half-bridge driving unit and the right half-bridge driving unit. The upper left arm input terminal of the H-bridge motor drive unit is provided with a first bootstrap boost circuit for increasing the power supply voltage of the upper left arm input terminal, and the upper right arm input terminal is provided with a second bootstrap boost circuit for increasing the power supply voltage of the upper right arm input terminal. The left half-bridge drive unit includes a left bridge upper arm drive module and a left bridge lower arm drive module. One input terminal of the left bridge upper arm drive module is connected to the PWM signal output unit through a first signal inversion module, and its other input terminal is connected to the power supply VCC. Its output terminal is connected to the left upper arm of the H-bridge motor drive unit. The input terminal of the left bridge lower arm drive module is connected to the PWM signal output unit and the power supply VCC. Its output terminal is connected to the left lower arm of the H-bridge motor drive unit. The input terminal of the right half-bridge drive unit is connected to the NOT gate circuit. It includes a right upper arm drive module and a right lower arm drive module. One input terminal of the right upper arm drive module is connected to the output terminal of the NOT gate circuit through a second signal inverting module, and its other input terminal is connected to the power supply VCC. Its output terminal is connected to the right upper arm of the H-bridge motor drive unit through a second bootstrap boost circuit. The input terminal of the right lower arm drive module is connected to the output terminal of the NOT gate circuit and the power supply VCC, respectively. Its output terminal is connected to the right lower arm of the H-bridge motor drive unit.

[0005] The H-bridge motor drive unit includes an eighth MOSFET connected to the left upper arm drive module, a twenty-fourth MOSFET connected to the left lower arm drive module, a seventh MOSFET Q7 connected to the right upper arm drive module, and a twenty-third MOSFET Q23 connected to the right lower arm drive module. The eighth MOSFET Q8 and the twenty-third MOSFET Q23 form a forward loop, and the seventh MOSFET Q7 and the twenty-fourth MOSFET Q24 form a reverse loop.

[0006] The first bootstrap boost circuit includes a first diode D1 and a first capacitor C1. The anode of the first diode D1 is connected to the enable circuit, and its cathode is connected to one end of the first capacitor C1. The other end of the first capacitor C1 is connected to the source of the eighth MOSFET Q8. The second bootstrap voltage boosting circuit includes a second diode D2 and a second capacitor C2. The anode of the second diode D2 is connected to the enable circuit, and its cathode is connected to one end of the second capacitor C2. The other end of the second capacitor C2 is connected to the source of the seventh MOSFET Q7.

[0007] The left bridge upper arm drive module and the right bridge upper arm drive module have a symmetrical structure. The left bridge upper arm drive module includes a first BUFF circuit and a first delay circuit. The input terminal of the first BUFF circuit is connected to the output terminal of the first delay circuit, and its output terminal is connected to the eighth MOS transistor Q8. The input terminal of the first delay circuit is connected to the power supply VCC and the output terminal of the first signal inversion module, respectively. The left bridge lower arm drive module and the right bridge lower arm drive module have a symmetrical structure. The left bridge lower arm drive module includes a second BUFF circuit and a second delay circuit. The structure of the second BUFF circuit is the same as that of the first BUFF circuit. The structure of the second delay circuit is the same as that of the first delay circuit. The input terminal of the second BUFF circuit is connected to the output terminal of the second delay circuit, and its output terminal is connected to the 24th MOS transistor Q24. The input terminal of the second delay circuit is connected to the PWM signal output unit.

[0008] Further, the first BUFF circuit includes a fifth MOSFET Q5, a sixth MOSFET Q6, a twelfth MOSFET Q12, and a thirteenth MOSFET Q13. The fifth MOSFET Q5 and the sixth MOSFET Q6 are P-type MOSFETs, and the twelfth MOSFET Q12 and the thirteenth MOSFET Q13 are N-type MOSFETs. The gate of the fifth MOSFET Q5 and the gate of the twelfth MOSFET Q12 are respectively connected to the output terminal of the first delay circuit. The source of the fifth MOSFET Q5 and the source of the sixth MOSFET Q6 are respectively connected to the power supply VCC, and their drains are respectively connected to the gate of the sixth MOSFET Q6, the drain of the twelfth MOSFET Q12, and the gate of the thirteenth MOSFET Q13. The drain of the sixth MOSFET Q6 and the drain of the thirteenth MOSFET Q13 are respectively connected to the gate of the eighth MOSFET Q8, and the source of the twelfth MOSFET Q12 and the source of the thirteenth MOSFET Q13 are respectively connected to the source of the eighth MOSFET Q8.

[0009] Further, the first delay circuit includes a third capacitor C3, a fifth resistor R5, a ninth resistor R9, and a seventeenth MOSFET Q17. One end of the third capacitor C3 and one end of the fifth resistor R5 are respectively connected to the power supply VCC and the output terminal of the first signal inverting module. The other end of the third capacitor C3 is respectively connected to one end of the ninth resistor R9 and the gate of the seventeenth MOSFET Q17. The other end of the fifth resistor R5 is respectively connected to the drain of the seventeenth MOSFET Q17, the gate of the fifth MOSFET Q5, and the gate of the seventh MOSFET Q7. The other end of the ninth resistor R9 and the source of the seventeenth MOSFET Q17 are respectively connected to the source of the eighth MOSFET Q8.

[0010] The NOT gate circuit includes an eleventh MOSFET Q11 and an eighteenth MOSFET Q18. The gates of the eleventh MOSFET Q11 and the eighteenth MOSFET Q18 are respectively connected to the PWM signal output unit. The drains of the eleventh MOSFET Q11 and the eighteenth MOSFET Q18 are respectively connected to the input terminals of the second signal inverting module and the right bridge lower arm drive module. The source of the eleventh MOSFET Q11 is connected to the power supply VCC, and the source of the eighteenth MOSFET Q18 is grounded.

[0011] The first signal inversion module includes a third resistor R3 and a sixteenth MOSFET Q16. One end of the third resistor R3 is connected to the power supply VCC, and the other end is connected to the drain of the sixteenth MOSFET Q16. The gate of the sixteenth MOSFET Q16 is connected to the PWM signal output unit, and its source is grounded. The second signal inversion module includes a fourth resistor R4 and a fifteenth MOSFET Q15. One end of the fourth resistor R4 is connected to the power supply VCC, and the other end is connected to the drain of the fifteenth MOSFET Q15 and the input terminal of the right bridge upper arm drive module, respectively. The gate of the fifteenth MOSFET Q15 is connected to the output terminal of the NOT gate circuit, and its source is grounded.

[0012] When the PWM signal is low, the eighth MOSFET Q8 and the twenty-third MOSFET Q23 are turned on, the seventh MOSFET Q7 and the twenty-fourth MOSFET Q24 are turned off, and the eighth MOSFET Q8 and the twenty-third MOSFET Q23 form a circuit. When the PWM signal is high, the eighth MOSFET Q8 and the twenty-third MOSFET Q23 are turned off, while the seventh MOSFET Q7 and the twenty-fourth MOSFET Q24 are turned on, forming a circuit.

[0013] Furthermore, the forward and reverse rotation control and speed control of the motor are achieved by adjusting the duty cycle of the PWM signal output by the PWM output signal unit; When the duty cycle of the PWM signal is greater than 50%, the seventh MOSFET Q7 and the twenty-fourth MOSFET Q24 form a circuit, and the motor rotates in the forward direction. When the duty cycle of the PWM signal is 100%, the motor rotates in the forward direction at the fastest speed. When the duty cycle of the PWM signal is less than 50%, the eighth MOSFET Q8 and the twenty-third MOSFET Q23 form a circuit, and the motor reverses. The motor reverses fastest when the duty cycle of the PWM signal is 0. The motor stops rotating when the duty cycle of the PWM signal is 50%.

[0014] The beneficial effects of this invention are as follows: 1) By setting a first signal inversion module at the input end of the left bridge upper arm drive module, the input signals of the left bridge upper arm drive module and the left bridge lower arm drive module are reversed. By setting a NOT gate circuit at the input end of the right half-bridge drive unit, the input signals of the left half-bridge drive unit and the right half-bridge drive unit are reversed. Furthermore, by setting a second signal inversion module at the input end of the right bridge upper arm drive module, the input signals of the right bridge upper arm drive module and the right bridge lower arm drive module are reversed. Thus, the bipolar control mode of the motor can be realized with only one PWM signal. The forward / reverse control of the motor can be realized by adjusting the duty cycle of the PWM signal. At the same time, the speed of the motor can also be adjusted. It is not only stable and reliable in performance, but also simple in structure and small in size.

[0015] 2) By setting a first bootstrap voltage boosting circuit at the upper left arm input terminal and a second bootstrap voltage boosting circuit at the upper right arm input terminal of the H-bridge motor drive unit, the power supply voltage at the upper left and upper right arm input terminals can be increased to drive the motor.

[0016] 3) By setting a first delay circuit at the input of the first BUFF circuit, the delay time of the drive signal can be controlled by adjusting the capacitance value of the third capacitor C3 and the resistance value of the ninth resistor R9 in the differentiating circuit. This avoids the upper and lower half-bridges of the H-bridge motor drive unit from being turned on at the same time, realizes the dead time function between the half-bridge switching transistors, and further ensures the reliability of the circuit. Attached Figure Description

[0017] Figure 1 This is a schematic diagram of the structure of the present invention.

[0018] Figure 2 This is a schematic diagram of the structure of the left half-bridge drive unit and the right half-bridge drive unit of the present invention.

[0019] Figure 3 This is the circuit diagram of the present invention.

[0020] Figure 4 This is a circuit diagram of the enabling circuit of the present invention.

[0021] Figure 5 This is a diagram of the input and output signals of the first delay circuit of the present invention.

[0022] In the diagram, 10 is the H-bridge motor drive unit, 20 is the left half-bridge drive unit, 21 is the left bridge upper arm drive module, 211 is the first BUFF circuit, 212 is the first delay circuit, 22 is the left bridge lower arm drive module, 221 is the second BUFF circuit, 222 is the second delay circuit, 30 is the right half-bridge drive unit, 31 is the right bridge upper arm drive module, 311 is the third BUFF circuit, 312 is the third delay circuit, 32 is the right bridge lower arm drive module, 321 is the fourth BUFF circuit, 322 is the fourth delay circuit, 40 is the first bootstrap boost circuit, 50 is the second bootstrap boost circuit, 60 is the enable circuit, 70 is the PWM signal output unit, 81 is the first signal inversion module, 82 is the second signal inversion module, and 90 is the NOT gate circuit. Detailed Implementation

[0023] The technical solution of the present invention will now be clearly and completely described with reference to the accompanying drawings and specific embodiments. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0024] Please see Figure 1 The present invention provides a drive circuit for a height-adjustable desk motor, comprising an H-bridge motor drive unit 10, a left half-bridge drive unit 20, a right half-bridge drive unit 30, a first bootstrap boost circuit 40, a second bootstrap boost circuit 50, an enable circuit 60, and a PWM signal output unit 70. This drive circuit is used to control the motor speed and realize the motor's forward and reverse rotation functions. This drive circuit is not limited to motor drive circuits; it can also be used in other drive circuits, such as DC switching power supply MOS drive circuits, demonstrating strong versatility.

[0025] like Figure 1 , Figure 3As shown, the H-bridge motor drive unit 10 includes a seventh MOSFET Q7, an eighth MOSFET Q8, a twenty-third MOSFET Q23, and a twenty-fourth MOSFET Q24. The seventh MOSFET Q7 is located in the upper right arm, the eighth MOSFET Q8 in the upper left arm, the twenty-third MOSFET Q23 in the lower right arm, and the twenty-fourth MOSFET Q24 in the lower left arm. The eighth MOSFET Q8 and the twenty-third MOSFET Q23 form a forward loop, and the seventh MOSFET Q7 and the twenty-fourth MOSFET Q24 form a reverse loop. In this embodiment, the seventh MOSFET Q7, the eighth MOSFET Q8, the twenty-third MOSFET Q23, and the twenty-fourth MOSFET Q24 are all N-type MOSFETs. Specifically, the gate of the eighth MOSFET Q8 is connected to the upper left bridge drive module 21, its source is connected to one input terminal of the motor, and its drain is connected to the power supply VIN. The gate of the seventh MOSFET Q7 is connected to the upper right bridge drive module 31, its source is connected to the other input terminal of the motor, and its drain is connected to the power supply VIN. The gate of the twenty-fourth MOSFET Q24 is connected to the left bridge lower arm drive module 22, its source is connected to ground PGND, and its drain is connected to one input terminal of the motor. The gate of the twenty-third MOSFET Q23 is connected to the right bridge lower arm drive module 32, its source is connected to ground PGND, and its drain is connected to the other input terminal of the motor.

[0026] like Figure 1 , Figure 3As shown, the left half-bridge drive unit 20 is located to the left of the H-bridge motor drive unit 10, and it is used to control the switching of the upper left arm and the lower left arm of the H-bridge motor drive unit 10. The right half-bridge drive unit 30 is symmetrical to the left half-bridge drive unit 20 and is located to the right of the H-bridge motor drive unit 10, and it is used to control the switching of the upper right arm and the lower right arm of the H-bridge motor drive unit 10. The left half-bridge drive unit 20 includes a left upper arm drive module 21 and a left lower arm drive module 22. The left upper arm drive module 21 delays the time of the upper left arm drive signal and shapes and enhances the drive signal to drive the upper left arm of the H-bridge motor drive unit 10. The left lower arm drive module 22 delays the time of the lower left arm drive signal and shapes and enhances the drive signal to drive the lower left arm of the H-bridge motor drive unit 10. One input terminal of the left upper bridge drive module 21 is connected to the PWM signal output unit 70 via the first signal inverting module 81, and its other input terminal is connected to the power supply VCC. Its output terminal is connected to the left upper arm of the H-bridge motor drive unit 10. The input terminal of the left lower bridge drive module 22 is connected to the PWM signal output unit 70 and the power supply VCC, and its output terminal is connected to the left lower arm of the H-bridge motor drive unit 10. The right half-bridge drive unit 30 includes a right upper bridge drive module 31 and a right lower bridge drive module 32. One input terminal of the right upper bridge drive module 31 is connected to the PWM signal output unit 70 via the NOT gate circuit 90 and the second signal inverting module 82, and its other input terminal is connected to the power supply VCC. Its output terminal is connected to the right upper arm of the H-bridge motor drive unit 10 via the second bootstrap boost circuit 50. The input terminals of the right lower bridge drive module 32 are connected to the output terminal of the NOT gate circuit 90 and the power supply VCC, respectively, and its output terminal is connected to the right lower arm of the H-bridge motor drive unit 10.

[0027] like Figure 2 , Figure 3As shown, the left upper arm drive module 21 drives the left upper arm of the H-bridge motor drive unit 10, and includes a first BUFF circuit 211 and a first delay circuit 212. The input terminal of the first BUFF circuit 211 is connected to the output terminal of the first delay circuit 212, and its output terminal is connected to the eighth MOSFET. The input terminal of the first delay circuit 212 is connected to the power supply VCC and the output terminal of the first signal inversion module 81, respectively. The left lower arm drive module 22 drives the left lower arm of the H-bridge motor drive unit 10, and includes a second BUFF circuit 221 and a second delay circuit 222. The structure of the second BUFF circuit 221 is the same as that of the first BUFF circuit 211, and the structure of the second delay circuit 222 is the same as that of the first delay circuit 212. The input terminal of the second BUFF circuit 221 is connected to the output terminal of the second delay circuit 222, and its output terminal is connected to the twenty-fourth MOSFET. The input terminal of the second delay circuit 222 is connected to the PWM signal output unit 70. The right upper arm drive module 31 is structurally symmetrical to the left upper arm drive module 21 and is used to drive the right upper arm of the H-bridge motor drive unit 10. It includes a third BUFF circuit 311 and a third delay circuit 312. The right lower arm drive module 32 is structurally symmetrical to the left lower arm drive module 22 and is used to drive the right lower arm of the H-bridge motor drive unit 10. It includes a fourth BUFF circuit 321 and a fourth delay circuit 322.

[0028] like Figure 2 , Figure 3 As shown, the first BUFF circuit 211 includes a fifth MOSFET Q5, a sixth MOSFET Q6, a twelfth MOSFET Q12, and a thirteenth MOSFET Q13. These four transistors form two sets of MOS NOT gates, which do not change the direction of the drive signal but achieve signal shaping and enhance the drive capability. Specifically, the fifth MOSFET Q5 and the sixth MOSFET Q6 are P-type MOSFETs, while the twelfth MOSFET Q12 and the thirteenth MOSFET Q13 are N-type MOSFETs. Specifically, the gate of the fifth MOSFET Q5 and the gate of the twelfth MOSFET Q12 are connected to the output terminal of the first delay circuit 212, respectively. The source of the fifth MOSFET Q5 and the source of the sixth MOSFET Q6 are connected to the power supply VCC, respectively, and their drains are connected to the gate of the sixth MOSFET Q6, the drain of the twelfth MOSFET Q12, and the gate of the thirteenth MOSFET Q13, respectively. The drains of the sixth MOSFET Q6 and the thirteenth MOSFET Q13 are connected to the gate of the eighth MOSFET Q8, respectively. The sources of the twelfth MOSFET Q12 and the thirteenth MOSFET Q13 are connected to the source of the eighth MOSFET Q8, respectively. Figure 3 As shown, the second BUFF circuit 221 has the same structure as the first BUFF circuit 211.

[0029] like Figure 2 , Figure 3 As shown, the first delay circuit 212 is located at the input terminal of the first BUFF circuit 211. It includes a third capacitor C3, a fifth resistor R5, a ninth resistor R9, and a seventeenth MOSFET Q17, used to implement dead-time control of the upper and lower MOSFET drives in the H-bridge motor drive unit 10. One end of the third capacitor C3 and one end of the fifth resistor R5 are connected to the power supply VCC and the output terminal of the first signal inverting module 81, respectively. The other end of the third capacitor C3 is connected to one end of the ninth resistor R9 and the gate of the seventeenth MOSFET Q17. The other end of the fifth resistor R5 is connected to the drain of the seventeenth MOSFET Q17, the gate of the fifth MOSFET Q5, and the gate of the seventh MOSFET Q7, respectively. The other end of the ninth resistor R9 and the source of the seventeenth MOSFET Q17 are connected to the source of the eighth MOSFET Q8. Figure 3 As shown, the structure of the second delay circuit 222 is the same as that of the first delay circuit 212.

[0030] Specifically, such as Figure 2 , Figure 3 , Figure 5 As shown, the third capacitor C3 and the ninth resistor R9 form a differentiating circuit. The input signal V1 of the first delay circuit 212 is delayed by the differentiating circuit to control the conduction time of the seventeenth MOSFET Q17. The delay time is adjusted based on the values ​​of the third capacitor C3 and the ninth resistor R9. After the delay, the following is obtained: Figure 5 The output signal V3 of the first delay circuit 212 shown can effectively form a dead zone, preventing the falling segment of the previous cycle from coinciding with the rising segment of the current cycle. Similarly, by adjusting the values ​​of the fifth capacitor C5 and the fifteenth resistor R15, the conduction time of the thirtieth MOSFET Q30 can be controlled to delay the output signal of the second delay circuit 222, thus forming a dead zone. By adjusting the values ​​of the fourth capacitor C4 and the tenth resistor R10, the conduction time of the fourteenth MOSFET Q14 can be controlled to delay the output signal of the third delay circuit 312, thus forming a dead zone. By adjusting the values ​​of the sixth capacitor C6 and the sixteenth resistor R16, the conduction time of the twenty-ninth MOSFET Q29 can be controlled to delay the output signal of the fourth delay circuit 322, thus forming a dead zone, thereby realizing the dead zone function between the switches of the H-bridge.

[0031] like Figure 1 , Figure 3As shown, a first bootstrap boost circuit 40 is provided at the input terminal of the upper left arm of the H-bridge motor drive unit 10 to increase the power supply voltage at the input terminal of the upper left arm. This first bootstrap boost circuit 40 includes a first diode D1 and a first capacitor C1. The anode of the first diode D1 is connected to the enable circuit 60, its cathode is connected to one end of the first capacitor C1, and the other end of the first capacitor C1 is connected to the source of the eighth MOSFET Q8. When the eighth MOSFET Q8 is off and the twenty-fourth MOSFET Q24 is on, the voltage across the first capacitor C1 is equal to the power supply VCC (ignoring the voltage drop of the first diode D1). When the twenty-fourth MOSFET Q24 is off and the eighth MOSFET Q8 is on, the voltage across the first capacitor C1 is equal to the power supply VIN voltage plus the power supply VCC voltage, thus providing the voltage source to drive the upper left half-bridge.

[0032] like Figure 1 , Figure 3 As shown, a second bootstrap boost circuit 50 is provided at the upper right arm input terminal of the H-bridge motor drive unit 10 to increase the power supply voltage at the upper right arm input terminal. This second bootstrap boost circuit 50 includes a second diode D2 and a second capacitor C2. The anode of the second diode D2 is connected to an enable circuit, and its cathode is connected to one end of the second capacitor C2. The other end of the second capacitor C2 is connected to the source of the seventh MOSFET Q7. When the seventh MOSFET Q7 is off and the twenty-third MOSFET Q23 is on, the voltage across the second capacitor C2 is equal to the power supply VCC (ignoring the voltage drop of the second diode D2). When the twenty-third MOSFET Q23 is off and the seventh MOSFET Q7 is on, the voltage across the second capacitor C2 is equal to the power supply VIN voltage plus the power supply VCC voltage, thus providing a voltage source to drive the upper right half-bridge.

[0033] like Figure 1 , Figure 3 and Figure 4 As shown, the input terminals of the left half-bridge drive unit 20 and the right half-bridge drive unit 30 are respectively connected to the enable circuit 60, which provides power supply VCC to the left half-bridge drive unit 20 and the right half-bridge drive unit 30. The enable circuit 60 includes a first MOSFET Q1, a second MOSFET Q2, a first resistor R1, and a second resistor R2. The source of the first MOSFET Q1 is connected to the power supply VDD and one end of the first resistor R1, while its gate is connected to the other end of the first resistor R1 and the drain of the second MOSFET. Its drain is connected to the power supply VCC. The gate of the second MOSFET Q2 is connected to the enable signal and one end of the second resistor R2, while its source and the other end of the second resistor R2 are grounded. When the enable signal output by the enable circuit 60 is high, the drive circuit is enabled; when the enable signal output by the enable circuit 60 is low, the power supply VCC is turned off, shutting down the entire drive circuit and achieving low standby power consumption.

[0034] Because bipolar control mode can operate in both forward and reverse directions, has fast start-up, high speed regulation accuracy, good dynamic performance, small speed regulation static error, and a large speed regulation range, it can accelerate, decelerate, brake, and reverse. It can provide reverse torque when the load exceeds the set speed and overcome the static friction of the motor bearings to generate very low speeds. Since the armature voltage polarity alternates between positive and negative, to achieve bipolar control, two sets of complementary PWM signals are needed to simultaneously control four MOSFETs. In this embodiment, bipolar control can be achieved using only one PWM signal. Specifically, at the input of the left upper arm drive module 21, the PWM signal is inverted into a complementary PWM' signal via the first signal inverting module 81, thus making the input signals of the left upper arm drive module 21 opposite to those of the left lower arm drive module 22. A NOT gate circuit 90 is set at the input of the right half-bridge drive unit 30, which inverts the PWM signal into a complementary PWM' signal, thus making the input signals of the left half-bridge drive unit 20 opposite to those of the right half-bridge drive unit 30. Meanwhile, at the input end of the right upper arm drive module 31, the PWM signal is inverted into a PWM signal through the second signal inversion module 82, so that the input signal of the right upper arm drive module 31 is opposite to the input signal of the right lower arm drive module 32, thereby realizing bipolar control with a single PWM signal.

[0035] Specifically, such as Figure 1 , Figure 3 As shown, one input terminal of the left bridge upper arm drive module 21 is connected to the PWM signal output unit 70 through the first signal inversion module 81, which inverts the PWM signal output by the PWM signal output unit 70 into a complementary PWM signal. The first signal inversion module 81 includes a third resistor R3 and a sixteenth MOSFET Q16. One end of the third resistor R3 is connected to the power supply VCC, and the other end is connected to the drain of the sixteenth MOSFET Q16. The gate of the sixteenth MOSFET Q16 is connected to the PWM signal output unit 70, and its source is grounded.

[0036] like Figure 1 , Figure 3As shown, the input terminal of the right half-bridge drive unit is connected to the PWM signal output unit 70 via a NOT gate circuit 90. One input terminal of the right bridge upper arm drive module 31 is connected to the output terminal of the NOT gate circuit 90 via a second signal inverting module 82. The PWM signal output by the PWM signal output unit 70 is inverted into a PWM' signal by the NOT gate circuit 90. One path drives the right bridge lower arm drive module 32, and the other path is inverted again by the second signal inverting module 82 to drive the right bridge upper arm drive module 31. Specifically, the second signal inverting module 82 includes a fourth resistor R4 and a fifteenth MOSFET Q15. One end of the fourth resistor R4 is connected to the power supply VCC, and the other end is connected to the drain of the fifteenth MOSFET Q15 and the input terminal of the right bridge upper arm drive module 31. The gate of the fifteenth MOSFET Q15 is connected to the output terminal of the NOT gate circuit 90, and its source is grounded. The NOT gate circuit 90 includes an eleventh MOSFET and an eighteenth MOSFET. The gates of the eleventh MOSFET Q11 and the eighteenth MOSFET Q18 are connected to the PWM signal output unit 70, the drains of the eleventh MOSFET Q11 and the eighteenth MOSFET Q18 are connected to the input terminals of the second signal inversion module 82 and the right bridge lower arm drive module 32, the source of the eleventh MOSFET Q11 is connected to the power supply VCC, and the source of the eighteenth MOSFET Q18 is grounded.

[0037] Since the armature voltage polarity alternates between positive and negative, and in this embodiment only one PWM signal is used, PWM and PWM' are complementary channels. The two diagonal MOSFETs, namely the eighth MOSFET Q8 and the twenty-third MOSFET Q23, and the seventh MOSFET Q7 and the twenty-fourth MOSFET Q24, are simultaneously turned on and off. When the PWM period is T and the PWM high-level time is t1, then: Umotor=[t1 / T-(T-t1) / T]U DC Simplifying, we get: Umotor = (2α-1)U DC Where α is the duty cycle.

[0038] From the above formula, we can see that: When α > 50%, the motor rotates in the forward direction; When α < 50%, the motor reverses direction; When α = 50%, the motor stops rotating; When α=0, the motor reverses direction and reaches its highest speed; When α = 100%, the motor rotates forward and reaches its highest speed.

[0039] Therefore, by adjusting the duty cycle of the PWM input, the motor can be made to rotate forward and backward, and the motor speed can also be adjusted.

[0040] like Figure 1 , Figure 2 , Figure 3 and Figure 4 As shown, the working principle of this embodiment is as follows: When the enable signal output by the enable circuit 60 is high and the PWM signal output by the PWM signal output unit 70 is low, the PWM signal is inverted by the sixteenth MOSFET Q16 to obtain a high-level PWM' signal. After being delayed by the first delay circuit 212, the fifth MOSFET Q5 and the thirteenth MOSFET Q13 are turned off, while the twelfth MOSFET Q12 and the sixth MOSFET Q6 are turned on. The PWM' signal is output from the drain of the sixth MOSFET Q6 to the gate of the eighth MOSFET Q8, thereby driving the eighth MOSFET Q8 to turn on. The other path is delayed by the second delay circuit 222. After being delayed by the second delay circuit 222, the twenty-seventh MOSFET Q27 and the twenty-second MOSFET Q22 are turned off, while the twenty-first MOSFET Q21 and the twenty-eighth MOSFET Q28 are turned on. The PWM signal is output from the twenty-eighth MOSFET Q28 to the gate of the twenty-fourth MOSFET Q24. Since the PWM signal is low, the twenty-fourth MOSFET Q24 is turned off. Meanwhile, the PWM signal is inverted by NOT gate 90 to obtain a high-level PWM' signal. One path of the PWM' signal is delayed by the fourth delay circuit 322, causing the twentieth MOSFET Q20 and the twenty-fifth MOSFET Q25 to turn off, while the twenty-sixth MOSFET Q26 and the nineteenth MOSFET Q19 turn on. The PWM' signal is output from the drain of the nineteenth MOSFET Q19 to the gate of the twenty-third MOSFET Q23, thus driving Q23 to turn on. The other path of the PWM' signal is inverted by the fifteenth MOSFET Q15 to obtain a low-level PWM signal. After being delayed by the third delay circuit 312, the third MOSFET Q3 and the tenth MOSFET Q10 turn off, while the fourth MOSFET Q4 and the ninth MOSFET Q9 turn on. The PWM signal is output from the ninth MOSFET Q9 to the gate of the seventh MOSFET Q7. Since the PWM signal is low, the seventh MOSFET Q7 turns off. Therefore, when the PWM signal is low, the eighth MOSFET Q8 and the twenty-third MOSFET Q23 form a loop.

[0041] When the enable signal output by the enable circuit 60 is high and the PWM signal output by the PWM signal output unit 70 is high, one path of the PWM signal is inverted by the sixteenth MOSFET Q16 to obtain a low-level PWM' signal. After being delayed by the first delay circuit 212, the fifth MOSFET Q5 and the thirteenth MOSFET Q13 are turned on, while the twelfth MOSFET Q12 and the sixth MOSFET Q6 are turned off. The PWM' signal is output from the drain of the thirteenth MOSFET Q13 to the gate of the eighth MOSFET Q8. Since the PWM' signal is low, the eighth MOSFET Q8 is turned off. Another path is delayed by the second delay circuit 222, turning on the twenty-seventh MOSFET Q27 and the twenty-second MOSFET Q22, while the twenty-first MOSFET Q21 and the twenty-eighth MOSFET Q28 are turned off. The PWM signal is output from the twenty-second MOSFET Q22 to the gate of the twenty-fourth MOSFET Q24. Since the PWM signal is high, it drives the twenty-fourth MOSFET Q24 to turn on. Meanwhile, the PWM signal is inverted by NOT gate 90 to obtain a low-level PWM' signal. This PWM' signal is then delayed by the fourth delay circuit 322, turning on the twentieth MOSFET Q20 and the twenty-fifth MOSFET Q25, while turning off the twenty-sixth MOSFET Q26 and the nineteenth MOSFET Q19. The PWM' signal is output from the drain of the twenty-fifth MOSFET Q25 to the gate of the twenty-third MOSFET Q23. Since the PWM' signal is low, the twenty-third MOSFET Q23 is turned off. The other path of the PWM' signal is inverted by the fifteenth MOSFET Q15 to obtain a high-level PWM signal. After being delayed by the third delay circuit 312, the third MOSFET Q3 and the tenth MOSFET Q10 are turned on, while the fourth MOSFET Q4 and the ninth MOSFET Q9 are turned off. The PWM signal is output from the third MOSFET Q3 to the gate of the seventh MOSFET Q7. Since the PWM signal is high, it drives the seventh MOSFET Q7 to turn on. Therefore, when the PWM signal is high, the seventh MOSFET Q7 and the twenty-fourth MOSFET Q24 form a loop.

[0042] When the duty cycle of the PWM signal is greater than 50%, the high-level time of the PWM signal is longer than the low-level time, forming a circuit between the seventh MOSFET Q7 and the twenty-fourth MOSFET Q24, causing the motor to rotate forward. The motor reaches its fastest forward speed when the PWM signal duty cycle is 100%. When the duty cycle of the PWM signal is less than 50%, the high-level time of the PWM signal is shorter than the low-level time, forming a circuit between the eighth MOSFET Q8 and the twenty-third MOSFET Q23, causing the motor to rotate in reverse. The motor reaches its fastest reverse speed when the PWM signal duty cycle is 0. When the PWM signal duty cycle is equal to 50%, the motor stops rotating. Therefore, the forward and reverse rotation of the motor, as well as the speed adjustment, can be achieved by adjusting the duty cycle of the PWM signal.

[0043] When the enable signal output by enable circuit 60 is low, the power supply VCC is turned off, the entire drive circuit is shut down, and low standby power consumption is achieved.

[0044] In summary, the drive circuit of the height-adjustable table motor of the present invention can realize the bipolar control mode of the motor through a single PWM signal, and achieve forward / reverse control of the motor by adjusting the duty cycle of the PWM signal. Simultaneously, the motor speed can also be adjusted. It is not only stable and reliable in performance, but also simple in structure and small in size. On the other hand, by setting a first bootstrap boost circuit 40 at the left upper arm input terminal and a second bootstrap boost circuit 50 at the right upper arm input terminal of the H-bridge motor drive unit 10, the power supply voltage at the left and right upper arm input terminals can be increased, thereby driving the eighth MOSFET Q8 and the seventh MOSFET Q7 to switch on. Furthermore, by setting a first delay circuit 212 at the input terminal of the first BUFF circuit 211, the delay time of the drive signal can be controlled by adjusting the capacitance of the third capacitor C3 and the resistance of the ninth resistor R9 in the differentiating circuit. This avoids the simultaneous conduction of the upper and lower half-bridges of the H-bridge motor drive unit 10, realizing the dead-time function between the half-bridge switches and further ensuring the reliability of the circuit. The present invention can also be used in other drive circuits, such as DC power supplies, and has strong versatility.

[0045] Although the present invention has been disclosed through the above embodiments, the scope of protection of the present invention is not limited thereto. Any modifications or substitutions made to the above components without departing from the concept of the present invention shall fall within the scope of the claims of the present invention.

Claims

1. A drive circuit for a height-adjustable desk motor, characterized in that, The drive circuit includes an H-bridge motor drive unit, a left half-bridge drive unit and a right half-bridge drive unit respectively connected to the H-bridge motor drive unit, an enable circuit and a PWM signal output unit respectively connected to the input terminals of the left half-bridge drive unit and the right half-bridge drive unit. The upper left arm input terminal of the H-bridge motor drive unit is provided with a first bootstrap boost circuit for increasing the power supply voltage of the upper left arm input terminal, and the upper right arm input terminal is provided with a second bootstrap boost circuit for increasing the power supply voltage of the upper right arm input terminal. The left half-bridge drive unit includes a left bridge upper arm drive module and a left bridge lower arm drive module. One input terminal of the left bridge upper arm drive module is connected to the PWM signal output unit through a first signal inversion module, and its other input terminal is connected to the power supply VCC. Its output terminal is connected to the left upper arm of the H-bridge motor drive unit. The input terminal of the left bridge lower arm drive module is connected to the PWM signal output unit and the power supply VCC. Its output terminal is connected to the left lower arm of the H-bridge motor drive unit. The input terminal of the right half-bridge drive unit is connected to the NOT gate circuit. It includes a right upper arm drive module and a right lower arm drive module. One input terminal of the right upper arm drive module is connected to the output terminal of the NOT gate circuit through a second signal inverting module, and its other input terminal is connected to the power supply VCC. Its output terminal is connected to the right upper arm of the H-bridge motor drive unit through a second bootstrap boost circuit. The input terminal of the right lower arm drive module is connected to the output terminal of the NOT gate circuit and the power supply VCC, respectively. Its output terminal is connected to the right lower arm of the H-bridge motor drive unit.

2. The drive circuit for the height-adjustable table motor as described in claim 1, characterized in that, The H-bridge motor drive unit includes an eighth MOS transistor connected to the left upper arm drive module, a twenty-fourth MOS transistor connected to the left lower arm drive module, a seventh MOS transistor connected to the right upper arm drive module, and a twenty-third MOS transistor connected to the right lower arm drive module. The eighth MOS transistor and the twenty-third MOS transistor form a forward loop, and the seventh MOS transistor and the twenty-fourth MOS transistor form a reverse loop.

3. The drive circuit for the height-adjustable table motor as described in claim 2, characterized in that, The first bootstrap voltage boosting circuit includes a first diode and a first capacitor. The anode of the first diode is connected to an enable circuit, its cathode is connected to one end of the first capacitor, and the other end of the first capacitor is connected to the source of the eighth MOS transistor. The second bootstrap voltage boosting circuit includes a second diode and a second capacitor. The anode of the second diode is connected to the enable circuit, and its cathode is connected to one end of the second capacitor. The other end of the second capacitor is connected to the source of the seventh MOS transistor.

4. The drive circuit for the height-adjustable table motor as described in claim 2, characterized in that, The left bridge upper arm drive module and the right bridge upper arm drive module have a symmetrical structure. The left bridge upper arm drive module includes a first BUFF circuit and a first delay circuit. The input terminal of the first BUFF circuit is connected to the output terminal of the first delay circuit, and its output terminal is connected to the eighth MOS transistor. The input terminal of the first delay circuit is connected to the power supply VCC and the output terminal of the first signal inversion module, respectively. The left bridge lower arm drive module and the right bridge lower arm drive module have a symmetrical structure. The left bridge lower arm drive module includes a second BUFF circuit and a second delay circuit. The structure of the second BUFF circuit is the same as that of the first BUFF circuit. The structure of the second delay circuit is the same as that of the first delay circuit. The input terminal of the second BUFF circuit is connected to the output terminal of the second delay circuit, and its output terminal is connected to the 24th MOS transistor. The input terminal of the second delay circuit is connected to the PWM signal output unit.

5. The drive circuit for the height-adjustable table motor as described in claim 4, characterized in that, The first BUFF circuit includes a fifth MOS transistor, a sixth MOS transistor, a twelfth MOS transistor, and a thirteenth MOS transistor. The fifth and sixth MOS transistors are P-type MOS transistors, and the twelfth and thirteenth MOS transistors are N-type MOS transistors. The gate of the fifth MOS transistor and the gate of the twelfth MOS transistor are respectively connected to the output terminal of the first delay circuit. The source of the fifth MOS transistor and the source of the sixth MOS transistor are respectively connected to the power supply VCC, and their drains are respectively connected to the gate of the sixth MOS transistor, the drain of the twelfth MOS transistor, and the gate of the thirteenth MOS transistor. The drain of the sixth MOS transistor and the drain of the thirteenth MOS transistor are respectively connected to the gate of the eighth MOS transistor, and the source of the twelfth MOS transistor and the source of the thirteenth MOS transistor are respectively connected to the source of the eighth MOS transistor.

6. The drive circuit for the height-adjustable table motor as described in claim 5, characterized in that, The first delay circuit includes a third capacitor, a fifth resistor, a ninth resistor, and a seventeenth MOSFET. One end of the third capacitor and one end of the fifth resistor are respectively connected to the power supply VCC and the output terminal of the first signal inverting module. The other end of the third capacitor is respectively connected to one end of the ninth resistor and the gate of the seventeenth MOSFET. The other end of the fifth resistor is respectively connected to the drain of the seventeenth MOSFET, the gate of the fifth MOSFET, and the gate of the seventh MOSFET. The other end of the ninth resistor and the source of the seventeenth MOSFET are respectively connected to the source of the eighth MOSFET.

7. The drive circuit for the height-adjustable table motor as described in claim 1, characterized in that, The NOT gate circuit includes an eleventh MOSFET and an eighteenth MOSFET. The gates of the eleventh MOSFET and the eighteenth MOSFET are respectively connected to the PWM signal output unit. The drains of the eleventh MOSFET and the eighteenth MOSFET are respectively connected to the input terminals of the second signal inversion module and the right bridge lower arm drive module. The source of the eleventh MOSFET is connected to the power supply VCC, and the source of the eighteenth MOSFET is grounded.

8. The drive circuit for the height-adjustable table motor as described in claim 1, characterized in that, The first signal inversion module includes a third resistor and a sixteenth MOSFET. One end of the third resistor is connected to the power supply VCC, and the other end is connected to the drain of the sixteenth MOSFET. The gate of the sixteenth MOSFET is connected to the PWM signal output unit, and its source is grounded. The second signal inversion module includes a fourth resistor and a fifteenth MOSFET. One end of the fourth resistor is connected to the power supply VCC, and the other end is connected to the drain of the fifteenth MOSFET and the input terminal of the right bridge upper arm drive module, respectively. The gate of the fifteenth MOSFET is connected to the output terminal of the NOT gate circuit, and its source is grounded.

9. The drive circuit for the height-adjustable table motor as described in claim 2, characterized in that, When the PWM signal is low, the eighth MOSFET and the twentieth MOSFET are turned on, the seventh MOSFET and the twentieth MOSFET are turned off, and the eighth MOSFET and the twentieth MOSFET form a loop; When the PWM signal is high, the eighth MOSFET and the twenty-third MOSFET are turned off, while the seventh MOSFET and the twenty-fourth MOSFET are turned on, forming a loop.

10. The drive circuit for the height-adjustable table motor as described in claim 9, characterized in that, The forward and reverse rotation and speed control of the motor are achieved by adjusting the duty cycle of the PWM signal output by the PWM output signal unit. When the duty cycle of the PWM signal is greater than 50%, the seventh MOSFET and the twenty-fourth MOSFET form a circuit, and the motor rotates in the forward direction. When the duty cycle of the PWM signal is 100%, the motor rotates in the forward direction at the fastest speed. When the duty cycle of the PWM signal is less than 50%, the eighth MOSFET and the twenty-third MOSFET form a circuit, and the motor reverses. The motor reverses fastest when the duty cycle of the PWM signal is 0. The motor stops rotating when the duty cycle of the PWM signal is 50%.

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