Method for processing special-shaped cavity structure in silicon-based terahertz circuit
By employing silicon-based MEMS technology and a two-layer bonding method, the technical problems of fabricating irregularly shaped cavity structures in existing technologies have been solved. This has enabled high-precision, low-cost mass production and increased design freedom for irregularly shaped cavities.
Patent Information
- Application Number
- CN202411499497.6
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-10-25
- Publication Date
- 2025-12-05
AI Technical Summary
Traditional CNC machine tools are unable to meet the processing requirements of micron- and nanometer-level cavity feature dimensions, and conventional rectangular cavities are difficult to meet the needs of complex devices and circuits. Irregular cavity structures cannot be processed by single-step etching processes, resulting in high process complexity.
Using silicon-based MEMS technology, irregular cavity structures in silicon-based terahertz circuits are fabricated through a two-layer structure bonding method. Deep reactive plasma etching equipment is used to complete the etching of different depth steps in one step, avoiding the load effect. An "All-In-One" process is adopted to improve efficiency.
It enables high-precision, low-cost mass production, increases the design freedom of irregular cavities, ensures good sidewall morphology, and simplifies the process flow.
Smart Images
Figure CN121063479A_ABST
Abstract
Description
TECHNICAL FIELD
[0001] The application belongs to the field of terahertz and semiconductor manufacturing, and particularly relates to a processing method of a special-shaped cavity structure in a silicon-based terahertz circuit. BACKGROUND
[0002] Terahertz waves have the properties of wide frequency band, low energy, good coherence, etc., and are widely used in the fields of wireless communication, nondestructive detection, etc. The waveguide cavities of traditional terahertz circuits and systems are mainly completed by numerical control machine tool processing. With the increase of the frequency of devices, the feature size of the cavities is reduced to the micron level, and the surface roughness is reduced to the nanometer level, so the numerical control machine tool processing can hardly meet the processing requirements of the cavities. The silicon-based MEMS processing technology is a semiconductor processing technology, and has the advantages of low cost, batch production, high integration, etc. and can be used to process the waveguide cavity structure in the terahertz circuit.
[0003] In the MEMS processing technology, the deep reactive ion etching process based on the Bosch technology has high etching rate and selectivity, and is commonly used to process the waveguide cavity structure. However, the load effect related to the etching aspect ratio makes it difficult to process the waveguide cavities with different widths. In addition, the conventional rectangular cavities are difficult to meet the requirements of complex devices and circuits, and the cavities are often designed into special-shaped structures such as recesses or multi-step shapes to meet the use requirements of the devices. Such special-shaped cavity structure cannot be processed by a single etching process, and the process complexity is high.
[0004] Therefore, it is necessary to provide a novel processing method of a special-shaped cavity structure in a silicon-based terahertz circuit to solve the above technical problems. SUMMARY
[0005] In view of the above problems, the purpose of the present application is to provide a processing method of a special-shaped cavity structure in a silicon-based terahertz circuit.
[0006] The specific technical scheme for achieving the purpose of the present application is as follows:
[0007] A processing method of a special-shaped cavity structure in a silicon-based terahertz circuit, comprising the following steps:
[0008] Step 1, determining the shape and parameters of the upper cavity of the special-shaped cavity structure in the silicon-based terahertz circuit;
[0009] Step 2, processing the upper cavity;
[0010] Step 3, processing the lower structure of the special-shaped cavity structure in the silicon-based terahertz circuit;
[0011] Step 4, bonding the processed upper cavity structure and the lower structure to complete the processing of the special-shaped cavity structure in the silicon-based terahertz circuit.
[0012] Compared with the prior art, the present application has the beneficial effects that:
[0013] (1) The scheme of the present application processes the special-shaped cavity in the terahertz circuit based on the silicon-based MEMS technology, has high processing precision, can be mass-produced, and has low cost, the two-layer structure can avoid the occurrence of the load effect in the deep reactive plasma etching process through the bonding mode, and increases the design freedom degree of the special-shaped cavity in the terahertz circuit.
[0014] (2) The scheme of the present application, after the special-shaped cavity structure in the silicon-based terahertz circuit is patterned by the hard mask silicon oxide, utilizes the deep reactive ion etching equipment to complete the etching of two different depth steps in one step, adopts the "All-In-One" mode to improve the process efficiency, and at the same time ensures that both steps have better side wall morphology.
[0015] The present application will be further described below in combination with specific embodiments. BRIEF DESCRIPTION OF DRAWINGS
[0016] Figure 1 A flow chart of a special-shaped cavity structure processing method in a silicon-based terahertz circuit of the present application.
[0017] Figure 2 A cross-sectional schematic view of the silicon-based special-shaped cavity structure in the embodiment of the present application.
[0018] Figure 3 A curve graph of the etching depth of the step changing with the width of the step in the embodiment of the present application.
[0019] Figure 4 A schematic view of a special-shaped cavity test area in the embodiment of the present application.
[0020] Figure 5 An etching depth profile graph of a part of the special-shaped cavity in the embodiment of the present application.
[0021] Figure 6 A top view of the special-shaped cavity containing three step depths processed in the embodiment of the present application.
[0022] Figure 7 A A-A cross-sectional schematic view of the special-shaped cavity containing three step depths processed in the embodiment of the present application. DETAILED DESCRIPTION
[0023] In order to clearly describe the technical solutions of the present application and the effects achieved, the technical solutions of the present application will be clearly explained below in combination with the drawings and specific examples of the present application, so that the skilled in the art can realize the present application without creative labor. The structure shown in the drawings is not the whole of the actual structure but only a part of the actual structure. It should be noted that all other examples made by the skilled in the art on the basis of the examples of the present application without creative labor shall fall within the protection scope of the present application.
[0024] The following listed partial examples are only for better illustrating the present application, but the content of the present application is not limited to the application in the listed examples. Therefore, the skilled in the art can make non-essential modifications to the embodiments on the basis of the above summary of the application and apply them to other examples, which are still within the protection scope of the present application. In addition, the experimental methods in the following examples without specific conditions shall be carried out according to the conventional or suggested conditions of the manufacturer. The expressions in the text are only used for distinguishing without other meanings if not specially stated.
[0025] In combination with Figure 1 A processing method of a special-shaped cavity structure in a silicon-based terahertz circuit, comprising the following steps:
[0026] Step 1, determining the shape and parameters of the upper layer cavity of the special-shaped cavity structure in the silicon-based terahertz circuit;
[0027] In combination with Figure 2 The special-shaped cavity structure in the silicon-based terahertz circuit is composed of two layers, the upper layer structure 1 includes grooves with no more than three steps, and the back of the silicon substrate contains a metal film 2; the lower layer structure 3 is a flat silicon substrate with a metal film 2 on the surface, and the special-shaped cavity structure is formed by bonding the upper and lower layers
[0028] The upper layer cavity structure of the special-shaped cavity structure in the silicon-based terahertz circuit is a silicon substrate including grooves;
[0029] The back of the silicon substrate has a metal film, and the surface of the silicon substrate is provided with grooves, the grooves are composed of no more than three depth cavities, and the width of the deepest step groove can be inconsistent;
[0030] This step determines the shape and parameters of the upper layer cavity of the special-shaped cavity structure in the silicon-based terahertz circuit according to the requirements. Specifically, it is the number of specific grooves including cavities of different depths, and the specific depth, width, etc. of each cavity.
[0031] Step 2, processing the upper layer cavity;
[0032] Specifically, when the groove is composed of cavities of three different depths, the specific process of processing the upper cavity in step 2 is as follows:
[0033] Step 2-1: Photoresist is formed on a portion of the silicon substrate surface using photolithography. The area on the silicon substrate without photoresist is the deepest cavity area. This area without photoresist is etched using ICP deep reactive plasma etching, and the etching depth is greater than the designed depth of the deepest cavity. Finally, the photoresist on the silicon substrate surface is removed using organic solvent or oxygen plasma.
[0034] Step 2-2: Deposit silicon oxide on the surface of the silicon substrate after the above operations using PECVD process as a masking layer for subsequent etching processes; and form photoresist in a portion of the silicon oxide masking layer using photolithography process. At this time, the area on the silicon oxide masking layer without photoresist is the shallowest cavity area. Etch the silicon oxide masking layer in the area without photoresist using RIE etching process to expose the silicon substrate, and remove the photoresist on the surface of the silicon oxide masking layer using organic solvent or oxygen plasma.
[0035] Steps 2-3: Photoresist is formed in a portion of the silicon oxide masking layer using photolithography. The area without photoresist on the silicon oxide masking layer is the intermediate depth cavity region. The silicon oxide masking layer in the area without photoresist is etched using RIE etching to expose the silicon substrate. Then, the silicon substrate in the area without photoresist masking is etched using ICP deep reactive plasma to obtain the desired shape of the intermediate depth cavity region.
[0036] This etching is the first etching of the intermediate depth cavity region, and the etching depth is determined based on the depths of the shallowest and deepest cavity regions.
[0037]
[0038] Where Thk is the first etching depth of the intermediate depth cavity region, H2 is the designed depth of the shallowest depth cavity region, H3 is the designed depth of the intermediate depth cavity region, and V2 and V3 are the theoretical etching depths corresponding to the widths of the shallowest depth cavity and the intermediate depth cavity under a certain etching menu (i.e., the actual etching depths determined experimentally based on the same etching menu in the past). In this embodiment, this can be achieved by querying... Figure 3 Obtain.
[0039] Steps 2-4: Use oxygen plasma to remove the photoresist from the entire surface of the silicon substrate, and perform ICP deep reactive plasma etching on the area of the silicon substrate without silicon oxide masking layer to obtain the shallowest depth cavity area and the intermediate depth cavity area that reach the designed depth. Then, use hydrofluoric acid and other solutions to etch away the silicon oxide masking layer on the entire surface of the silicon substrate.
[0040] Step 2-5, thinning the back surface of the silicon substrate, thinning the thickness of the silicon substrate to the depth of the deepest cavity and exposing the deepest cavity, at this time depositing a thin film of metal on the back surface of the silicon substrate.
[0041] When the recess is composed of two depths of cavities, the specific process of processing the upper layer of cavities in step 2 is as follows:
[0042] Step 2-1, forming photoresist on part of the surface of the silicon substrate by photolithography process, at this time the area without photoresist on the silicon substrate is the deepest cavity area, etching the area without photoresist by ICP deep reactive plasma etching process, and the etching depth is greater than the design value of the depth of the deepest cavity, and finally removing the photoresist on the surface of the silicon substrate by organic solvent or oxygen plasma;
[0043] Step 2-2, forming photoresist on part of the surface of the silicon substrate by photolithography process, at this time the area without photoresist on the silicon substrate is another depth cavity area, etching the area without photoresist by ICP deep reactive plasma etching process to obtain the cavity area of the designed depth, and finally removing the photoresist on the surface of the silicon substrate by organic solvent or oxygen plasma;
[0044] Step 2-3, thinning the back surface of the silicon substrate, thinning the thickness of the silicon substrate to the depth of the deepest cavity and exposing the deepest cavity, at this time depositing a thin film of metal on the back surface of the silicon substrate.
[0045] When the recess is composed of one depth of cavities, the specific process of processing the upper layer of cavities in step 2 is as follows:
[0046] Step 2-1, forming photoresist on part of the surface of the silicon substrate by photolithography process, at this time the area without photoresist on the silicon substrate is the cavity area, etching the area without photoresist by ICP deep reactive plasma etching process, and the etching depth is greater than the design value of the depth of the cavity, and finally removing the photoresist on the surface of the silicon substrate by organic solvent or oxygen plasma;
[0047] Step 2-2, thinning the back surface of the silicon substrate, thinning the thickness of the silicon substrate to the depth of the cavity and exposing the cavity, at this time depositing a thin film of metal on the back surface of the silicon substrate.
[0048] Step 3, processing the lower structure of the shaped cavity structure in the silicon-based terahertz circuit, i.e. processing the silicon substrate of the lower structure of the shaped cavity structure in the silicon-based terahertz circuit, and depositing a layer of metal thin film on the surface of the silicon substrate of the lower structure.
[0049] Step 4, bonding the processed upper cavity structure and the lower structure to complete the processing of the shaped cavity structure in the silicon-based terahertz circuit.
[0050] The metal film comprises an adhesion layer and a bonding layer;
[0051] The adhesion layer metal is titanium, chromium, nickel, tungsten or a composite of the above metals or an alloy thereof, and the thickness ranges from 100 to 400 nm;
[0052] The bonding layer metal is gold, copper, tin, indium or a composite of the above metals or an alloy thereof, and the thickness ranges from 500 to 2000 nm.
[0053] Embodiment 1
[0054] The silicon substrate used in this embodiment has a thickness of 400 um and a diameter of 150 mm. The upper layer structure of the shaped cavity comprises a groove with two different depth cavity steps. The deepest cavity groove is composed of two grooves with different widths, and the groove widths are 140 um and 240 um, respectively.
[0055] In step 2-1, a photoresist with a pattern is formed on the silicon substrate by a photolithography process. The area without photoresist on the silicon substrate is the area of the deepest step of the shaped cavity. The area without photoresist mask is etched away by an ICP deep reactive plasma etching process. The etching depth is 260 um, and the design value is 240 um. The photoresist on the surface of the silicon substrate is removed by oxygen plasma.
[0056] In step 2-2, a photoresist with a pattern is formed on the silicon substrate by a photolithography process. The area without photoresist on the silicon substrate is the area of the remaining one depth step of the shaped cavity. The area without photoresist mask is etched away by an ICP etching process. The etching depth is 80 um. The photoresist on the surface of the silicon substrate is removed by an organic solvent.
[0057] In step 2-3, the silicon substrate is thinned from the back to 240 um. A metal film of TiW and Au is deposited on the back of the silicon substrate, with thicknesses of 200 nm and 1000 nm, respectively.
[0058] In step 3, a metal composite film of TiW and Au is deposited on the surface of the lower layer structure of the silicon substrate, with thicknesses of 150 nm and 800 nm, respectively.
[0059] In step 4, the upper and lower layer structures are bonded together by a bonding process.
[0060] The deepest step in the upper layer structure is composed of two different widths. Based on the loading effect of the etching aspect ratio, the etching depth of the two different width regions will be different. In this embodiment, the etching menu is used as an example. The etching depths of the grooves with different widths are different, and the larger the groove width, the deeper the etching depth. See Figure 3 As can be seen from the figure, the step depths of the two groove widths differ by about 10 um.
[0061] Etching depth test was conducted on different width groove area, test area refer to Figure 4 , test results refer to Figure 5 , it can be seen from the figure that the etching depth of the narrower width groove is shallower, and the smaller the etching depth difference near the wider groove area, the maximum etching depth difference is dz=10.678um, which is basically consistent with Figure 3 analysis results. Therefore, in this embodiment, the etching depth in step A is 260um, which is 20um larger than the design value, covering the etching depth difference, ensuring that the etching depth of different groove widths can reach more than 240um, meeting the subsequent process requirements.
[0062] Example 2
[0063] The silicon substrate used in this embodiment has a thickness of 500um and a diameter of 150mm. The upper structure of the special-shaped cavity contains three grooves with different depths, grooves 4, 5 and 6, as shown in Figure 6 , groove 4 has a depth of 85um and a width of 83um, groove 5 has a depth of 17um and a width of 90um, and groove 6 has a depth of 235um and is composed of two different widths, 140um and 240um.
[0064] In step 2-1, a photoresist with a pattern is formed on the silicon substrate by photolithography process, and the area without photoresist on the silicon substrate is the area of the deepest step of the special-shaped cavity; the area without photoresist mask is etched away by ICP deep reactive plasma etching process, the etching depth is 260um, and the design value is 235um; the photoresist on the surface of the silicon substrate is removed by oxygen plasma;
[0065] In step 2-2, a layer of silicon oxide with a thickness of 500nm is deposited on the silicon substrate after the above process by PECVD process, which is used as a mask layer for subsequent etching process; a photoresist with a pattern is formed on the silicon oxide mask layer by photolithography process, and the area without photoresist is the area of the shallowest step of the special-shaped cavity; the area without photoresist mask is etched away by RIE etching process, exposing the silicon substrate; the photoresist on the surface of the silicon substrate is removed by oxygen plasma;
[0066] In step 2-3, a photoresist with a pattern is formed on the silicon oxide mask layer by photolithography process, and the area without photoresist is the area of the remaining one depth step of the special-shaped cavity; the area without photoresist mask is etched away by RIE etching process, exposing the silicon substrate, and the area without photoresist mask is etched away by ICP deep reactive plasma etching process, the etching depth is calculated by formula 1, where H2 is 17um, H3 is 85um, V2 and V3 are obtained by querying Figure 3 , respectively 256um and 253um, refer to Figure 3 , the etching depth is
[0067]
[0068] In step 2-4, the photoresist on the surface of the silicon substrate is removed by using oxygen plasma in an ICP deep reactive plasma device; the silicon substrate in the non-silicon oxide mask area is etched by an ICP deep reactive plasma etching process, and the etching depth is 17 um; the silicon oxide mask layer on the surface of the silicon substrate is etched away by a hydrofluoric acid solution.
[0069] In step 2-5, the silicon substrate is thinned from the back to 235 um; a metal thin film TiW and Au is deposited on the back of the silicon substrate, and the thicknesses are 200 nm and 1500 nm respectively.
[0070] In step 3, a new silicon substrate surface is deposited with a metal composite thin film TiW and Au, and the thicknesses are 100 nm and 1000 nm respectively.
[0071] In step 4, the upper and lower structures are bonded together by a bonding process.
[0072] The A-A profile schematic diagram of the special-shaped cavity completed by the embodiment is shown in Figure 7 As can be seen from the figure, the three step depths are consistent with the design values, and the sidewall state is good.
[0073] In step 2-3, after the groove 4 patterning process is completed, the ICP deep reactive plasma etching process is used to partially etch the groove 4, then the photoresist is removed by using oxygen plasma in an ICP deep reactive plasma etching machine, the remaining silicon oxide is used as a mask layer, and the ICP deep reactive plasma etching process is used to etch again to form two grooves with different step depths. This "All-In-One" etching method reduces the process steps, improves the process efficiency, and avoids the sidewall damage in multiple etching steps.
[0074] The above-described embodiments only express several embodiments of the present application, and the description is more specific and detailed, but it should not be understood as limiting the scope of the patent. It should be noted that for ordinary skilled in the art, without departing from the concept of the present application, a number of modifications and improvements can be made, which are within the scope of the present application. Therefore, the scope of protection of the present application patent should be subject to the appended claims.
Claims
1. A method for processing a special-shaped cavity structure in a silicon-based terahertz circuit, characterized in that, The method comprises the following steps: Step 1, determining the shape and parameters of the upper layer cavity structure of the shaped cavity structure in the silicon-based terahertz circuit; Step 2, processing the upper layer cavity structure; Step 3, processing the lower layer structure of the shaped cavity structure in the silicon-based terahertz circuit; Step 4, bonding the processed upper layer cavity structure and the lower layer structure to complete the processing of the shaped cavity structure in the silicon-based terahertz circuit.
2. The method of claim 1, wherein the method further comprises: The upper layer cavity structure of the shaped cavity structure in the silicon-based terahertz circuit is a silicon substrate comprising a groove; The silicon substrate has a metal film on the back surface, and the groove is formed on the surface of the silicon substrate and comprises cavities with no more than three depths.
3. The method of claim 2, wherein the method further comprises: When the groove comprises cavities with three depths, the specific process of processing the upper layer cavity structure in step 2 is as follows: Step 2-1, forming photoresist on part of the surface of the silicon substrate by a photoetching process, at this time, the area without photoresist on the silicon substrate is the deepest cavity area, the area is etched by an etching process, and the etching depth is greater than the design value of the depth of the deepest cavity, and finally the photoresist on the surface of the silicon substrate is removed; Step 2-2, depositing silicon oxide on the surface of the silicon substrate, and forming photoresist on part of the surface of the silicon oxide mask layer by a photoetching process, at this time, the area without photoresist on the silicon oxide mask layer is the shallowest depth cavity area, the silicon oxide mask layer in the area without photoresist is etched by an etching process to expose the silicon substrate, and the photoresist on the surface of the silicon oxide mask layer is removed; Step 2-3, forming photoresist on part of the surface of the silicon oxide mask layer by a photoetching process, at this time, the area without photoresist on the silicon oxide mask layer is the intermediate depth cavity area, the silicon oxide mask layer in the area without photoresist is etched by an etching process to expose the silicon substrate, and the silicon substrate in the area without photoresist is etched to obtain the shape of the intermediate depth cavity area; Step 2-4, removing the photoresist on the surface of the silicon substrate, and etching the area without silicon oxide mask layer on the surface of the silicon substrate to obtain the shallowest depth cavity area and the intermediate depth cavity area with the designed depth, and then removing the silicon oxide mask layer on the surface of the silicon substrate; Step 2-5, thinning the back surface of the silicon substrate, thinning the thickness of the silicon substrate to the depth of the deepest cavity and exposing the deepest cavity, and then depositing a metal film on the back surface of the silicon substrate.
4. The method of claim 3, wherein the method further comprises: The etching depth of the silicon substrate in the area without photoresist in step 2-3 is determined according to the design depth and actual etching depth difference of the shallowest depth cavity area and the intermediate depth cavity area: Wherein, Thk is the first etching depth of the intermediate depth cavity area, H2 is the design depth of the shallowest depth cavity area, H3 is the design depth of the intermediate depth cavity area, and V2 and V3 are the theoretical etching depths corresponding to the widths of the shallowest depth cavity and the intermediate depth cavity respectively under a certain etching menu.
5. The method of claim 2, wherein the method further comprises: When the groove comprises cavities with two depths, the specific process of processing the upper layer cavity structure in step 2 is as follows: Step 2-1, photoresist is formed on part of the surface of the silicon substrate by a photoetching process, at this time, the area without photoresist on the silicon substrate is the deepest cavity area, the area without photoresist is etched by an etching process, and the etching depth is greater than the design value of the depth of the deepest cavity, and finally the photoresist on the surface of the silicon substrate is removed; Step 2-2, photoresist is formed on part of the surface of the silicon substrate by a photoetching process, at this time, the area without photoresist on the silicon substrate is another deep cavity area, the area without photoresist is etched by an etching process to obtain the cavity area of the design depth, and finally the photoresist on the surface of the silicon substrate is removed; Step 2-3, the back of the silicon substrate is thinned to the depth of the deepest cavity and the deepest cavity is exposed, at this time, a metal film is deposited on the back of the silicon substrate.
6. The method of claim 2, wherein the method further comprises: When the groove is composed of a cavity of one depth, the specific process of processing the upper cavity in step 2 is as follows: Step 2-1, photoresist is formed on part of the surface of the silicon substrate by a photoetching process, at this time, the area without photoresist on the silicon substrate is the cavity area, the area without photoresist is etched by an etching process, and the etching depth is greater than the design value of the depth of the cavity, and finally the photoresist on the surface of the silicon substrate is removed; Step 2-2, the back of the silicon substrate is thinned to the depth of the cavity and the cavity is exposed, at this time, a metal film is deposited on the back of the silicon substrate.
7. The method of claim 1, wherein the method further comprises: In step 3, the silicon substrate of the lower layer structure of the special-shaped cavity structure in the silicon-based terahertz circuit is processed, and a layer of metal film is deposited on the surface of the silicon substrate of the lower layer structure.
8. The method of claim 2 or 7, wherein the method further comprises: The metal film includes an adhesion layer and a bonding layer; The adhesion layer metal is titanium, chromium, nickel, tungsten, or a composite or alloy thereof, and the thickness ranges from 100 to 400 nm; The bonding layer metal is gold, copper, tin, indium, or a composite or alloy thereof, and the thickness ranges from 500 to 2000 nm.