A high-security transistor testing system and method with nanosecond-level delay

Abstract

A high-safety transistor testing system and method with nanosecond-level delay is disclosed, belonging to the field of transistor testing. It enables transistor characteristic testing under arbitrary drain voltage stress values, drain voltage stress durations, and load currents based on nanosecond-level measurement delays, while ensuring the safety of the testing system and personnel. The circuit includes: a switch. S 1, S 2, S 3. Resistance R A , R C Schottky diode D 1, D 2. Power Inductor L ,power supply V DD Control switch S 1. The conduction time can control the high voltage that the subsequent circuit can withstand. V DD Duration; control switch S 2. On-time can control the power inductor L Current value at the end of charging; test switch S From the voltage and current of 3, we can determine the switch. S 3. Switching transient characteristics, on-resistance characteristics, etc. Simulation and experiments show that the measurement delay of switching to the test state after the drain voltage stress ends is on the order of nanoseconds, and there is no situation of "accidental opening of series switch leading to large current conduction", so the circuit safety is higher.

Description

Technical Field

[0001] This invention belongs to the field of transistor testing, specifically relating to a high-safety transistor testing system and method with nanosecond-level delay. It can measure the transistor characteristics of the transistor under test under arbitrary drain voltage stress values, drain voltage stress durations, and load currents based on nanosecond-level measurement delays, while ensuring the safety of the testing system and experimental personnel. Background Technology

[0002] The double-pulse circuit can be used to study the hard-switching characteristics of a transistor when it is simultaneously subjected to drain voltage stress and load current. The double-pulse circuit test method involves applying two consecutive pulses to the gate of the transistor under test (TUT), causing the TUT to switch on and off twice. When the transistor is turned on, the high-voltage power supply charges the load inductor. By controlling the duration of the first turn-on of the TUT, the current at the end of the first charging of the power inductor can be precisely controlled. When the TUT is turned on for the second time, it simultaneously experiences a large switching of drain voltage and drain current, which is the hard-switching process.

[0003] Traditional dual-pulse circuits typically involve a significant measurement delay when switching from drain voltage stress to measurement mode. This delay includes the time it takes for the transistor under test to first turn on (typically 2 to 10 microseconds) and the time it takes for the transistor to first turn off and for the inductor current to freewheel through the Schottky diode (typically 1 to 3 microseconds). For some novel transistors made from new materials, drain voltage stress can cause carrier trapping, threshold voltage drift, and on-resistance degradation due to internal defects. After the drain voltage stress is removed, these internal defects gradually release the carriers. Depending on the type of defect, the time constant for carrier release can be on the order of microseconds, milliseconds, or seconds. A measurement delay of several microseconds (e.g., 3 to 13 microseconds) can lead to inaccurate measurement results, failing to display the true state of the transistor after drain voltage stress in real time. Clearly, the data measured by traditional dual-pulse circuits cannot reflect the instantaneous switching and conduction characteristics of the transistor under test after drain voltage stress.

[0004] References 1 (Application No.: CN202410251482.1) and 2 (Application No.: CN202511171475.1) disclose "a test circuit and method for power devices with nanosecond-level delay" and "a transistor reliability test system and method with nanosecond-level delay," respectively. These methods can shorten the measurement delay of transistors after drain voltage stress to several nanoseconds, achieving significant benefits. However, both References 1 (Application No.: CN202410251482.1) and 2 (Application No.: CN202511171475.1) include a "half-bridge structure" with two "switching transistors" directly connected in series. During high-frequency, high-voltage experiments, parasitic parameters in the circuit can easily cause the "half-bridge structure" to mis-conduct, leading to instantaneous high current, overheating of the circuit board, and even explosion, threatening the safety of experimental personnel and equipment. Summary of the Invention

[0005] The purpose of this invention is to provide a high-safety transistor testing system and method with nanosecond-level delay. Addressing the problem of long delay times (typically 3 to 13 microseconds) between the end of drain voltage stress and the start of measurement of transistor turn-on transients and on-resistance in traditional dual-pulse test circuits, this invention discloses a nanosecond-level delay transistor testing system. This system can test the transistor's switching transients and on-resistance under arbitrary drain voltage stress values, drain voltage stress durations, and load currents, while maintaining nanosecond-level measurement delays. Furthermore, the circuit of this invention does not contain a "half-bridge structure" with two "switching transistors" directly connected in series. This eliminates the possibility of "two series switches accidentally turning on, leading to a large current flow," resulting in higher circuit safety and ensuring the safety of experimental personnel and the testing system.

[0006] To achieve the above objectives, the specific technical solution adopted is as follows:

[0007] The first objective of this invention is to provide a high-security transistor testing system with nanosecond-level delays.

[0008] The testing system includes: a switch S 1, S 2, S 3. Resistance R A , R C Schottky diode D 1, D 2. Power Inductor L ,power supply V DD .

[0009] Among them: control switch S 1, S 2,S 3 is one of the following: insulated gate field-effect transistor (MOSFET), junction field-effect transistor (JFET), bipolar junction transistor (BJT), insulated gate bipolar transistor (IGBT), high electron mobility transistor (HEMT), or relay and gate drive chip.

[0010] The resistor can be replaced by a variety of equivalent devices, including but not limited to: (a) an enhancement-mode PMOS with gate-drain shorted as a load, (b) an enhancement-mode PMOS with fixed gate voltage as a load, (c) an enhancement-mode NMOS with gate-drain shorted as a load, or (d) a depletion-mode NMOS with gate-source shorted as a load.

[0011] The circuit connection of this system is as follows: switch S One end of 1 is connected to the power supply. V DD ,switch S The other end of 1 is connected to a resistor. R A One end, Schottky diode D 1's negative terminal, power inductor L One end, resistor R C One end, resistor R A The other end is connected to GND, Schottky diode D The positive terminal of 1 is connected to the power inductor. L The other end, switch S 2, one end of the Schottky diode D 2's positive terminal, switch S The other end of 2 is connected to GND, Schottky diode. D 2. Negative terminal connected to resistor R C The other end, switch S 3, switch S The other end of 3 is connected to GND.

[0012] The second objective of this invention is to provide a method for testing the reliability of transistors with nanosecond-level delays, implemented using the system provided in the first aspect of this invention, comprising the following steps:

[0013] 1) Determine the switch S 3. The duration of voltage stress, and the determination of the switch accordingly. S 1. On-time duration;

[0014] 2) Determine the switch S 3. The initial current value at the instant of closing, and the switch value determined accordingly. S 2. On-time duration;

[0015] 3) Then, the switch is determined according to the experimental objective. S 3. On-time duration;

[0016] 4) Then determine the switch S 3. The stress value when disconnected, and thereby determine the parameters required for the high-voltage power supply;

[0017] 5) Set the high-voltage power supply parameters and control the switches sequentially. S 1. Switch S 2. Switch S 3. Switch status;

[0018] 6) Obtain the switch using an oscilloscope S 3. Voltage and current parameters;

[0019] 7) Obtain the switch parameters from voltage and current parameters. S 3. Switching transient characteristics and conduction characteristics;

[0020] 8) Finally, the switch was obtained. S 3. Reliability parameters under nanosecond-level delays.

[0021] Furthermore, in the method of the present invention, the switch S When disconnected, there is no voltage in the subsequent circuit. V DD Input, switch S When 1 is turned on, the subsequent circuit has voltage. V DD Input; control switch S 1. The conduction time can control the high voltage that the subsequent circuit can withstand. V DD Duration, switch S 1. Under the premise of conduction, if the switch S If 2 is turned on, then the power inductor L Potential difference between the two ends V DD Flow through the power inductor L The current gradually increases, satisfying the formula L ×di / dt= V DD When the switch S 2. When turned off, the power inductor L There is no high voltage potential difference between the two ends. Since the inductor current cannot change abruptly, the power inductor... L Through a Schottky diode connected in parallel with it D 1. Freewheeling, Schottky diode D 2 is used to connect power inductors. L Low-voltage side ports and switches S One end of 3; due to the Schottky diode D 2. Unidirectional conductivity, when a Schottky diode... D2. When the positive electrode potential is low, it is in the cutoff state and will not activate the Schottky diode. D 2. Negative terminal, i.e., switch S Pulling one end of the 3rd terminal low ensures the power inductor L via switch S 2. During charging, the Schottky diode D 2. The negative electrode still "passes through the resistor" R C and the conducting switch S 1” withstands high voltage electricity V DD Voltage stress; when switching S 3. When the switch is turned off, S One end of 3 "passes through a resistor" R C and the conducting switch S 1” withstands high voltage electricity V DD Voltage stress; when switching S 3. When turned on, the power inductor L Power inductors act as inductive loads in circuits. L Potential difference between the two ends V DD Flow through the power inductor L The current gradually increases, satisfying the formula L ×di / dt= V DD When the switch S 3. When turned off again, the power inductor L There is no high voltage potential difference between the two ends. Since the inductor current cannot change abruptly, the power inductor... L Through a Schottky diode connected in parallel with it D 1. Perform freewheeling; test the switch. S 3. Voltage and current, to know the switch S 3. Switching transient characteristics and on-resistance characteristics.

[0022] The beneficial effects of this invention are:

[0023] 1. This invention relates to a high-safety transistor testing system and method with nanosecond-level delay. The main circuit structure is a switch-resistor series connection, avoiding the direct series connection of two switches. This eliminates the possibility of "two series switches accidentally turning on, leading to a large current flow," resulting in higher circuit safety and ensuring the safety of personnel and the testing system. References 1 (application number: CN202410251482.1) and 2 (application number: CN202511171475.1) both involve a "half-bridge structure" with two "switching transistors" directly connected in series. During high-frequency, high-voltage experiments, parasitic parameters in the circuit can easily cause the "half-bridge structure" to mis-turn on, leading to instantaneous large currents, circuit board overheating, and even explosion, threatening the safety of personnel and equipment.

[0024] 2. This invention can test switches while measuring delays at the nanosecond level. S 3 (or the transistor under test) switches on and off under arbitrary voltage stress values, voltage stress durations, and currents. S 3. (Or the transistor under test) Switching transients and on-resistance.

[0025] 3. This invention contains only 3 switches (which can be replaced by transistors). Compared with Reference 1 (Application No.: CN202410251482.1) and Reference 2 (Application No.: CN202511171475.1), the circuit structure of this invention is greatly simplified, reducing the complexity of the test system and experiments, and improving the ease of use of the test system. Attached Figure Description

[0026] The invention will be better understood from the following description, which relates to a preferred embodiment given by way of non-limiting example and explained with reference to the accompanying schematic diagram, wherein:

[0027] Figure 1 This is a circuit block diagram of a high-security transistor test system with nanosecond-level delay.

[0028] Figure 2 This is the circuit schematic of a high-security transistor testing system with nanosecond-level delay.

[0029] Figure 3 yes Figure 2 Several other equivalent alternatives to the medium resistance. Among them, (a) an enhancement-mode PMOS with gate-drain shorted as the load; (b) an enhancement-mode PMOS with fixed gate voltage as the load; (c) an enhancement-mode NMOS with gate-drain shorted as the load; and (d) a depletion-mode NMOS with gate-source shorted as the load.

[0030] Figure 4 This is a flowchart of a high-security transistor test system with nanosecond-level delay.

[0031] Figure 5 This is an example of a high-security transistor testing system with nanosecond-level delay.

[0032] Figure 6 yes Figure 5 Simulation results of the example. Detailed Implementation

[0033] The present invention will now be described in further detail with reference to the accompanying drawings. The specific embodiments described herein are for illustrative purposes only and are not intended to limit the scope of the invention.

[0034] This invention relates to a high-safety transistor testing system and method with nanosecond-level delay, which can measure the transistor characteristics of the transistor under test under arbitrary drain voltage stress values, drain voltage stress durations, and load currents based on nanosecond-level measurement delay while ensuring the safety of the testing system and experimental personnel.

[0035] Figure 1 This is a circuit block diagram of a high-security transistor testing system with nanosecond-level delays. It consists of four parts: experimental setup, external input, power circuit, and external monitoring. First, the experimental setup involves designing the drain voltage stress value, drain voltage stress duration, load current value, and conduction time of the transistor under test (TUT) according to experimental requirements. Next, three pulse signals are designed based on the drain voltage stress duration, load current value, and TUT conduction time. These three pulse signals are then input to the gate driver chip in the power circuit, which drives the power transistor. A drain clamping module is also added to the power circuit to improve the testing accuracy of the TUT drain voltage. Finally, external monitoring is performed using testing instruments such as an oscilloscope to obtain key information such as the TUT gate drive voltage, drain voltage, and drain-source current.

[0036] Figure 2 This is a circuit schematic of a high-security transistor testing system with nanosecond-level delays. The circuit includes switches. S 1, S 2, S 3. Resistance R A , R C Schottky diode D 1, D 2. Power Inductor L ,power supply V DD It's worth mentioning that the control switch... S 1, S 2, S3 can be an insulated gate field-effect transistor (MOSFET), a junction field-effect transistor (JFET), a bipolar junction transistor (BJT), an insulated gate bipolar transistor (IGBT), a high electron mobility transistor (HEMT), or even a relay or a gate driver chip.

[0037] The circuit connection is as follows: switch S One end of 1 is connected to the power supply. V DD ,switch S The other end of 1 is connected to a resistor. R A One end, Schottky diode D 1's negative terminal, power inductor L One end, resistor R C One end of the resistor. R A The other end is connected to GND, Schottky diode D The positive terminal of 1 is connected to the power inductor. L The other end, switch S 2, one end of the Schottky diode D The positive terminal of 2. Switch. S The other end of 2 is connected to GND, Schottky diode. D 2. Negative terminal connected to resistor R C The other end, switch S One end of 3. Switch S The other end of 3 is connected to GND.

[0038] Based on the above system, this invention proposes a high-security transistor testing method with nanosecond-level delay, comprising the following steps:

[0039] 1) Determine the switch S 3. The duration of voltage stress, and the determination of the switch accordingly. S 1. On-time duration;

[0040] 2) Determine the switch S 3. The initial current value at the instant of closing, and the switch value determined accordingly. S 2. On-time duration;

[0041] 3) Then, the switch is determined according to the experimental objective. S 3. On-time duration;

[0042] 4) Then determine the switch S 3. The stress value when disconnected, and thereby determine the parameters required for the high-voltage power supply;

[0043] 5) Set the high-voltage power supply parameters and control the switches sequentially. S1. Switch S 2. Switch S 3. Switch status;

[0044] 6) Obtain the switch using an oscilloscope S 3. Voltage and current parameters;

[0045] 7) Obtain the switch parameters from voltage and current parameters. S 3. Switching transient characteristics and conduction characteristics;

[0046] 8) Finally, the switch was obtained. S 3. Reliability parameters under nanosecond-level delays.

[0047] The working principle of the circuit of this invention is as follows: switch S When disconnected, there is no voltage in the subsequent circuit. V DD Input. Switch S When 1 is turned on, the subsequent circuit has voltage. V DD Input. Control switch S 1. The conduction time can control the high voltage that the subsequent circuit can withstand. V DD Duration. Switch S 1. Under the premise of conduction, if the switch S If 2 is turned on, then the power inductor L Potential difference between the two ends V DD Flow through the power inductor L The current gradually increases, satisfying the formula L ×di / dt= V DD When the switch S 2. When turned off, the power inductor L There is no high voltage potential difference between the two ends. Since the inductor current cannot change abruptly, the power inductor... L Through a Schottky diode connected in parallel with it D 1. Freewheeling is performed, therefore the Schottky diode... D 1. Also known as a freewheeling diode. Schottky diode. D 2 is used to connect power inductors. L Low-voltage side ports and switches S One end of 3. Due to the Schottky diode D 2. Unidirectional conductivity, when a Schottky diode... D 2. When the positive electrode potential is low, it is in the cutoff state and will not activate the Schottky diode. D 2 Negative pole (switch) S Pull the potential of one end of 3 low to ensure the power inductor L via switch S 2. During charging, the Schottky diode D2 Negative pole (switch) S One end of 3) still "passes through the resistor" R C and the conducting switch S 1” withstands high voltage electricity V DD Voltage stress. When the switch... S 3. When the switch is turned off, S One end of 3 "passes through a resistor" R C and the conducting switch S 1” withstands high voltage electricity V DD Voltage stress; when switching S 3. When turned on, the power inductor L It acts as an inductive load in the circuit. Power inductor. L Potential difference between the two ends V DD Flow through the power inductor L The current gradually increases, satisfying the formula L ×di / dt= V DD When the switch S 3. When turned off again, the power inductor L There is no high voltage potential difference between the two ends. Since the inductor current cannot change abruptly, the power inductor... L Through a Schottky diode connected in parallel with it D 1. Perform freewheeling. Test switch. S From the voltage and current of 3, we can determine the switch. S 3. Switching transient characteristics, on-resistance characteristics, etc.

[0048] Figure 3 yes Figure 2 Several other equivalent alternatives to silicon resistors are shown. In integrated circuit design, due to various considerations, silicon resistors are often not fabricated on the chip; instead, other electronic components are used to generate the equivalent resistance. This diagram is intended to illustrate... Figure 2 The resistor in the diagram can be replaced by various equivalent devices, but as long as it functions as a resistor, it can be considered as such. Figure 2 The same circuit, Figure 3 Several methods for equating other electronic components to resistors are demonstrated, with only a few examples listed. (a) An enhancement-mode PMOS with its gate and drain shorted as a load, (b) An enhancement-mode PMOS with its gate voltage fixed as a load, (c) An enhancement-mode NMOS with its gate and drain shorted as a load, and (d) A depletion-mode NMOS with its gate and source shorted as a load.

[0049] Figure 4This is a flowchart of a high-safety transistor testing system with nanosecond-level delays. In the experimental setup phase, the drain voltage stress duration of the transistor under test (TUT) is first determined, and the pulse width of pulse 1 is determined accordingly. Then, the current value of the TUT is determined, and the pulse width of pulse 2 is determined accordingly. Next, the turn-on duration of the TUT is determined, and the pulse width of pulse 3 is determined accordingly. Finally, the drain voltage stress value of the TUT is determined, and the parameters required for the high-voltage power supply are set accordingly. In the testing phase, the high-voltage power supply parameters are first set. Then, pulses 1, 2, and 3 are input and drive the three transistors via the gate drive module. The testing system also includes clamping circuitry to improve testing accuracy. In the data analysis phase, the voltage and current parameters of the TUT are obtained using an oscilloscope. From these parameters, the switching transient characteristics and conduction characteristics (on-resistance) of the TUT can be determined. Finally, the reliability parameters of the TUT under nanosecond-level delays are summarized and analyzed.

[0050] Figure 5 This is an example of a high-security transistor testing system with nanosecond-level delays. Based on circuit function, the power circuit can be divided into three parts: a voltage stress value and stress duration control module, a current control module, and a transient and on-resistance testing module.

[0051] The voltage stress value and stress duration control module includes NMOS power transistors. Q A and resistance R A Among them, NMOS power transistors Q A source and resistor R A One end is connected to form a common end and V SA Connection, NMOS power transistor Q A drain connection V DD Terminal, its gate is connected V GA ,resistance R A The other end is grounded.

[0052] The current control module includes NMOS power transistors. Q B Schottky diode D 1 and D 2. Power Inductor L Among them, NMOS transistors Q B Drain and power inductor L one end and Schottky diode D 1 and DThe two positive terminals are connected together, and the power inductor is... L The other end and the Schottky diode D The negative terminal of 1 is connected to the transistor in the voltage stress value and stress duration control module. Q A The source pole and V SA The common connection terminals are connected; NMOS transistors Q B The source is grounded; NMOS transistor Q B gate connection V GB end.

[0053] The power circuit section of the transient and on-resistance test module includes NMOS power transistors. Q C and resistance R C And clamping circuit. Among them, resistors R C With NMOS transistors Q C The drain connection forms a common terminal with the Schottky diode of the current control module. D 2 negative terminals are connected together and V DC Connection; Resistor R C The other end is connected to the Schottky diode of the current control module. D 1. Negative terminal, power inductor L and the resistor of the voltage stress value and stress duration control module. R A One end, NMOS transistor Q A The source pole, V SA The common connection terminals are connected. NMOS transistor Q C gate connection V GC NMOS power transistor Q C The NMOS transistor in the source connection current control module Q B The source electrode and the resistor of the voltage stress value and stress duration control module R A One end, NMOS power transistor Q C gate connection V GC The NMOS transistor mentioned above QB The source and NMOS transistor Q C The common connection terminal of the source and the resistor R C One end, NMOS transistor Q C Drain and Schottky diode D A clamping circuit is provided between the common connection terminals of the two negative terminals.

[0054] The circuit working principle in this embodiment is as follows:

[0055] For the voltage stress value and stress duration control module, when Q A When shut down V SA The voltage is 0 volts, and there is no high-voltage input to the subsequent circuit. Q A When conducting V SA2 The voltage is the supply voltage of the high-voltage power supply. V DD The subsequent circuit receives a high-voltage input. This controls the upper transistor. Q A The conduction time can control the high voltage that the subsequent circuit can withstand. V DD Duration.

[0056] For the current control module, when the transistor Q B When turned on, the power inductor L Potential difference between the two ends V DD Flow through the power inductor L The current gradually increases, satisfying the formula L ×di / dt= V DD When transistors Q B When turned off, the power inductor L There is no high voltage potential difference between the two ends. Since the inductor current cannot change abruptly, the power inductor... L Through a Schottky diode connected in parallel with it D 1. Freewheeling is performed, therefore the Schottky diode... D 1. Also known as a freewheeling diode. Schottky diode. D 2 is used to connect power inductors. L Low-voltage side port and transistor under test Q C Drain. Due to the Schottky diode D 2. Unidirectional conductivity, when a Schottky diode... D2. When the positive electrode potential is low, it is in the cutoff state and will not activate the Schottky diode. D 2. Negative electrode (transistor under test) Q C Pulling the drain potential low ensures the power inductor L Through transistors Q B During charging, the Schottky diode D 2. Negative electrode (transistor under test) Q C The drain remains (through the resistor) R C and conduction Q A (bearing high voltage electricity) V DD Voltage stress.

[0057] For transient and on-resistance testing modules. When Q C When shut down Q C The drain is connected to a resistor R C and conduction Q A Withstand stable high voltage V DD .when Q C Power inductor when turned on L Power inductors act as inductive loads in circuits. L Potential difference between the two ends V DD Flow through the power inductor L The current gradually increases, satisfying the formula L ×di / dt= V DD When transistors Q C When turned off, the power inductor L There is no high voltage potential difference between the two ends. Since the inductor current cannot change abruptly, the power inductor... L Through a Schottky diode connected in parallel with it D 1. Perform freewheeling. Test the transistor under test. Q C By analyzing the gate voltage, drain voltage, and drain-source current, we can determine the transistor under test. Q C During hard-switching testing, the transient switching characteristics and on-resistance characteristics are examined. Clamping circuitry is used to improve the performance of the transistor under test. Q C The accuracy of drain voltage testing will not be discussed further here.

[0058] Figure 6yes Figure 5 Simulation results of the embodiment. The horizontal axis represents time, and the vertical axis, from top to bottom, represents transistors. Q A gate voltage V GA ,transistor Q B gate voltage V GB ,transistor Q C gate voltage V GC ,transistor Q A Source voltage V SA ,transistor Q B drain voltage V DB ,transistor Q C drain voltage V DC ,transistor Q C Drain source current I C The current of the power inductor I L . T 1~ T 6 is the key time point marked in the diagram. Initial stage transistors Q A , Q B , Q C All are turned off, and their gate voltages are all 0 V. T At time 1, the transistor Q A Conduction, at this time V SA , V DB , V DC Start to withstand voltage V DD (i.e., 200 V) voltage stress. T At time 2, the transistor Q B When the transistor is turned on, it is in a state of conduction. Q B Drain-source voltage V DB Reduced to near 0 V, V DD After transistor Q A Power inductorL ,transistor Q B Forming a circuit, power inductor L The potential difference between the two ends is the voltage. V DD (i.e., 200 V), which satisfies the formula L ×di / dt= V DD At this point, the current in the power inductor can be observed. I L Gradually increase. T At time 3, the transistor Q B Off, voltage V DD With power inductor L There is no loop between them, power inductor L When charging stops, the power inductor cannot change its current due to the inductor's inability to change its current. L Through a Schottky diode connected in parallel with it D 1. Perform a continuous stream. T At time 4, the transistor Q C When the transistor is turned on, it is in a state of conduction. Q C Drain-source voltage V DC Reduced to near 0 V, V DD After transistor Q A Power inductor L Schottky diode D 2. Transistor Q C Forming a circuit, power inductor L The potential difference between the two ends is the voltage. V DD (i.e., 200V), which satisfies the formula L ×di / dt= V DD At this point, the current in the power inductor can be observed. I L Gradually increase. T 4-time transistor Q C At the moment of conduction, the transistor Q C Simultaneously withstands large drain voltage stress V DD (i.e., 200 V), drain-source current (current of the power inductor) I L (This is a hard switch.) T At time 5, the transistor QC Off, voltage V DD With power inductor L There is no loop between them, power inductor L When charging stops, the power inductor cannot change its current due to the inductor's inability to change its current. L Through a Schottky diode connected in parallel with it D 1. Perform a continuous stream. T 4 o'clock T The period between 5 and 6 is the key focus of this experiment, during which the transistor... Q C After hard switching, transistors Q C The switching transient and conduction steady-state characteristics are of great significance for evaluating transistor characteristics. T At time 6, the transistor Q A Shut down and complete the test.

[0059] Those skilled in the art will readily understand that the above description is merely a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of the present invention should be included within the scope of protection of the present invention.

Claims

1. A transistor testing system with high safety nanosecond order delay, characterized in that, The test system comprises switches S1, S2, S3, resistors R A , C , Schottky diodes D1, D2, a power inductor L, a power supply V DD ; Wherein: one end of switch S1 is connected with power supply V DD , the other end of switch S1 is connected with one end of resistor R A , negative pole of Schottky diode D1, one end of power inductor L, one end of resistor R C , the other end of resistor R A is connected with GND, positive pole of Schottky diode D1 is connected with the other end of power inductor L, one end of switch S2, positive pole of Schottky diode D2, the other end of switch S2 is connected with GND, negative pole of Schottky diode D2 is connected with the other end of resistor R C , one end of switch S3, the other end of switch S3 is connected with GND; The control switches S1, S2 and S3 are one of an insulated gate field effect transistor (MOSFET), a junction field effect transistor (JFET), a bipolar junction transistor (BJT), an insulated gate bipolar transistor (IGBT), a high electron mobility transistor (HEMT), or a relay, and a gate drive chip; The transistor reliability test of nanosecond delay is realized by the switching states of the three switches.

2. The high safety nanosecond delay transistor test system according to claim 1, wherein, The resistor can be replaced by a variety of equivalent devices, including but not limited to: (a) a gate-drain shorted enhancement mode PMOS as a load, (b) a gate voltage fixed enhancement mode PMOS as a load, (c) a gate-drain shorted enhancement mode NMOS as a load, or (d) a gate-source shorted depletion mode NMOS as a load.

3. A transistor testing method for high safety nanosecond order delay, characterized by, The system is realized by the steps of: 1) determining the stress duration of the switch S3 under voltage stress, and determining the conduction duration of the switch S1 accordingly; 2) determining the initial current value at the moment when the switch S3 is closed, and determining the conduction duration of the switch S2 accordingly; 3) then determining the conduction duration of the switch S3 according to the experimental target; 4) then determining the stress value when the switch S3 is opened, and determining the required parameters of the high-voltage power supply accordingly; 5) setting the parameters of the high-voltage power supply and controlling the switching states of the switches S1, S2 and S3 in turn; 6) obtaining the voltage and current parameters of the switch S3 through an oscilloscope; 7) obtaining the switching transient characteristics and conduction characteristics of the switch S3 from the voltage and current parameters; 8) finally obtaining the reliability parameters of the switch S3 under nanosecond delay.

4. The method of claim 3, wherein the nanosecond delay transistor is a high safety transistor. When switch S1 is open, there is no voltage V in the subsequent circuit. DD When the input switch S1 is turned on, the subsequent circuit has a voltage V. DD Input; the conduction time of control switch S1 can control the high voltage V that the subsequent circuit can withstand. DD The duration of the voltage difference V across the power inductor L, assuming switch S1 is on, is as follows: DD The current flowing through the power inductor L gradually increases, satisfying the formula L×di / dt=V DD When switch S2 is off, there is no high voltage potential difference across the power inductor L. Since the inductor current cannot change abruptly, the power inductor L freewheels through the Schottky diode D1 connected in parallel with it. The Schottky diode D2 is used to connect the low-voltage side of the power inductor L to one end of switch S3. Due to the unidirectional conductivity of the Schottky diode D2, when the positive terminal of the Schottky diode D2 has a low potential, it is in the cutoff state and will not pull down the potential of the negative terminal of the Schottky diode D2, i.e., one end of switch S3. This ensures that during the charging of the power inductor L through switch S2, the negative terminal of the Schottky diode D2 still flows through resistor R. C And the conducting switch S1” withstands high voltage V DD Voltage stress; when switch S3 is turned off, one end of switch S3 passes through resistor R C And the conducting switch S1” withstands high voltage V DD Voltage stress; when switch S3 is turned on, the power inductor L acts as an inductive load in the circuit, and the potential difference V across the power inductor L is... DD The current flowing through the power inductor L gradually increases, satisfying the formula L×di / dt=V DD When switch S3 is turned off again, there is no high voltage potential difference across the power inductor L. Since the inductor current cannot change abruptly, the power inductor L freewheels through the Schottky diode D1 connected in parallel with it. By testing the voltage and current of switch S3, the transient characteristics and on-resistance characteristics of switch S3 can be obtained.

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