Gating gate, reference circuit and chip

Abstract

The invention discloses a strobe gate, a reference circuit and a chip, the strobe gate comprises a first transmission tube and a second transmission tube, the influence of the bulk effect can be reduced, the conduction impedance and the leakage current of the second transmission tube can be reduced by connecting a power supply voltage greater than or equal to N times to the substrate of the second transmission tube as a substrate bias voltage, and the reliability of the strobe gate can be improved. Therefore, the conduction impedance and the leakage current of the gating gate are reduced, and the overall power consumption is reduced.

Description

Technical Field

[0001] This application relates to the field of electronic circuit technology, specifically to a gating gate, a reference circuit, and a chip. Background Technology

[0002] A gating gate is used to selectively enable or isolate a signal path under the action of a control signal.

[0003] However, the on-resistance of the gating gate has a significant impact on its performance. Therefore, there is an urgent need to provide a gating gate that can reduce the on-resistance. Summary of the Invention

[0004] This application provides a gating gate, a reference circuit, and a chip to alleviate the technical problem.

[0005] In a first aspect, this application provides a gate comprising a first transmission transistor and a second transmission transistor. The first terminal of the first transmission transistor is connected to the first terminal of the second transmission transistor, and the second terminal of the first transmission transistor is connected to the second terminal of the second transmission transistor. The control terminal of the first transmission transistor is connected to one of a first target clock signal and a second target clock signal. The substrate of the first transmission transistor is connected to a ground terminal. The control terminal of the second transmission transistor is connected to the other of the first target clock signal and the second target clock signal. The substrate of the second transmission transistor is connected to a substrate bias voltage. The first target clock signal and the second target clock signal are out of phase. The substrate bias voltage is greater than or equal to N times the power supply voltage.

[0006] Secondly, this application also provides a reference circuit, which includes the aforementioned gating gate.

[0007] Thirdly, this application also provides a chip that includes the aforementioned reference circuit.

[0008] The gating gate, reference circuit, and chip provided in this application reduce the influence of the bulk effect by applying a power supply voltage greater than or equal to N times to the substrate of the second transmission transistor as a substrate bias voltage. This reduces the on-resistance and leakage current of the second transmission transistor, thereby reducing the on-resistance and leakage current of the gating gate and ultimately reducing the overall power consumption. Attached Figure Description

[0009] The technical solution and other beneficial effects of this application will become apparent from the following detailed description of specific embodiments in conjunction with the accompanying drawings.

[0010] Figure 1 A schematic block diagram of the reference circuit provided in the embodiments of this application.

[0011] Figure 2 The circuit diagram of the clock oscillation circuit provided in the embodiments of this application is shown.

[0012] Figure 3 The circuit diagram of the clock voltage doubler circuit provided in the embodiments of this application.

[0013] Figure 4 The circuit diagram of the gating gate provided in the embodiments of this application.

[0014] Figure 5 The circuit diagram is shown for the emitter voltage generation circuit provided in the embodiment of this application.

[0015] Figure 6 The first circuit schematic diagram of the switched capacitor circuit provided in the embodiments of this application.

[0016] Figure 7 This is a second circuit schematic diagram of the switched capacitor circuit provided in the embodiments of this application.

[0017] Figure 8 for Figure 7 The diagram shows a simplified circuit diagram of the switched capacitor circuit.

[0018] Figure 9 This is a schematic diagram illustrating the relationship between reference voltage and temperature provided in an embodiment of this application.

[0019] Figure 10 This is a schematic diagram showing the relationship between power supply voltage, average current, and reference voltage provided in the embodiments of this application.

[0020] Figure 11 This is a schematic diagram illustrating the process of establishing different reference voltages provided in the embodiments of this application.

[0021] Figure 12 A schematic diagram of voltage changes at some nodes of the reference circuit provided in the embodiments of this application.

[0022] Figure 13 This is a schematic diagram of the chip structure provided in an embodiment of this application. Detailed Implementation

[0023] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of them. All other embodiments obtained by those skilled in the art based on the embodiments of this application without creative effort are within the scope of protection of this application.

[0024] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Features thus defined as "first" or "second" may explicitly or implicitly include one or more of the stated features. In the description of this invention, "a plurality of" means two or more unless otherwise explicitly specified.

[0025] like Figure 1 As shown, this embodiment provides a reference circuit 100, which includes a clock oscillation circuit 10, a clock voltage multiplier circuit 20, an emitter voltage generation circuit 30, and a switched capacitor circuit 40. The output terminal of the clock oscillation circuit 10 is connected to the input terminal of the clock voltage multiplier circuit 20, and the output terminal of the clock voltage multiplier circuit 20 is connected to the input terminal of the emitter voltage generation circuit 30 and the input terminal of the switched capacitor circuit 40, respectively. The output terminal of the emitter voltage generation circuit 30 is connected to the input terminal of the switched capacitor circuit 40.

[0026] It should be noted that the clock oscillation circuit 10 is used to generate a first initial clock signal P1 and a second initial clock signal P2. The clock voltage multiplier circuit 20 is used to generate a first target clock signal Φ1 and a second target clock signal Φ2 based on the power supply voltage Vin, the first initial clock signal P1, and the second initial clock signal P2. The emitter voltage generation circuit 30 is used to generate a first emitter voltage VEB1 and a second emitter voltage VEB2 based on the first target clock signal Φ1 and the second target clock signal Φ2. The switched capacitor circuit 40 is used to generate a reference voltage VREF based on the first target clock signal Φ1, the second target clock signal Φ2, the first emitter voltage VEB1, and the second emitter voltage VEB2.

[0027] like Figure 2 As shown, the clock oscillation circuit 10 includes a bias current generation module 11 and a clock oscillation module 12, with the bias current generation module 11 connected to the clock oscillation module 12. The bias current generation module 11 generates a bias current I0 based on the bias voltage VBIAS, and the clock oscillation module 12 generates a first initial clock signal P1 and a second initial clock signal P2 based on the bias current I0.

[0028] The bias current generation module 11 establishes the following voltage-current relationship through transistor NM0, transistor NM1, and resistor R0:

[0029]

[0030] Vs1=I0×R0 (1-3)

[0031] Vg1=Vgs(NM0) (1-4)

[0032] Substituting equation 1-1 into equation 1-4, and then substituting equations 1-3 and 1-4 into equation 1-2, we obtain the following equation 1-5:

[0033]

[0034] Where Vgs(NM0) represents the gate-source voltage difference of transistor NM0, Vth(NM0) represents the threshold voltage of transistor NM0, W0 represents the channel width of transistor NM0, L0 represents the channel length of transistor NM0, and K is the product of carrier mobility (μ) and gate oxide capacitance per unit area (Cox).

[0035] Vgs(NM1) represents the gate-source voltage difference of transistor NM1, Vth(NM1) represents the threshold voltage of transistor NM1, W1 represents the channel width of transistor NM1, L1 represents the channel length of transistor NM1, Vs1 represents the source voltage of transistor NM1, and Vg1 represents the gate voltage of transistor NM1.

[0036] R0 represents the resistance value of resistor R0, and I0 represents the bias current value of bias current I0.

[0037] The bias current generation module 11 provides bias voltage to transistor NM1 and resistor R0 through Vgs(NM0) of transistor NM0. Then, it adjusts the width-to-length ratio of transistor NM0 and transistor NM1 and the resistance value of R0 to make the circuit work in the desired state. Then, it mirrors the current of the two branches through transistors PM0 and PM1 to obtain bias current I0.

[0038] As can be seen from calculation formula 1-5, the bias current generating module 11 has a degeneracy point, requiring an additional startup circuit to keep the circuit in a working state at all times.

[0039] In the clock oscillation module 12, transistor PM2 generates a bias current I0 based on the bias voltage VBIAS, which is provided to the inverter composed of transistors PM3 and NM2. The inverter inverts the signal IP and generates a signal through capacitor C01. Transistor PMX1 pulls the voltage of this signal up to the power supply voltage Vin according to the enable EN. The inverter composed of transistors PM4 and NM3 is connected to this signal. The first NOR gate NOR1 performs a NOR operation on the output signal of the inverter and the enable ENb. The second NOR gate NOR2 performs a NOR operation on the output signal of the first NOR gate NOR1 and the output signal of the fourth NOR gate NOR4. Inverter INV01 inverts the output signal of the second NOR gate NOR2 to generate the signal IP. Inverter INV02 inverts the signal IP to generate the first initial clock signal P1.

[0040] Similarly, transistor PM5 generates a bias current I0 based on the bias voltage VBIAS, which is provided to the inverter composed of transistors PM6 and NM4. This inverter inverts the signal EP and generates a signal through capacitor C02. The inverter composed of transistors PM7 and NM5 is connected to this signal. The third NOR gate NOR3 performs a NOR operation on the output signal of the inverter and the enable EN. The fourth NOR gate NOR2 performs a NOR operation on the output signals of the third NOR gate NOR3 and the second NOR gate NOR2. Inverter INV03 inverts the output signal of the fourth NOR gate NOR4 to generate the signal EP. Inverter INV04 inverts the signal EP to generate the second initial clock signal P2.

[0041] The first initial clock signal P1 is out of phase with the second initial clock signal P2. The voltage of the first initial clock signal P1 and the voltage of the second initial clock signal P2 are both greater than or equal to 0V and less than or equal to the power supply voltage Vin.

[0042] In some embodiments, the high voltage of the first initial clock signal P1 and the high voltage of the second initial clock signal P2 are both greater than or equal to the power supply voltage Vin.

[0043] It should be noted that the duration of half a cycle of the first initial clock signal P1 and the second initial clock signal P2 is t = C0 × Vth(NM3, NM5) / I0. Here, transistors NM3 and NM5 need to be matched in the layout. C0 represents the capacitance value of capacitor C01 or capacitor C02. I0 represents the bias current value I0. Vth(NM3, NM5) represents the threshold voltage of transistor NM3 or transistor NM5.

[0044] Therefore, the frequencies of the first initial clock signal P1 and the second initial clock signal P2 are f = 1 / 2t.

[0045] When enable EN is low and enable Enb is high, signal IP is low and signal EP is high. At this time, the bias voltage VBIAS is set to high through the enable signal. The entire circuit has no static power consumption. The voltage on the upper plate of capacitor C01 is the power supply voltage Vin, and the voltage on the upper plate of capacitor C02 is 0V.

[0046] When enable EN is high and enable Enb is low, signal IP is high and signal EP is low. The voltage on the upper plate of capacitor C01 discharges to 0V, and the voltage on the upper plate of capacitor C02 charges to the power supply voltage Vin. Then, signal IP is set low and signal EP is set high. The voltage on the upper plate of capacitor C01 charges to the power supply voltage Vin, and the voltage on the upper plate of capacitor C02 discharges to 0V. This process is repeated, thereby generating the first initial clock signal P1 and the second initial clock signal P2 with a frequency of f.

[0047] In some embodiments, such as Figure 3 As shown, the clock multiplier circuit 20 includes an intermediate clock generation module 21, which includes a first intermediate clock generation unit 211, a second intermediate clock generation unit 212, and a voltage control unit 213. The first intermediate clock generation unit 211 is used to generate a first intermediate clock signal X1 based on the power supply voltage Vin and the first initial clock signal P1. The second intermediate clock generation unit 212 is used to generate a second intermediate clock signal X2 based on the power supply voltage Vin and the second initial clock signal P2. The voltage control unit 213 is used to control the low voltage of at least one of the first intermediate clock signal X1 and the second intermediate clock signal X2 to reach the power supply voltage Vin.

[0048] It is understood that the clock multiplier circuit 20 provided in this embodiment generates a first intermediate clock signal X1 based on the power supply voltage Vin and the first initial clock signal P1, and generates a second intermediate clock signal X2 based on the power supply voltage Vin and the second initial clock signal P2. The voltage control unit 213 controls at least one of the first intermediate clock signal X1 and the second intermediate clock signal X2 to reach the power supply voltage Vin. This avoids the diode connection from clamping the low voltage of the clock signal to the potential difference between the power supply voltage Vin and the threshold voltage. Thus, the high voltage of the clock signal can be doubled to reach twice the power supply voltage Vin.

[0049] It should be noted that by controlling the voltage of at least one of the first intermediate clock signal X1 and the second intermediate clock signal X2 to the power supply voltage Vin through the voltage control unit 213, the gate-source voltage difference of the diode-connected transistor can be made equal to 0V, thereby reducing the leakage current generated by the diode-connected transistor. Here, "to achieve" can be greater than or equal to.

[0050] In some embodiments, such as Figure 3 As shown, the voltage control unit 213 includes a first transistor NM7. The first terminal of the first transistor NM7 is connected to the power supply voltage Vin, the second terminal of the first transistor NM7 is connected to the first intermediate clock signal X1, and the control terminal of the first transistor NM7 is connected to the second intermediate clock signal X2.

[0051] It should be noted that for the same transistor, the first terminal can be either the source or the drain, the second terminal can be either the source or the drain, and the control terminal can be either the gate or the base. For example, when the first terminal is the source, the second terminal is the drain; or, when the first terminal is the drain, the second terminal is the source.

[0052] The first transistor NM7 is used to control the voltage of the first intermediate clock signal X1 to the power supply voltage Vin according to the second intermediate clock signal X2. Specifically, when the first transistor NM7 is turned on, the voltage of the first intermediate clock signal X1 is pulled up to the power supply voltage Vin. This is different from the first intermediate clock signal X1, which is the difference between the power supply voltage Vin and the threshold voltage, thus avoiding the loss of the threshold voltage. When the first transistor NM7 is turned off, it will not affect other parts.

[0053] In some embodiments, such as Figure 3 As shown, the voltage control unit 213 also includes a second transistor NM8. The first terminal of the second transistor NM8 is connected to the power supply voltage Vin, the second terminal of the second transistor NM8 is connected to the second intermediate clock signal X2, and the control terminal of the second transistor NM8 is connected to the first intermediate clock signal X1.

[0054] It should be noted that the second transistor NM8 is used to control the voltage of the second intermediate clock signal X2 to the power supply voltage Vin based on the first intermediate clock signal X1. Specifically, when the second transistor NM8 is turned on, the voltage of the second intermediate clock signal X2 is pulled up to the power supply voltage Vin. This is different from the voltage of the second intermediate clock signal X2, which is the difference between the power supply voltage Vin and the threshold voltage, thus avoiding the loss of the threshold voltage. When the second transistor NM8 is turned off, it will not affect other parts.

[0055] In some embodiments, both the first transistor NM7 and the second transistor NM8 are N-channel transistors. This allows the second transistor NM8 to pull the voltage of the second intermediate clock signal X2 to the power supply voltage Vin when the voltage of the first intermediate clock signal X1 is 2Vin; and the first transistor NM7 to pull the voltage of the first intermediate clock signal X1 to the power supply voltage Vin when the voltage of the second intermediate clock signal X2 is 2Vin.

[0056] In some embodiments, such as Figure 3As shown, the first intermediate clock generation unit 211 includes a third transistor NM6 and a first capacitor C1. The first terminal of the third transistor NM6 is connected to the control terminal of the third transistor NM6 and the first terminal of the first transistor NM7. The first terminal of the first capacitor C1 is connected to the second terminal of the third transistor NM6 and the second terminal of the first transistor NM7. The second terminal of the first capacitor C1 is connected to the first initial clock signal P1. The first terminal of the first capacitor C1 generates the first intermediate clock signal X1.

[0057] In some embodiments, such as Figure 3 As shown, the first intermediate clock generation unit 211 also includes a first inverter INV1. The input terminal of the first inverter INV1 is connected to the first initial clock signal P1, and the output terminal of the first inverter INV1 is connected to the second terminal of the first capacitor C1.

[0058] It should be noted that the third transistor NM6 is a low threshold voltage (LVT) N-channel field-effect transistor (MOS) using a diode connection. The gate-source voltage difference Vgs of the third transistor NM6 is shown below:

[0059] Vgs=Vth+Vod (2-1)

[0060] Among them, the Vth value of LVT MOS is relatively small, generally around 150mV.

[0061] The current calculation formula for the third transistor NM6 is as follows:

[0062]

[0063] By transforming Equation 2-1 and substituting it into Equation 2-2, we can obtain the calculation of the overdrive voltage, Vod.

[0064] Equation 2-3 is shown below:

[0065]

[0066] Where Id represents the transistor's leakage current, μ represents the carrier mobility, Cox represents the gate oxide capacitance per unit area, W / L represents the transistor's width-to-length ratio, Vth represents the transistor's threshold voltage, Vs represents the transistor's source voltage, and Vds represents the transistor's drain-source voltage.

[0067] When the current Id≈0, Vod≈0, that is, when it starts working, Vgs=Vds≈Vth, that is, Vs=Vin-Vth. The source voltage of the third transistor NM6 will be at Vin-Vth. When the first initial clock signal P1 and the second initial clock signal P2 are input at opposite fixed frequencies, due to the characteristics of the capacitor, that is, the voltage difference between the upper and lower plates of the capacitor cannot change abruptly (Q=C*V, where C represents the capacitance value and V represents the voltage difference between the upper and lower plates of the capacitor), the potential of Vs switches back and forth between Vin-Vth and 2Vin-Vth. Even though the design uses LVT MOS, it still cannot reach the expected amplitude potential of 2Vin, so there is a loss of Vth.

[0068] In this embodiment, when the voltage of the first initial clock signal P1 is a low voltage of 0V, the first inverter INV1 outputs a high voltage Vin. Since the voltage across the first capacitor C1, for example, Vin, does not change abruptly, this causes the voltage of the first intermediate clock signal X1 to become 2Vin. When the voltage of the first initial clock signal P1 is a high voltage of Vin, the first inverter INV1 outputs a low voltage of 0V. Since the voltage across the first capacitor C1, for example, Vin, does not change abruptly, this causes the voltage of the first intermediate clock signal X1 to become Vin. Compared to the voltage of the first intermediate clock signal X1 being Vin-Vth, by using the first transistor NM7 to set the voltage of the first intermediate clock signal X1 to Vin, the loss of Vth in the voltage of the first intermediate clock signal X1 is reduced, thereby allowing the low voltage and high voltage of the first intermediate clock signal X1 to reach Vin and 2Vin, respectively. Here, Vth refers to the threshold voltage of the third transistor NM6, and Vin refers to the power supply voltage Vin.

[0069] Furthermore, since the third transistor NM6 uses an LVT-based NMOS, Vth decreases. As shown in Equation 2-2, a decrease in Vth leads to an increase in Id, the leakage current. In this embodiment, the second intermediate clock signal X2 controls the first transistor NM7 to pull the source potential of the third transistor NM6 up to the power supply voltage Vin, thereby reducing the gate-source voltage difference of the third transistor NM6 from Vth to 0V. According to Equation 2-2, this reduces the leakage current generated by the diode-connected third transistor NM6, thus reducing overall power consumption.

[0070] In some embodiments, such as Figure 3As shown, the second intermediate clock generation unit 212 includes a fourth transistor NM9 and a second capacitor C2. The first terminal of the fourth transistor NM9 is connected to the control terminal of the fourth transistor NM9 and the first terminal of the second transistor NM8. The first terminal of the second capacitor C2 is connected to the second terminal of the fourth transistor NM9 and the second terminal of the second transistor NM8. The second terminal of the second capacitor C2 is connected to the second initial clock signal P2. The first terminal of the second capacitor C2 generates the second intermediate clock signal X2.

[0071] In some embodiments, such as Figure 3 As shown, the second intermediate clock generation unit 212 also includes a second inverter INV2. The input terminal of the second inverter INV2 is connected to the second initial clock signal P2, and the output terminal of the second inverter INV2 is connected to the second terminal of the second capacitor C2.

[0072] It should be noted that the operation of the fourth transistor NM9 is similar to that of the third transistor NM6. When the current Id≈0, Vod≈0, that is, when it starts working, Vgs=Vds≈Vth, that is, Vs=Vin-Vth. The source voltage of the fourth transistor NM9 will be at Vin-Vth. When the first initial clock signal P1 and the second initial clock signal P2 are input at opposite fixed frequencies, due to the characteristics of the capacitor, that is, the voltage difference between the upper and lower plates of the capacitor cannot change abruptly (Q=C*V, where C represents the capacitance value and V represents the voltage difference between the upper and lower plates of the capacitor), the potential of Vs switches back and forth between Vin-Vth and 2Vin-Vth. Even though this design uses LVT MOS, it still cannot reach the expected amplitude potential of 2Vin, so there is a loss of Vth.

[0073] In this embodiment, when the voltage of the second initial clock signal P2 is a low voltage of 0V, the second inverter INV2 outputs a high voltage Vin. Since the voltage across the second capacitor C2, for example, Vin, does not change abruptly, this causes the voltage of the second intermediate clock signal X2 to become 2Vin. When the voltage of the second initial clock signal P2 is a high voltage of Vin, the second inverter INV2 outputs a low voltage of 0V. Since the voltage across the second capacitor C2, for example, Vin, does not change abruptly, this causes the voltage of the second intermediate clock signal X2 to become Vin. Compared to the voltage of the second intermediate clock signal X2 being Vin-Vth, by using the second transistor NM8 to set the voltage of the second intermediate clock signal X2 to Vin, the loss of Vth in the voltage of the second intermediate clock signal X2 is reduced, thereby allowing the low voltage and high voltage of the second intermediate clock signal X2 to reach Vin and 2Vin, respectively. Here, Vth refers to the threshold voltage of the fourth transistor NM9, and Vin refers to the power supply voltage Vin.

[0074] Furthermore, since the fourth transistor NM9 uses an LVT-based NMOS, Vth decreases. As shown in Equation 2-2, a decrease in Vth leads to an increase in Id, the leakage current. In this embodiment, the first intermediate clock signal X1 controls the second transistor NM8 to pull the source potential of the fourth transistor NM9 up to the power supply voltage Vin, thereby reducing the gate-source voltage difference of the fourth transistor NM9 from Vth to 0V. According to Equation 2-2, this reduces the leakage current generated by the diode-connected fourth transistor NM9, thus reducing overall power consumption.

[0075] In some embodiments, the capacitance of the first capacitor C1 is the same as that of the second capacitor C2, so that the voltage across the first capacitor C1 is the same as that across the second capacitor C2, both being the power supply voltage Vin.

[0076] In some embodiments, such as Figure 3 As shown, the first intermediate clock signal X1 and the second intermediate clock signal X2 are out of phase. The voltage of the first intermediate clock signal X1 and the voltage of the second intermediate clock signal X2 are both greater than or equal to the power supply voltage Vin, and less than or equal to twice the power supply voltage Vin.

[0077] In some embodiments, the high voltage of the first intermediate clock signal X1 and the high voltage of the second intermediate clock signal X2 are both greater than or equal to N times the power supply voltage Vin, where N is an integer greater than or equal to 1.

[0078] It should be noted that the voltages of the first initial clock signal P1 and the second initial clock signal P2 can be increased by a boost circuit, and then the voltages across the corresponding capacitors can be superimposed to achieve a high voltage of the first intermediate clock signal X1 and a high voltage of the second intermediate clock signal X2 that are both greater than or equal to N times the power supply voltage Vin.

[0079] In some embodiments, such as Figure 3 As shown, the first target clock signal Φ1 and the second target clock signal Φ2 are out of phase. The voltage of the first target clock signal Φ1 and the voltage of the second target clock signal Φ2 are both greater than or equal to 0V and less than or equal to twice the power supply voltage Vin.

[0080] In some embodiments, the high voltage of the first target clock signal Φ1 and the high voltage of the second target clock signal Φ2 are both greater than or equal to N times the power supply voltage Vin, where N is an integer greater than or equal to 1.

[0081] In some embodiments, such as Figure 3As shown, the clock multiplier circuit 20 also includes a target clock generation module 22, which is connected to the intermediate clock generation module 21. It should be noted that the target clock generation module 22 is used to generate a first target clock signal Φ1 and a second target clock signal Φ2 based on the first intermediate clock signal X1 and the second intermediate clock signal X2.

[0082] In some embodiments, such as Figure 3 As shown, the target clock generation module 22 includes a first target clock generation unit 221, a second target clock generation unit 222, and a substrate effect elimination unit 223. The first target clock generation unit 221 is used to generate a first target clock signal Φ1 based on a second initial clock signal P2, a first intermediate clock signal X1, and a second intermediate clock signal X2. The second target clock generation unit 222 is used to generate a second target clock signal Φ2 based on the first initial clock signal P1, the first intermediate clock signal X1, and the second intermediate clock signal X2. The substrate effect elimination unit 223 is used to generate a substrate bias voltage Vb greater than the power supply voltage Vin based on the power supply voltage Vin, the first intermediate clock signal X1, and the second intermediate clock signal X2. The substrate bias voltage Vb is connected to at least one of the first target clock generation unit 221 and the second target clock generation unit 222.

[0083] It is understood that in this embodiment, the substrate effect elimination unit 223 generates a substrate bias voltage Vb greater than the power supply voltage Vin based on the power supply voltage Vin, the first intermediate clock signal X1, and the second intermediate clock signal X2, and connects it to at least one of the first target clock generation unit 221 and the second target clock generation unit 222. Compared with the P-channel transistors in the first target clock generation unit 221 and the second target clock generation unit 222, which use the power supply voltage Vin as the substrate voltage and have a higher on-resistance, the on-resistance of at least one of the first target clock generation unit 221 and the second target clock generation unit 222 can be reduced, thereby reducing the overall power consumption.

[0084] It should be noted that the substrate bias voltage Vb can be used to reduce the on-resistance of at least one of the first target clock generation unit 221 and the second target clock generation unit 222. Therefore, the substrate effect elimination unit 223 can mitigate or eliminate the substrate effect of the corresponding transistor.

[0085] In some embodiments, such as Figure 3As shown, the substrate effect elimination unit 223 includes a first field-effect transistor NM10 and a second field-effect transistor PM8. The first terminal of the first field-effect transistor NM10 is connected to the control terminal of the first field-effect transistor NM10 and connected to the power supply voltage Vin. The first terminal of the second field-effect transistor PM8 is connected to the second terminal of the first field-effect transistor NM10 and generates a substrate bias voltage Vb. The second terminal of the second field-effect transistor PM8 is connected to the first intermediate clock signal X1, and the control terminal of the second field-effect transistor PM8 is connected to the second intermediate clock signal X2.

[0086] It should be noted that the first field-effect transistor NM10 can be an N-channel field-effect transistor, such as a low threshold voltage field-effect transistor, which uses a diode connection to clamp the substrate bias voltage Vb between Vin and Vth, where Vth refers to the threshold voltage of the first field-effect transistor NM10. The second field-effect transistor PM8 is a P-channel field-effect transistor. The second field-effect transistor PM8 can increase the substrate bias voltage Vb to 2Vin according to the second intermediate clock signal X2 through the first intermediate clock signal X1. For example, when the voltage of the second intermediate clock signal X2 is Vin, the second field-effect transistor PM8 is turned on. At this time, the voltage of the first intermediate clock signal X1 is 2Vin. The first intermediate clock signal X1 of 2Vin is transmitted to the first terminal of the second field-effect transistor PM8, thereby increasing the substrate bias voltage Vb to 2Vin.

[0087] In some embodiments, such as Figure 3 As shown, the substrate effect elimination unit 223 also includes a third field-effect transistor PM9. The first terminal of the third field-effect transistor PM9 is connected to the second terminal of the first field-effect transistor NM10 and the first terminal of the second field-effect transistor PM8. The second terminal of the third field-effect transistor PM9 is connected to the second intermediate clock signal X2, and the control terminal of the third field-effect transistor PM9 is connected to the first intermediate clock signal X1.

[0088] It should be noted that the third field-effect transistor PM9 is a P-channel field-effect transistor. The third field-effect transistor PM9 can increase the substrate bias voltage Vb to 2Vin according to the first intermediate clock signal X1 and the second intermediate clock signal X2. For example, when the voltage of the first intermediate clock signal X1 is Vin, the third field-effect transistor PM9 is turned on. At this time, the voltage of the second intermediate clock signal X2 is 2Vin. The second intermediate clock signal X2 of 2Vin is transmitted to the first terminal of the third field-effect transistor PM9, thereby increasing the substrate bias voltage Vb to 2Vin.

[0089] The substrate effect elimination unit 223 may include at least one of the second field-effect transistor PM8 and the third field-effect transistor PM9. When only one of them is present, the substrate bias voltage Vb is not always kept at 2Vin, but switches between Vin and 2Vin, which can improve the substrate effect to a certain extent and thus reduce the on-resistance of the P-channel transistor. When the substrate effect elimination unit 223 may include the second field-effect transistor PM8 and the third field-effect transistor PM9, the second field-effect transistor PM8 and the third field-effect transistor PM9 can alternately keep the substrate bias voltage Vb at 2Vin, which can better improve the substrate effect, thereby reducing the on-resistance of the P-channel transistor and thus reducing the overall power consumption.

[0090] In some embodiments, such as Figure 3 As shown, the substrate effect elimination unit 223 also includes a fourth capacitor C3. The first end of the fourth capacitor C3 is connected to the second terminal of the first field-effect transistor NM10, the first terminal of the second field-effect transistor PM8, and the first terminal of the third field-effect transistor PM9. The second end of the fourth capacitor C3 is connected to the ground terminal GND.

[0091] It should be noted that the fourth capacitor C3 is optional. The fourth capacitor C3 can be used to filter and regulate the substrate bias voltage Vb, so that the substrate bias voltage Vb is more stably maintained at 2Vin. As the frequencies (f) of the first intermediate clock signal X1 and the second intermediate clock signal X2 increase, the switching frequency also increases, resulting in a larger ripple in the substrate bias voltage Vb. Therefore, the capacitance value of the fourth capacitor C3 is proportional to the frequencies of the first intermediate clock signal X1 and the second intermediate clock signal X2, which can reduce the ripple of the substrate bias voltage Vb, making the substrate bias voltage Vb more stable.

[0092] In some embodiments, the channel type of the first field-effect transistor NM10 is different from that of the second field-effect transistor PM8, and the channel type of the second field-effect transistor PM8 is the same as that of the third field-effect transistor PM9. For example, the first field-effect transistor NM10 can be an N-channel field-effect transistor, and the second field-effect transistor PM8 and the third field-effect transistor PM9 can both be P-channel field-effect transistors.

[0093] In some embodiments, such as Figure 3As shown, the first target clock generation unit 221 includes a fourth field-effect transistor PM11 and a fifth field-effect transistor NM12. The first terminal of the fourth field-effect transistor PM11 is connected to the second intermediate clock signal X2, the control terminal of the fourth field-effect transistor PM11 is connected to the first intermediate clock signal X1, and the substrate of the fourth field-effect transistor PM11 is connected to the substrate bias voltage Vb. The first terminal of the fifth field-effect transistor NM12 is connected to the second terminal of the fourth field-effect transistor PM11 to generate the first target clock signal Φ1. The control terminal of the fifth field-effect transistor NM12 is connected to the second initial clock signal P2, and the second terminal of the fifth field-effect transistor NM12 is connected to the ground terminal GND.

[0094] It should be noted that the fourth field-effect transistor PM11 is exemplarily a P-channel field-effect transistor, and the fifth field-effect transistor NM12 is exemplarily an N-channel field-effect transistor.

[0095] For PMOS, the leakage current, Id, is calculated using the following formula (3-1):

[0096]

[0097] If the PMOS substrate (body terminal) is connected to a power supply voltage Vin, and the drain and source terminals transmit a voltage of 2Vin, the body effect (Vsb > 0) causes |Vth| to decrease. According to Equation 3-1, the leakage current (Id) increases, and the power consumption increases. Here, Vsb is the voltage between the substrate and the source; |Vth| represents the absolute value of the PMOS threshold voltage; and |Vgs| represents the absolute value of the PMOS gate-source voltage difference.

[0098] When the first intermediate clock signal X1 is high (2Vin), the second intermediate clock signal X2 is low (Vin), and the fourth field-effect transistor PM11 is off. At this time, the second initial clock signal P2 is high (Vin), the fifth field-effect transistor NM12 is on, and the first target clock signal Φ1 is low (0V). (The reverse is repeated in the original text.)

[0099] Since the fourth field-effect transistor PM11 is connected to a substrate bias voltage Vb of 2Vin, compared to the substrate bias voltage Vb connected to Vin, the body effect is reduced, which increases the absolute value of the threshold voltage, thereby reducing the on-resistance and leakage current, and thus reducing power consumption.

[0100] In some embodiments, such as Figure 3As shown, the second target clock generation unit 222 includes a sixth field-effect transistor PM10 and a seventh field-effect transistor NM11. The first terminal of the sixth field-effect transistor PM10 is connected to the first intermediate clock signal X1, the control terminal of the sixth field-effect transistor PM10 is connected to the second intermediate clock signal X2, and the substrate of the sixth field-effect transistor PM10 is connected to the substrate bias voltage Vb. The first terminal of the seventh field-effect transistor NM11 is connected to the second terminal of the sixth field-effect transistor PM10 to generate the second target clock signal Φ2. The control terminal of the seventh field-effect transistor NM11 is connected to the first initial clock signal P1, and the second terminal of the seventh field-effect transistor NM11 is connected to the ground terminal GND.

[0101] It should be noted that, since the sixth field-effect transistor PM10 is exemplarily a P-channel field-effect transistor, if the substrate (body terminal) is connected to a power supply voltage Vin, and the drain (drain terminal) and source (source terminal) transmit a voltage of 2Vin, the body effect (Vsb > 0) causes |Vth| to decrease. According to calculation formula 3-1, the leakage current Id increases, and the power consumption increases. Here, Vsb is the voltage between the substrate and the source; |Vth| represents the absolute value of the PMOS threshold voltage; and |Vgs| represents the absolute value of the PMOS gate-source voltage difference. The seventh field-effect transistor NM11 is exemplarily an N-channel field-effect transistor.

[0102] When the first intermediate clock signal X1 is high (2Vin), the second intermediate clock signal X2 is low (Vin), and the sixth field-effect transistor PM10 is turned on. At this time, the first initial clock signal P1 is low (0V), the seventh field-effect transistor NM11 is turned off, and the second target clock signal Φ2 is high (2Vin). (This is repeated twice in the original text.)

[0103] Since the sixth field-effect transistor PM10 is connected to a substrate bias voltage Vb of 2Vin, compared with the substrate bias voltage Vb connected to Vin, the body effect is reduced, which increases the absolute value of the threshold voltage, thereby reducing the on-resistance and leakage current, and thus reducing power consumption.

[0104] In some embodiments, such as Figure 4As shown, this application embodiment also provides a gate XTM, which includes a first transmission transistor M1 and a second transmission transistor M2. The first terminal of the first transmission transistor M1 is connected to the first terminal of the second transmission transistor M2, and the second terminal of the first transmission transistor M1 is connected to the second terminal of the second transmission transistor M2. The control terminal of the first transmission transistor M1 is connected to one of a first target clock signal Φ1 and a second target clock signal Φ2. The substrate of the first transmission transistor M1 is connected to the ground terminal GND. The control terminal of the second transmission transistor M2 is connected to the other of the first target clock signal Φ1 and the second target clock signal Φ2. The substrate of the second transmission transistor M2 is connected to a substrate bias voltage Vb. The first target clock signal Φ1 is connected to the ground terminal GND.

[0105] 1. The second target clock signal Φ2 is out of phase; the substrate bias voltage Vb is greater than or equal to N times the power supply voltage, where N is an integer greater than 1.

[0106] It is understood that by applying a power supply voltage Vin greater than or equal to N times to the substrate of the second transmission transistor M2 as the substrate bias voltage Vb, the influence of the body effect can be reduced, thereby reducing the on-resistance and leakage current of the second transmission transistor M2, and thus reducing the overall power consumption.

[0107] When the voltage of the first target clock signal Φ1 is 2Vin, the voltage of the second target clock signal Φ2 is 0V. At this time, both the first transmission transistor M1 and the second transmission transistor M2 are turned on, and they can be connected in parallel, thereby further reducing the impedance of the branch. When the voltage of the first target clock signal Φ1 is 0V, the voltage of the second target clock signal Φ2 is 2Vin, and both the first transmission transistor M1 and the second transmission transistor M2 are turned off.

[0108] It should be noted that the first transmission transistor M1 is an N-channel field-effect transistor, and the second transmission transistor M2 is a P-channel field-effect transistor. In this embodiment, the substrate bias voltage Vb can be generated by the substrate effect elimination unit 223 or directly provided by a DC power supply.

[0109] In some embodiments, such as Figure 5 As shown, the emitter voltage generation circuit 30 includes a first emitter voltage generation module 31, which includes a first switched capacitor unit 311 and a first clamping unit 312. The first switched capacitor unit 311 is connected to the first clamping unit 312.

[0110] It should be noted that the first switched capacitor unit 311 is used to generate a first voltage based on the power supply voltage Vin, the first target clock signal Φ1 and the second target clock signal Φ2; the first clamping unit 312 is used to clamp the first voltage as the first emitter voltage VEB1.

[0111] Compared to the first emitter voltage generation module 31, which requires three clock signals, this embodiment can generate the required first emitter voltage VEB1 by using only two clock signals: the first target clock signal Φ1 and the second target clock signal Φ2. This reduces the number of clock signals and simplifies the circuit structure.

[0112] In some embodiments, such as Figure 5 As shown, the first switched capacitor unit 311 includes a first switch S1, a second switch S2, a third switch S3, a fourth switch S4, and a fifth capacitor CE1. The first terminal of the first switch S1 is connected to the first terminal of the second switch S2 and connected to the power supply voltage Vin. The second terminal of the first switch S1 is connected to the first terminal of the fifth capacitor CE1 and the first terminal of the fourth switch S4. The second terminal of the second switch S2 is connected to the second terminal of the fifth capacitor CE1 and the first terminal of the third switch S3. The second terminal of the third switch S3 is connected to the ground terminal GND. The second terminal of the fourth switch S4 is connected to the first clamping unit 312.

[0113] It should be noted that when at least one of the first switch S1 and the third switch S3 is a gate XTM, the control electrode of the first transmission tube M1 is connected to the second target clock signal Φ2, and the control electrode of the second transmission tube M2 is connected to the first target clock signal Φ1; when at least one of the second switch S2 and the fourth switch S4 is a gate XTM, the control electrode of the first transmission tube M1 is connected to the first target clock signal Φ1, and the control electrode of the second transmission tube M2 is connected to the second target clock signal Φ2.

[0114] Among them, the first transmission tube M1 and the second transmission tube M2 are synchronously turned on or off.

[0115] Since at least one of the first switch S1, the second switch S2, the third switch S3, and the fourth switch S4 employs a gating gate XTM, it is beneficial to further reduce impedance and leakage current, thereby reducing overall power consumption.

[0116] When the voltage of the first target clock signal Φ1 is 2Vin and the voltage of the second target clock signal Φ2 is 0V, the first switch S1 and the third switch S3 are both turned on, the second switch S2 and the fourth switch S4 are both turned off, the voltage of the upper plate of the fifth capacitor CE1 is the power supply voltage Vin, and the voltage of the lower plate of the fifth capacitor CE1 is 0V; when the voltage of the first target clock signal Φ1 is 0V and the voltage of the second target clock signal Φ2 is 2Vin, the first switch S1 and the third switch S3 are both turned off, the second switch S2 and the fourth switch S4 are both turned on, the voltage of the upper plate of the fifth capacitor CE1 is 2Vin, and the voltage of the lower plate of the fifth capacitor CE1 is the power supply voltage Vin.

[0117] In some embodiments, such as Figure 5As shown, the first clamping unit 312 includes a first transistor Q1 and a capacitor CS1. The emitter of the first transistor Q1 is connected to the second terminal of the fourth switch S4 and the first terminal of the capacitor CS1 and outputs a first emitter voltage VEB1. The second terminal of the capacitor CS1 is connected to the ground terminal GND. The base of the first transistor Q1 is connected to the collector of the first transistor Q1 and the ground terminal GND.

[0118] It should be noted that since the first transistor Q1 is connected in a diode configuration, the first voltage can be clamped to the emitter voltage of the first transistor Q1, thereby generating the first emitter voltage VEB1.

[0119] In some embodiments, such as Figure 5 As shown, the emitter voltage generation circuit 30 also includes a second emitter voltage generation module 32, which includes a second switched capacitor unit 321 and a second clamping unit 322. The second switched capacitor unit 321 is connected to the second clamping unit 322.

[0120] It should be noted that the second switched capacitor unit 321 is used to generate a second voltage based on the power supply voltage Vin, the first target clock signal Φ1 and the second target clock signal Φ2; the second clamping unit 322 is used to clamp the second voltage as the second emitter voltage VEB2.

[0121] Compared to the second emitter voltage generation module 32, which requires three clock signals, this embodiment can generate the required second emitter voltage VEB2 by using only two clock signals: the first target clock signal Φ1 and the second target clock signal Φ2. This reduces the number of clock signals and simplifies the circuit structure.

[0122] In some embodiments, such as Figure 5 As shown, the second switched capacitor unit 321 includes a fifth switch S5, a sixth switch S6, a seventh switch S7, an eighth switch S8, and a sixth capacitor CE2. The first terminal of the fifth switch S5 is connected to the first terminal of the sixth switch S6 and connected to the power supply voltage Vin. The second terminal of the fifth switch S5 is connected to the first terminal of the sixth capacitor CE2 and the first terminal of the eighth switch S8. The second terminal of the sixth switch S6 is connected to the second terminal of the sixth capacitor CE2 and the first terminal of the seventh switch S7. The second terminal of the seventh switch S7 is connected to the ground terminal GND. The second terminal of the eighth switch S8 is connected to the second clamping unit 322.

[0123] It should be noted that when at least one of the fifth switch S5 and the seventh switch S7 is a gating gate XTM, the control electrode of the first transmission tube M1 is connected to the second target clock signal Φ2, and the control electrode of the second transmission tube M2 is connected to the first target clock signal Φ1; when at least one of the sixth switch S6 and the eighth switch S8 is a gating gate XTM, the control electrode of the first transmission tube M1 is connected to the first target clock signal Φ1, and the control electrode of the second transmission tube M2 is connected to the second target clock signal Φ2.

[0124] Since at least one of the fifth switch S5, the sixth switch S6, the seventh switch S7 and the eighth switch S8 uses a gating gate XTM, it is beneficial to further reduce impedance and leakage current, thereby reducing overall power consumption.

[0125] When the voltage of the first target clock signal Φ1 is 2Vin and the voltage of the second target clock signal Φ2 is 0V, the fifth switch S5 and the seventh switch S7 are both turned on, and the sixth switch S6 and the eighth switch S8 are both turned off. The voltage of the upper plate of the sixth capacitor CE2 is the power supply voltage Vin, and the voltage of the lower plate of the sixth capacitor CE2 is 0V.

[0126] In some embodiments, such as Figure 5 As shown, the second clamping unit 322 includes a second transistor Q2 and a capacitor CS2. The emitter of the second transistor Q2 is connected to the second terminal of the eighth switch S8 and the first terminal of the capacitor CS2 and outputs a second emitter voltage VEB2. The second terminal of the capacitor CS2 is connected to the ground terminal GND. The base of the second transistor Q2 is connected to the collector of the second transistor Q2 and the ground terminal GND.

[0127] It should be noted that since the second transistor Q2 is connected in a diode configuration, the second voltage can be clamped to the emitter voltage of the second transistor Q2, thereby generating the first emitter voltage VEB1.

[0128] In some embodiments, such as Figure 6 and Figure 7 As shown, the switched capacitor circuit 40 includes a base voltage generation module 41, a voltage regulation module 42, and a voltage output module 43. The base voltage generation module 41 is connected to the voltage output module 43 through the voltage regulation module 42.

[0129] It should be noted that the base voltage generation module 41 is used to generate a base voltage based on the first target clock signal Φ1, the second target clock signal Φ2, and the first emitter voltage VEB1; the voltage regulation module 42 is used to generate an adjustable voltage based on the first target clock signal Φ1, the second target clock signal Φ2, and the second emitter voltage VEB2; and the voltage output module 43 is used to output a voltage related to the base voltage and the adjustable voltage as a reference voltage VREF based on the first target clock signal Φ1.

[0130] In some embodiments, such as Figure 6 and Figure 7 As shown, the voltage regulation module 42 includes a first electronic switch K1 and a multi-stage voltage regulation unit. The first terminal of the first electronic switch K1 is connected to the second emitter voltage VEB2, and the control terminal of the first electronic switch K1 is connected to the second target clock signal Φ2. The multi-stage voltage regulation unit is connected to the base voltage generation module 41, the voltage output module 43, and the second terminal of the first electronic switch K1.

[0131] In some embodiments, at least one of the switches in the switched capacitor circuit 40 is a gating gate XTM. This helps to further reduce impedance and leakage current, thereby reducing overall power consumption.

[0132] It should be noted that, in Figure 6 In this configuration, the multi-stage voltage regulation unit comprises n-stage voltage regulation units connected in sequence, where n is an integer greater than 1. For example, there is a first-stage voltage regulation unit 421, a second-stage voltage regulation unit 422, ..., an (n-1)th-stage voltage regulation unit 42n-1, and an nth-stage voltage regulation unit 42n. As the order of the voltage regulation unit increases, the adjustable range of the reference voltage VREF also increases.

[0133] Figure 7 An embodiment with n=4 is shown. In this case, the n-stage voltage regulating units connected in sequence include a first-stage voltage regulating unit 421, a second-stage voltage regulating unit 422, a third-stage voltage regulating unit 423, and a fourth-stage voltage regulating unit 424.

[0134] In some embodiments, such as Figure 6 and Figure 7 As shown, the voltage regulation unit includes a second electronic switch K2, a third electronic switch K3, and a third capacitor Cb. The first terminal of the second electronic switch K2 is connected to the base voltage generation module 41, the control terminal of the second electronic switch K2 is connected to the first target clock signal Φ1, and the second terminal of the second electronic switch K2 is connected to the second terminal of the first electronic switch K1. The first terminal of the third electronic switch K3 is connected to the first terminal of the second electronic switch K2, and the control terminal of the third electronic switch K3 is connected to the second target clock signal Φ2. The first terminal of the third capacitor Cb is connected to the second terminal of the third electronic switch K3, and the second terminal of the third capacitor Cb is connected to the second terminal of the second electronic switch K2.

[0135] In some embodiments, the capacitance value of the third capacitor Cb in each voltage regulating unit is the same. At least one of the first electronic switch K1, the second electronic switch K2, and the third electronic switch K3 can be a gate XTM, which helps to further reduce impedance and leakage current, thereby reducing overall power consumption.

[0136] In some embodiments, such as Figure 6 and Figure 7 As shown, the voltage output module 43 includes a switch K4 and a capacitor CREF. The first end of the switch K4 is connected to the voltage regulation module 42. The control end of the switch K4 is connected to the first target clock signal Φ1. The second end of the switch K4 is connected to the first end of the capacitor CREF and outputs the reference voltage VREF. The second end of the capacitor CREF is connected to the ground terminal GND.

[0137] In some embodiments, such as Figure 6 and Figure 7 As shown, the base voltage generation module 41 includes switches K5, K6, and K7, capacitors Ca1 and Ca2. The first terminal of switch K5 is connected to the first terminal of switch K6 and the first terminal of capacitor Ca1. The second terminal of switch K5 is connected to the second terminal of capacitor Ca1 and the ground terminal GND. The control terminal of switch K5 is connected to the second target clock signal Φ2. The second terminal of switch K6 is connected to the first terminal of capacitor Ca2, the first terminal of switch K7, and the voltage regulation module 42. The second terminal of capacitor Ca2 is connected to the ground terminal GND. The control terminal of switch K6 is connected to the first target clock signal Φ1. The control terminal of switch K7 is connected to the second target clock signal Φ2. The second terminal of switch K7 is connected to the first emitter voltage VEB1.

[0138] like Figure 7 As shown, when the first target clock signal Φ1 is at a high level of 2Vin and the second target clock signal Φ2 is at a low level of 0V, the second electronic switches K2, K4, and K6 connected to the first target clock signal Φ1 are all open, while the first electronic switches K1, K3, K5, and K7 connected to the second target clock signal Φ2 are all closed. Figure 7 The switched capacitor circuit 40 shown can be simplified as follows: Figure 8 The upper half of the circuit is shown in the figure. The charge in the upper half of the circuit is Q(Φ).

[0139] 1=2Vin, Φ2=0)=Ca2×VEB1+4×Cb(VEB1-VEB2).

[0140] like Figure 7As shown, when the first target clock signal Φ1 is low (0V) and the second target clock signal Φ2 is high (2Vin), the second electronic switches K2, K4, and K6 connected to the first target clock signal Φ1 are all turned on, while the first electronic switches K1, K3, K5, and K7 connected to the second target clock signal Φ2 are all turned off. Figure 7 The switched capacitor circuit 40 shown can be simplified as follows: Figure 8 The lower half of the circuit is shown. The charge in this lower half of the circuit is Q(Φ1=0,Φ...).

[0141] 2 = 2Vin) is as follows:

[0142] Q(Φ1=0, Φ2=2Vin)=VREF×((Ca1+Ca2) / / (Cb / 4) / / (CREF)).

[0143] According to the law of conservation of charge, Q(Φ1=2Vin,Φ2=0)=Q(Φ1=0,Φ2=2Vin). Substituting these values ​​and making changes, we can obtain the reference voltage VREF as shown below:

[0144] VREF=(Ca2×VEB1+4×Cb×(VEB1-VEB2)) / ((Ca1+Ca2) / / (Cb / 4) / / (CREF)).

[0145] In this diagram, " / / " indicates a parallel connection, and the capacitance value is calculated based on the parallel connection of the capacitors. "×" indicates multiplication, " / " indicates division, and "-" indicates subtraction. Ca1 represents the capacitance value of capacitor Ca1, Ca2 represents the capacitance value of capacitor Ca2, Cb represents the capacitance value of the third capacitor Cb, and CREF represents the capacitance value of capacitor CREF. VEB1 represents the potential of the first emitter voltage VEB1, and VEB2 represents the potential of the second emitter voltage VEB2.

[0146] Please continue reading. Figure 6 When the voltage regulation module 42 includes an n-order voltage regulation unit, and the first target clock signal Φ1 is a high level of 2Vin and the second target clock signal Φ2 is a low level of 0V, Figure 6 The charge Q (Φ1=2Vin, Φ2=0) of the switched capacitor circuit 40 shown is as follows:

[0147] Q(Φ1=2Vin, Φ2=0)=Ca2×VEB1+n×Cb(VEB1-VEB2).

[0148] When the first target clock signal Φ1 is low (0V) and the second target clock signal Φ2 is high (2Vin), Figure 6The charge Q (Φ1=0, Φ2=2Vin) of the switched capacitor circuit 40 shown is as follows:

[0149] Q(Φ1=0, Φ2=2Vin)=VREF×((Ca1+Ca2) / / (Cb / n) / / (CREF)).

[0150] According to the law of conservation of charge, Q(Φ1=2Vin,Φ2=0)=Q(Φ1=0,Φ2=2Vin). Substituting these values ​​and making changes, we can obtain the reference voltage VREF as shown below:

[0151] VREF=(Ca2×VEB1+n×Cb×(VEB1-VEB2)) / ((Ca1+Ca2) / / (Cb / n) / / (CREF)).

[0152] Let VEB1-VEB2=ΔVEB. After simplifying the coefficients of VEB1 and ΔVEB, we can obtain VREF=A×VEB1+B×ΔVEB.

[0153] It should be noted that at least one of switches K4, K5, K6 and K7 can be a gating gate XTM, which helps to further reduce impedance and leakage current, thereby reducing overall power consumption.

[0154] Extending the voltage regulation unit by an nth order allows for better adjustment of the reference voltage VREF to the target value, which is beneficial for meeting usage requirements. In actual circuit design, the value of n is determined by the designer based on the size and area of ​​the reference circuit 100. The larger the value of n, the larger the reference voltage VREF, and the larger the capacitance values ​​of the fifth capacitor CE1 and the sixth capacitor CE2 are required to provide more charge. The driving capability of the clock voltage multiplier circuit 20 also needs to be greater, and the overall power consumption is also greater.

[0155] Figure 9 This diagram illustrates the relationship between the reference voltage VREF and temperature, as provided in an embodiment of this application. By example, with the power supply voltage Vin set to 1.1V, when the temperature varies within the range of -40 to 125°C, the reference voltage VREF varies between 0.2607V and 0.2649V. The maximum voltage change of the reference voltage VREF, ΔV = 0.2649V - 0.2607V, is approximately 4.2mV. This demonstrates that the reference voltage VREF provided in this application has extremely low sensitivity to temperature changes and exhibits excellent stability and reliability under extreme temperature conditions, making it particularly suitable for applications with stringent accuracy requirements.

[0156] Figure 10This is a schematic diagram showing the relationship between the power supply voltage Vin, the average current, and the reference voltage VREF provided in the embodiments of this application. Figure 11 This diagram illustrates the process of establishing different reference voltages as provided in the embodiments of this application. The average current is the average current in the reference circuit 100 connected to the corresponding power supply voltage Vin.

[0157] from Figure 10 It can be seen that as the power supply voltage Vin increases from 0.4V to 1.21V, the average current increases from 32.09nA to 1241nA, and the reference voltage VREF changes from 0.403V to 0.2686V. The point value of the reference voltage VREF is... Figure 11 The average value of the stable portion of each corresponding curve.

[0158] exist Figure 11 In the figure, the six curves from bottom to top show the process of establishing the reference voltage VREF when the power supply voltage Vin is 0.4V, 0.5V, 0.6V, 0.99V, 1.1V, and 1.21V.

[0159] When the power supply voltage Vin is 0.4V, then as follows: Figure 10 The average current shown is 32.09 nA, and the reference voltage VREF can still be established (as shown). Figure 11 (The first curve from bottom to top). This shows that the reference circuit 100 can still operate even when the power supply voltage Vin is low or at a low voltage.

[0160] Figure 12 A schematic diagram of voltage changes at some nodes of the reference circuit 100 provided in an embodiment of this application.

[0161] The data, from top to bottom, represent the voltage variations of the reference voltage VREF, the first initial clock signal P1, the first target clock signal Φ1, the second target clock signal Φ2, the substrate bias voltage Vb, the first emitter voltage VEB1, and the second emitter voltage VEB2.

[0162] At any given moment, the voltage of the first emitter voltage VEB1 can be higher than the voltage of the second emitter voltage VEB2. The reference voltage VREF can be maintained at a stable voltage value. The substrate bias voltage Vb can be maintained at a voltage value of 2Vin.

[0163] In some embodiments, such as Figure 13 As shown, this application embodiment also provides a chip 200, which includes the aforementioned reference circuit 100. It should be noted that the chip 200 may be, but is not limited to, a memory chip such as Nor Flash, or other integrated circuits suitable for use with the reference circuit 100, such as an MCU.

[0164] It is understood that since the chip 200 provided in this embodiment includes the aforementioned reference circuit 100, it can also generate a first intermediate clock signal X1 based on the power supply voltage Vin and the first initial clock signal P1, and generate a second intermediate clock signal X2 based on the power supply voltage Vin and the second initial clock signal P2. The voltage control unit 213 controls at least one of the first intermediate clock signal X1 and the second intermediate clock signal X2 to reach the power supply voltage Vin. This avoids the diode connection from clamping the low voltage of the clock signal to the potential difference between the power supply voltage Vin and the threshold voltage. As a result, the high voltage of the clock signal can be doubled to reach twice the power supply voltage Vin.

[0165] Since the voltage of at least one of the first intermediate clock signal X1 and the second intermediate clock signal X2 is controlled to the power supply voltage Vin by the voltage control unit 213, the gate-source voltage difference of the diode-connected transistor can be made equal to 0V, thereby reducing the leakage current generated by the diode-connected transistor.

[0166] The substrate effect elimination unit 223 generates a substrate bias voltage Vb that is greater than the power supply voltage Vin based on the power supply voltage Vin, the first intermediate clock signal X1, and the second intermediate clock signal X2. Compared with the P-channel transistors in the first target clock generation unit 221 and the second target clock generation unit 222, which use the power supply voltage Vin as the substrate voltage, the P-channel transistors have higher on-resistance. This can reduce the on-resistance of at least one of the first target clock generation unit 221 and the second target clock generation unit 222, thereby reducing the overall power consumption.

[0167] By applying a substrate bias voltage Vb to the substrate of the second transmission transistor M2 with a voltage greater than or equal to twice the power supply voltage Vin, the influence of the bulk effect can be reduced, thereby reducing the on-resistance and leakage current of the second transmission transistor M2, and thus reducing the overall power consumption.

[0168] In the above embodiments, the descriptions of each embodiment have different focuses. For parts not described in detail in a certain embodiment, please refer to the relevant descriptions in other embodiments.

[0169] The gating gate XTM, reference circuit 100, and chip 200 provided in the embodiments of this application have been described in detail above. Specific examples have been used to illustrate the principles and implementation methods of this application. The descriptions of the above embodiments are only for the purpose of helping to understand the technical solutions and core ideas of this application. Those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. These modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of this application.

Claims

1. A gating gate, characterized in that, The gate includes a first transmission tube and a second transmission tube. The first terminal of the first transmission tube is connected to the first terminal of the second transmission tube, and the second terminal of the first transmission tube is connected to the second terminal of the second transmission tube. The control terminal of the first transmission tube is connected to one of the first target clock signal and the second target clock signal. The substrate of the first transmission tube is connected to the ground terminal. The control terminal of the second transmission tube is connected to the other of the first target clock signal and the second target clock signal. The substrate of the second transmission tube is connected to the substrate bias voltage. Wherein, the first target clock signal is out of phase with the second target clock signal; the substrate bias voltage is greater than or equal to N times the power supply voltage, where N is an integer greater than 1.

2. The gate according to claim 1, characterized in that, The first transmission transistor is an N-channel field-effect transistor, and the second transmission transistor is a P-channel field-effect transistor.

3. The gate according to claim 1, characterized in that, The substrate bias voltage is generated by a substrate effect elimination unit, which includes: The first field-effect transistor, wherein the first terminal of the first field-effect transistor is connected to the control terminal of the first field-effect transistor and is connected to the power supply voltage; The second field-effect transistor has its first terminal connected to the second terminal of the first field-effect transistor to generate the substrate bias voltage. The second terminal of the second field-effect transistor is connected to a first intermediate clock signal, and the control terminal of the second field-effect transistor is connected to a second intermediate clock signal.

4. The gate according to claim 3, characterized in that, The substrate effect elimination unit further includes a third field-effect transistor. The first terminal of the third field-effect transistor is connected to the second terminal of the first field-effect transistor and the first terminal of the second field-effect transistor. The second terminal of the third field-effect transistor is connected to the second intermediate clock signal, and the control terminal of the third field-effect transistor is connected to the first intermediate clock signal.

5. The gate according to claim 4, characterized in that, The substrate effect elimination unit further includes a fourth capacitor, the first end of which is connected to the second terminal of the first field-effect transistor, the first terminal of the second field-effect transistor, and the first terminal of the third field-effect transistor, and the second end of which is connected to the ground terminal.

6. The gate according to claim 4, characterized in that, The channel type of the first field-effect transistor is different from that of the second field-effect transistor, and the channel type of the second field-effect transistor is the same as that of the third field-effect transistor.

7. The gate according to any one of claims 3-6, characterized in that, The first target clock signal is generated by the first target clock generation unit, and the second target clock signal is generated by the second target clock generation unit. The first target clock generation unit and the second target clock generation unit are respectively connected to the substrate effect elimination unit.

8. The gate according to any one of claims 1-6, characterized in that, The voltage of the first target clock signal and the voltage of the second target clock signal are both greater than or equal to 0V and less than or equal to twice the power supply voltage.

9. A reference circuit, characterized in that, The reference circuit includes a gating gate as described in any one of claims 1-8.

10. The reference circuit according to claim 9, characterized in that, The reference circuit also includes: A clock oscillation circuit is used to generate a first initial clock signal and a second initial clock signal. A clock multiplier circuit is used to generate the first target clock signal and the second target clock signal based on the first initial clock signal and the second initial clock signal; Emitter voltage generation circuit, used to generate a first emitter voltage and a second emitter voltage according to the first target clock signal and the second target clock signal; A switched capacitor circuit is used to generate a reference voltage based on the first target clock signal, the second target clock signal, the first emitter voltage, and the second emitter voltage.

11. The reference circuit according to claim 10, characterized in that, The emitter voltage generating circuit includes a first emitter voltage generating module, which includes: The first switched capacitor unit is used to generate a first voltage based on the power supply voltage, the first target clock signal, and the second target clock signal; The first clamping unit is used to clamp the first voltage as the first emitter voltage.

12. The reference circuit according to claim 11, characterized in that, The first switched capacitor unit includes a first switch, a second switch, a third switch, a fourth switch, and a fifth capacitor. The first terminal of the first switch is connected to the first terminal of the second switch and is connected to the power supply voltage. The second terminal of the first switch is connected to the first terminal of the fifth capacitor and the first terminal of the fourth switch. The second terminal of the second switch is connected to the second terminal of the fifth capacitor and the first terminal of the third switch. The second terminal of the third switch is connected to the ground terminal. The second terminal of the fourth switch is connected to the first clamping unit. Wherein, when at least one of the first switch and the third switch is the gate, the control electrode of the first transmission tube is connected to the second target clock signal, and the control electrode of the second transmission tube is connected to the first target clock signal; When at least one of the second switch and the fourth switch is the gate, the control electrode of the first transmission tube is connected to the first target clock signal, and the control electrode of the second transmission tube is connected to the second target clock signal.

13. The reference circuit according to claim 10, characterized in that, The emitter voltage generating circuit further includes a second emitter voltage generating module, which includes: The second switched capacitor unit is used to generate a second voltage based on the power supply voltage, the first target clock signal, and the second target clock signal; The second clamping unit is used to clamp the second voltage as the second emitter voltage.

14. The reference circuit according to claim 13, characterized in that, The second switched capacitor unit includes a fifth switch, a sixth switch, a seventh switch, an eighth switch, and a sixth capacitor. The first terminal of the fifth switch is connected to the first terminal of the sixth switch and is connected to the power supply voltage. The second terminal of the fifth switch is connected to the first terminal of the sixth capacitor and the first terminal of the eighth switch. The second terminal of the sixth switch is connected to the second terminal of the sixth capacitor and the first terminal of the seventh switch. The second terminal of the seventh switch is connected to the ground terminal. The second terminal of the eighth switch is connected to the second clamping unit. Wherein, when at least one of the fifth switch and the seventh switch is the gate, the control electrode of the first transmission tube is connected to the second target clock signal, and the control electrode of the second transmission tube is connected to the first target clock signal; When at least one of the sixth switch and the eighth switch is the gate, the control electrode of the first transmission tube is connected to the first target clock signal, and the control electrode of the second transmission tube is connected to the second target clock signal.

15. The reference circuit according to claim 10, characterized in that, The switched capacitor circuit includes: A base voltage generation module is used to generate a base voltage based on the first target clock signal, the second target clock signal, and the first emitter voltage. The voltage regulation module is used to generate an adjustable voltage based on the first target clock signal, the second target clock signal, and the second emitter voltage; A voltage output module is used to output a voltage related to the base voltage and the adjustable voltage as the reference voltage according to the first target clock signal.

16. The reference circuit according to claim 15, characterized in that, The voltage regulating module includes: A first electronic switch, wherein a first terminal of the first electronic switch is connected to the second emitter voltage, and a control terminal of the first electronic switch is connected to the second target clock signal; An n-order voltage regulating unit is connected to the base voltage generating module, the voltage output module, and the second terminal of the first electronic switch. Each voltage regulating unit includes: A second electronic switch, the first end of which is connected to the base voltage generating module, the control end of which is connected to the first target clock signal, and the second end of which is connected to the second end of the first electronic switch; A third electronic switch, wherein the first end of the third electronic switch is connected to the first end of the second electronic switch, and the control end of the third electronic switch is connected to the second target clock signal; The third capacitor has its first terminal connected to the second terminal of the third electronic switch, and its second terminal connected to the second terminal of the second electronic switch.

17. The reference circuit according to claim 15, characterized in that, At least one of the switches in the switched capacitor circuit is the gating gate.

18. A chip, characterized in that, The chip includes a reference circuit as described in any one of claims 9-17.

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