True rail-to-rail input and output reference voltage buffer circuit suitable for high-precision ADC

Abstract

The invention provides a true rail-to-rail input and output reference voltage buffer circuit suitable for a high-precision ADC (Analog to Digital Converter). When the circuit works, a sampling phase F1 and a holding phase F2 are alternately executed; according to the circuit, a sampling capacitor Cs tracks input reference voltage on a bottom plate of a sampling phase F1, and a top plate is reset to the ground; the level shifting capacitor CLVL synchronously samples the difference value between the input reference voltage and the output common-mode voltage of the transconductance operational amplifier OTA at the sampling phase F1, and is connected to the output end of the transconductance operational amplifier OTA at the holding phase F2, so that the true rail-to-rail range expansion of the output voltage is realized; the charge of the feedback capacitor Cf is not reset at a sampling phase F1, the feedback capacitor Cf is connected with the sampling capacitor Cs in parallel at a holding phase F2, and the establishment of output voltage is realized through charge averaging; the switch network is used for controlling the capacitor connection state of the sampling phase F1 and the holding phase F2. According to the embodiment of the invention, real rail-to-rail input and output and high equivalent input impedance can be realized.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of integrated circuit design, in particular to a true rail-to-rail input and output reference voltage buffer circuit suitable for high-precision ADC. BACKGROUND

[0002] High-precision ADC is a core component in precision instruments, power management and medical electronic devices, etc. applications, responsible for weak signal detection in the system. High-precision ADC usually adopts two kinds of switched capacitor structures of sigma-delta type ADC and SAR type ADC, and its working principle is as follows: in the sampling phase of ADC, the input signal is tracked by the sampling capacitor inside the ADC, and the input signal is sampled at the falling edge. In the conversion phase (i.e. holding phase) of ADC, the internal D / A capacitor array of ADC is connected to the reference voltage, and the input signal sampled in the sampling phase is converted. For Sigma-Delta type ADC, the first stage integrator also needs to integrate the residual signal in the holding phase, and the integrated voltage is sampled by the rear integrator at the falling edge of the holding phase. In order to avoid the disturbance of the reference voltage caused by the D / A capacitor array in the holding phase, the ADC chip usually has an on-chip reference voltage buffer to isolate the D / A capacitor of the ADC from the input reference voltage. The reference voltage buffer needs to have the characteristics of high precision, low noise and sufficient driving ability, and its equivalent input impedance and input voltage range determine the flexibility of the design of the input reference voltage of the ADC chip.

[0003] In the traditional technical solution, due to the limitation of the structure of the operational amplifier, the lowest output voltage of the operational amplifier needs to be at least one NMOS saturation voltage higher than the ground voltage, and the highest output voltage needs to be at least one PMOS saturation voltage lower than the analog power supply voltage, which limits the input voltage range and cannot cover the complete power rail to ground rail range. In order to eliminate the operational amplifier imbalance and imbalance temperature drift, the chopping technology is introduced to modulate the imbalance to the chopping frequency, resulting in periodic ripple of the output reference voltage; for SAR type ADC, a large number of off-chip decoupling capacitors need to be additionally introduced to reduce the ripple amplitude to within 1 least significant bit (LSB), which increases the complexity and cost of circuit design. SUMMARY

[0004] The purpose of the present application is to provide a true rail-to-rail input and output reference voltage buffer circuit suitable for high-precision ADC, which solves the problem that the traditional reference voltage buffer cannot realize true rail-to-rail input and output and low input impedance, and provides a more flexible and efficient solution for high-precision ADC design.

[0005] To solve the above technical problems, the embodiment of the present application provides a true rail-to-rail input and output reference voltage buffer circuit suitable for high-precision ADC, which alternately performs a sampling phase F1 and a holding phase F2 during operation; the circuit comprises: a sampling capacitor module, a level shift capacitor module, a feedback capacitor module, a transconductance operational amplifier (OTA) and a switch network; the sampling capacitor module comprises at least one pair of sampling capacitors C s , the level shift capacitor module comprises at least one pair of level shift capacitors C LVL , and the feedback capacitor module comprises at least one pair of feedback capacitors C f . The sampling capacitor C s tracks the input reference voltage at the bottom plate in the sampling phase F1 and is reset to the ground at the top plate, and is used for sampling the input signal; The level shift capacitor C LVL synchronously samples the difference between the input reference voltage and the output common-mode voltage of the transconductance operational amplifier (OTA) in the sampling phase F1, and is connected to the output end of the transconductance operational amplifier (OTA) in the holding phase F2, so as to realize the range expansion of the output voltage in the true rail-to-rail range; The feedback capacitor C f does not clear the charge in the sampling phase F1, and is connected in parallel with the sampling capacitor C s in the holding phase F2, so as to realize the establishment of the output voltage through charge averaging; The switch network is used for controlling the connection state of the capacitors in the sampling phase F1 and the holding phase F2.

[0006] Optionally, the level shift capacitor C LVL is connected to the input reference voltage at the top plate and is connected to the output common-mode voltage of the transconductance operational amplifier (OTA) at the bottom plate in the sampling phase F1; and is connected to the output end of the transconductance operational amplifier (OTA) at the top plate and is connected to the output reference voltage at the bottom plate in the holding phase F2, so that the voltage at the output end of the transconductance operational amplifier (OTA) is shifted to the output common-mode voltage.

[0007] Optionally, the feedback capacitor C f maintains a floating state in the sampling phase F1, and the charge stored thereon is not reset, so as to reduce the charge extraction of the input reference voltage and improve the equivalent input impedance.

[0008] Optionally, the feedback capacitor C f does not clear the charge in the sampling phase F1, and the charge stored on the feedback capacitor C f remains unchanged in the sampling phase F1.

[0009] Optionally, the transconductance operational amplifier (OTA) performs a self-zeroing operation in the sampling phase F1, and stores the operational amplifier offset voltage through a self-zeroing capacitor C AZ , so as to eliminate the offset error.

[0010] Optionally, the timing control of the switch network satisfies: In the sampling phase F1, switches SW1, SW2, SW4, SW8, SW9 are closed, and SW3, SW5, SW6, SW7 are opened. In the holding phase F2, switches SW3, SW5, SW6, SW7 are closed, and SW1, SW2, SW4, SW8, SW9 are opened.

[0011] Optionally, the switch device includes a switch pair, and the switch pairs are symmetrically arranged.

[0012] Optionally, the high-precision ADC includes a feedforward structure sigma-delta ADC or a synchronous SAR ADC.

[0013] Optionally, the circuit has a low-pass filtering effect on the noise introduced in the sampling process, and the output noise power of the circuit is The following relationship is satisfied: Wherein, k is the Boltzmann constant, and T is the absolute temperature.

[0014] Optionally, the true rail-to-rail input and output are specifically: the range of the input reference voltage covers the analog power voltage to the analog ground voltage, and the range of the output reference voltage synchronously covers the analog power voltage to the analog ground voltage.

[0015] Compared with the prior art, in the embodiment of the present application, another pair of level shift capacitors is introduced to sample the input reference voltage synchronously while the sampling capacitors sample the input reference voltage. Then, in the holding phase, the level shift capacitors are connected between the output of the operational amplifier and the output reference voltage, so that the operational amplifier output voltage works within a reasonable output range, realizing true rail-to-rail output of the reference voltage. In addition, the original sampling and holding process is replaced by a sampling and integration process in the embodiment of the present application, so that the charge on the feedback capacitor is not cleared in the sampling phase, thereby reducing the charge extraction amount of the input reference voltage and improving the equivalent input impedance. Compared with the traditional sampling and holding reference voltage buffer circuit, the embodiment of the present application realizes the advantages of true rail-to-rail input and output of the reference voltage and high equivalent input impedance by introducing the level shift capacitors and the mechanism of not clearing the feedback capacitor. BRIEF DESCRIPTION OF DRAWINGS

[0016] One or more embodiments are illustrated by way of example in the accompanying drawings that are not intended to be limiting of the embodiments, in which like references numbers refer to like elements, unless otherwise specified. The drawings are not necessarily to scale, the emphasis instead being placed upon illustrating the principles of the embodiments.

[0017] Figure 1is a true rail-to-rail input-output reference voltage buffer circuit diagram suitable for high-precision ADC according to one embodiment of the present application; Figure 2 is a true rail-to-rail input-output reference voltage buffer circuit diagram at sampling phase F1 according to one embodiment of the present application; Figure 3 is a true rail-to-rail input-output reference voltage buffer circuit diagram at holding phase F2 according to one embodiment of the present application. DETAILED DESCRIPTION

[0018] Following are examples of implementing the present application, and persons skilled in the art can easily understand other advantages and purposes of the present application from the content disclosed in the specification. Obviously, the described embodiments are only a part of the embodiments of the present application, but not all the embodiments. The present application can also be implemented or applied through other different specific embodiments, and the details in the specification can be modified or changed based on different views and applications without departing from the spirit of the present application. It should be noted that the following embodiments and features in the embodiments can be combined with each other without conflict. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative labor are within the scope of protection of the present application.

[0019] It should be noted that the various aspects described below are within the scope of the appended claims. It should be apparent that the aspects described herein can be embodied in a wide variety of forms and that any specific structure and / or function described herein is merely illustrative. Based on the teachings provided herein one skilled in the art will appreciate that one or more aspects described herein can be implemented independently of any other aspects and that non-dependent aspects can be implemented in conjunction with each other in any way. For example, a device can be implemented using any number and combination of aspects described herein. Additionally, an apparatus and / or method can be implemented using other structures and / or functionality in addition to or instead of the aspects described herein.

[0020] It should also be noted that the drawings included in the following embodiments are only to illustrate the basic concept of the present application, and only the components related to the present application are shown in the drawings, not the number, shape and size of the components when actually implemented, and the shape, number and ratio of each component when actually implemented can be arbitrarily changed, and the layout of the components can also be more complex.

[0021] In addition, in the following description, specific details are provided to facilitate a thorough understanding of the examples. However, one skilled in the art will understand that the application can be practiced without these specific details.

[0022] To address the issues of existing reference voltage buffers failing to achieve true rail-to-rail input / output and having low input impedance, this application provides a true rail-to-rail input / output reference voltage buffer circuit suitable for high-precision ADCs, such as... Figure 1 As shown, it includes: a sampling capacitor module, a level shifting capacitor module, a feedback capacitor module, a transconductance operational amplifier (OTA), and a switching network; the sampling capacitor module includes at least one pair of sampling capacitors C. s The level shifting capacitor module includes at least one pair of level shifting capacitors C. LVL The feedback capacitor module includes at least one pair of feedback capacitors C. f ; The circuit alternately executes sampling phase F1 and holding phase F2 during operation; Sampling capacitor C s The bottom plate tracks the input reference voltages VRPI and VRNI in the sampling phase F1, and the top plate is reset to ground for sampling the input signal; Level shift capacitor C LVL The difference between the input reference voltages VRPI and VRNI and the output common-mode voltage VCMO of the transconductance operational amplifier OTA is simultaneously sampled in sampling phase F1, and connected to the output terminal of the transconductance operational amplifier OTA in holding phase F2 to realize the true rail to rail range extension of the output voltage. Feedback capacitor C f The charge is not cleared in sampling phase F1, and the charge is kept constant in phase F2 and the sampling capacitor C. s The parallel connection achieves the establishment of the output voltage through charge averaging. In this embodiment, the feedback capacitor C... f With sampling capacitor C s The capacitors are connected in parallel, and their charges are evenly distributed to establish the output voltage. After several cycles of alternating sampling phase F1 and hold phase F2, the feedback capacitor C... f The differential output voltage will be fully established to the input reference voltages VRPI and VRNI. After that, the output reference voltages of the phase output buffer F2 are VRPO=VRPI and VRNO=VRNI.

[0023] The switching network (such as SW1-SW9) is used to control the capacitor connection state of sampling phase F1 and holding phase F2.

[0024] In this embodiment of the application, the true rail-to-rail input and output specifically means that the range of the input reference voltage covers the analog power supply voltage to the analog ground voltage, and the range of the output reference voltage simultaneously covers the analog power supply voltage to the analog ground voltage.

[0025] In an optional embodiment, the level shifting capacitor C LVLThe top plate of the sampling phase F1 is connected with the input reference voltage VRPI, VRNI, and the bottom plate is connected with the output common mode voltage VCMO of the transconductance operational amplifier OTA; the top plate of the holding phase F2 is connected with the output end of the transconductance operational amplifier OTA, and the bottom plate is connected with the output reference voltage VRPO, VRNO, so that the output end voltage of the transconductance operational amplifier OTA is shifted to the output common mode voltage VCMO, and the output reference voltage VRPO, VRNO realizes the rail-to-rail range.

[0026] The feedback capacitor C f The bottom plate of the sampling phase F1 is kept floating, and the charge stored thereon is not reset, reducing the charge draw of the input reference voltage, thereby improving the equivalent input impedance. Specifically, the two ends of the feedback capacitor C f are not connected to the reset voltage, the bottom plate of the feedback capacitor C f is floating, and the charge cannot be discharged, so it is not cleared, the charge is retained, and other switches (such as SW3, SW5) are also disconnected, ensuring that the feedback capacitor C f is isolated from the output end of the transconductance operational amplifier OTA, and the charge stored thereon remains unchanged in the sampling phase F1.

[0027] The transconductance operational amplifier OTA performs self-zeroing operation in the sampling phase F1, and stores the operational amplifier offset voltage through the self-zeroing capacitor C AZ to eliminate the offset error, and the sampling capacitor C s and the level shift capacitor C LVL complete the sampling of the input reference voltage in the falling edge of F1D.

[0028] In an optional embodiment, as shown in Figure 1 , the switch network includes a plurality of switch devices, such as SW1-SW9, and the switch devices include switch pairs, such as the switch device SW1 including the switch pair SW1a, SW1b, the switch device SW2 including the switch pair SW2a, SW2b, and so on. The switch pairs are symmetrically arranged.

[0029] The timing control of the switch network satisfies: In the sampling phase F1, as shown in Figure 2 , the switches SW1 (SW1a, SW1b), SW2 (SW2a, SW2b), SW4 (SW4a, SW4b), SW8 (SW8a, SW8b), SW9 (SW9a, SW9b) are closed, and SW3 (SW3a, SW3b), SW5 (SW5a, SW5b), SW6 (SW6a, SW6b), SW7 (SW7a, SW7b) are opened. In the holding phase F2, as shown in Figure 3As shown, switches SW3 (SW3a, SW3b), SW5 (SW5a, SW5b), SW6 (SW6a, SW6b), SW7 (SW7a, SW7b) are closed, and SW1 (SW1a, SW1b), SW2 (SW2a, SW2b), SW4 (SW4a, SW4b), SW8 (SW8a, SW8b), SW9 (SW9a, SW9b) are open.

[0030] Specifically, in the sampling phase F1 stage: the input reference voltages VRPI, VRNI are connected to the sampling capacitor C s through switches SW9a, SW9b; the bottom plate of the sampling capacitor C s is connected to the common node through SW1a, SW1b; the bottom plate of the self-zeroing capacitor C AZ is connected to the input terminal of the transconductance operational amplifier OTA through SW2a, SW2b to store the operational amplifier offset voltage; the top plate of the level shifting capacitor C LVL is connected to the input reference voltages VRPI, VRNI through SW8a, SW8b; the bottom plate of the level shifting capacitor C LVL is connected to the common mode voltage VCMO through SW4a, SW4b; and the bottom plate of the feedback capacitor C f is connected to the common node through SW5b, SW5a, SW6b, SW6a, SW7b, SW7a, which are open, to retain the historical charge (without zero clearing).

[0031] In the hold phase F2 stage: the bottom plate of the feedback capacitor C f is connected to the output reference voltages VRPO, VRNO through SW6b, SW6a; the bottom plate of the sampling capacitor C s is connected to the output reference voltages VRPO, VRNO through SW7b, SW7a, SW6b, SW6a; the feedback capacitor C f is connected in parallel with the sampling capacitor C s to achieve charge averaging; the bottom plate of the level shifting capacitor C LVL is connected to the differential output terminal of the transconductance operational amplifier OTA through SW3a, SW3b; and the top plate of the level shifting capacitor C LVL is connected to the output reference voltages VRNO, VRPO through SW5a, SW5b, SW6b, SW6a, to use the voltage difference "VRPI, VRNI-VCMO" stored in the sampling phase F1 stage to shift the output of the transconductance operational amplifier OTA to the common mode voltage VCMO range, and finally make the output reference voltages VRPO, VRNO track the input reference voltages VRPI, VRNI to achieve true rail-to-rail output; at the same time, the self-zeroing capacitor C AZ continuously offsets the transconductance operational amplifier OTA offset, and the feedback capacitor C f does not clear the mechanism to improve the equivalent input impedance.

[0032] Therefore, in the embodiment of the present application, in the sampling phase F1, the input voltage is sampled, the op-amp offset is stored, and the level shift difference value is recorded, to prepare for the holding phase F2; In the holding phase F2, the charge is averaged through the parallel connection of the capacitors, the level shift breaks through the limitation of the op-amp output range, and finally the true rail-to-rail reference voltage is output.

[0033] The high-precision ADC in the embodiment of the present application includes a feedforward structure sigma-delta ADC or a synchronous SAR ADC.

[0034] The reference voltage buffer proposed in the embodiment of the present application has the following two points. LVL The true rail-to-rail reference voltage output is realized. Specifically, assuming that the input reference voltages VRPI and VRNI are completely rail-to-rail, i.e., VRPI=AVDD (positive power supply voltage) and VRNI=AVSS (negative power supply voltage, usually ground). In the F1 phase, the storage voltage of the level shift capacitor C LVL connected to the output reference voltage VRPO is AVDD-VCMO, and the storage voltage of the level shift capacitor C LVL connected to the output reference voltage VRNO is AVSS-VCMO. When the holding phase F2 comes, the level shift capacitor C LVL shifts the negative output end of the transconductance op-amp to AVSS-(AVSS-VCMO)=VCMO, and the positive output end to AVDD-(AVDD-VCMO)=VCMO. It can be seen that in the F2 phase, although the output voltage of the reference voltage buffer is the power supply ground rail, the positive and negative output ends of the transconductance op-amp OTA are both at the output common-mode voltage of the transconductance op-amp OTA, thereby ensuring the normal operation of the transconductance op-amp OTA.

[0035] The second point is that the non-reset operation of the feedback capacitor C f increases the equivalent input resistance. When the voltage on the feedback capacitor C f is established to the input reference voltages VRPI and VRNI, the sampling capacitor C s is connected to the input reference voltage in a full-charge state at the beginning of each sampling phase F1, which makes the input reference voltage not need to be charged and discharged on the sampling capacitor C s in each cycle, but only need to be charged and discharged on part of the parasitic capacitance in the circuit, which reduces the input reference voltage and greatly improves the equivalent input impedance of the reference buffer.

[0036] Furthermore, the reference voltage buffer circuit in this embodiment of the application has a low-pass filtering effect on the kT / C noise introduced by the sampling capacitor Cs in the sampling phase F1 during the sampling of the input reference voltage VRPI / VRNI. This allows the capacitance of Cs to be smaller than the capacitance required by a conventional sample-and-hold reference voltage buffer, under the same sampling noise budget. The following is an explanation of the principle of the noise filtering effect: Assume the input differential voltage VRPI-VRNI signal is... The output differential voltage signal VRPO-VRNO is Vo. Therefore, for the (n+1)th cycle, due to charge conservation, we have:

[0037] After Z-transformation and simplification, we get:

[0038] z represents the complex variable in the z-transform. This represents the expression for the output differential voltage Vo(VRPO-VRNO) in the z-domain. Indicates input differential voltage The expression of (VRPI-VRNI) in the z-domain.

[0039] The transfer function is:

[0040] The amplitude-frequency response of this function is a low-pass function, with an amplitude of 1 at DC. The power of the kT / C noise is kT / Cs, and the one-sided noise density is kT / (πCs). The noise power after this noise is transmitted to the VRPO-VRNO is... for:

[0041] Solving the above definite integral yields:

[0042] Where k is the Boltzmann constant and T is the absolute temperature.

[0043] As can be seen from the above formula, the kT / C noise introduced by VRPI-VRNI sampling is controlled by the feedback capacitor. Attenuation, under the same kT / C noise budget, can be achieved by increasing the feedback capacitor. To reduce the sampling capacitance .

[0044] In this embodiment of the application, due to the feedback capacitor C fThe charge on the feedback capacitor is not reset, and the charging process of the sampling capacitor Cs to Cf can be regarded as an integration process. Due to the averaging effect of integration on sampling noise, the sampling capacitor C s The capacitance of the sampling capacitor can be smaller than that required by a conventional sample-and-hold reference voltage buffer, and the averaging effect of the sampling integration process on noise reduces the noise effect.

[0045] Compared with the prior art, the embodiment of the present application introduces another pair of level shift capacitors to sample the input reference voltage at the same time as the sampling capacitor samples the input reference voltage. Then, in the hold phase, the level shift capacitors are connected between the output of the operational amplifier and the output reference voltage, so that the output voltage of the operational amplifier works in a reasonable output range, realizing true rail-to-rail output of the reference voltage. In addition, the original sampling establishment process is replaced by a sampling integration process in the embodiment of the present application, which does not clear the charge on the feedback capacitor in the sampling phase, thereby reducing the charge extraction amount of the input reference voltage and improving the equivalent input impedance. Compared with the conventional sample-and-hold reference voltage buffer circuit, the embodiment of the present application realizes the advantages of true rail-to-rail input and output capability of the reference voltage and high equivalent input impedance by introducing the mechanism of level shift capacitors and non-zero feedback capacitor.

[0046] The technical features of the above-described embodiments can be combined in any manner. To make the description concise, not all possible combinations of the technical features in the above-described embodiments are described, but as long as the combinations of the technical features do not exist contradictions, they should be considered as the scope of the present disclosure.

[0047] The above-described embodiments only express several implementation manners of the present application, and the description is more specific and detailed, but it should not be understood as a limitation on the patent scope of the application. It should be pointed out that for ordinary skilled persons in the art, several modifications and improvements can be made without departing from the concept of the present application, and these all belong to the protection scope of the present application. Therefore, the patent protection scope of the present application should be subject to the appended claims.

[0048] Those skilled in the art can understand that the above-described embodiments are specific embodiments for implementing the present application, and in actual applications, various changes can be made in form and details without departing from the spirit and scope of the present application.

Claims

1. A true rail-to-rail input / output reference voltage buffer circuit suitable for high-precision ADCs, characterized in that, The circuit alternately executes sampling phase F1 and holding phase F2 during operation; the circuit includes: a sampling capacitor module, a level shifting capacitor module, a feedback capacitor module, a transconductance operational amplifier (OTA), and a switching network; the sampling capacitor module includes at least one pair of sampling capacitors C. s The level shifting capacitor module includes at least one pair of level shifting capacitors C. LVL The feedback capacitor module includes at least one pair of feedback capacitors C. f ; Sampling capacitor C s The bottom plate tracks the input reference voltage in sampling phase F1, and the top plate is reset to ground for sampling the input signal; Level shift capacitor C LVL The difference between the input reference voltage and the output common-mode voltage of the transconductance operational amplifier OTA is sampled synchronously in sampling phase F1, and connected to the output terminal of the transconductance operational amplifier OTA in holding phase F2, so as to realize the true rail to rail range extension of the output voltage; Feedback capacitor C f The charge is not cleared in sampling phase F1, while maintaining the relationship between phase F2 and sampling capacitor C. s Parallel connection, achieving output voltage establishment through charge averaging; The switching network is used to control the capacitor connection state of sampling phase F1 and holding phase F2.

2. The circuit according to claim 1, characterized in that, The level shifting capacitor C LVL The input reference voltage is connected to the top plate of the sampling phase F1, and the common-mode voltage of the transconductance operational amplifier OTA is connected to the bottom plate; the output terminal of the transconductance operational amplifier OTA is connected to the top plate of the holding phase F2, and the output reference voltage is connected to the bottom plate, so that the output voltage of the transconductance operational amplifier OTA is shifted to the output common-mode voltage.

3. The circuit according to claim 1, characterized in that, The feedback capacitor C f The sampling phase F1 remains in a floating state, and the charge stored on it is not reset, which reduces the charge draw from the input reference voltage and improves the equivalent input impedance.

4. The circuit according to claim 3, characterized in that, The feedback capacitor C f The specific operation of not clearing the charge in sampling phase F1 is as follows: the feedback capacitor C f The two ends of the device are not connected to a reset voltage, and the charge stored on it remains unchanged during the sampling phase F1.

5. The circuit according to claim 1, characterized in that, The transconductance operational amplifier OTA performs a self-zeroing operation at sampling phase F1 through the self-zeroing capacitor C. AZ Store the op-amp offset voltage to eliminate offset error.

6. The circuit according to any one of claims 1-5, characterized in that, The switching network includes several switching devices, and the timing control of the switching network satisfies: During sampling phase F1, switches SW1, SW2, SW4, SW8, and SW9 are closed, while switches SW3, SW5, SW6, and SW7 are open. While maintaining phase F2, switches SW3, SW5, SW6, and SW7 are closed, while switches SW1, SW2, SW4, SW8, and SW9 are open.

7. The circuit according to claim 6, characterized in that, The switching device includes a pair of switches, all of which are symmetrically arranged.

8. The circuit according to claim 1, characterized in that, The high-precision ADC includes a feedforward sigma-delta ADC or a synchronous SAR ADC.

9. The circuit according to claim 1, characterized in that: The circuit described above provides low-pass filtering for noise introduced during the sampling process, and its output noise power... The following relationship must be satisfied: Where k is the Boltzmann constant and T is the absolute temperature.

10. The circuit according to claim 1, characterized in that, The true rail-to-rail input and output are specifically defined as follows: the range of the input reference voltage covers the analog power supply voltage to the analog ground voltage, and the range of the output reference voltage simultaneously covers the analog power supply voltage to the analog ground voltage.

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