Semiconductor memory device

Abstract

A semiconductor memory device includes a plurality of conductive layers arranged in a vertical direction, a plurality of active layers connected to the plurality of conductive layers, a plurality of through gates each penetrating the plurality of active layers, and a plurality of through gate insulating layers respectively surrounding sidewalls of the plurality of through gates.

Description

TECHNICAL FIELD

[0001] The disclosure relates generally to a semiconductor memory device and an electronic system including the same, and more particularly, to a three-dimensional semiconductor memory device and an electronic system including the same. BACKGROUND

[0002] Semiconductor memory devices are applied to electronic systems in various fields including automobiles, medical instruments, data centers, etc., in addition to compact electronic devices. Accordingly, the demand for semiconductor memory devices increases.

[0003] A semiconductor memory device can include memory cells for data storage. A three-dimensional semiconductor memory device includes a plurality of memory cells arranged in three dimensions, which is advantageous for large capacity storage compared to a two-dimensional semiconductor memory device.

[0004] The integration of memory cells in a three-dimensional semiconductor device can be improved by increasing the number of layers of memory cells. When the number of layers of memory cells increases, the number of layers of conductive layers connected to the memory cells can increase. As the number of layers of conductive layers increases, the area occupied by a peripheral circuit structure that controls the layer structure of the conductive layers can increase. SUMMARY

[0005] According to an embodiment of the disclosure, a semiconductor memory device can include: a plurality of cell pillar structures extending in a vertical direction, the plurality of cell pillar structures arranged to be spaced apart from each other in a horizontal direction; a word line layer stack surrounding the plurality of cell pillar structures, the word line layer stack including a plurality of cell gate layers arranged to be spaced apart from each other in the vertical direction; a plurality of cell level contact conductive layers spaced apart from the plurality of cell gate layers in the horizontal direction, the plurality of cell level contact conductive layers arranged to be spaced apart from each other in the vertical direction; a plurality of cell level active layers connected to the plurality of cell gate layers, the plurality of cell level active layers extending in the horizontal direction to be connected to the plurality of cell level contact conductive layers, the plurality of cell level active layers arranged to be spaced apart from each other in the vertical direction; a plurality of pass gates spaced apart from each other in the horizontal direction, each of the plurality of pass gates penetrating the plurality of cell level active layers; a plurality of pass gate insulating layers surrounding sidewalls of the plurality of pass gates, respectively; and a plurality of insulating pillar structures alternately arranged with the plurality of pass gates one by one in the horizontal direction, the plurality of insulating pillar structures penetrating the plurality of cell level active layers.

[0006] According to embodiments of the present disclosure, a semiconductor memory device can include a source layer having a first surface and a second surface facing opposite directions to each other and extending in a horizontal direction; a bit line disposed to be spaced apart from the second surface of the source layer in a vertical direction; a plurality of insulating layers including a local area, a global area spaced apart from the local area in the horizontal direction, and a plurality of through transistor array areas between the local area and the global area, the plurality of insulating layers being spaced apart from each other in the vertical direction between the second surface of the source layer and the bit line; a plurality of first conductive layers alternately disposed with the plurality of insulating layers in the local area one by one in the vertical direction; a plurality of cell pillar structures penetrating the plurality of first conductive layers and the plurality of insulating layers; a plurality of active layers alternately disposed with the plurality of insulating layers in the through transistor array areas one by one in the vertical direction; a plurality of through gates each including a first end portion facing the same direction as the first surface of the source layer and a second end portion facing the same direction as the second surface of the source layer, each of the plurality of through gates penetrating the plurality of active layers and the plurality of insulating layers; and a plurality of through gate insulating layers respectively surrounding sidewalls of the plurality of through gates, wherein the first end portion of each of the plurality of through gates is disposed closer to the plurality of insulating layers than the first surface of the source layer. BRIEF DESCRIPTION OF DRAWINGS

[0007] In the drawings, the size of some of the elements can be exaggerated for clarity and clarity.

[0008] Figure 1 is a block diagram illustrating a semiconductor memory device according to an embodiment of the present disclosure.

[0009] Figure 2A and Figure 2B is a circuit diagram illustrating a memory cell array and a through circuit according to an embodiment of the present disclosure.

[0010] Figure 3 , Figure 4A , Figure 4B and Figure 4C is a diagram illustrating a semiconductor memory device according to an embodiment of the present disclosure.

[0011] Figure 5 and Figure 6 is a diagram illustrating a semiconductor memory device according to an embodiment of the present disclosure.

[0012] Figure 7 is a plan view illustrating a semiconductor memory device according to an embodiment of the present disclosure.

[0013] Figure 8A and Figure 8B is a cross-sectional view illustrating a semiconductor memory device according to an embodiment of the present disclosure.

[0014] Figure 9 is a plan view illustrating a semiconductor memory device according to an embodiment of the present disclosure.

[0015] Figure 10 is a cross-sectional view illustrating a global region of a stacked structure according to an embodiment of the present disclosure.

[0016] Figure 11 is a cross-sectional view illustrating a semiconductor memory device according to an embodiment of the present disclosure.

[0017] Figure 12A 、 Figure 12B 、 Figure 13A 、 Figure 13B 、 Figure 14A 、 Figure 14B 、 Figure 15A 、 Figure 15B 、 Figure 16A 、 Figure 16B 、 Figure 17A 、 Figure 17B 、 Figure 17C 、 Figure 18 、 Figure 19 、 Figure 20A 、 Figure 20B 、 Figure 21A 、 Figure 21B 、 Figure 21C 、 Figure 22A 、 Figure 22B and Figure 23 are diagrams illustrating a method of manufacturing a semiconductor memory device according to an embodiment of the present disclosure.

[0018] Figure 24A 、 Figure 24B and Figure 24C are cross-sectional views illustrating a method of manufacturing a semiconductor memory device according to an embodiment of the present disclosure.

[0019] Figure 25A and Figure 25B are diagrams illustrating a semiconductor memory device according to an embodiment of the present disclosure.

[0020] Figure 26 is a block diagram illustrating an electronic system according to an embodiment of the present disclosure. DETAILED DESCRIPTION

[0021] The specific configurations or functional descriptions of the embodiments according to the concept of the present disclosure disclosed in the present specification or the present application are illustrated to describe the embodiments according to the concept of the present disclosure. The embodiments according to the concept of the present disclosure are not construed as being limited to the embodiments described in the present specification or the present application, and can be modified in various ways and replaced with other equivalent embodiments.

[0022] It will be understood that, although the terms“first,”“second,” etc. can be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another. The order or sequence of components described is not limited by the terms“first,”“second,” etc. unless otherwise specifically stated. Further, a component should not be construed as having to be limited to a single implementation unless specifically stated. Spatially relative terms, such as“beneath,”“below,”“lower,”“above,”“upper,” and the like, can be used herein for ease of description to describe one element or feature’s relationship to another element(s) or feature(s) as illustrated in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientations depicted in the figures. For example, if a device in the figures is inverted, elements described as“below” or“beneath” other elements or features would then be oriented“above” the other elements or features. Thus, the term“below” can encompass both an orientation of above and below. The devices can be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly. It will be understood that when an element or layer is referred to as being“on” or“connected to” or“coupled to” another element or layer, it can be directly on, connected or coupled to the other element or layer, or intervening elements or layers can be present. In contrast, when an element or layer is referred to as being“directly on,”“directly connected to,” or“directly coupled to” another element or layer, there are no intervening elements or layers present. Cross-hatching illustrated in the drawings represents optional features of the various elements, and does not limit the elements to a particular number of the optional features unless otherwise specifically stated.

[0023] Various embodiments can provide a semiconductor memory device capable of reducing an area occupied by a peripheral circuit structure.

[0024] Figure 1 is a block diagram illustrating a semiconductor memory device according to an embodiment of the disclosure.

[0025] Referring to Figure 1 The semiconductor memory device 50 can include a memory cell array 10, a pass circuit 40, and a peripheral circuit structure PE.

[0026] The memory cell array 10 can include a plurality of memory blocks. Each memory block can include a plurality of memory cells. Each memory cell can be a non-volatile memory cell. In an embodiment, each memory cell can be a NAND flash memory cell.

[0027] The pass circuit 40 can be connected to the memory cell array 10 by local lines. The local lines can include a plurality of word lines WL, a plurality of source select lines SSL, and a plurality of drain select lines DSL.

[0028] The peripheral circuit structure PE can be configured to perform a program operation for storing data in the memory cell array 10, a read operation for outputting data stored in the memory cell array 10, and an erase operation for erasing data stored in the memory cell array 10. In an embodiment, the peripheral circuit structure PE can include an input / output circuit 21, a control circuit 23, a voltage generation circuit 31, a block decoder 33, a column decoder 35, a page buffer 37, and a source line driver 39.

[0029] The input / output circuit 21 can transfer a command CMD and an address ADD received from an external device (e.g., a memory controller) of the semiconductor memory device 50 to the control circuit 23. The input / output circuit 21 can exchange data DATA with the external device and the column decoder 35.

[0030] The control circuit 23 can output an operation signal OP_S, a row address RADD, a source line control signal SL_S, a page buffer control signal PB_S, and a column address CADD in response to the command CMD and the address ADD.

[0031] The voltage generation circuit 31 can generate and output various operation voltages for the program operation, the read operation, and the erase operation in response to the operation signal OP_S. The operation voltages output from the voltage generation circuit 31 can be transmitted to the pass circuit 40 through a plurality of global lines GLL.

[0032] The block decoder 33 can output a block selection signal in response to the row address RADD. The block selection signal output from the block decoder 33 can be transmitted to the pass circuit 40 through a block selection line BSEL. The pass circuit 40 can include a plurality of pass transistor groups corresponding to a plurality of memory blocks of the memory cell array 10, respectively. Each block selection line BSEL can be connected to a corresponding pass transistor group of the plurality of pass transistor groups of the pass circuit 40. Each pass transistor group can transfer the operation voltages transmitted to the plurality of global lines GLL to a drain selection line DSL, a word line WL, and a source selection line SSL connected to a corresponding memory block in response to a block selection signal corresponding thereto.

[0033] The column decoder 35 can transmit data DATA input from the input / output circuit 21 to the page buffer 37 or transmit data DATA stored in the page buffer 37 to the input / output circuit 21 in response to the column address CADD. The column decoder 35 can exchange data DATA with the input / output circuit 21 through a column line CL. The column decoder 35 can exchange data DATA with the page buffer 37 through a data line DL.

[0034] The page buffer 37 can store read data received through the bit line BL in response to a page buffer control signal PB_S. The page buffer 37 can sense a voltage or a current of the bit line BL in a read operation. The page buffer 37 can be connected to the memory cell array 10 through the bit line BL.

[0035] The source line driver 39 can control a voltage applied to the common source line CSL in response to a source line control signal SL_S. The source line driver 39 can be connected to the memory cell array 10 through the common source line CSL.

[0036] Figure 2A and Figure 2B are circuit diagrams illustrating a memory cell array and a pass circuit according to an embodiment of the disclosure.

[0037] Referring to Figure 2A and Figure 2B Each memory block in the memory cell array 10 can include a plurality of memory cell strings CS. The plurality of memory cell strings CS can be connected to a plurality of bit lines BL and a source layer SR. The plurality of memory cell strings CS can be connected to Figure 1 a common source line CSL as shown.

[0038] Each memory cell string CS can include at least one source select transistor SST, a plurality of memory cells MC, and at least one drain select transistor DST.

[0039] The source select transistor SST can control an electrical connection between the plurality of memory cells MC and the source layer SR. The drain select transistor DST can control an electrical connection between the plurality of memory cells MC and the bit line BL.

[0040] One source select transistor SST or two or more source select transistors SST connected in series can be provided between the source layer SR and the plurality of memory cells MC. One drain select transistor DST or two or more drain select transistors DST connected in series can be provided between each bit line BL and the plurality of memory cells MC of the memory cell string CS corresponding thereto.

[0041] A plurality of cell gate layers of the plurality of memory cells MC can be connected to a plurality of word lines WL, respectively. A source select gate of the source select transistor SST can be connected to a source select line SSL. A drain select gate of the drain select transistor DST can be connected to a drain select line DSL.

[0042] The plurality of cell strings CS can include a first cell string CS1 and a second cell string CS2 connected in parallel to one word line WL and one bit line BL. The first cell string CS1 and the second cell string CS2 can be connected to one source select line SSL and individually connected to a first drain select line group DSL1 and a second drain select line group DSL2 isolated from each other. However, embodiments of the present disclosure are not limited thereto. Although not shown in the drawing, in an embodiment, the first cell string CS1 and the second cell string CS2 can be individually connected to different source select line groups.

[0043] The source select line SSL, the drain select line DSL, and the plurality of word lines WL can be connected to a pass transistor forming a pass circuit 40 as shown in FIG. 1. The pass transistor can include a plurality of first pass transistors PT1 connected to the plurality of word lines WL, a second pass transistor PT2 connected to the drain select line DSL, and a third pass transistor PT3 connected to the source select line SSL. Figure 1

[0044] The plurality of first pass transistors PT1, the second pass transistor PT2, and the third pass transistor PT3 can be connected to global lines GWL, GDSL, and GSSL. The global lines can include a plurality of global word lines GWL, a global drain select line GDSL, and a global source select line GSSL. The plurality of first pass transistors PT1, the second pass transistor PT2, and the third pass transistor PT3 can be connected to local lines WL, DSL, and SSL of a corresponding memory block. The local lines of the memory block can include a plurality of word lines WL, a drain select line DSL, and a source select line SSL. A source and a drain of each first pass transistor PT1 can be connected to a corresponding global word line GWL and a corresponding word line WL, respectively. A source and a drain of the second pass transistor PT2 can be connected to the global drain select line GDSL and the drain select line DSL, respectively. A source and a drain of the third pass transistor PT3 can be connected to the global source select line GSSL and the source select line SSL, respectively.

[0045] Gate electrodes of the plurality of first pass transistors PT1 can be connected to one block select line BSEL or BSEL1. Gate electrodes of the second pass transistor PT2 and the third pass transistor PT3 can be connected to one block select line BSEL or individually connected to different block select lines BSEL1 and BSEL2. In an embodiment, as shown in FIG. 1, the gate electrodes of the second pass transistor PT2 and the third pass transistor PT3 can be connected to the block select line BSEL to which the plurality of first pass transistors PT1 are connected. In another embodiment, as shown in FIG. 2, the gate electrodes of the second pass transistor PT2 and the third pass transistor PT3 can be individually connected to different block select lines BSEL1 and BSEL2. Figure 2A Figure 2B ​​As shown, the gate electrodes of the plurality of first pass transistors PT1 and the gate electrodes of the plurality of third pass transistors PT3 can be connected to a first block select line BSEL1, and the gate electrodes of the plurality of second pass transistors PT2 can be connected to a second block select line BSEL2.

[0046] Referring to Figure 2A and Figure 2B , each of the plurality of first pass transistors PT1, the plurality of second pass transistors PT2, and the plurality of third pass transistors PT3 can transfer a voltage applied to the plurality of global word lines GWL, global drain select lines GDSL, and global source select lines to the plurality of word lines WL, drain select lines DSL, and source select lines SSL in response to a block select signal applied to the block select line BSEL, BSEL1, or BSEL2 corresponding thereto.

[0047] The plurality of word lines WL, drain select lines DSL, and source select lines SSL can be configured with a first conductive layer. The first conductive layer can include a word line layer stack including a plurality of cell gate layers forming the plurality of word lines WL. The plurality of first pass transistors PT1 can include a plurality of cell level active layers connected to the plurality of cell gate layers. The plurality of cell level active layers can form a layer stack corresponding to the word line layer stack.

[0048] Figure 3 , Figure 4A , Figure 4B and Figure 4C are diagrams illustrating a semiconductor memory device according to an embodiment of the disclosure.

[0049] Referring to Figure 3 , Figure 4A , Figure 4B and Figure 4C , a memory block of a semiconductor memory device can include a layer stack ST, ST_A, ST_B, or ST_C, a plurality of pillar structures PS penetrating the layer stack ST, ST_A, ST_B, or ST_C, a plurality of gate pillar structures GP penetrating the layer stack ST, ST_A, ST_B, or ST_C, a plurality of conductive gate contact structures GC, a plurality of global conductive patterns GBC, a plurality of bit lines BL, a conductive connection pattern CCP, a conductive via structure VS, and a block select line BSEL. The layer stack ST, ST_A, ST_B, or ST_C can include a plurality of horizontal layers CDL11, CDL21, CDL31, ACT1, ACT2, ACT3, CDL12, CDL22, and CDL32 extending in a horizontal direction and a plurality of insulating layers. The first direction DR1 and the second direction DR2 shown in the diagram are directions of axes intersecting each other on a plane, and each direction can be defined as a horizontal direction. Although Figure 3A plurality of insulating layers are not shown but can be disposed in the vertical direction alternately with the plurality of horizontal layers CDL11, CDL21, CDL31, ACT1, ACT2, ACT3, CDL12, CDL22, and CDL32 one by one. The third direction DR3 shown in the figure can be defined as the vertical direction. For example, the first direction DR1, the second direction DR2, and the third direction DR3 can correspond to the X-axis direction, the Y-axis direction, and the Z-axis direction, respectively.

[0050] The stacked structure ST, ST_A, ST_B, or ST_C can include a local area LAR, a through transistor array area AAR, and a global area GAR. The global area GAR can be spaced apart from the local area LAR in the horizontal direction, and the through transistor array area AAR can be disposed between the local area LAR and the global area GAR. In an embodiment, the local area LAR, the through transistor array area AAR, and the global area GAR can be arranged along the first direction DR1. The global area GAR can be connected to the local area LAR via the through transistor array area AAR. The stacked structure ST, ST_A, ST_B, or ST_C can include a first sub-stacked structure ST1, a second sub-stacked structure ST2, and a third sub-stacked structure ST3 stacked in the third direction DR3.

[0051] Figure 3 A portion of the stacked structure ST forming a memory block is exemplified.

[0052] Referring to Figure 3The stacked structure ST can include a plurality of horizontal layers CDL11, CDL21, CDL31, ACT1, ACT2, ACT3, CDL12, CDL22, and CDL32 extending in the first direction DR1 and the second direction DR2. The plurality of horizontal layers CDL11, CDL21, CDL31, ACT1, ACT2, ACT3, CDL12, CDL22, and CDL32 can include a plurality of first conductive layers CDL11, CDL21, and CDL31, a plurality of active layers ACT1, ACT2, and ACT3, and a plurality of second conductive layers CDL12, CDL22, CDL32. Each of the plurality of first conductive layers CDL11, CDL21, and CDL31 and the plurality of second conductive layers CDL12, CDL22, CDL32 can include various conductive materials such as a doped semiconductor layer and a metal layer. The doped semiconductor layer can include a doped silicon layer. The metal layer can include tungsten, copper, molybdenum, etc. Each of the plurality of first conductive layers CDL11, CDL21, and CDL31 and the plurality of second conductive layers CDL12, CDL22, CDL32 can further include a metal nitride layer provided as a barrier layer. The metal nitride layer can include titanium nitride, tantalum nitride, molybdenum nitride, etc. Each of the plurality of active layers ACT1, ACT2, and ACT3 can include a semiconductor layer such as silicon serving as a channel layer.

[0053] The plurality of first conductive layers CDL11, CDL21, and CDL31 can be disposed in the local area LAR of the stacked structure ST to be spaced apart from each other in the third direction DR3. The plurality of first conductive layers CDL11, CDL21, and CDL31 can include at least one source select gate layer CDL11 of the first sub-stacked structure ST1, a plurality of cell gate layers CDL21 of the second sub-stacked structure ST2, and at least one drain select gate layer CDL31 of the third sub-stacked structure ST3. The source select gate layer CDL11 can serve as a source select line SSL as illustrated, the plurality of cell gate layers CDL21 can serve as a plurality of word lines WL as illustrated, and the drain select gate layer CDL31 can serve as a drain select line DSL as illustrated. Figure 2A Figure 2A Figure 2A

[0054] ​​​The plurality of active layers ACT1, ACT2, and ACT3 can be disposed in the transistor array region AAR of the stack structure ST to be spaced apart from each other in the third direction DR3. The plurality of active layers ACT1, ACT2, and ACT3 can be disposed at substantially the same height as the plurality of first conductive layers CDL11, CDL21, and CDL31, respectively. The plurality of active layers ACT1, ACT2, and ACT3 can be connected to the plurality of first conductive layers CDL11, CDL21, and CDL31. In an embodiment, the plurality of active layers ACT1, ACT2, and ACT3 can be adjacent to the plurality of first conductive layers CDL11, CDL21, and CDL31 in the first direction DR1 and can be connected to sidewalls of the plurality of first conductive layers CDL11, CDL21, and CDL31, respectively. The plurality of active layers ACT1, ACT2, and ACT3 can include at least one source select level active layer ACT1 of the first sub-stack structure ST1, a plurality of cell level active layers ACT2 of the second sub-stack structure ST2, and at least one drain select level active layer ACT3 of the third sub-stack structure ST3.

[0055] The plurality of second conductive layers CDL12, CDL22, and CDL32 can be disposed in the global region GAR of the stack structure ST to be spaced apart from each other in the third direction DR3. The plurality of second conductive layers CDL12, CDL22, and CDL32 can be disposed at substantially the same height as the plurality of first conductive layers CDL11, CDL21, and CDL31, respectively. The plurality of second conductive layers CDL12, CDL22, and CDL32 can be spaced apart from the plurality of first conductive layers CDL11, CDL21, and CDL31 in a horizontal direction and connected to the plurality of active layers ACT1, ACT2, and ACT3. In an embodiment, the plurality of second conductive layers CDL12, CDL22, and CDL32 can be spaced apart from the plurality of first conductive layers CDL11, CDL21, and CDL31 in the first direction DR1 and adjacent to the plurality of active layers ACT1, ACT2, and ACT3 in the first direction DR1. The plurality of second conductive layers CDL12, CDL22, and CDL32 can be connected to sidewalls of the plurality of active layers ACT1, ACT2, and ACT3, respectively. The plurality of second conductive layers CDL12, CDL22, and CDL32 can include at least one source select level contact conductive layer CDL12 of the first sub-stack structure ST1, a plurality of cell level contact conductive layers CDL22 of the second sub-stack structure ST2, and at least one drain select level contact conductive layer CDL32 of the third sub-stack structure ST3.

[0056] Figure 4A and Figure 4Bis a plan view illustrating the stacked structure ST_A, the stacked structure ST_B, and the stacked structure ST_C spaced apart from each other. The stacked structure ST_A and the stacked structure ST_C are adjacent to each other in the second direction DR2, and the stacked structure ST_B is interposed therebetween. In Figure 4A and Figure 4B , the stacked structure ST_B is mainly illustrated, and a partial region of each of the stacked structure ST_A and the stacked structure ST_C adjacent to the stacked structure ST_B is illustrated. Figure 4A the layout of the second sub-stacked structure ST2 in each of the stacked structure ST_A, ST_B, or ST_C is illustrated, and Figure 4B the layout of the third sub-stacked structure ST3 in each of the stacked structure ST_A, ST_B, or ST_C is illustrated. Figure 3 The illustrated stacked structure ST can correspond to Figure 4A and Figure 4B a portion of each of the stacked structure ST_A, the stacked structure ST_B, and the stacked structure ST_C illustrated in

[0057] Referring to Figure 4A and Figure 4B , the semiconductor memory device can include a first isolation structure AS, a second isolation structure GS, and a third isolation structure GBS that divide the stacked structure ST_A, ST_B, and ST_C. The first isolation structure AS, the second isolation structure GS, and the third isolation structure GBS can form an isolation group. Each isolation group can include one corresponding first isolation structure AS, one corresponding second isolation structure GS, and one corresponding third isolation structure GBS. The first isolation structure AS, the second isolation structure GS, and the third isolation structure GBS in each isolation group can be arranged in a row in a local area LAR, through a transistor array area AAR, and a global area GAR. In an embodiment, the first isolation structure AS, the second isolation structure GS, and the third isolation structure GBS in each isolation group can be arranged in a row in the first direction DR1. A sidewall of each of the stacked structure ST_A, ST_B, or ST_C can be defined along a sidewall of the first isolation structure AS, the second isolation structure GS, and the third isolation structure GBS arranged in a row in the first direction DR1. The sidewall of each of the first isolation structure AS, the second isolation structure GS, and the third isolation structure GBS can include an uneven portion, and the uneven portion defined along the sidewall of each of the first isolation structure AS, the second isolation structure GS, and the third isolation structure GBS can be formed on the sidewall of each of the stacked structure ST_A, ST_B, or ST_C.

[0058] Each of the stacked structure ST_A, ST_B, or ST_C can include Figure 3The diagram shows multiple active layers ACT1, ACT2, and ACT3, and the first isolation structure AS can be adjacent to each other in the second direction DR2. Figure 3 Multiple active layers ACT1, ACT2, and ACT3 are interposed therebetween. Each stack-up structure ST_A, ST_B, or ST_C may include... Figure 3 The diagram shows multiple first conductive layers CDL11, CDL21, and CDL31, and the second isolation structure GS can be adjacent to each other in the second direction DR2. Figure 3 Multiple first conductive layers CDL11, CDL21, and CDL31 are interposed therebetween. A second isolation structure GS can be connected to the first isolation structure AS. Each stacked structure ST_A, ST_B, or ST_C may include... Figure 3 The diagram shows multiple second conductive layers CDL12, CDL22, and CDL32, and the third isolation structure GBS can be adjacent to each other in the second direction DR2. Figure 3 Multiple second conductive layers CDL12, CDL22, and CDL32 are inserted therebetween. The third isolation structure GBS can be connected to the first isolation structure AS.

[0059] Reference Figure 3 , Figure 4A and Figure 4B The third sub-layer structure ST3 can be penetrated by the selective isolation structure SS. The depth of the selective isolation structure SS can be designed such that it does not penetrate the first sub-layer structure ST1 and the second sub-layer structure ST2. In the third sub-layer structure ST3, each drain-select gate layer CDL31 can be isolated by the selective isolation structure SS. Figure 2A The drain selection line DSL is shown. The selection isolation structure SS can extend in the first direction DR1 to penetrate the drain selection stage active layer ACT3 and the drain selection stage contact conductive layer CDL32. Therefore, the drain selection stage active layer ACT3 can be isolated into sub-active layers corresponding to the drain selection line by the selection isolation structure SS, and the drain selection stage contact conductive layer CDL32 can be isolated into sub-contact conductive layers corresponding to the drain selection line by the selection isolation structure SS.

[0060] In the local LAR region, each stacked structure ST, ST_A, ST_B, or ST_C can be penetrated by multiple pillar structures PS. These multiple pillar structures PS can extend along the third-direction DR3 to penetrate multiple first conductive layers CDL11, CDL21, and CDL31.

[0061] Figure 4C yes Figure 4B An enlarged plan view of the multiple column structures PS set in region X shown.

[0062] Referring to Figure 4C , the plurality of pillar structures PS can include a plurality of cell pillar structures CPS (i.e., Figure 4C , shown as "PS / CPS" in FIG. 1B). The plurality of cell pillar structures CPS can be arranged to be spaced apart from each other in the first direction DR1 and the second direction DR2. Each cell pillar structure CPS can be connected to a bit line BL corresponding thereto via a conductive bit line contact structure BCT.

[0063] The plurality of cell pillar structures CPS can be disposed on a plurality of rows and a plurality of columns. The cell pillar structures CPS of each row can be arranged in a row in the first direction DR1, and the cell pillar structures CPS of each column can be arranged in a row in the second direction DR2. The selection isolation structures SS can be disposed between some of the plurality of rows configured with the plurality of cell pillar structures CPS.

[0064] The plurality of pillar structures PS can further include dummy pillar structures DPS overlapping the selection isolation structures SS. However, various embodiments of the disclosure are not limited thereto. In an embodiment, the dummy pillar structures DPS can be omitted, and the selection isolation structures SS can overlap a portion of each cell pillar structure CPS arranged on two rows adjacent thereto.

[0065] Each pillar structure PS can include a memory layer ML and a channel structure CH. The memory layer ML can extend along a sidewall of the channel structure CH. The channel structure CH can serve as a channel structure of a memory cell string. The channel structure CH can be formed of a semiconductor material such as silicon (Si), germanium (Ge), or any mixture thereof. The memory layer ML can include a blocking insulating layer BI, a data storage layer DS, and a tunnel insulating layer TI. The tunnel insulating layer TI can extend along an outer wall of the channel structure CH and include an insulating material such as a silicon oxide layer. The data storage layer DS can continuously extend in a third direction DR3 along an outer wall of the tunnel insulating layer TI, or be isolated as data storage patterns spaced apart from each other in the third direction DR3. The data storage patterns can be respectively disposed in a height at which the first conductive layers CDL11, CDL21, and CDL31 shown in FIG. 1B are disposed. Figure 3 The data storage layer DS can be formed of a material layer capable of storing data using a Fowler-Nordheim tunneling change. In an embodiment, the data storage layer DS can be formed of a charge-trapping insulating layer, formed of a floating gate layer, or formed of an insulating layer including conductive nano dots. The charge-trapping insulating layer can include a silicon nitride layer. The blocking insulating layer BI can extend along an outer wall of the data storage layer DS. The blocking insulating layer BI can include one or more of a silicon dioxide layer (SiO2) and a high dielectric layer having a dielectric constant higher than that of the silicon dioxide layer. The high dielectric layer can include an aluminum oxide layer, a hafnium oxide layer, etc.

[0066] Referring to Figure 3and Figure 4C Each of the source select gate layer CDL11, the cell gate layer CDL21, and the drain select gate layer CDL31 can surround a plurality of cell pillar structures CPS among the plurality of pillar structures PS. The drain select gate layer CDL31 can be isolated into drain select lines by the select isolation structures SS such that drain select lines disposed in the same layer can surround different cell pillar structures.

[0067] Referring to Figure 3 , Figure 4A and Figure 4B The plurality of gate pillar structures GP can penetrate each of the layer stack structures ST, ST_A, ST_B, or ST_C through the transistor array region AAR. The plurality of gate pillar structures GP can extend in the third direction DR3 to penetrate the plurality of active layers ACT1, ACT2, and ACT3. Each gate pillar structure GP can include a through gate GE extending in the third direction DR3 to penetrate the plurality of active layers ACT1, ACT2, and ACT3, and a through gate insulating layer GI surrounding a sidewall of the through gate GE. The through gate GE can include various conductive materials such as a doped semiconductor layer and a metal layer. The through gate GE can further include a metal nitride layer provided as a barrier layer.

[0068] The plurality of through gates GE of the plurality of gate pillar structures GP can be spaced apart from each other in the second direction DR2. The plurality of through gates GE can be disposed on a plurality of rows. Each through gate GE can have a cross-sectional structure having a long axis in the first direction DR1 and a short axis in the second direction DR2 intersecting the plurality of rows. In an embodiment, the cross-section of the through gate GE can have a rectangular shape with the long axis in the first direction DR1. However, various embodiments of the disclosure are not limited thereto, and the cross-section of the through gate GE can be variously designed such as an elliptical shape.

[0069] Each of the plurality of through gates GE can function as a gate electrode of a through transistor corresponding thereto. The plurality of through gates GE and the plurality of cell-level active layers ACT2 can form a through transistor group including first through transistors connected to the plurality of cell gate layers CDL21. The sub-active layers configured with the drain select-level active layers ACT3 and the through gates GE can form second through transistors connected to corresponding drain select lines among the drain select lines configured with the drain select gate layers CDL31. The plurality of through gates GE and the source select-level active layers ACT1 can form a through transistor group of third through transistors connected to the source select gate layers CDL11. Because the plurality of active layers ACT1, ACT2, and ACT3 of each layer stack structure ST, ST_A, ST_B, or ST_C surround the through gates GE, a current flow path can be provided around each through gate GE.

[0070] The plurality of conductive gate contact structures GC can respectively extend from the plurality of through gates GE in the third direction DR3. A cross-section of each conductive gate contact structure GC can be various, such as a circular shape, an elliptical shape, and a polygonal shape. The plurality of conductive gate contact structures GC can be disposed on a plurality of rows. The conductive gate contact structures GC of each row can be lined up in the second direction DR2. The conductive gate contact structures GC of different rows can be connected to through gates GE that penetrate different layer stacks. For example, the conductive gate contact structures GC of a first row can be connected to through gates GE that penetrate the layer stack ST_A, and the conductive gate contact structures GC of a second row can be connected to through gates GE that penetrate the layer stack ST_B.

[0071] The conductive gate contact structures GC of each row can be connected to one block select line BSEL. In embodiments, the block select line BSEL can be connected to the conductive gate contact structures GC of a corresponding row via a conductive connection pattern CCP and a conductive via structure VS. The conductive connection pattern CCP can extend in the second direction DR2 to connect the conductive gate contact structures GC of a corresponding row to each other. The conductive connection pattern CCP can be connected to the block select line BSEL corresponding thereto via the conductive via structure VS. However, various embodiments of the present disclosure are not limited thereto. In embodiments, the conductive gate contact structures GC of each row can be directly connected to the block select line BSEL corresponding thereto.

[0072] The plurality of global conductive patterns GBC can extend from the plurality of second conductive layers CDL12, CDL22, and CDL23 in the third direction DR3. The plurality of global conductive patterns GBC can be used as Figure 1 the global line GLL shown. The global conductive patterns GBC connected to the source select level contact conductive layer CDL12 can be used as Figure 2A the global source select line GSSL shown. The global conductive patterns GBC connected to the cell level contact conductive layer CDL22 can be used as Figure 2A the global word line GWL shown, and the global conductive patterns GBC connected to the sub-contact conductive layer configured with the drain select level contact conductive layer CDL32 can be used as Figure 2A the global drain select line GDSL shown.

[0073] The plurality of second conductive layers CDL12, CDL22, and CDL32 can be formed as a staircase structure in the global area GAR. The plurality of global conductive patterns GBC can be respectively connected to a plurality of end portions of the plurality of second conductive layers CDL12, CDL22, and CDL32 formed as the staircase structure.

[0074] Figure 3 、 Figure 4A and Figure 4BThe illustrated semiconductor memory device can control the source select gate layer CDL11, the plurality of cell gate layers CDL21, and the drain select gate layer CDL31 by passing transistors stacked in a vertical direction, so that a planar area allocated to the passing transistors can be reduced in an embodiment. Figure 3 、 Figure 4A and Figure 4B The illustrated semiconductor memory device can directly connect the plurality of active layers ACT1, ACT2, and ACT3 of the passing transistors to the source select gate layer CDL11, the plurality of cell gate layers CDL21, and the drain select gate layer CDL31 without a separate connection structure.

[0075] In an embodiment of the disclosure to be described later, a detailed description of components overlapping with the components illustrated in Figure 3 、 Figure 4A and Figure 4B will be omitted or simplified. In an embodiment of the disclosure to be described later, the first direction DR1, the second direction DR2, and the third direction DR3 can be defined with reference to Figure 3 、 Figure 4A and Figure 4B .

[0076] Figure 5 and Figure 6 are diagrams illustrating a semiconductor memory device according to an embodiment of the disclosure.

[0077] With reference to Figure 5 and Figure 6 , the stacked structure ST, ST_A, ST_B, or ST_C of the memory block can include a local area LAR, a passing transistor array area AAR, and a global area GAR. The stacked structure ST, ST_A, ST_B, or ST_C can include a plurality of horizontal layers CDL11, CDL21, CDL31, ACT1, ACT2, CDL12, and CDL22 and a plurality of insulating layers extending in a horizontal direction. The stacked structure ST, ST_A, ST_B, or ST_C can include a first sub-stacked structure ST1, a second sub-stacked structure ST2, and a third sub-stacked structure ST3 stacked in the third direction DR3.

[0078] Figure 5 The illustrated stacked structure ST can correspond to a portion of each of the stacked structure ST_A, the stacked structure ST_B, and the stacked structure ST_C illustrated in Figure 6 . The stacked structure ST of the semiconductor memory device is illustrated in Figure 5 , and plan views of the stacked structure ST_A, the stacked structure ST_B, and the stacked structure ST_C spaced apart from each other are illustrated in Figure 6 .

[0079] With reference toFigure 6 A portion of the edge of each stack structure ST_A, ST_B, or ST_C can extend in the first direction DR1 along sidewalls of an isolation group configured with the first isolation structure AS, the second isolation structure GS, and the third isolation structure GBS. The isolation group configured with the first isolation structure AS, the second isolation structure GS, and the third isolation structure GBS can define edges of first and second sub-stack structures ST1 and ST2 of the stack structure ST, ST_A, ST_B, or ST_C. The sidewalls of each of the first isolation structure AS, the second isolation structure GS, and the third isolation structure GBS can include an uneven portion, and the uneven portion defined along the sidewalls of the first isolation structure AS, the second isolation structure GS, and the third isolation structure GBS can be formed on sidewalls of each of the first and second sub-stack structures ST1 and ST2.

[0080] Another portion of the edge of each stack structure ST_A, ST_B, or ST_C can be defined along sidewalls of a block isolation structure SS’. The block isolation structure SS’ can define an edge of a third sub-stack structure ST3 of each stack structure ST_A, ST_B, or ST_C. The sidewalls of the third sub-stack structure ST3 and the sidewalls of the block isolation structure SS’ can extend in the first direction DR1. The block isolation structure SS’ can overlap the second isolation structure GS.

[0081] Referring to Figure 5 The stack structure ST can include a plurality of horizontal layers CDL11, CDL21, CDL31, ACT1, ACT2, CDL12, and CDL22 extending in the first direction DR1 and the second direction DR2. The plurality of horizontal layers CDL11, CDL21, CDL31, ACT1, ACT2, CDL12, and CDL22 can include a plurality of first conductive layers CDL11, CDL21, and CDL31, a plurality of active layers ACT1 and ACT2, and a plurality of second conductive layers CDL12 and CDL22.

[0082] The plurality of first conductive layers CDL11, CDL21, and CDL31 can be disposed in the local area LAR of the stack structure ST to be spaced apart from each other in the third direction DR3. The plurality of first conductive layers CDL11, CDL21, and CDL31 can include at least one source select gate layer CDL11 of the first sub-stack structure ST1, a plurality of cell gate layers CDL21 of the second sub-stack structure ST2, and at least one drain select gate layer CDL31 of the third sub-stack structure ST3. The source select gate layer CDL11 can function as a source select line SSL as illustrated in FIG. 1, the plurality of cell gate layers CDL21 can function as a plurality of word lines WL as illustrated in FIG. 1, and the drain select gate layer CDL31 can function as a drain select line DSL as illustrated in FIG. 1. Figure 2B The plurality of first conductive layers CDL11, CDL21, and CDL31 can be disposed in the local area LAR of the stack structure ST to be spaced apart from each other in the third direction DR3. The plurality of first conductive layers CDL11, CDL21, and CDL31 can include at least one source select gate layer CDL11 of the first sub-stack structure ST1, a plurality of cell gate layers CDL21 of the second sub-stack structure ST2, and at least one drain select gate layer CDL31 of the third sub-stack structure ST3. The source select gate layer CDL11 can function as a source select line SSL as illustrated in FIG. 1, the plurality of cell gate layers CDL21 can function as a plurality of word lines WL as illustrated in FIG. 1, and the drain select gate layer CDL31 can function as a drain select line DSL as illustrated in FIG. 1. Figure 2B The plurality of first conductive layers CDL11, CDL21, and CDL31 can be disposed in the local area LAR of the stack structure ST to be spaced apart from each other in the third direction DR3. The plurality of first conductive layers CDL11, CDL21, and CDL31 can include at least one source select gate layer CDL11 of the first sub-stack structure ST1, a plurality of cell gate layers CDL21 of the second sub-stack structure ST2, and at least one drain select gate layer CDL31 of the third sub-stack structure ST3. The source select gate layer CDL11 can function as a source select line SSL as illustrated in FIG. 1, the plurality of cell gate layers CDL21 can function as a plurality of word lines WL as illustrated in FIG. 1, and the drain select gate layer CDL31 can function as a drain select line DSL as illustrated in FIG. 1.Figure 2B The drain select line DSL is shown.

[0083] The plurality of active layers ACT1 and ACT2 can be disposed in the transistor array region AAR of the stack structure ST to be spaced apart from each other in the third direction DR3. The plurality of active layers ACT1 and ACT2 can include at least one source select level active layer ACT1 of the first sub-stack structure ST1 and a plurality of cell level active layers ACT2 of the second sub-stack structure ST2. The source select level active layer ACT1 can be disposed at substantially the same height as the source select gate layer CDL11, adjacent to the source select gate layer CDL11 in the first direction DR1, and connected to the sidewall of the source select gate layer CDL11. The plurality of cell level active layers ACT2 can be disposed at substantially the same height as the plurality of cell gate layers CDL21, can be adjacent to the plurality of cell gate layers CDL21 in the first direction DR1, and can be connected to the sidewall of the plurality of cell gate layers CDL21, respectively.

[0084] The plurality of second conductive layers CDL12 and CDL22 can be disposed in the global region GAR of the stack structure ST to be spaced apart from each other in the third direction DR3. The plurality of second conductive layers CDL12 and CDL22 can include at least one source select level contact conductive layer CDL12 of the first sub-stack structure ST1 and a plurality of cell level contact conductive layers CDL22 of the second sub-stack structure ST2. The source select level contact conductive layer CDL12 can be disposed at substantially the same height as the source select gate layer CDL11 and can be spaced apart from the source select gate layer CDL11 in the first direction DR1. The source select level contact conductive layer CDL12 can be adjacent to the source select level active layer ACT1 in the first direction DR1 and can be connected to the sidewall of the source select level active layer ACT1. The plurality of cell level contact conductive layers CDL22 can be disposed at substantially the same height as the plurality of cell gate layers CDL21, respectively, and can be spaced apart from the plurality of cell gate layers CDL21 in the first direction DR1. The plurality of cell level contact conductive layers CDL22 can be adjacent to the plurality of cell level active layers ACT2 in the first direction DR1 and can be connected to the sidewall of the plurality of cell level active layers ACT2, respectively.

[0085] Referring to Figure 5 and Figure 6 , the third sub-stack structure ST3 can be penetrated by the select isolation structure SS. The depth of the select isolation structure SS can be designed not to penetrate the first sub-stack structure ST1 and the second sub-stack structure ST2. Each of the drain select gate layers CDL31 in the third sub-stack structure ST3 can be isolated by the select isolation structure SS as Figure 2A and Figure 2B The drain select line DSL is shown.

[0086] Each of the stack structures ST, ST_A, ST_B, or ST_C in the local area LAR can be penetrated by a plurality of pillar structures PS. The plurality of pillar structures PS can extend in the third direction DR3 to penetrate the plurality of first conductive layers CDL11, CDL21, and CDL31. As mentioned with reference to Figure 4C The plurality of pillar structures PS can include a plurality of cell pillar structures connected to bit lines, and further include dummy cell pillar structures overlapping the select isolation structures SS. As mentioned with reference to Figure 4C Each of the pillar structures PS can include a channel structure and a memory layer.

[0087] With reference to Figure 5 and Figure 6 Each of the stack structures ST, ST_A, ST_B, or ST_C can be penetrated by a plurality of gate pillar structures GP in the transistor array region AAR. The plurality of gate pillar structures GP can extend in the third direction DR3 to penetrate the plurality of active layers ACT1 and ACT2. Each of the gate pillar structures GP can include a pass gate GE extending in the third direction DR3 to penetrate the plurality of active layers ACT1 and ACT2, and a pass gate insulating layer GI surrounding sidewalls of the pass gate GE.

[0088] The plurality of pass gates GE of the plurality of gate pillar structures GP can be spaced apart from each other in the second direction DR2. The plurality of pass gates GE can be arranged on a plurality of rows. Each of the pass gates GE can have a cross-sectional structure having a long axis in the first direction DR1 and a short axis in the second direction DR2 intersecting the plurality of rows.

[0089] Each of the plurality of pass gates GE can function as a gate electrode of a pass transistor corresponding thereto. A pass transistor group including Figure 2B The first pass transistor PT1 as shown can be configured with the plurality of pass gates GE and the plurality of cell-level active layers ACT2. Figure 2B The third pass transistor PT3 as shown can be configured with the plurality of pass gates GE and the source-select-level active layers ACT1.

[0090] A plurality of conductive gate contact structures GC can extend in the third direction DR3 from the plurality of pass gates GE, respectively. The plurality of conductive gate contact structures GC can be disposed on a plurality of rows. The conductive gate contact structures GC of each row can be connected to one first block select line BSEL1. In an embodiment, the first block select line BSEL1 can be connected to the conductive gate contact structures GC of a corresponding row via a conductive connection pattern CCP and a conductive via structure VS. The conductive connection pattern CCP can extend in the second direction DR2 to connect the conductive gate contact structures GC of the corresponding row. The conductive connection pattern CCP can be connected to the first block select line BSEL1 corresponding thereto via the conductive via structure VS.

[0091] The plurality of global conductive patterns GBC can extend from the plurality of second conductive layers CDL12 and CDL22 in the third direction DR3. The plurality of global conductive patterns GBC can include a global source select line GSSL connected to the source select level contact conductive layer CDL12 to function as Figure 2B The global conductive pattern of the global source select line GSSL shown and the global conductive pattern of the global word line GWL shown can be connected to the unit level contact conductive layer CDL22 to function as Figure 2B The global conductive pattern of the global word line GWL shown.

[0092] The plurality of second conductive layers CDL12 and CDL22 can be disposed in a staircase structure in the global area GAR. The plurality of global conductive patterns GBC can be connected to a plurality of end portions of the plurality of second conductive layers CDL12 and CDL22 forming the staircase structure.

[0093] The third sub-stack structure ST3 can not overlap with the stack structure ST, ST_A, ST_B, or ST_C through the transistor array area AAR and the global area GAR to not block the plurality of active layers ACT1 and ACT2 and the plurality of second conductive layers CDL12 and CDL22. Drain select gate layers CDL31 of the third sub-stack structure ST3 configured and isolated by a select isolation structure SS can be connected to conductive local contact structures LC, respectively. Each conductive local contact structure LC can extend from a drain select gate layer CDL31 forming a drain select line corresponding thereto in the third direction DR3. A plurality of conductive gate contact structures GC can be disposed between the conductive local contact structures LC and the plurality of global conductive patterns GBC.

[0094] Although not shown in the figures, the plurality of global conductive patterns GBC can be connected to the plurality of second conductive layers CDL12 and CDL22 to function as Figure 2B The second block select line BSEL2, the second pass transistor PT2, and the global drain select line GDSL shown can be disposed in a structure separated in height from a height of each stack structure ST, ST_A, ST_B, or ST_C including the third sub-stack structure ST3.

[0095] Figure 5 And Figure 6 The semiconductor memory device shown can control the source select gate layer CDL11 and the plurality of unit gate layers CDL21 by the pass transistors stacked in the vertical direction so that a planar area allocated to the pass transistors can be reduced in embodiments. Figure 5 And Figure 6 The semiconductor memory device shown can directly connect the plurality of active layers ACT1 and ACT2 of the pass transistors to the source select gate layer CDL11 and the plurality of unit gate layers CDL21 without a separate connection structure.

[0096] Figure 7is a plan view illustrating a semiconductor memory device according to an embodiment of the present disclosure.

[0097] Referring to Figure 7 , a memory block of the semiconductor memory device can include a stacked structure ST_A, ST_B, or ST_C, a plurality of pillar structures PS, a plurality of gate pillar structures GP”, and a plurality of insulating pillar structures IP penetrating the stacked structure ST_A, ST_B, or ST_C, a plurality of conductive gate contact structures GC”, and a plurality of global conductive patterns GBC.

[0098] Figure 8A and Figure 8B is a cross-sectional view illustrating a semiconductor memory device according to an embodiment of the present disclosure. Figure 8A and Figure 8B Each of Figure 7 illustrates a cross-sectional view of a semiconductor memory device taken along lines I-I’, II-II’, and III-III’ shown in

[0099] Referring to Figure 7 , Figure 8A and Figure 8B , the stacked structure ST_A, ST_B, or ST_C can overlap with a source layer SR, and an intermediate insulating layer IIL is interposed therebetween. The source layer SR can include a first surface SU1 and a second surface SU2 facing opposite directions to each other and extending in a horizontal direction. A bit line BL of the semiconductor memory device can be disposed spaced apart from the second surface SU2 of the source layer SR in a third direction DR3. The intermediate insulating layer IIL and the stacked structure ST_A, ST_B, or ST_C can be disposed at a height between the second surface SU2 of the source layer SR and the bit line BL.

[0100] The source layer SR can include at least one doped semiconductor layer. The source layer SR can include n-type impurities as majority carriers. A region including n-type impurities as majority carriers can be provided as a source region.

[0101] Referring to Figure 8AIn an embodiment, the source layer SR can include a first doped semiconductor layer L1, a second doped semiconductor layer L2, and a third doped semiconductor layer L3. One of the first doped semiconductor layer L1, the second doped semiconductor layer L2, and the third doped semiconductor layer L3 can include an n-type impurity as a majority carrier, and the others of the first doped semiconductor layer L1, the second doped semiconductor layer L2, and the third doped semiconductor layer L3 can include an n-type impurity or a p-type impurity as a majority carrier. In an embodiment, the second doped semiconductor layer L2 can include an n-type impurity as a majority carrier and be provided as a source region. The third doped semiconductor layer L3 can include an n-type impurity as a majority carrier or include a p-type impurity as a majority carrier. According to an embodiment in which the third doped semiconductor layer L3 includes a p-type impurity as a majority carrier, the third doped semiconductor layer L3 can be provided as a well region. The first doped semiconductor layer L1 can include an n-type impurity or a p-type impurity as a majority carrier.

[0102] Referring to Figure 8B In an embodiment, the source layer SR can be formed as a single doped semiconductor layer. The single doped semiconductor layer can include a first conductivity type doped region including an n-type impurity as a majority carrier. The single doped semiconductor layer can further include a second conductivity type doped region including a p-type impurity as a majority carrier.

[0103] Referring to Figure 7 , Figure 8A and Figure 8B The stacked structure ST_A, ST_B, or ST_C can include a plurality of horizontal layers CDL11, CDL21, CDL31, ACT1, ACT2, ACT3, CDL12, CDL22, and CDL32 and a plurality of insulating layers IL1, IL2, and IL3 extending in the first direction DR1 and the second direction DR2.

[0104] The plurality of insulating layers IL1, IL2, and IL3 can be spaced apart from each other in the third direction DR3 between the second surface SU2 of the source layer SR and the bit line BL. The plurality of insulating layers IL1, IL2, and IL3 can include a local region LAR, a through-array region AAR, and a global region GAR.

[0105] The plurality of horizontal tiers CDL11, CDL21, CDL31, ACT1, ACT2, ACT3, CDL12, CDL22, and CDL32 can include a plurality of first conductive tiers CDL11, CDL21, and CDL31, a plurality of active tiers ACT1, ACT2, and ACT3, and a plurality of second conductive tiers CDL12, CDL22, and CDL32. In the local area region LAR, the plurality of insulating tiers IL1, IL2, and IL3 can be disposed in the third direction DR3 alternately with the plurality of first conductive tiers CDL11, CDL21, and CDL31 one by one. In the transistor array region AAR, the plurality of insulating tiers IL1, IL2, and IL3 can be disposed in the third direction DR3 alternately with the plurality of active tiers ACT1, ACT2, and ACT3 one by one. In the global area region GAR, the plurality of insulating tiers IL1, IL2, and IL3 can be disposed in the third direction DR3 alternately with the plurality of second conductive tiers CDL12, CDL22, and CDL32 one by one.

[0106] The stacked structure ST_A, ST_B, or ST_C can include a first sub-stacked structure ST1, a second sub-stacked structure ST2, and a third sub-stacked structure ST3 stacked in the third direction DR3. The plurality of insulating tiers IL1, IL2, and IL3 can include at least one first insulating tier IL1 of the first sub-stacked structure ST1, a plurality of second insulating tiers IL2 of the second sub-stacked structure ST2, and at least one third insulating tier IL3 of the third sub-stacked structure ST3. The plurality of first conductive tiers CDL11, CDL21, and CDL31 can include at least one source select gate tier CDL11 of the first sub-stacked structure ST1, a plurality of cell gate tiers CDL21 of the second sub-stacked structure ST2, and at least one drain select gate tier CDL31 of the third sub-stacked structure ST3. The source select gate tier CDL11 can function as Figure 2A the source select line SSL as illustrated, the plurality of cell gate tiers CDL21 can function as Figure 2A the plurality of word lines WL as illustrated, and the drain select gate tier CDL31 can function as Figure 2A the drain select line DSL as illustrated. The plurality of active tiers ACT1, ACT2, and ACT3 can include at least one source select level active tier ACT1 of the first sub-stacked structure ST1, a plurality of cell level active tiers ACT2 of the second sub-stacked structure ST2, and at least one drain select level active tier ACT3 of the third sub-stacked structure ST3. The plurality of second conductive tiers CDL12, CDL22, and CDL32 can include at least one source select level contact conductive tier CDL12 of the first sub-stacked structure ST1, a plurality of cell level contact conductive tiers CDL22 of the second sub-stacked structure ST2, and at least one drain select level contact conductive tier CDL32 of the third sub-stacked structure ST3.

[0107] The intermediate insulating layer IIL and the plurality of insulating layers IL1, IL2 and IL3 can be penetrated by the first isolation structures AS, the second isolation structures GS and the third isolation structures GBS. The first isolation structures AS can penetrate the intermediate insulating layer IIL and the plurality of insulating layers IL1, IL2 and IL3 in the transistor array region AAR and spaced apart from each other in the second direction DR2 with the plurality of active layers ACT1, ACT2 and ACT3 interposed therebetween. The second isolation structures GS can penetrate the intermediate insulating layer IIL and the plurality of insulating layers IL1, IL2 and IL3 in the local region LAR and spaced apart from each other in the second direction DR2 with the plurality of first conductive layers CDL11, CDL21 and CDL31 interposed therebetween. The second isolation structures GS can be connected to the first isolation structures AS, respectively. The third isolation structures GBS can penetrate the intermediate insulating layer IIL and the plurality of insulating layers IL1, IL2 and IL3 in the global region GAR and spaced apart from each other in the second direction DR2 with the plurality of second conductive layers CDL12, CDL22 and CDL32 interposed therebetween. The third isolation structures GBS can be connected to the first isolation structures AS, respectively.

[0108] The first isolation structures AS, the second isolation structures GS and the third isolation structures GBS in a row in the first direction DR1 can form an isolation group. A sidewall of each of the intermediate insulating layer IIL and the plurality of insulating layers IL1, IL2 and IL3 can be defined along sidewalls of the first isolation structures AS, the second isolation structures GS and the third isolation structures GBS of the isolation group. The sidewall of each of the first isolation structures AS, the second isolation structures GS and the third isolation structures GBS can include an uneven portion. The uneven portion defined along the sidewalls of the first isolation structures AS, the second isolation structures GS and the third isolation structures GBS can be formed on the sidewall of each of the intermediate insulating layer IIL and the plurality of insulating layers IL1, IL2 and IL3.

[0109] The third sub-stack structure ST3 can be penetrated by the selection isolation structure SS. A depth of the selection isolation structure SS can be designed to not penetrate the first sub-stack structure ST1 and the second sub-stack structure ST2. Each of the drain select gate layers CDL31 in the third sub-stack structure ST3 can be isolated as a drain select line DSL by the selection isolation structure SS. The selection isolation structure SS can extend in the first direction DR1 to penetrate the drain select stage active layers ACT3 and the drain select stage contact conductive layers CDL32. Accordingly, the drain select stage active layers ACT3 can be isolated as sub-active layers corresponding to drain select lines, respectively, by the selection isolation structure SS, and the drain select stage contact conductive layers CDL32 can be isolated as sub-contact conductive layers corresponding to drain select lines, respectively, by the selection isolation structure SS. Figure 2A

[0110] ​The plurality of pillar structures PS can extend in the third direction DR3 to penetrate the intermediate insulating layer IIL, the plurality of insulating layers IL1, IL2 and IL3 and the plurality of first conductive layers CDL11, CDL21 and CDL31. The plurality of pillar structures PS can be disposed between the second isolation structures GS. As referred to above, the plurality of pillar structures PS can include a plurality of cell pillar structures CPS connected to the bit lines BL, and further include dummy cell pillar structures overlapping the select isolation structures SS. As referred to above, each pillar structure PS can include a channel structure CH and a memory layer ML. The channel structure CH can be a tubular structure having a length extending in the third direction DR3. A core insulating layer CO can be disposed in a central region defined by the tubular structure of the channel structure CH. The channel structure CH can include a cap portion. The cap portion of the channel structure CH can form one end of the channel structure CH facing the third direction DR3. The cap portion of the channel structure CH can surround an end of the core insulating layer CO facing the bit line BL, and can include one or more of an n-type impurity and a p-type impurity. In an embodiment, the cap portion of the channel structure can include the n-type impurity as a majority carrier. Figure 4C Figure 4C The memory layer ML can extend along a sidewall of the channel structure CH. The memory layer ML can be disposed between the channel structure CH and the intermediate insulating layer IIL. The memory layer ML can extend in the third direction DR3 to be interposed between each of the first sub-stack structure ST1, the second sub-stack structure ST2 and the third sub-stack structure ST3 and the channel structure CH.

[0111] The memory layer ML can extend along a sidewall of the channel structure CH. The memory layer ML can be disposed between the channel structure CH and the intermediate insulating layer IIL. The memory layer ML can extend in the third direction DR3 to be interposed between each of the first sub-stack structure ST1, the second sub-stack structure ST2 and the third sub-stack structure ST3 and the channel structure CH.

[0112] The channel structure CH can include a contact surface in contact with the source layer SR. The contact surface can be defined at a portion of a sidewall of the channel structure CH, another end of the channel structure CH, etc. The other end of the channel structure CH can face a direction opposite to a direction in which the above-described cap portion faces.

[0113] Referring to Figure 8A In an embodiment, the memory layer ML can be penetrated by the second doped semiconductor layer L2 of the source layer SR, and be isolated into a first memory layer ML1 and a second memory layer ML2. The second doped semiconductor layer L2 of the source layer SR can be in contact with a portion of a sidewall of the channel structure CH. Accordingly, a contact surface between the channel structure CH and the source layer SR can be defined. The first memory layer ML1 can be interposed between each of the first sub-stack structure ST1, the second sub-stack structure ST2 and the third sub-stack structure ST3 and the channel structure CH, and extend between the third doped semiconductor layer L3 of the source layer SR and the channel structure CH. The second memory layer ML2 can be interposed between the first doped semiconductor layer L1 of the source layer SR and the channel structure CH.

[0114] ​Referring to Figure 8B In an embodiment, the source layer SR can include a recess. The other end of the channel structure CH can protrude inward of the memory layer ML and be inserted into the recess of the source layer SR. A contact surface between the channel structure CH and the source layer SR can be defined along the recess of the source layer SR.

[0115] Referring to Figure 7 , Figure 8A and Figure 8B Each of the plurality of gate pillar structures GP” can include a gate via GE” and a gate via insulating layer GI” surrounding a sidewall of the gate via GE”. The plurality of gate vias GE” of the plurality of gate pillar structures GP” can extend in the third direction DR3 to penetrate the intermediate insulating layer IIL, the plurality of insulating layers IL1, IL2 and IL3 and the plurality of active layers ACT1, ACT2 and ACT3. Each gate via GE” can include a first end portion EP1 facing the same direction as the first surface SU1 of the source layer SR and a second end portion EP2 facing the same direction as the second surface SU2 of the source layer SR.

[0116] The plurality of gate pillar structures GP” can be provided using a process of forming the plurality of pillar structures PS. Accordingly, similar to the plurality of pillar structures PS, the plurality of gate pillar structures GP” can extend to a height between the first surface SU1 and the second surface SU2 of the source layer SR while penetrating the intermediate insulating layer IIL. As a result, the first end portion EP1 of the gate via GE” can be disposed closer to the plurality of insulating layers IL1, IL2 and IL3 than the first surface SU1 of the source layer SR.

[0117] Referring to Figure 8A In an embodiment, the source layer SR can extend to overlap the plurality of active layers ACT1, ACT2 and ACT3. Each pillar structure PS and gate via GE” can extend to an inside of the source layer SR while penetrating the second surface SU2 of the source layer SR and form a depth not to penetrate the first surface SU1 of the source layer SR.

[0118] Referring to Figure 8B In an embodiment, the source layer SR can be penetrated by a source level insulating layer SIL. The source level insulating layer SIL can extend to overlap the plurality of active layers ACT1, ACT2 and ACT3 and the plurality of second conductive layers CDL12, CDL22 and CDL32. Each pillar structure PS and gate via GE” can extend to an inside of the source level insulating layer SIL.

[0119] Referring to Figure 7 , Figure 8A and Figure 8BThe plurality of pass gates GE” can be spaced apart from each other in the first direction DR1 and the second direction DR2. The plurality of pass gates GE” and the plurality of insulating pillar structures IP can be arranged on a plurality of rows and a plurality of columns. Two or more pass gates GE” can be arranged in a row in the first direction DR1 on each row, and two or more pass gates GE” can be arranged in a row in the second direction DR2 on each column. The plurality of insulating pillar structures IP can be alternately arranged with the plurality of pass gates GE” in the first direction DR1 and the second direction DR2. A cross section of each pass gate GE” and each insulating pillar structure IP can be various designs, such as a circular shape, an elliptical shape, a square shape, and a rectangular shape.

[0120] The plurality of insulating layers IL1, IL2, and IL3 and the plurality of second conductive layers CDL12, CDL22, and CDL32 can be formed as a staircase structure in the global area GAR. The staircase structure can be covered by a fill insulating layer FIL.

[0121] The fill insulating layer FIL and the third sub-stack structure ST3 can be covered by a fourth insulating layer IL4. The fourth insulating layer IL4 can be penetrated by a conductive bit line contact structure BCT, a plurality of conductive gate contact structures GC”, and a plurality of global conductive patterns GBC.

[0122] The conductive bit line contact structure BCT can be disposed between the bit line BL and the cell pillar structure CPS to connect the bit line BL and the cell pillar structure CPS to each other.

[0123] The plurality of conductive gate contact structures GC” can respectively correspond to a plurality of rows configured with the plurality of pass gates GE”. Each conductive gate contact structure GC” can extend in the first direction DR1 to connect to the pass gates GE” of the row corresponding thereto.

[0124] The plurality of global conductive patterns GBC can penetrate a corresponding insulating layer among the plurality of insulating layers IL1, IL2, and IL3 and the fill insulating layer FIL to respectively connect to the plurality of second conductive layers CDL12, CDL22, and CDL32.

[0125] The bit line BL can be disposed inside a fifth insulating layer IL5. The fifth insulating layer IL5 can extend to cover the fourth insulating layer IL4 and the plurality of conductive gate contact structures GC”. The fifth insulating layer IL5 can be penetrated by a first conductive connection pattern CCP1 and a plurality of second conductive connection patterns CCP2 except for the bit line BL. The first conductive connection pattern CCP1 can extend in the second direction DR2 to connect to the conductive gate contact structures GC” adjacent to each other in the second direction DR2. The plurality of second conductive connection patterns CCP2 can respectively connect to the plurality of conductive gate contact structures GC”.

[0126] The fifth insulating layer IL5, the bit line BL, the first conductive connection pattern CCP1, and the plurality of second conductive connection patterns CCP2 can be covered by a sixth insulating layer IL6. The sixth insulating layer IL6 can be penetrated by a conductive via structure VS. The conductive via structure VS can be connected to the first conductive connection pattern CCP1.

[0127] The sixth insulating layer IL6 and the conductive via structure VS can be covered by a seventh insulating layer IL7. A block select line BSEL can be formed inside the seventh insulating layer IL7. The block select line BSEL can be connected to the conductive via structure VS. The block select line BSEL can be commonly connected to the plurality of rows of pass gates GE” via the conductive via structure VS, the first conductive connection pattern CCP1, and the plurality of conductive gate contact structures GC”.

[0128] The semiconductor memory device can include a peripheral circuit structure PE. The peripheral circuit structure PE can include a plurality of transistors TR’. In an embodiment, the plurality of transistors TR’ can include Figure 1 The illustrated transistors of the page buffer 37. Each transistor TR’ can be disposed in an active region of the semiconductor substrate SUB partitioned by an isolation layer ISO. Each transistor TR’ can include junctions JN1’ and JN2’, a gate insulating layer GI’, and a gate electrode GE’. The junctions JN1’ and JN2’ can be disposed in the active region of the semiconductor substrate SUB spaced apart from each other, and the gate insulating layer GI’ and the gate electrode GE’ can be laminated on the active region between the junctions JN1’ and JN2’.

[0129] The plurality of transistors TR’ can be covered on the semiconductor substrate SUB with a peripheral insulating structure PIL. A plurality of interconnects IC can be disposed inside the peripheral insulating structure PIL. The plurality of interconnects IC can include one or more of a plurality of conductive lines and a plurality of conductive contact structures for electrical connection.

[0130] Referring to Figure 8A In an embodiment, the peripheral circuit structure PE can be disposed closer to the source layer SR than the bit line BL. The source layer SR can be disposed between the peripheral insulating structure PIL and the first sub-lamination structure ST1.

[0131] Referring to Figure 8B In an embodiment, the peripheral circuit structure PE can be disposed closer to the bit line BL than the source layer SR. The bit line BL can be disposed between the peripheral insulating structure PIL and the third sub-lamination structure ST3. The seventh insulating layer IL7 and the block select line BSEL can be disposed between the bit line BL and the peripheral insulating structure PIL, and an eighth insulating layer IL8 can be interposed between the peripheral insulating structure PIL and each of the seventh insulating layer IL7 and the block select line BSEL.

[0132] Multiple unit-side bonding patterns (CBPs) can be disposed within the eighth insulating layer (IL8). Multiple peripheral circuit-side bonding patterns (PBPs) corresponding to the multiple unit-side bonding patterns (CBPs) can be disposed within the peripheral insulating structure (PIL). The multiple unit-side bonding patterns (CBPs) can be bonded to the multiple peripheral circuit-side bonding patterns (PBPs).

[0133] Some of the multiple unit-side bonding patterns CBP can be electrically connected to the bit line BL via at least one bit line connection structure. In an embodiment, the first unit-side bonding pattern of the multiple unit-side bonding patterns CBP can be electrically connected to the bit line BL via a first bit line connection structure BC1 and a second bit line connection structure BC2. The first bit line connection structure BC1 can penetrate the sixth insulating layer IL6, and the second bit line connection structure BC2 can penetrate the seventh insulating layer IL7.

[0134] Some of the multiple peripheral circuit-side bonding patterns (PBPs) can be electrically connected to transistors in the page buffer via an interconnect IC. The peripheral circuit-side bonding patterns of the transistors electrically connected to the page buffer can be bonded to the first cell-side bonding pattern. Therefore, the bit line BL can be electrically connected to the page buffer via both the first cell-side bonding pattern and the peripheral circuit-side bonding pattern.

[0135] Figure 7 , Figure 8A and Figure 8B The semiconductor memory device shown can control the source select gate layer CDL11, multiple unit gate layers CDL21 and drain select gate layer CDL31 by passing transistors stacked in the vertical direction, so that the planar area allocated to the passing transistors can be reduced in the embodiment. Figure 7 , Figure 8A and Figure 8B The semiconductor memory device shown can directly connect multiple active layers ACT1, ACT2 and ACT3 of transistors to source select gate layer CDL11, multiple unit gate layers CDL21 and drain select gate layer CDL31 without separate interconnection structures.

[0136] Figure 8A or Figure 8B The peripheral circuit structure PE and source layer SR shown can be applied to Figure 3 and Figure 5 The semiconductor memory device shown.

[0137] Figure 9 This is a plan view illustrating a semiconductor memory device according to an embodiment of the present disclosure.

[0138] Reference Figure 9The memory block of a semiconductor memory device may include a stacked structure ST_A, ST_B, or ST_C, multiple pillar structures PS, multiple conductive local contact structures LC, multiple gate pillar structures GP, multiple insulating pillar structures IP, multiple conductive gate contact structures GC, and multiple global conductive patterns GBC. The semiconductor memory device may include... Figure 8A or Figure 8B The peripheral circuit structure PE and source layer SR are shown.

[0139] The stacked structure ST_A, ST_B or ST_C may include multiple insulating layers and multiple horizontal layers extending in the first direction DR1 and the second direction DR2.

[0140] Multiple insulating layers may include, as referenced Figure 7 , Figure 8A and Figure 8B The description includes the local area LAR, the transistor array area AAR, and the global area GAR. Multiple insulating layers may include, for example... Figure 8A and Figure 8B The first sub-layer structure ST1 shown has at least one first insulating layer IL1, the second sub-layer structure ST2 has multiple second insulating layers IL2, and the third sub-layer structure ST3 has at least one third insulating layer IL3.

[0141] Each of the plurality of horizontal layers may include a plurality of first conductive layers, a plurality of active layers, and a plurality of second conductive layers extending in a first direction DR1 and a second direction DR2. For example... Figure 8A and Figure 8B As shown, the plurality of first conductive layers may include at least one source-select gate layer CDL11 of the first sub-layer structure ST1, a plurality of unit gate layers CDL21 of the second sub-layer structure ST2, and at least one drain-select gate layer CDL31 of the third sub-layer structure ST3. The plurality of active layers may include at least one source-select level active layer of the first sub-layer structure ST1 and a plurality of unit-level active layers of the second sub-layer structure ST2. For example... Figure 8A and Figure 8B As shown, the source-selective active layer ACT1 of the first sub-layer structure ST1 can be adjacent to the source-selective gate layer CDL11 in the first direction DR1, and can be connected to the sidewall of the source-selective gate layer CDL11. Figure 8A and Figure 8B As shown, the multiple unit-level active layers ACT2 of the second sub-layer structure ST2 can be adjacent to the multiple unit-level gate layers CDL21 in the first direction DR1, and can be respectively connected to the sidewalls of the multiple unit-level gate layers CDL21. The multiple second conductive layers can include at least one source selection level contact conductive layer of the first sub-layer structure ST1 and multiple unit-level contact conductive layers of the second sub-layer structure ST2. For example... Figure 8Aand Figure 8B As shown, the source select level contact conductive layers CDL12 of the first sub-tier structure ST1 can be adjacent to the source select level active layers ACT1 in the first direction DR1 and can be connected to sidewalls of the source select level active layers ACT1. As shown, Figure 8A and Figure 8B As shown, the plurality of cell level contact conductive layers CDL22 of the second sub-tier structure ST2 can be adjacent to the plurality of cell level active layers ACT2 in the first direction DR1 and can be connected to sidewalls of the plurality of cell level active layers ACT2, respectively.

[0142] Referring to Figure 9 , a portion of the edge of the tier structure ST_A, ST_B or ST_C can extend in the first direction DR1 along sidewalls of an isolation group configured by the first isolation structure AS, the second isolation structure GS and the third isolation structure GBS. The isolation group configured by the first isolation structure AS, the second isolation structure GS and the third isolation structure GBS can define the edge of each of the first sub-tier structure ST1 and the second sub-tier structure ST2 of the tier structure ST_A, ST_B or ST_C. The sidewalls of each of the first isolation structure AS, the second isolation structure GS and the third isolation structure GBS can include an uneven portion, and the uneven portion defined along the sidewalls of each of the first isolation structure AS, the second isolation structure GS and the third isolation structure GBS can be formed on the sidewalls of the first sub-tier structure ST1 and the second sub-tier structure ST2.

[0143] Another portion of the edge of the tier structure ST_A, ST_B or ST_C can be defined along sidewalls of a block isolation structure SS’. The block isolation structure SS’ can define the edge of the third sub-tier structure ST3 of each tier structure ST_A, ST_B or ST_C. The sidewalls of the third sub-tier structure ST3 and the sidewalls of the block isolation structure SS’ can extend in the first direction DR1. The block isolation structure SS’ can overlap the second isolation structure GS.

[0144] Each of the first sub-tier structure ST1 and the second sub-tier structure ST2 can be divided into a local area LAR, a through transistor array area AAR and a global area GAR. As shown, Figure 5 As shown, the third sub-tier structure ST3 can overlap the local area LAR of each of the first sub-tier structure ST1 and the second sub-tier structure ST2 and can not overlap the through transistor array area AAR and the global area GAR of each of the first sub-tier structure ST1 and the second sub-tier structure ST2 to open the through transistor array area AAR and the global area GAR of each of the first sub-tier structure ST1 and the second sub-tier structure ST2.

[0145] Referring toFigure 9 The arrangement and configuration of the plurality of pillar structures PS can be the same as described with reference to Figure 7 , Figure 8A and Figure 8B The arrangement and configuration of the plurality of conductive local contact structures LC can be the same as described with reference to Figure 5 and Figure 6 Each of the plurality of gate pillar structures GP” can include a gate GE” and a gate insulating layer GI” surrounding the gate GE”. The arrangement and configuration of each of the plurality of gate pillar structures GP” and the plurality of insulating pillar structures IP can be the same as described with reference to Figure 7 , Figure 8A and Figure 8B The arrangement and configuration of each of the plurality of conductive gate contact structures GC” and the plurality of global conductive patterns GBC can be the same as described with reference to Figure 5 and Figure 6 .

[0146] Figure 9 The semiconductor memory device illustrated in FIG. 1A can control the source select gate layer of the first sub-stack structure ST1 and the plurality of cell gate layers of the second sub-stack structure ST2 by the pass transistors stacked in the vertical direction, so that the planar area allocated to the pass transistors can be reduced in embodiments. Figure 9 The semiconductor memory device illustrated in FIG. 1A can directly connect the plurality of active layers of the pass transistors connected to the source select gate layer and the plurality of cell gate layers to the source select gate layer and the plurality of cell gate layers without a separate connection structure.

[0147] With reference to Figure 3 , Figure 4A , Figure 4B , Figure 5 , Figure 6 , Figure 7 , Figure 8A , Figure 8B and Figure 9 , the first to third sub-stack structures ST1, ST2, and ST3 can be formed as a stepped structure in the global area GAR. However, embodiments of the present disclosure are not limited thereto.

[0148] Figure 10 is a cross-sectional view illustrating a global area of a stack structure according to an embodiment of the present disclosure.

[0149] With reference to Figure 10The stack structure ST can include the first insulating layer IL1 and the source select level contact conductive layer CDL12 of the first sub-stack structure ST1, the plurality of second insulating layers IL2 and the plurality of cell level contact conductive layers CDL22 of the second sub-stack structure ST2, and the third insulating layer IL3 and the drain select level contact conductive layer CDL32 of the third sub-stack structure ST3. The stack structure ST can be covered with a fourth insulating layer IL4, and the fourth insulating layer IL4 can be covered with a fifth insulating layer IL5.

[0150] The first, second, and third insulating layers IL1, IL2, and IL3 of the stack structure ST can not be formed in a stepped structure in the global area GAR, but can extend in the first and second directions DR1 and DR2 to surround at least one of the plurality of global conductive patterns GBC. The source select level contact conductive layer CDL12, the plurality of cell level contact conductive layers CDL22, and the drain select level contact conductive layer CDL32 of the stack structure ST can not be formed in a stepped structure in the global area GAR, but can extend in the first and second directions DR1 and DR2 to overlap the global area GAR of the first, second, and third insulating layers IL1, IL2, and IL3.

[0151] Each of the plurality of global conductive patterns GBC can extend in the third direction DR3 to penetrate from a corresponding conductive layer among the source select level contact conductive layer CDL12, the plurality of cell level contact conductive layers CDL22, and the drain select level contact conductive layer CDL32, an insulating layer above the corresponding conductive layer, and a conductive layer above the corresponding conductive layer. A sidewall insulating layer SWI can surround a sidewall of each global conductive pattern GBC. The sidewall insulating layer SWI can insulate the global conductive pattern GBC and the conductive layer above it from each other.

[0152] The global conductive pattern GBC and the sidewall insulating layer SWI can extend to penetrate the fourth insulating layer IL4. The global conductive pattern GBC can be connected to a conductive connection pattern CCP inside the fifth insulating layer IL5.

[0153] Figure 11 is a cross-sectional view illustrating a semiconductor memory device according to an embodiment of the present disclosure.

[0154] Referring to Figure 11, Each of the first conductive layer CDL[1], the active layer ACT, and the second conductive layer CDL[2] of the semiconductor memory device according to the embodiment of the disclosure can extend in the first direction DR1 and the second direction DR2, and can be interposed between the insulating layers IL adjacent to each other in the third direction DR3. The first conductive layer CDL[1] can be interposed between the insulating layers IL in the local area LAR, and surround a sidewall of a pillar structure including a core insulating layer CO, a channel structure CH, and a memory layer ML. The second conductive layer CDL[2] can be interposed between the insulating layers IL in the global area GAR, and can be spaced apart from the first conductive layer CDL[1]. The active layer ACT can be interposed between the insulating layers IL in the transistor array area AAR, and include one side in contact with the first conductive layer CDL[1] and the other side connected to the second conductive layer CDL[2].

[0155] The memory layer ML can include a tunnel insulating layer TI, a data storage layer DS, and a blocking insulating layer BI as described with reference to Figure 4C The semiconductor memory device can further include a first blocking insulating layer BI' and a second blocking insulating layer BI" in addition to the blocking insulating layer BI of the memory layer ML. The first blocking insulating layer BI' and the second blocking insulating layer BI" can include an aluminum oxide layer, a hafnium oxide layer, or the like. The first blocking insulating layer BI' can be interposed between the insulating layer IL and the first conductive layer CDL[1], and can extend between the blocking insulating layer BI and the first conductive layer CDL[1]. The second blocking insulating layer BI" can be interposed between the insulating layer IL and the second conductive layer CDL[2]. When the insulating layer IL is formed as a staircase structure in the global area GAR, the semiconductor memory device can include a fill insulating layer FIL covering the staircase structure. The second blocking insulating layer BI" can extend to be interposed between the fill insulating layer FIL and the second conductive layer CDL[2].

[0156] The first conductive layer CDL[1] and the second conductive layer CDL[2] can be formed of the same conductive material. In an embodiment, each of the first conductive layer CDL[1] and the second conductive layer CDL[2] can include a metal material M2 and a metal nitride M1 formed along a surface of the metal material M2.

[0157] Hereinafter, a method of manufacturing a semiconductor memory device according to an embodiment of the disclosure will be described mainly with respect to a component of a height formed between a source layer and a bit line.

[0158] Figure 12A , Figure 12B , Figure 13A , Figure 13B , Figure 14A , Figure 14B , Figure 15A ,Figure 15B Figure 16A Figure 16B Figure 17A Figure 17B Figure 17C Figure 18 Figure 19 Figure 20A Figure 20B Figure 21A Figure 21B Figure 21C Figure 22A Figure 22B Figure 23 FIGS. 1 through 8 are diagrams of a method of manufacturing a semiconductor memory device according to embodiments of the present disclosure.

[0159] Figure 12A Figure 13A Figure 14A Figure 15A Figure 16A Figure 17A Figure 18 Figure 19 Figure 20A Figure 22A Figure 22B Each of FIGS. 9 through 16 illustrates a plan view of a method of manufacturing a semiconductor memory device. Figure 12B Figure 13B Figure 14B Figure 17B Figure 20B Figure 21A Figure 21B Figure 21C Figure 23 Each of FIGS. 17 through 20 illustrates a cross-sectional view of a process result taken along lines I-I', II-II', and III-III' shown in the corresponding plan view. Figure 15B Figure 16B Figure 17C Each of FIGS. 21 through 24 illustrates a cross-sectional view of a process result taken along line IV-IV' shown in the corresponding plan view.

[0160] Figure 12A Figure 12B FIGS. 25 through 27 are diagrams illustrating a process of forming a mold structure 100 and a plurality of sacrificial pillars 115A, 115B, and 115C.

[0161] Referring to FIGS. 1 through 8, an intermediate insulating layer 101 can be formed on a lower structure (not shown). Although not shown in the drawings, in an embodiment, the lower structure can include a peripheral circuit structure PE shown in FIG. 28, a memory array structure MA shown in FIG. 29, and a substrate SUB shown in FIG. 30. Figure 12A Figure 12B Referring to FIGS. 1 through 8, an intermediate insulating layer 101 can be formed on a lower structure (not shown). Although not shown in the drawings, in an embodiment, the lower structure can include a peripheral circuit structure PE shown in FIG. 28, a memory array structure MA shown in FIG. 29, and a substrate SUB shown in FIG. 30. Figure 8A Figure 8A ​​​​​​​​​​​​​​​​​​​​​​​​​​​​​​​​​​​​​​A preliminary source layer of the sacrificial structure of the first doped semiconductor layer L1, the third doped semiconductor layer L3, and between the first doped semiconductor layer L1 and the third doped semiconductor layer L3 is shown. The sacrificial structure of the preliminary source layer can be replaced in a subsequent process Figure 8A The second doped semiconductor layer L2 shown is replaced. In another embodiment, the lower structure can be a sacrificial substrate formed of a silicon wafer or the like. The sacrificial substrate can be replaced by a substrate of a different material, such as a silicon-on-insulator (SOI) substrate. Figure 8B The source layer SR shown is replaced.

[0162] The intermediate insulating layer 101 can include a top surface extending in the first direction DR1 and the second direction DR2. The plurality of sacrificial layers 103A, 103B, and 103C and the plurality of insulating layers 105A, 105B, and 105C can be alternately stacked one by one in the third direction DR3 on the top surface of the intermediate insulating layer 101. The plurality of sacrificial layers 103A, 103B, and 103C can be formed of a material having etching selectivity with respect to the intermediate insulating layer 101 and the plurality of insulating layers 105A, 105B, and 105C. In an embodiment, the intermediate insulating layer 101 and the plurality of insulating layers 105A, 105B, and 105C can include an insulating material such as a silicon oxide layer or a silicon oxynitride layer, and the plurality of sacrificial layers 103A, 103B, and 103C can include a sacrificial insulating material.

[0163] The plurality of sacrificial layers 103A, 103B, and 103C and the plurality of insulating layers 105A, 105B, and 105C can be divided into a first sub-stacked structure 100[1], a second sub-stacked structure 100[2], and a third sub-stacked structure 100[3]. Specifically, the plurality of sacrificial layers can include at least one first sacrificial layer 103A of the first sub-stacked structure 100[1], a plurality of second sacrificial layers 103B of the second sub-stacked structure 100[2], and at least one third sacrificial layer 103C of the third sub-stacked structure 100[3]. The plurality of insulating layers can include a first insulating layer 105A of the first sub-stacked structure 100[1], a plurality of second insulating layers 105B of the second sub-stacked structure 100[2], and at least one third insulating layer 105C of the third sub-stacked structure 100[3]. The intermediate insulating layer 101 and the plurality of insulating layers 105A, 105B, and 105C can form a molded structure 100. The molded structure 100 can include a first area AR1, a second area AR2, and a third area AR3. The first area AR1 and the third area AR3 can be spaced apart from each other in a horizontal direction, and the second area AR2 can be disposed between the first area AR1 and the third area AR3. In an embodiment, the first area AR1, the second area AR2, and the third area AR3 can be arranged in a row in the first direction DR1.

[0164] Subsequently, a plurality of holes 113A, 113B, and 113C can be formed using the same masking process. The plurality of holes may include a plurality of first holes 113A, a plurality of second holes 113B, and a plurality of third holes 113C. The plurality of first holes 113A can penetrate the first region AR1 of the molded structure 100 and the plurality of sacrificial layers 103A, 103B, and 103C. The plurality of second holes 113B can penetrate the second region AR2 of the molded structure 100 and the plurality of sacrificial layers 103A, 103B, and 103C. In an embodiment, the plurality of second holes 113B can be formed as... Figure 3 or Figure 5 The diagram shows the structure and arrangement corresponding to the multiple gate pillar structures GP. In another embodiment, multiple second holes 113B can be formed as... Figure 7 or Figure 9 The diagram shows the structure and arrangement corresponding to the multiple gate pillar structures (GP) and multiple insulating pillar structures (IP). In the following text, the multiple second holes 113B will be formed as... Figure 7 or Figure 9 The method of manufacturing a semiconductor memory device is described by illustrating the structure and arrangement of the plurality of gate pillar structures (GP) and the plurality of insulating pillar structures (IP). A plurality of third holes (113C) can be formed in multiple rows. The third holes (113C) in each row can be arranged in a single row along a first direction (DR1). The third holes (113C) in each row can be divided into a first group penetrating a first region AR1 of the molding structure 100 and a plurality of sacrificial layers 103A, 103B, and 103C; a second group penetrating a second region AR2 of the molding structure 100 and a plurality of sacrificial layers 103A, 103B, and 103C; and a third group penetrating a third region AR3 of the molding structure 100 and a plurality of sacrificial layers 103A, 103B, and 103C.

[0165] In one embodiment, a plurality of third holes 113C may be formed in a first row Ra and a second row Rb adjacent to each other in the second direction DR2. A plurality of first holes 113A and a plurality of second holes 113B may be disposed between the first row Ra and the second row Rb.

[0166] Although not shown in the figures, multiple holes 113A, 113B, and 113C can extend into the interior of the lower structure. In an embodiment, the lower structure includes... Figure 8A The first doped semiconductor layer L1 and shown Figure 8A When the third doped semiconductor layer L3 is shown, the multiple holes 113A, 113B and 113C can extend to Figure 8A The interior of the first doped semiconductor layer L1 is shown. In another embodiment, when the lower structure includes a sacrificial substrate, a plurality of holes 113A, 113B and 113C may extend into the interior of the sacrificial substrate.

[0167] After this, a plurality of sacrificial pillars 115A, 115B, and 115C can be formed in the plurality of holes 113A, 113B, and 113C, respectively. The plurality of sacrificial pillars 115A, 115B, and 115C can include a material having etch selectivity with respect to the plurality of sacrificial layers 103A, 103B, and 103C. In an embodiment, the plurality of sacrificial layers 103A, 103B, and 103C can include amorphous carbon, tungsten, a titanium nitride layer, or the like. The plurality of sacrificial pillars can include a plurality of first sacrificial pillars 115A inside the plurality of first holes 113A, a plurality of second sacrificial pillars 115B inside the plurality of second holes 113B, and a plurality of third sacrificial pillars 115C inside the plurality of third holes 113C.

[0168] Before the plurality of holes 113A, 113B, and 113C are formed or after the plurality of sacrificial pillars 115A, 115B, and 115C are formed, the plurality of sacrificial layers 103A, 103B, and 103C and the plurality of insulating layers 105A, 105B, and 105C can be etched, thereby forming a staircase structure. The staircase structure can be formed in the third area AR3 and can be covered by the fill insulating layer 111. The fill insulating layer 111 can be formed of an insulating material such as a silicon oxide layer. However, various embodiments of the disclosure are not limited thereto, and a process of forming the staircase structure can be omitted.

[0169] Figure 13A and Figure 13B is a diagram illustrating a process of forming a plurality of pillar structures 120.

[0170] Referring to Figure 13A and Figure 13B The plurality of first sacrificial pillars 115A illustrated in Figure 12A and Figure 12B may be removed. Accordingly, the plurality of first holes can be opened. "113A'" denotes the plurality of opened first holes after the first sacrificial pillars 115A are removed. The plurality of pillar structures 120 can be formed in the plurality of opened first holes 113A', respectively.

[0171] The process of forming the plurality of pillar structures 120 can include a process of forming a memory layer 121 along the inner wall of the first hole 113A' and a process of forming a channel structure 123 and a core insulating layer 125 in a central area of the first hole 113A' opened by the memory layer 121. The memory layer 121 can include a blocking insulating layer, a data storage layer, and a tunnel insulating layer as described with reference to Figure 4C .

[0172] In an embodiment, the process of forming the channel structure 123 and the core insulating layer 125 can include a process of forming a channel layer along the inner wall of the memory layer 121 and a process of filling a central region having a tubular structure defined by the channel layer with the core insulating layer 125 and a cap pattern. The channel layer can be formed of a semiconductor material such as silicon (Si), germanium (Ge), or any mixture thereof, which serves as a channel region. The cap pattern can be formed of a doped semiconductor layer. The channel layer and the cap pattern can form the channel structure 123.

[0173] Figure 14A and Figure 14B are diagrams illustrating a process of forming the insulating pillar structure 131.

[0174] Referring to Figure 14A and Figure 14B , as some of the plurality of second sacrificial pillars 115B are removed, some of the plurality of second holes can be opened. “113B’” denotes the opened second holes. The opened second holes 113B’ can be disposed alternately with the remaining second sacrificial pillars 115B in the first direction DR1 and the second direction DR2 one by one.

[0175] Subsequently, the plurality of insulating pillar structures 131 can be provided by filling the second holes 113B’ with an insulating material.

[0176] Figure 15A , Figure 15B , Figure 16A and Figure 16B are diagrams illustrating a process of forming the first isolation structure 135.

[0177] Referring to Figure 15A and Figure 15B , some of the plurality of third sacrificial pillars 115C can be removed such that a second group of third holes on each row are opened. “113C’” denotes the opened third holes.

[0178] The intermediate insulating layer 101, a portion of each of the plurality of sacrificial layers 103A, 103B, and 103C, and the plurality of insulating layers 105A, 105B, and 105C can be etched through the second group of third holes 113C’, such that the second group of third holes 113C’ are connected to each other. Accordingly, the first trench 133 can be formed. The first trench 133 can be defined by the second group of third holes 113C’ connected to each other. The first trench 133 can have an uneven portion corresponding to a cross-section of each third hole 113’ of the second group.

[0179] Referring to Figure 16A and Figure 16BThe first isolation structure 135 can be filled with a first trench 133. The first isolation structure 135 can be formed of a material different from the materials of the plurality of sacrificial layers 103A, 103B, and 130C and the remaining third sacrificial pillars 115C. In an embodiment, the first isolation structure 135 can include an insulating material such as a silicon oxide layer.

[0180] Figure 17A Figure 17B and Figure 17C are diagrams illustrating a process of isolating the preliminary layer stack structures 100A, 100B, and 100C from each other.

[0181] Referring to Figure 17A Figure 17B and Figure 17C the remaining third sacrificial pillars 115C can be removed such that the third holes of the first and third groups are opened. “113C”” denotes the opened third holes.

[0182] The middle insulating layer 101, a portion of each of the plurality of sacrificial layers 103A, 103B, and 103C, and the plurality of insulating layers 105A, 105B, and 105C can be etched through the third holes 113C” of each of the first and third groups such that the third holes 113C” of the first group can be connected to each other and the third holes 113C” of the third group can be connected to each other. Accordingly, a second trench 137A and a third trench 137B can be formed. The second trench 137A can be defined by the third holes 113C” of the first group connected to each other. The third trench 137B can be defined by the third holes 113C” of the third group connected to each other. Each of the second and third trenches 137A and 137B can have an uneven portion corresponding to a cross-section of each of the third holes 113C”. Each of the second and third trenches 137A and 137B can open the first isolation structure 135, and a portion of the first isolation structure 135 can be etched while each of the second and third trenches 137A and 137B is formed.

[0183] Subsequently, a first portion of the plurality of sacrificial layers 103A, 103B, and 103C overlapping the first region AR1 of the mold structure 100 and a second portion of the plurality of sacrificial layers 103A, 103B, and 103C overlapping the third region AR3 of the mold structure 100 can be removed through the second trench 137A and the third trench 137B. Subsequently, a conductive material can be formed inside each region where the first and second portions of the plurality of sacrificial layers 103A, 103B, and 103C are removed. Before the conductive material is formed, a material such as a silicon oxide layer can be formed in the region where the first portion of the plurality of sacrificial layers 103A, 103B, and 103C is removed, with reference to Figure 11 ​​The first barrier insulating layer is described, and can be formed in the region where the second portions of the plurality of sacrificial layers 103A, 103B, and 103C are removed Figure 11 The second barrier insulating layer is described.

[0184] The conductive material formed in the region where the first portions of the plurality of sacrificial layers 103A, 103B, and 103C are removed can form a plurality of first conductive layers 141A1, 141B1, and 141C1 overlapping the first region AR1 of the molded structure 100. The conductive material formed in the region where the second portions of the plurality of sacrificial layers 103A, 103B, and 103C are removed can form a plurality of second conductive layers 141A2, 141B2, and 141C2 overlapping the third region AR3 of the molded structure 100. The plurality of first conductive layers can include at least one source select gate layer 141A1, a plurality of cell gate layers 141B1, and at least one drain select gate layer 141C1. The plurality of second conductive layers can include at least one source select level contact conductive layer 141A2, a plurality of cell level contact conductive layers 141B2, and at least one drain select level contact conductive layer 141C2.

[0185] The molded structure 100 can be isolated into preliminary layer stack structures 100A, 100B, and 100C by the second trench 137A, the first isolation structure 135, and the third trench 137B connected to each other. Each preliminary layer stack structure 100A, 100B, or 100C can include the plurality of first conductive layers 141A1, 141B1, and 141C1, the plurality of second conductive layers 141A2, 141B2, and 141C2, and the plurality of sacrificial layers 103A, 103B, and 103C between the plurality of first conductive layers 141A1, 141B1, and 141C1 and the plurality of second conductive layers 141A2, 141B2, and 141C2.

[0186] Figure 18 is a plan view illustrating the cell gate layer 141B1, the second sacrificial layer 103B, and the cell level contact conductive layer 141B2 along the line A-A’ shown in Figure 17B and Figure 17C is a plan view illustrating the cell gate layer 141B1, the second sacrificial layer 103B, and the cell level contact conductive layer 141B2 along the line A-A’ shown in

[0187] Referring to Figure 18 , the cell gate layer 141B1, the second sacrificial layer 103B, and the cell level contact conductive layer 141B2 can be arranged in the first direction DR1 along the second trench 137A, the first isolation structure 135, and the third trench 137B.

[0188] Figure 19 is a plan view illustrating a process of forming the second isolation structure 145A and the third isolation structure 145B.

[0189] Referring to Figure 19Each of the second trench 137A and the third trench 137B can be filled with at least one of an insulating layer, a conductive layer, and a semiconductor layer. Therefore, a second isolation structure 145A can be formed inside the second trench 137A, and a third isolation structure 145B can be formed inside the third trench 137B. When each of the second isolation structure 145A and the third isolation structure 145B includes a conductive layer or a semiconductor layer, a spacer insulating layer can be formed on the sidewall of each of the second trench 137A and the third trench 137B before forming the conductive layer or the semiconductor layer.

[0190] Figure 20A and Figure 20B This is a diagram illustrating the process of forming a protective layer 151 including an opening 155.

[0191] Reference Figure 20A and Figure 20B A protective layer 151 can be formed to cover and fill the insulating layer 111 and Figure 19 The preliminary laminated structures 100A, 100B, and 100C are shown. The protective layer 151 may be formed of a material different from the material of the remaining second sacrificial pillar 115B and the plurality of sacrificial layers 103A, 103B, and 103C. In an embodiment, the protective layer 151 may include a silicon oxide layer.

[0192] Subsequently, an opening 155 can be formed by etching a portion of the protective layer 151. The opening 155 can overlap with the second region AR2 of the molded structure 100 and open the remaining second sacrificial pillar 115B and insulating pillar structure 131.

[0193] Figure 21A , Figure 21B and Figure 21C This is a diagram illustrating the process of forming multiple active layers 161A, 161B and 161C, as well as the process of forming the gate pillar structure.

[0194] Reference Figure 21A , Figure 20B The remaining second sacrificial post 115B shown can be removed through opening 155. Therefore, a second hole can be opened. "113B" indicates the opened second hole. The second hole 113B can be alternately arranged with the insulating post structure 131 in the first direction DR1 and the second direction DR2.

[0195] Reference Figure 21B After removing multiple sacrificial layers overlapping with the second region AR2 of the molded structure 100 through the second hole 113B, multiple active layers 161A, 161B, and 161C can be formed in the region where the multiple sacrificial layers have been removed. In an embodiment, multiple insulating pillar structures 131 can be used as supports capable of reducing deformation of the structure of the second region AR2 of the molded structure 100.

[0196] Although not shown in the drawings, in the case of an embodiment in which a first barrier insulating layer is formed along a surface of each of the plurality of first conductive layers 141A1, 141B1, and 141C1 and a second barrier insulating layer is formed along a surface of each of the plurality of second conductive layers 141A2, 141B2, and 141C2, a portion of each of the first barrier insulating layer and the second barrier insulating layer can be removed by the second hole 113B” before the plurality of active layers 161A, 161B, and 161C are formed. Therefore, a sidewall of each of the plurality of first conductive layers 141A1, 141B1, and 141C1 and the plurality of second conductive layers 141A2, 141B2, and 141C2 can be exposed and can be in contact with the plurality of active layers 161A, 161B, and 161C which are formed later.

[0197] The plurality of active layers 161A, 161B, and 161C can include a source select level active layer 161A, a plurality of cell level active layers 161B, and a drain select level active layer 161C.

[0198] Referring to Figure 21C A gate pillar structure including the gate insulating layer 163 and the gate electrode 165 can be formed inside each of the second holes 113B”.

[0199] The process of forming the gate pillar structure can include a process of forming the gate insulating layer 163 along the inner wall of the second hole 113B”, a process of filling a central region of the second hole 113B” opened by the gate insulating layer 163 with a conductive material, and a process of planarizing the conductive material and the gate insulating layer 163. Figure 21B The protective layer 151 shown can be removed by a planarization process.

[0200] Figure 22A is a plan view of the cell gate layer 141B1, the cell level active layer 161B, and the cell level contact conductive layer 141B2 taken along Figure 21C is a plan view of the cell gate layer 141B1, the cell level active layer 161B, and the cell level contact conductive layer 141B2 taken along

[0201] Referring to Figure 22A A sidewall of the cell gate layer 141B1 can extend in the first direction DR1 along the second isolation structure 145A and have an uneven portion. The cell gate layer 141B1 can surround the plurality of pillar structures 120.

[0202] The cell-level active layer 161B can have a first sidewall extending in the first direction DR1 along the first isolation structure 135 and a second sidewall intersecting the first sidewall and extending in the second direction DR2. The first sidewall can have an uneven portion along the first isolation structure 135. The second sidewall can contact the cell gate layer 141B1 or the cell-level contact conductive layer 141B2 and have an uneven portion. The cell-level active layer 161B can extend between the gate insulating layer 163 and the insulating pillar structure 131.

[0203] A sidewall of the cell-level contact conductive layer 141B2 can extend in the first direction DR1 along the third isolation structure 145B and have an uneven portion.

[0204] Figure 22B is a plan view of the second insulating layer 105B taken along the line B-B’ shown in FIG. 1B. Figure 21C

[0205] Referring to Figure 22B , the second insulating layer 105B can extend continuously along the first region AR1, the second region AR2, and the third region AR3.

[0206] Figure 23 Some processes continuing after a process of forming the through-gate 165 are exemplified.

[0207] Referring to Figure 23 , the fourth insulating layer 167 can be formed to cover the fill insulating layer 111, the molding structure 100, the pillar structure 120, and the through-gate 165. Subsequently, the Figure 3 , Figure 4A or Figure 7 selective line isolation structure SS shown in FIG. 1C can be formed. Thereafter, the conductive bit line contact structure 171A, the conductive gate contact structure 171B, and the plurality of global conductive patterns 171C penetrating at least one of the insulating layer 105A, 105B, or 105C of the fill insulating layer 111 and the molding structure 100 through the fourth insulating layer 167 can be formed. Thereafter, subsequent processes such as a process of forming a bit line can be performed.

[0208] Figure 24A , Figure 24B and Figure 24C are cross-sectional views exemplifying a method of manufacturing a semiconductor memory device according to an embodiment of the disclosure.

[0209] Referring to Figure 24A , the method of manufacturing a semiconductor memory device according to an embodiment of the disclosure can be used with reference to Figure 12A , Figure 12B , Figure 13A , Figure 13B , Figure 14A , Figure 14B , Figure 15A ​、 Figure 15B 、 Figure 16A 、 Figure 16B 、 Figure 17A 、 Figure 17B 、 Figure 17C 、 Figure 18 、 Figure 19 、 Figure 20A 、 Figure 20B 、 Figure 21A 、 Figure 21B and Figure 21C The process described forms a lower layer stack 140A. The lower layer stack 140A can include a molded structure 100’ that includes the middle insulating layer 101, the at least one first insulating layer 105A and the plurality of second insulating layers 105B, the at least one source select gate layer 141A1, the at least one source select level contact conductive layer 141A2, the at least one source select level active layer 161A, the plurality of cell gate layers 141B1, the plurality of cell level contact conductive layers 141B2, and the plurality of cell level active layers 161B. When the lower structure 140A is formed as a staircase structure, the staircase structure can be covered with a first fill insulating layer 111.

[0210] The first region of the molded structure 100’ and the source select gate layers 141A1 and the plurality of cell gate layers 141B1 overlapping therewith can be penetrated by a first pillar structure 120A, and the first pillar structure 120A can include a memory layer 121, a channel structure 123, and a core insulating layer 125. The second region AR2 of the molded structure 100’ and the source select level active layers 161A and the plurality of cell level active layers 161B overlapping therewith can be penetrated by a gate pillar structure including a through gate insulating layer 163 and a through gate 165, and an insulating pillar structure 131. The source select contact conductive layers 141A2 and the plurality of cell level contact conductive layers 141B2 can overlap with a third region AR3 of the molded structure 100’.

[0211] Referring to Figure 24B At least one drain select gate layer 141C and at least one third insulating layer 105C can be stacked on the lower layer stack 140A, thereby forming an upper layer stack 140B. The upper layer stack 140B can be etched as a staircase structure to open the second region AR2 and the third region AR3 of the molded structure 100’ and overlap with the first region AR1 of the molded structure 100’. Subsequently, a second pillar structure 120B penetrating the upper layer stack 140B can be formed. The second pillar structure 120B can be connected to the first pillar structure 120A. The second pillar structure 120B can include a gate insulating layer 121’, an upper channel structure 123’, and an upper core insulating layer 125’. Subsequently, a select isolation structure isolating the drain select gate layers 141C of the upper layer stack 140B into drain select lines can be formed.

[0212] Referring to Figure 24C The insulating structure 170 can be formed to cover the upper layer stack 140B, the lower layer stack 140A, and the fill insulating layer 111. Subsequently, the conductive bit line contact structure 171A, the conductive local contact structure 171D, the conductive gate contact structure 171B, and the plurality of global conductive patterns 171C that penetrate the insulating structure 170 can be formed. The conductive bit line contact structure 171A can be connected to the channel structure 123’ of the second pillar structure 120B. The conductive local contact structure 171D can be connected to the drain select gate layer 141C corresponding thereto while penetrating the third insulating layer 105C. The conductive gate contact structure 171B can be connected to the pass gate 165. Each of the global conductive patterns 171C can be connected to the corresponding contact conductive layer among the source select level contact conductive layer 141A2 and the cell level contact conductive layer 141B2 while penetrating the corresponding insulating layer among the first insulating layer 105A and the second insulating layer 105B.

[0213] Figure 25A and Figure 25B is a diagram illustrating a semiconductor memory device according to an embodiment of the disclosure.

[0214] Figure 25A is a plan view illustrating a second region of the molding structure 100, and Figure 25B is a cross-sectional view of the semiconductor memory device taken along the line IIb-IIb’ shown in Figure 25A .

[0215] Referring to Figure 25A and Figure 25B The molding structure 100, the plurality of active layers 161A, 161B, and 161C, the plurality of pass gate insulating layers 163, the plurality of pass gates 165, and the plurality of insulating pillar structures 131 can be formed using the processes described with reference to Figure 12A , Figure 12B , Figure 13A , Figure 13B , Figure 14A , Figure 14B , Figure 15A , Figure 15B , Figure 16A , Figure 16B , Figure 17A , Figure 17B , Figure 17C , Figure 18 , Figure 19 , Figure 20A , Figure 20B , Figure 21A , Figure 21B and Figure 21C .

[0216] As described with reference to Figure 21AThe plurality of active layers 161A, 161B, and 161C can be formed in regions in which the plurality of sacrificial layers are removed through the opened second holes, respectively. Before the plurality of sacrificial layers are removed, the second holes can be enlarged such that the opened second holes expose the insulating pillar structure 131. "113BB" denotes the enlarged second holes. Thereafter, the plurality of active layers 161A, 161B, and 161C can replace the plurality of sacrificial layers through the enlarged second holes 113BB. Thus, the insulating pillar structure 131 can be connected through the gate insulating layer 163.

[0217] Figure 26 is a block diagram illustrating an electronic system according to an embodiment of the disclosure.

[0218] Referring to Figure 26 The electronic system 1000 can be a computing system, a medical device, a communication device, a wearable device, a memory system, or the like. The electronic system 1000 can include a host 1100 and a storage device 1200.

[0219] The host 1100 can store data in the storage device 1200 or read data stored in the storage device 1200 based on an interface. The interface can include one or more of a double data rate (DDR) interface, a universal serial bus (USB) interface, a multimedia card (MMC) interface, an embedded MMC (eMMC) interface, a peripheral component interconnect (PCI) interface, a fast PCI (PCI-E) interface, an advanced technology attachment (ATA) interface, a serial ATA (SATA) interface, a parallel ATA (PATA) interface, a small computer system interface (SCSI), an enhanced small disk interface (ESDI), an integrated drive electronics (IDE) interface, a firewire interface, a universal flash memory (UFS) interface, and a non-volatile memory express (NVMe) interface.

[0220] The storage device 1200 can include a memory controller 1210 and a semiconductor memory device 1220. In an embodiment, the storage device 1200 can be a storage medium such as a solid state drive (SSD) or a universal serial bus (USB) memory.

[0221] The memory controller 1210 can store data in the semiconductor memory device 1220 or read data stored in the semiconductor memory device 1220 under the control of the host 1100.

[0222] The semiconductor memory device 1220 can include one memory chip or a plurality of memory chips. The semiconductor memory device 1220 can store data or output the stored data under the control of the memory controller 1210.

[0223] In an embodiment, the semiconductor memory device 1220 can be a nonvolatile memory device. In an embodiment, the semiconductor memory device 1220 can include a plurality of conductive layers arranged in a vertical direction, a plurality of active layers connected to the plurality of conductive layers, a plurality of pass gates penetrating the plurality of active layers, and a plurality of pass gate insulating layers respectively surrounding sidewalls of the plurality of pass gates.

[0224] According to various embodiments of the present disclosure, the plurality of active layers arranged in the vertical direction and the pass gates penetrating the plurality of active layers can form a pass transistor group. Accordingly, in an embodiment, although a planar area occupied by the pass transistor group does not increase, the number of layers of the active layers increases in correspondence with the number of layers of the conductive layers, so that the conductive layers can be controlled. As a result, in an embodiment, a planar area occupied by the pass transistor group in a peripheral circuit structure can be reduced.

[0225] CROSS-REFERENCE TO RELATED APPLICATIONS

[0226] This application claims priority to Korean Patent Application No. 10-2024-0081982, filed on June 24, 2024, in the Korean Intellectual Property Office, the disclosure of which is incorporated herein in its entirety by reference.

Claims

1. A semiconductor memory device, the semiconductor memory device comprising: Multiple unit column structures, the multiple unit column structures extending in the vertical direction, the multiple unit column structures being arranged to be spaced apart from each other in the horizontal direction; A word line stack-up structure, the word line stack-up structure surrounding the plurality of cell pillar structures, the word line stack-up structure including a plurality of cell gate layers arranged to be spaced apart from each other in the vertical direction; Multiple unit-level contact conductive layers, the multiple unit-level contact conductive layers being spaced apart from the multiple unit gate layers in the horizontal direction, and the multiple unit-level contact conductive layers being arranged to be spaced apart from each other in the vertical direction; Multiple cell-level active layers are connected to multiple cell gate layers, the multiple cell-level active layers extend in the horizontal direction to connect to multiple cell-level contact conductive layers, and the multiple cell-level active layers are arranged to be spaced apart from each other in the vertical direction. A plurality of through gates, the plurality of through gates being spaced apart from each other in the horizontal direction, each of the plurality of through gates penetrating the plurality of cell-level active layers; Multiple through-gate insulating layers, the multiple through-gate insulating layers respectively surrounding the sidewalls of the multiple through-gates; as well as Multiple insulating pillar structures are alternately arranged with the multiple gates in the horizontal direction, and the multiple insulating pillar structures penetrate the multiple unit-level active layers.

2. The semiconductor memory device of claim 1, further comprising a plurality of conductive gate contact structures corresponding to a plurality of rows arranged through gates. in, Two or more of the plurality of through gates in each of the plurality of rows are arranged in a row in a first direction, and Each of the plurality of conductive gate contact structures extends in the first direction to connect to the through gate of the corresponding row among the plurality of rows.

3. The semiconductor memory device according to claim 2, further comprising: A conductive connection pattern, wherein the conductive connection pattern is connected to the plurality of conductive gate contact structures; as well as Block select lines are connected to the plurality of through gates via the plurality of conductive gate contact structures and the conductive connection pattern.

4. The semiconductor memory device according to claim 1, wherein, The plurality of cell-level active layers and the plurality of transistor groups connected to the plurality of cell gate layers are formed through gates.

5. The semiconductor memory device of claim 1, further comprising a plurality of global conductive patterns connected to the plurality of cell-level contact conductive layers, the plurality of global conductive patterns extending in the vertical direction.

6. The semiconductor memory device of claim 1, further comprising a source-select gate layer and a drain-select gate layer, the source-select gate layer and the drain-select gate layer being spaced apart from each other in the vertical direction and the word line stack structure being inserted between the source-select gate layer and the drain-select gate layer, the source-select gate layer and the drain-select gate layer surrounding the plurality of cell pillar structures.

7. The semiconductor memory device of claim 6, further comprising a selection isolation structure that penetrates the drain selection gate layer and isolates the drain selection gate layer into at least two drain selection lines surrounding different cell pillar structures among the plurality of cell pillar structures.

8. The semiconductor memory device of claim 7, further comprising: A drain-select active layer extends in the horizontal direction from each of the at least two drain select lines and surrounds a corresponding through gate among the plurality of through gates. as well as A drain selection stage contact conductive layer extends from the drain selection stage active layer in the horizontal direction. The selective isolation structure extends to penetrate the drain selection active layer and the drain selection contact conductive layer.

9. The semiconductor memory device according to claim 8, wherein, The drain selection active layer and the corresponding transistor formed by the gate are connected to the corresponding drain selection line among the at least two drain selection lines.

10. The semiconductor memory device of claim 8, further comprising a global conductive pattern connected to the drain selection contact conductive layer, the global conductive pattern extending in the vertical direction.

11. The semiconductor memory device of claim 7, further comprising at least two conductive local contact structures extending from the at least two drain selection lines in the vertical direction.

12. The semiconductor memory device of claim 11, further comprising: Multiple global conductive patterns are respectively connected to multiple unit-level contact conductive layers, and the multiple global conductive patterns extend in the vertical direction; as well as A plurality of conductive gate contact structures, the plurality of conductive gate contact structures corresponding to a plurality of rows configured with a plurality of through gates, the plurality of conductive gate contact structures extending in a first direction to connect to the through gate of the corresponding row among the plurality of rows. The plurality of conductive gate contact structures are disposed between the at least two conductive local contact structures and the plurality of global conductive patterns.

13. The semiconductor memory device of claim 6, further comprising: A source-selection level active layer, the source-selection level active layer extending from the source-selection gate layer in the horizontal direction, the source-selection level active layer surrounding the plurality of through gates; as well as A source selection stage contact conductive layer extends from the source selection stage active layer in the horizontal direction.

14. The semiconductor memory device according to claim 13, wherein, The source-selective active layer and the plurality of transistor groups connected to the source-selective gate layer are formed through gates.

15. The semiconductor memory device of claim 13, further comprising a global conductive pattern connected to the source selection level contact conductive layer, the global conductive pattern extending in the vertical direction.

16. A semiconductor memory device, the semiconductor memory device comprising: A source layer having a first surface and a second surface facing opposite directions and extending in a horizontal direction; Bit lines are configured to be spaced apart from the second surface of the source layer in the vertical direction; Multiple insulating layers, the multiple insulating layers including a local region, a global region spaced apart from the local region in the horizontal direction, and a region through a transistor array between the local region and the global region, the multiple insulating layers being spaced apart from each other in the vertical direction between the second surface of the source layer and the bit line; Multiple first conductive layers are alternately disposed with the multiple insulating layers in the local area in the vertical direction; Multiple unit pillar structures, wherein the multiple unit pillar structures penetrate the multiple first conductive layers and the multiple insulating layers; Multiple active layers are alternately disposed in the vertical direction with the multiple insulating layers in the transistor array region; Multiple through gates, each of the multiple through gates including a first end and a second end, the first end being in the same direction as the first surface of the source layer, the second end being in the same direction as the second surface of the source layer, and each of the multiple through gates penetrating the multiple active layers and the multiple insulating layers; as well as Multiple through-gate insulating layers, each of which surrounds the sidewalls of the multiple through-gates. Wherein, the first end of each of the plurality of gates is configured to be closer to the plurality of insulating layers than the first surface of the source layer.

17. The semiconductor memory device of claim 16, further comprising a first isolation structure that penetrates the plurality of insulating layers in the transistor array region, the first isolation structures being spaced apart from each other and the plurality of gates and the plurality of active layers being interposed between the first isolation structures.

18. The semiconductor memory device according to claim 17, wherein, The plurality of active layers are connected to the first conductive layer and are adjacent to the plurality of first conductive layers in a first direction, and The first isolation structures are adjacent to each other in a second direction that intersects with the first direction.

19. The semiconductor memory device of claim 17, further comprising: A second isolation structure, which penetrates the plurality of insulating layers in the local area, is respectively connected to the first isolation structure; A third isolation structure, which penetrates the plurality of insulating layers in the global region, is respectively connected to the first isolation structure; Multiple second conductive layers are alternately disposed with the multiple insulating layers in the global region in the vertical direction; as well as Multiple global conductive patterns extend from the multiple second conductive layers in the vertical direction.

20. The semiconductor memory device of claim 19, wherein, The plurality of unit column structures and the plurality of first conductive layers are disposed between the second isolation structure. The plurality of second conductive layers are disposed between the third isolation structure. The plurality of second conductive layers are connected to the plurality of active layers and are adjacent to the plurality of active layers in a first direction. The first isolation structures are adjacent to each other in a second direction that intersects with the first direction.

21. The semiconductor memory device of claim 19, wherein, Uneven portions are formed on the sidewalls of each of the plurality of insulating layers extending along the first, second, and third isolation structures in the horizontal direction.

22. The semiconductor memory device of claim 16, wherein, The plurality of active layers and the plurality of transistor groups connected to the plurality of first conductive layers via gates.

23. The semiconductor memory device of claim 16, further comprising: Multiple conductive gate contact structures, the multiple conductive gate contact structures corresponding to multiple rows configured with multiple gates; as well as A block select line, which is connected to the plurality of conductive gate contact structures.

24. The semiconductor memory device of claim 23, wherein, Each of the plurality of through gates has a cross-sectional structure with a major axis in a first direction and a minor axis in a second direction intersecting the plurality of rows. Wherein, the plurality of gates are spaced apart from each other in the second direction, and The plurality of conductive gate contact structures are respectively connected to the plurality of through gates.

25. The semiconductor memory device according to claim 23, wherein, Two or more of the plurality of through gates in each of the plurality of rows are arranged in a row in a first direction, and Each of the plurality of conductive gate contact structures extends in the first direction to connect to two or more of the plurality of through gates in each of the plurality of rows.

26. The semiconductor memory device of claim 16, further comprising a plurality of insulating pillar structures that penetrate the plurality of insulating layers and the plurality of active layers in the transistor array region. in, The plurality of insulating pillar structures are alternately arranged with the plurality of gates in the horizontal direction.

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