PTL-based processor calculation unit design method, basic gate circuit, processor calculation unit and processor

Abstract

The invention discloses a PTL-based processor calculation unit design method, which comprises the following steps: multiplexing a processor dual-port register, and obtaining the input of a PTL basic gate circuit from the output of the dual-port register, so as to form a PTL gate circuit as the design basis of a processor calculation unit. The PTL basic gate circuit comprises a NOT gate, an AND gate, an OR gate, an NAND gate, a NOR gate, an XOR gate, an XNOR gate or a transmission gate. And the processor calculation unit comprises an adder, a multiplier or a logical operation unit. And the dual-port register outputs complementary signal pair input of the PTL basic gate circuit.

Description

TECHNICAL FIELD

[0001] The present disclosure belongs to the technical field of computer processors, and particularly relates to a PTL-based processor computing unit design method, a basic gate circuit, a processor computing unit and a processor. BACKGROUND

[0002] The operation unit in a processor is an important component of a microprocessor core, and its main function is to complete various basic computing tasks including arithmetic operations, logical judgments, shift operations, etc. The performance of the operation unit directly affects the computing speed, energy consumption and overall performance of the entire processor. Therefore, the design optimization of the operation unit is one of the important research directions in the field of processor architecture. Especially in the current emerging technology scenarios of Internet of Things, edge computing and artificial intelligence, higher requirements are put forward for the performance and energy efficiency of the processor, which makes the optimization of the operation unit an important way to improve the overall performance of the system.

[0003] Most of the existing processor operation unit designs widely adopt the traditional CMOS logic design method. However, with the continuous reduction of CMOS process nodes into the nanometer era, Moore's Law has gradually slowed down, and the process scaling of traditional CMOS logic has not been able to effectively improve the transistor integration density, and the power consumption reduction has also tended to be saturated. Therefore, the computing unit based on traditional CMOS process is difficult to make significant breakthroughs in power consumption and area efficiency, especially not suitable for end-side computing scenarios sensitive to energy efficiency and area.

[0004] To solve the limitations of traditional CMOS design methods in power consumption and area, Pass Transistor Logic (PTL) has gradually attracted attention. Compared with traditional CMOS logic, the basic principle of PTL is to use transistors as controlled switches directly, and use input signals to control the connection between the output node and the logic level, thereby realizing the logic function. Figure 1 is the schematic diagram of the transmission tube logic, and Figure 1 For example, as shown in the complementary logic transmission gate structure of (a), when the input signals X or Y are high, the output node F is directly connected to the signal A or its inverse signal, thereby avoiding the NMOS and PMOS tube combination structure that must appear in pairs in CMOS logic. This structure eliminates the complementary PMOS-NMOS structure required when implementing logic functions in traditional CMOS logic, fundamentally reducing the number of transistors, theoretically saving more than half of the transistor overhead, and effectively reducing the area and power consumption of the logic unit.

[0005] According to the existing research results, a variety of key arithmetic operation units have been successfully implemented using transmission gate logic. For example, Chaitanya et al. optimized the design of an adder unit for a multiplier using transmission gate logic, which outperformed the traditional CMOS in terms of area, delay, and power consumption. Senthilpari et al. constructed an 8x8-bit multiplier based on non-clock-controlled transmission gate logic, which reduced power consumption by up to 97.6% and significantly improved delay performance compared to traditional design schemes. In addition, Kumar and Pandey proposed an XOR-XNOR circuit based on a 5-transistor transmission gate logic design, which reduced the power-delay product (PDP) by more than 50% compared to traditional designs, fully demonstrating the potential of transmission gate logic in implementing low-power and high-performance circuits. The above research results fully verify the effectiveness and feasibility of transmission gate logic in practical applications, providing a solid theoretical basis and practical experience for further development of high-efficiency processor computing units based on transmission gate logic. SUMMARY

[0006] One of the embodiments of the present disclosure is a processor computing unit design method based on transmission gate logic. A dual-port register is multiplexed, and the output of the dual-port register is used to obtain the input of a PTL basic gate circuit to form a PTL gate circuit as the basis for designing a processor computing unit. The PTL basic gate circuit includes a NOT gate, an AND gate, an OR gate, a NAND gate, a NOR gate, an XOR gate, an XNOR gate, or a transmission gate. The processor computing unit includes an adder, a multiplier, or a logic operation unit. The dual-port register outputs a complementary signal pair of the PTL basic gate circuit. The processor computing unit designed based on the PTL basic gate circuit includes cascaded PTL basic gate circuits and transmission gates.

[0007] The PTL-based processor computing unit design method of the present disclosure successfully eliminates the defects of PTL itself by multiplexing a dual-port register and designing cascaded transmission gate and transmission gate circuits. The present disclosure can be widely used in PTL-based computing circuit design. BRIEF DESCRIPTION OF DRAWINGS

[0008] The above and other objects, features and advantages of the exemplary embodiments of the present disclosure will be readily understood through reading the following detailed description, with reference to the accompanying drawings. In the drawings, several embodiments of the present disclosure are illustrated by way of example and not limitation in which:

[0009] Figure 1 Schematic diagram of transmission gate logic principle.

[0010] Figure 2 Schematic diagram of TSMC180 PDK DFFX1 standard cell.

[0011] Figure 3 Full adder subcircuit 1 schematic diagram according to one of the embodiments of the present disclosure.

[0012] Figure 4 Full adder subcircuit 2 schematic diagram according to one of the embodiments of the present disclosure.

[0013] Figure 5 Full adder circuit schematic diagram according to one of the embodiments of the present disclosure

[0014] Figure 6 PTL full adder function verification waveform diagram schematic diagram according to one of the embodiments of the present disclosure.

[0015] Figure 7 Power consumption, delay simulation circuit diagram schematic diagram according to one of the embodiments of the present disclosure.

[0016] Figure 8 PTL full adder delay schematic diagram under different input signal flip conditions according to one of the embodiments of the present disclosure.

[0017] Figure 9 PTL full adder delay schematic diagram under different input signal flip conditions according to one of the embodiments of the present disclosure.

[0018] Figure 10 Non-sign bit multiplication circuit schematic diagram according to one of the embodiments of the present disclosure.

[0019] Figure 11 Sign bit multiplication calculation circuit schematic diagram according to one of the embodiments of the present disclosure. DETAILED DESCRIPTION

[0020] Although the prior art proposes a variety of processor computing unit architectures based on transmission tube logic (PTL), including full adder, multiplier and various logic function modules, the number of required transistors is significantly lower than that of traditional CMOS design, showing significant area and power consumption advantages, however, there are still several key technical bottlenecks in actual design and application which have not been effectively solved.

[0021] Firstly, PTL technology itself inherently has signal voltage drop problems due to the physical mechanism of NMOS and PMOS devices. When using an NMOS transistor to transmit a logic high level, the level of the output node can only reach VDD-Vth at most, and there is a threshold voltage loss. Similarly, when using a PMOS transistor to transmit a logic low level, the level of the output node will be lifted to be higher than the ground level (GND+|Vth|). In a multi-stage or long logic path, this non-ideal voltage transmission effect will accumulate stage by stage, causing continuous degradation of the signal amplitude, and eventually possibly causing logic misjudgment or failure, especially in processor computing units and other modules that are highly dependent on accurate logic determination. Although existing research schemes attempt to compensate for this voltage drop through cross-coupled inverters or special level restoration circuits, the additional 2-4 transistors at each restoration node not only weaken the transistor quantity advantage brought by the PTL architecture itself, but also introduce additional timing delay, reducing the overall speed of the circuit. Among the parameters of MOSFET (Metal Oxide Semiconductor Field Effect Transistor), VDD and Vth are two important voltage parameters. VDD is the power supply voltage, which is the positive power supply voltage connected to the drain or source of the MOSFET. Vth is the threshold voltage, also known as the turn-on voltage or threshold voltage, which refers to the minimum voltage of the gate relative to the source when the MOSFET starts to conduct. Only when the gate voltage exceeds this threshold voltage, the MOSFET will change from the off state to the on state.

[0022] Secondly, PTL designs often need to provide a complete set of complementary input signals, that is, each input logic variable needs to provide both the original signal and its inverse signal (such as A and A non, B and B non). Since the PTL logic unit itself does not have the ability to generate complementary signals, the generation of additional complementary signals usually relies on external CMOS inverters. This design requirement causes at least one inverter to be added to each input port, which will significantly increase the hidden area overhead in processor computing units with a large number of logic inputs. For example, a multi-bit operation unit (such as an N-bit adder or multiplier) usually needs to additionally configure 2N transistors for generating complementary input signals. This hidden transistor overhead not only offsets the transistor quantity benefits provided by PTL itself, but also causes an increase in metal wiring density and an increase in layout difficulty, which is particularly evident at advanced process nodes.

[0023] In summary, the existing processor computing unit design based on PTL technology has not effectively solved the logic misjudgment risk caused by signal pressure drop and the implicit area overhead problem caused by complementary signal generation while realizing the advantages of high integration density and low power consumption. Therefore, it is urgent to propose an innovative processor computing unit design scheme based on PTL, which can simultaneously avoid or alleviate the above two technical bottlenecks, so as to more fully exert the high integration and low power potential of PTL in processor chip design.

[0024] Therefore, the technical problems to be solved by the present disclosure include:

[0025] (1) PTL logic gate needs to be implemented by a pair of complementary signals to realize pass gating, and the signal pair cannot be generated inside the transmission tube structure. The existing design is forced to configure an independent CMOS inverter for each input, resulting in additional implicit area cost.

[0026] (2) The transmission tube itself is constrained by the physical mechanism of the device, which will cause non-ideal pressure drop in signal transmission, which will lead to logic error after accumulation, forcing the existing scheme to introduce a level restoration circuit to offset the area advantage of PTL and introduce timing uncertainty.

[0027] According to one or more embodiments, the processor unit design scheme proposed by the present disclosure adopts,

[0028] (1) multiplexing a dual-port output register, and

[0029] (2) cascading the transmission tube logic and the transmission gate.

[0030] These two optimization methods solve the complementary input signal pair and signal pressure drop problems in PTL design. The following will take the design process of a full adder as an example to gradually introduce the design method proposed by the present disclosure, and finally show the complete design, and verify the effectiveness of the proposed method through experiments.

[0031] 1. Multiplexing processor dual-port output register.

[0032] Firstly, the present disclosure considers that in the design of processor arithmetic operation unit, in order to avoid the performance bottleneck caused by too long combinational logic pass, a register is usually inserted to improve the working frequency. When high bit width operation is performed, the processor needs to read operands A and B from the source register for calculation, and write the result back to the target register. There is a dual-port output register in each process library, which can output the signal itself and its negation latched in the last cycle at the same time, for example, the DFFX1 cell is provided in the TSMC180nm process library. As shown in Figure 2As shown, the DFFX1 unit simultaneously outputs Q and Q non-signal, which can be used as a complementary input pair of PTL logic. Therefore, to solve the problem of needing a complementary input signal pair for PTL design, the present method multiplexes the dual-port output D flip-flop in the standard cell library of the processor, which makes the present disclosure directly obtain the required complementary input signal pair without additional design of independent inverters. Through this multiplexing mode, the present disclosure effectively reduces the implicit overhead of transistors.

[0033] After obtaining the complementary input signal pair, the present disclosure constructs a subcircuit 1 to implement the A XOR B (XOR) logic function, as shown in Figure 3 The specific method is to connect the complementary signals B and B non to the source of the NMOS transmission tube, and connect A and A non to the gate of the NMOS transmission tube. This structure efficiently implements the XOR logic, but due to the threshold voltage loss of the high-level transmission of the NMOS tube, there may be a signal pressure drop.

[0034] Figure 3 The circuit includes a first D flip-flop and a second D flip-flop, and the input signals A and B pass through the first D flip-flop and the second D flip-flop, respectively, to output two signal pairs: A and A non (the inverse of A), and B and B non (the inverse of B). The circuit also includes a first NMOS tube and a second NMOS tube, and the source of each transistor is connected to the complementary signals A and A non, and the gate is controlled by the complementary signals B and B non. The drain of the first NMOS tube and the second NMOS tube is connected in parallel to output A XOR B, which is the XOR logic operation result of A and B.

[0035] 2. Transmission tube logic cascade transmission gate eliminates pressure drop.

[0036] To solve the problem of pressure drop of the output signal of the subcircuit 1, the present disclosure further designs a subcircuit 2. The subcircuit 2 first uses a CMOS inverter to take the inverse of the XOR signal to obtain a strong "0" signal, which forms a complementary transmission gate control pair with the weak "1" signal output by the subcircuit 1. The weak "1" signal drives the gate of the complementary transmission gate, causing a weak gate control condition. The complementary transmission gate is composed of an NMOS tube and a PMOS tube in complementary, so even if it is driven by a weak "1" or a weak "0", the complementary transmission gate can still remain on. When transmitting a weak "1", even if the NMOS is off, the PMOS can still remain on to transmit a strong "1". Similarly, when transmitting a weak "0". Thus, through the cascade structure of the subcircuit 1 and the subcircuit 2, the threshold voltage drop generated by the subcircuit 1 is completely eliminated, ensuring signal integrity.

[0037] As shown in Figure 4 C in is the carry-in of the full adder, S (Sum) is the sum output of the full adder, and C outCarry out of the full adder, A and B are two operand inputs of the full adder. Figure 4 The circuit includes an inverter and a plurality of complementary pass gates each comprising two MOS transistors connected in parallel. The output of the inverter is connected to the gate of the first MOS transistor of the first complementary pass gate and to the source of the second MOS transistor of the second complementary pass gate.

[0038] In the sub-circuit 2, an inverter is included, and the A and B signals are input into the inverter. The sub-circuit 2 includes a first complementary pass gate, a second complementary pass gate, a third complementary pass gate and a fourth complementary pass gate. The complementary pass gates each comprise a pair of a NMOS transistor and a PMOS transistor connected in parallel. in The B signal is input into the fourth complementary pass gate, and the S (Sum) signal is connected to the parallel output of the first complementary pass gate and the second complementary pass gate. out The C signal is connected to the parallel output of the third complementary pass gate and the fourth complementary pass gate.

[0039] The input of the inverter is connected to the gate of the first MOS transistor of the first complementary pass gate, the source of the second MOS transistor of the second complementary pass gate, the gate of the third MOS transistor of the third complementary pass gate and the gate of the fourth MOS transistor of the fourth complementary pass gate.

[0040] The output of the inverter is connected to the gate of the first PMOS transistor of the first complementary pass gate, the source of the second PMOS transistor of the second complementary pass gate, the gate of the third NMOS transistor of the third complementary pass gate and the gate of the fourth PMOS transistor of the fourth complementary pass gate.

[0041] The working principle of the sub-circuit 2 is that, for the Sum signal, the A and B signals input into the sub-circuit 2 are inverted by the inverter to become A and B, which respectively drive the gates of the NMOS and PMOS transistors in the complementary pass gates. When A and B are 1 (weak "1"), the complementary pass gates are opened, and the Sum signal depends on the C in signal (when A and B are 1, either A = 0 and B = 0 or A = 1 and B = 1, and the Sum signal at this time depends on the C in signal); when A and B are 0 (must be strong "0"), when the C in signal is 0, the PMOS transistors of the following two pass gates are turned on, and the output is the exclusive or (must be strong "1") of A and B, and when the C in signal is 1, the NMOS transistors of the pass gates are turned on, and the output is the same or (strong "0") of A and B. For the C out signal, the principle is similar to the analysis of the Sum signal.

[0042] Finally, on the basis of solving the problems of complementary input signal generation and signal pressure drop, the full adder circuit based on the PTL is completely constructed, as shown in Figure 5The complete full adder circuit integrates sub-circuit 1 and sub-circuit 2, realizes the complete full adder function, and realizes the required arithmetic logic function using only 12 transistors without considering the register overhead.

[0043] 3. Functional verification and experimental results.

[0044] In order to verify the effectiveness of the design method proposed in the present disclosure, the present disclosure builds a simulation circuit based on the TSMC 180nm process library, and uses the Virtuoso platform for simulation verification, completes the functional correctness evaluation, and the quantitative analysis of delay, power consumption and area, and compares the results with the traditional CMOS circuit implementation.

[0045] First of all, functional verification. The present disclosure sets square wave signals with periods of 5 ns, 10 ns and 20 ns as the input signals A, B and Cin of the full adder, so as to comprehensively cover all possible input combination situations of the full adder. The simulation results are as shown in Figure 6 Although there is a certain glitch phenomenon in the Sum signal and the Cout signal, the overall function is still accurate and reliable, and there is no weak "0" or weak "1" output.

[0046] Figure 6 The English terms involved include:

[0047] Transient Response - Transient response,

[0048] Name - Name,

[0049] V(V) - Voltage (Volt),

[0050] time (ns) - Time (nanoseconds),

[0051] Analysis - Analysis,

[0052] transient time - transient time.

[0053] Secondly, the power consumption, performance and area evaluation of the circuit. In order to accurately and efficiently measure the power consumption and delay of the circuit, the present disclosure builds a simulation circuit as shown in Figure 7 Among them, two cascaded inverters are used to simulate the double-port output of the register, and a full adder circuit with the same structure is used as a load.

[0054] In terms of delay measurement, the present disclosure takes the input ends A, B and Cin of the full adder as the signal starting point, and the output ends Sum and Cout as the terminal point, and measures the overall delay of the circuit. In order to determine the critical path, the present disclosure systematically traverses all 56 possible signal flip situations corresponding to the 8 input states, as shown inFigure 8 The simulation shows that when the input state is switched from '100' to '110', the circuit delay reaches a maximum value of 200.3 ps.

[0055] In terms of power consumption measurement, since the PTL structure is different from the traditional CMOS circuit, there is a direct current flow between the logic stages, so the accurate power consumption cannot be simply obtained by multiplying the VDD current inside the PTL by the power supply voltage. Therefore, the disclosure simultaneously considers the additional current generated by the input inverter during the measurement process. By also traversing the 56 input signal flip conditions, the power consumption statistical results are obtained as shown in the following table: Figure 9 As shown in the table, the average power consumption of the PTL full adder is calculated to be about 21.03 μW.

[0056] In terms of area evaluation, since the gate length of the transistor is usually constant in the fixed process library, the disclosure quantitatively characterizes the circuit area by accumulating the gate width of all transistors.

[0057] Finally, through logic synthesis, the disclosure obtains the power consumption, delay and area parameters of the standard cell ADDFHX1 (full adder of traditional CMOS structure) using the same TSMC 180nm process library, and also uses the method of accumulating the transistor gate width for area calculation, and performs performance comparison, as shown in the following table:

[0058] Implementation Power consumption Area Delay CMOS 24uW 28.52u 0.24ns PTL 21.03uW 9.6u 0.2ns Profit

[0059] Compared with the traditional CMOS implementation, the PTL full adder design method proposed by the disclosure realizes a power consumption reduction of about 1.14 times, an area reduction of about 2.97 times, and a delay reduction of about 1.20 times, which fully verifies the effectiveness and advantages of the design method in practical circuit applications.

[0060] The embodiment of the disclosure eliminates the voltage drop problem of the PTL itself caused by the physical characteristics of NMOS and PMOS devices by cascading the transmission gate and the transmission tube. Due to the multiplexing of the double-port output register, the implicit area overhead problem caused by the complementary signal input pair of the PTL is solved, and the integration density of the PTL circuit is effectively released.

[0061] According to one or more embodiments, the design method proposed by the disclosure can be widely applied to the design of various processor computing units. The following takes the multiplication circuit of ternary weight and FP8 activation as an example to demonstrate the application of the design method of the disclosure.

[0062] With the evolution of quantization algorithms for large models, the weight bit width of the model is constantly decreasing. In 2024, Microsoft proposed BitNet1.58b, which successfully quantized the weights of large models into a ternary network composed of {-1, 0, +1}. However, the multiplication of 3-value weights and FP8 high bit width activations is not efficiently supported on existing hardware, so dedicated hardware design for this type of calculation can help improve the inference performance of the model. The design method proposed in this disclosure can be applied to the multiplication circuit design in the following way:

[0063] First, use 2-bit signals to represent weights, with the following encoding rules: 00 or 10 represents a weight of 0, 01 represents a weight of +1, and 11 represents a weight of -1. The activation value is represented in FP8 format.

[0064] To achieve efficient hardware multiplication operations, the circuit follows the following two core design principles:

[0065] (1) Read out the signal and its inverse simultaneously:

[0066] The activation value and the weight are stored in registers, and standard D flip-flop structures are used to implement data retention. At the output end of each register, the original signal (Q) and its inverse (Q̅) are obtained simultaneously, simplifying the selection control logic of the later stage. Based on this structure, the transmission gate can flexibly select to transmit the activation value itself or its inverse code according to the current weight value, thereby achieving the required sign control and zero value processing for ternary multiplication.

[0067] (2) Use transmission gates to achieve signal selection and enhancement:

[0068] The circuit uses NMOS transmission tubes and CMOS transmission gates to conditionally control and transmit the activation signal. The encoded value of the weight controls the switching path of the transmission gate, with the following specific logic:

[0069] For the non-sign part A[0–6], use a 2T AND gate structure for processing, with the output being a weak signal, as shown in Figure 10 .

[0070] If W[1] = 1, the activation signal Q is transmitted through the NMOS transmission tube, indicating that the numerical value remains unchanged;

[0071] If W[1] = 0, the node level is pulled low through the NMOS, implementing numerical zeroing.

[0072] For the sign bit A[7], first control the inversion through a 4T XOR gate, and then enhance the signal strength through a 3T AND gate, with the output being a strong signal, as shown in Figure 11 .

[0073] If W = 00, then Q is transmitted through the transmission gate, indicating that the symbol remains unchanged;

[0074] If W = 01, then Q̅ is transmitted through the transmission gate, indicating that the symbol is negated;

[0075] If W = 00 or 10, the output is grounded through the NMOS, indicating that the result is zero.

[0076] The embodiment of the present disclosure fully utilizes the double-output characteristics of the register structure and the selective transmission capability of the transmission gate while maintaining the trivalent logic expression capability, realizes the accurate control and signal enhancement of the multiplication result, and is suitable for the design scene of low-power and high-density neural network accelerator chips.

[0077] The present disclosure proposes a processor computing unit design method based on transmission tube logic, which eliminates the voltage drop and complementary input signal pair problem of traditional transmission tube logic by multiplexing a double-port output register and cascading a complementary transmission gate, and through experimental verification, the method proposed in the present disclosure applied to a single-bit full adder design can achieve lower delay and higher integration density under similar power consumption as traditional CMOS circuits.

[0078] Therefore, the beneficial effects of the present disclosure include:

[0079] (1) A method for obtaining a complementary input signal pair by multiplexing a double-port output register in a processor is proposed, which significantly reduces the implicit area overhead caused by additional inverters in traditional PTL design, and effectively releases the transistor integration density advantage of PTL technology.

[0080] (2) A cascaded complementary transmission gate structure is proposed, which effectively eliminates the logic misjudgment problem caused by transistor threshold voltage drop in PTL logic circuits, significantly improves the stability and reliability of circuit signal transmission, and improves the overall performance of the processor computing unit.

[0081] (3) The core idea of the method of the present disclosure is widely applicable and can be widely applied to various processor computing unit designs based on PTL technology, including but not limited to adders, multipliers, logic operation units, etc., has important research value and strong practical application potential, and can provide effective technical support for the development of high-performance and low-power processor architecture.

[0082] It should be understood that in the embodiments of the present disclosure, the term "and / or" only describes the association relationship of the associated objects, which means that there can be three relationships. For example, A and / or B can mean that A exists alone, A and B exist together, and B exists alone. In addition, the character " / " in the present disclosure generally represents that the front and rear associated objects are in an "or" relationship.

[0083] It is to be understood that while the forgoing has been described in some detail by way of illustration and example for purposes of clarity of understanding, it is the essence of the disclosure that is sought to be protected. It is therefore necessary that only those limitations shown and described be treated as describing the true spirit and scope of the disclosure. The disclosure is intended to cover any and all modifications and equivalents within the scope of the following claims.

Claims

1. A method for designing a PTL-based processor computing unit, characterized by, The multiplexing processor dual-port register outputs a complementary signal pair of the PTL basic gate circuit.

2. The method of claim 1, wherein, The PTL basic gate circuit comprises a NOT gate, an AND gate, an OR gate, a NAND gate, a NOR gate, an XOR gate, an XNOR gate or a pass gate.

3. The method of claim 1, wherein, The processor computing unit comprises an adder, a multiplier or a logic operation unit.

4. The method of claim 1, wherein, The dual-port register outputs a complementary signal pair of the PTL basic gate circuit.

5. The method of claim 4, wherein, The dual-port register is based on a D flip-flop.

6. The method of claim 3, wherein, The processor computing unit designed based on the PTL basic gate circuit comprises cascaded PTL basic gate circuits and pass gates.

7. A PTL basic gate circuit characterized by comprising: The gate circuit is obtained by the design method of claim 1.

8. A processor computing unit, characterized by The processor computing unit comprises the basic gate circuit of claim 7, Preferably, the processor computing unit comprises a full adder.

9. A processor, comprising: The processor computing unit of claim 8 is comprised.

10. An electronic device, comprising: The processor of claim 9 is comprised.

Images