Improved circuit design method for DDR (Double Data Rate) type dynamic memory write training

Abstract

The invention discloses an improved circuit design method for DDR type dynamic memory write training, and relates to the technical field of semiconductor memories. The method comprises the following steps: integrating a counter and a data comparison module in a dynamic memory particle to realize real-time comparison and correct frequency statistics of training data. The writing training score is comprehensively calculated by dynamically setting the length of a writing training sequence and based on the success rate of multiple times of training and the time consumption of single time of training in a historical statistical window. And carrying out iterative optimization on the write training sequence length by adopting a directional search strategy so as to obtain the optimal sequence length for balancing the training precision and speed. And finally, solidifying the optimal sequence length into a counting final value of a counter, and generating a write training circuit with self-adaptive capability in combination with a continuous comparison data comparison module. According to the circuit design method, the optimal training performance can be automatically maintained under different working conditions, and the initialization speed and the operation stability of a memory system are effectively improved.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of semiconductor memory, in particular to an improved circuit design method for write training of DDR dynamic memory. BACKGROUND

[0002] With the continuous growth of the demand of computing systems for memory bandwidth, the data transmission rate of DDR dynamic memory is constantly improving. High-speed data transmission puts extremely stringent requirements on signal timing. Write training is a key process to ensure that the controller writes data can be accurately captured by the memory.

[0003] The traditional write training method usually uses a fixed training sequence length, and there is an inherent contradiction between training accuracy and training speed. Too short training sequence may result in insufficient accuracy, which cannot fully evaluate the signal integrity. Too long training sequence will result in too long training time, affecting the startup efficiency and even runtime performance. SUMMARY

[0004] The present application provides an improved circuit design method for write training of DDR dynamic memory, which solves the technical problem that the fixed write training sequence length in the prior art cannot adaptively balance the training accuracy and the training speed.

[0005] The technical solution of the present application to solve the above technical problems is as follows: The present application provides an improved circuit design method for write training of DDR dynamic memory, which includes: Setting a counter and a data comparison module in the dynamic memory in the DDR dynamic memory; Randomly setting the write training sequence length for write training; Obtaining the accuracy parameter and the speed parameter of the write training according to the write training sequence length, and calculating the write training score; Iteratively optimizing the write training sequence length to obtain the optimal write training sequence length, and combining the counter and the data comparison module to obtain the write training circuit design result.

[0006] The present application has the following beneficial effects: Compared with the prior art, the application firstly breaks through the limitation of the fixed sequence length scheme by setting the write training sequence length as a variable that can be dynamically optimized and constructing a comprehensive evaluation mechanism that integrates statistical stability and time efficiency. Secondly, the introduction of the precision parameter based on the effectiveness statistics of multiple executions can more accurately reflect the reliability and timing margin of the training results, thereby significantly improving the robustness of the training precision evaluation. Thirdly, the directional search iteration strategy adopted can automatically and efficiently find the optimal solution that balances precision and speed, so that the finally determined sequence length has high reliability and high training efficiency. Finally, the entire optimization process is finally solidified into a specific hardware circuit design, and the generated write training circuit has adaptability and can automatically maintain optimal performance under different working voltages, temperatures and process deviations, effectively improving the startup speed, running stability and overall energy efficiency of the memory system. BRIEF DESCRIPTION OF DRAWINGS

[0007] Figure 1 A flowchart of an improved circuit design method for DDR dynamic memory write training is provided. Figure 2 A schematic diagram of the architecture of an improved circuit design method for DDR dynamic memory write training is provided. DETAILED DESCRIPTION

[0008] The technical solutions in the embodiments of the application will be described clearly and completely below with reference to the drawings in the embodiments of the application. Obviously, the described embodiments are only part of the embodiments of the application, not all. Based on the embodiments in the application, all other embodiments obtained by those skilled in the art without creative labor are within the scope of protection of the application.

[0009] In the description of the application, the terms "first", "second" are used only for the purpose of description, and cannot be understood as indicating or implying relative importance or implicitly indicating the number of indicated technical features. Therefore, the features defined with "first", "second" can explicitly or implicitly include one or more of the features. In the description of the application, the meaning of "multiple" is two or more, unless otherwise specifically limited.

[0010] In the description of the present application, the term "for example" is used to mean "serving as an instance, example or illustration". Any embodiment described as "for example" in the present application is not necessarily to be construed as preferred or advantageous over other embodiments. The following description is presented to enable any person skilled in the art to make and use the present application. In the following description, for the purpose of explanation, details are set forth in order to provide a thorough understanding of the present application. It will be apparent to one skilled in the art that the present application can be practiced without the specific details presented herein. In other instances, well known structures and processes are not elaborated upon in order to avoid obscuring the present application. Thus, the present application is not intended to be limited to the embodiments shown, but is to be accorded the widest scope consistent with the principles and features presented herein.

[0011] As shown in the embodiments, the present application provides an improved circuit design method for DDR dynamic memory write training, comprising: Figure 1 As shown in the embodiments, the present application provides an improved circuit design method for DDR dynamic memory write training, comprising: S10: setting a counter and a data comparison module in a dynamic memory in a DDR dynamic memory; DDR dynamic memory, i.e. double data rate dynamic memory, is a kind of high-speed volatile memory widely used in modern computing devices. Volatility refers to the characteristic that the memory cannot save data after power failure. This kind of memory realizes high data throughput capacity by transmitting data at the rising and falling edges of the clock signal at the same time. With the continuous increase of memory operating frequency, the accuracy requirements of timing parameters in the transmission and sampling process of signals are also increased. In the data write path, the phase relationship between the data signal and the data selection signal is easily affected by factors such as transmission path difference, power noise and semiconductor process fluctuation, so that the setup time or hold time of the data signal is insufficient, which further leads to write errors and affects the reliability of the storage system.

[0012] As shown in the embodiments, the present application provides an improved circuit design method for DDR dynamic memory write training, comprising: Figure 2 As shown in the embodiments, the present application provides an improved circuit design method for DDR dynamic memory write training, comprising:

[0013] Therefore, the application firstly proposes to directly integrate a dedicated counter and data comparison module inside a dynamic memory chip, so that the key data comparison operation can be completed immediately inside the memory chip without relying on the intervention and data return of an external controller. In the write training process, the write data sent by the controller is fed into the internal data comparison circuit at the same time as entering the storage array, and is compared with a preset expected data template in real time. The result signal generated by the comparison is captured and counted by the integrated counter circuit in real time, so as to accurately quantify the timing tolerance of the write path. This built-in training mechanism effectively avoids the overhead and error caused by read-write switching and long path return in the traditional scheme, and can more directly and efficiently evaluate the signal integrity of the write interface, thereby providing hardware-level support for realizing fast and accurate timing convergence.

[0014] Specifically, the data comparison module is used for comparing the received write training data with a preset expected data pattern in real time inside the dynamic memory grain, and outputting a comparison result signal. The counter is used for continuously accumulating and counting the comparison result signal output by the data comparison module during the write training sequence, so as to record the total number of times of correct data comparison.

[0015] Specifically, the core function of the data comparison module is to perform real-time data comparison operation. In the write training process, the data comparison module continuously receives the write training data sequence sent from the memory controller. The received data is compared bit by bit with an expected data pattern stored in the module. The expected data pattern is a known, fixed pseudo-random sequence or a specific format test vector. The comparison operation is performed in real time, and once any inconsistency is found between the received data and the expected pattern, the data comparison module immediately generates a signal representing a comparison error; otherwise, if the data is consistent, a signal representing a correct comparison is output. The comparison result signal is output in real time, which provides a basis for subsequent statistics and analysis.

[0016] In addition, the counter is responsible for monitoring and recording the comparison result signal generated by the data comparison module. The counter performs continuous accumulation and counting operation, and each comparison result signal judged as correct data during the write training sequence is counted incrementally. When the entire write training sequence is completed, the final count value saved in the counter module is the cumulative number of correct data comparisons in the entire training process. The cumulative value as a core quantitative parameter directly reflects the stability of the write data channel under the current training configuration. The higher the cumulative number is, the more matched the data signal and clock timing relationship is, and the greater the success probability of the write operation is, thereby providing an important numerical basis for evaluating the signal transmission quality.

[0017] S20: randomly set a write training sequence length for write training; Specifically, the write training sequence length for write training is randomly set, including: According to the protocol specification of the DDR type dynamic memory, determine the effective value range of the write training sequence length; Randomly generate a candidate write training sequence length within the effective value range; Configure the candidate write training sequence length value into the controller to perform the write training operation according to the write training sequence length value.

[0018] The counter module and the data comparison module integrated in step S10 provide efficient hardware support for the write training process. On the basis of this hardware, how to scientifically configure the training parameters to fully exert the efficiency of the hardware structure becomes a core design problem to be solved. Among them, the selection of the write training sequence length has a decisive influence on the efficiency and accuracy of the training process. If the write training sequence length is set too short, the sampling data obtained is insufficient, and it is difficult to form an accurate statistical evaluation of the signal quality; if the write training sequence length is set too long, it will significantly increase the time consumption of the training process, resulting in a decline in overall efficiency. Therefore, after having accurate internal data comparison and counting ability, a method for automatically finding the optimal write training sequence length is needed to realize high-performance write training.

[0019] Specifically, the write training sequence length is randomly set to start the iterative optimization process. First, according to the protocol specification of the double data rate dynamic memory, the effective value range of the write training sequence length is determined to ensure the compliance of the training operation. The effective value range is set according to the training sequence requirements in the memory industry standard JESD79 series protocol, for example, the write training sequence length is usually limited to between 64 and 4096 clock cycles. Second, a candidate write training sequence length value is randomly generated within the effective value range, and the write training sequence length value is written into the controller through the configuration register interface of the memory controller. The controller performs the write training operation according to the write training sequence length, and the counter module inside the memory records the cumulative number of correct data comparisons in real time. This random initialization process establishes an effective starting benchmark for the subsequent performance evaluation-based directional optimization process.

[0020] S30: Obtain the accuracy parameter and the speed parameter of the write training performed according to the write training sequence length, and calculate the write training score; Specifically, the accuracy parameter and the speed parameter of the write training performed according to the write training sequence length are obtained, and the write training score is calculated, including: In a historical time period, the write training is performed multiple times using the current write training sequence length, and the number of times of successfully completing the write training is counted, and a ratio of the number of successful times to the total number of times is calculated, and the ratio is quantified as the accuracy parameter; The number of clock cycles consumed from the start to the end of the write training is recorded, and the number of clock cycles is quantified as the speed parameter; According to the accuracy parameter and the speed parameter, the write training score is calculated by the preset scoring function, wherein the scoring function is used to comprehensively evaluate the performance of accuracy and speed.

[0021] The performance of the write training sequence length is quantified by the write training score, which is calculated based on the accuracy parameter and the speed parameter by the preset scoring function. The accuracy parameter is the success rate obtained by counting the number of successful times and the total number of training times after performing training multiple times using the same write training sequence length in a historical time period; the speed parameter is the number of clock cycles consumed in a single write training process, which directly reflects the time cost of the training process.

[0022] Specifically, the accuracy parameter and the speed parameter are introduced in the write training process, aiming to build a quantitative index system that can comprehensively evaluate the performance of the write training sequence length. The core purpose of setting the accuracy parameter is to measure the reliability and stability of the output results of the write training sequence length. A write training sequence length with excellent performance not only needs to be successful in a single training, but also should maintain a high and consistent success rate under repeated training and possible changes in voltage and temperature conditions. By counting the success rate of training using the same write training sequence length in a historical time period and quantifying it as the accuracy parameter, write training sequence length configurations with weak anti-interference ability and unstable performance can be screened out, avoiding accidental data errors in subsequent operation caused by fluctuations in training quality, and significantly improving the long-term working reliability of the storage system.

[0023] In addition, the setting of the speed parameter is a direct quantification of the time cost of the write training process. For application scenarios that need to be started quickly, or systems that need to respond to power state switching in time during operation, the time delay of the write training phase is crucial. The speed parameter accurately records the number of clock cycles consumed in a single write training operation, providing an objective basis for evaluating the time efficiency of different write training sequence lengths, ensuring that the optimization algorithm does not simply pursue a high training success rate while ignoring the time cost, thereby preventing the convergence to a write training sequence length with an accurate training result but an unacceptable training time. By balancing accuracy and speed, the training time can be shortened to the maximum extent on the premise of ensuring the training quality, and the overall response performance and user experience of the system are optimized.

[0024] First, the precision parameter is obtained by long-term statistical evaluation of the reliability of the write training result. Specifically, the current set write training sequence length is repeatedly used to perform multiple complete write training processes in a historical time period. The length of the historical time period is set according to the stability and reliability requirements of the memory, for example, the historical time period can be set to the duration corresponding to 1024 consecutive write training operations to ensure that the statistical results are sufficiently representative. After each training is completed, it is determined whether the stable write data window is found in this training according to the output results of the dynamic memory internal data comparison module and the counter module. Second, the number of successful completions is counted among all training times, and the ratio of the number of successful completions to the total training times is calculated. The ratio is quantified as the precision parameter. The higher the value of the precision parameter, the more stable and reliable the result of the training using the current write training sequence length.

[0025] The speed parameter focuses on the efficiency of a single write training process. When each write training operation is performed, the total number of clock cycles consumed from the start of the training to the end of the training is recorded. The number of clock cycles directly reflects the time cost of completing one training, which is quantified as the speed parameter. The smaller the value of the speed parameter, the faster the speed of the training using the current sequence length.

[0026] After obtaining the precision parameter and the speed parameter, the two are comprehensively calculated by a pre-set scoring function to finally obtain a write training score. The design of the write training scoring function aims to balance the reliability of the training result and the efficiency of the training process. For example, the scoring function adopts a linear weighting form and is expressed as: write training score = a x precision parameter + β x (1 / speed parameter), where a and β are pre-set weighting coefficients, which are set based on the specific requirements of the target application scenario for training quality and training speed, and are used to adjust the relative importance of training result reliability and training process efficiency in the comprehensive score, for example, in mobile terminal applications with strict requirements on system startup time, a larger β value can be set to focus more on training speed, while in server applications with extremely high requirements on data reliability, a larger a value can be set to focus more on training precision.

[0027] Through the scoring function, the precision and speed performance indicators in different dimensions are fused into a single comprehensive evaluation value, thereby realizing direct and effective comparison of the performance of different write training sequence lengths.

[0028] S40: iteratively optimize the write training sequence length, obtain an optimal write training sequence length, and obtain a write training circuit design result in combination with the counter and data comparison module.

[0029] First, iteratively optimize the write training sequence length to obtain an optimal write training sequence length, including: Based on the current write training sequence length and its corresponding write training score, a new write training sequence length is automatically adjusted and generated by using a directional search strategy; The steps of setting the training sequence length, obtaining the parameter calculation score, and automatically adjusting are repeatedly performed for multiple iterations; When a preset number of iterations is reached or the improvement of the write training score is less than a preset threshold, the iterations are terminated, and the sequence length corresponding to the highest write training score in all iterations is selected as the optimal write training sequence length.

[0030] Specifically, based on the current write training sequence length and its corresponding write training score, a new write training sequence length is automatically adjusted and generated by using a directional search strategy, including: Determining the gradient or change trend of the score to determine the optimization direction; In the optimization direction, the current write training sequence length is updated by a preset adjustment step to generate the new write training sequence length.

[0031] In the iterative optimization process, the implementation of the directional search strategy depends on the quantitative analysis of the performance evaluation results. This process calculates the gradient value of the score change or determines its change trend by comparing the change of the write training score in adjacent iteration periods. If the score shows an upward trend, it indicates that the current adjustment direction is beneficial to performance improvement, and the same optimization direction should be maintained in the future; if the score decreases, it indicates that the optimization direction needs to be changed.

[0032] Secondly, after the optimization direction is determined, the write training sequence length is accurately updated according to a preset adjustment step. This adjustment step is set according to the timing accuracy requirement of the memory interface, for example, the length is adjusted in units of clock cycles. When it is determined that the write training sequence length needs to be increased, the current value is increased by one step value; when it needs to be reduced, the corresponding step value is subtracted. Through this adjustment mechanism based on the combination of gradient direction and fixed step, directional exploration in the solution space can be effectively performed, and the optimal write training sequence length configuration is gradually approached.

[0033] Further, the optimization process repeatedly performs the following steps: setting a new training sequence length, performing a write training operation to obtain parameters, calculating a write training score, and automatically adjusting the sequence length based on the score result. This loop process is iterated multiple times to gradually improve the write training score.

[0034] The conditions for terminating the iteration include two scenarios: one is to reach the preset maximum iteration number, for example, the upper limit of the iteration number is set to 100 times; the second is to monitor that the improvement amplitude of the write training score is less than the preset improvement threshold, wherein the preset improvement threshold is set according to the training accuracy requirement and the convergence characteristics, for example, when the score improvement amplitude of three consecutive iterations is less than 1%, it is considered to be converged. When any condition is met, the optimization process is terminated. Subsequently, all the write training scores recorded in the iteration process are traversed, and the sequence length corresponding to the highest score is selected as the final optimal write training sequence length.

[0035] Further, in combination with the counter and the data comparison module, a write training circuit design result is obtained, including: configuring the optimal write training sequence length as the counting end value of the counter; configuring the data comparison module to continuously compare the received data with the expected data during the write training process; generating a write training completion signal when the counting value of the counter reaches the counting end value; based on the configured counting end value, data comparison module and write training completion signal, generating a final write training circuit design result.

[0036] After obtaining the optimal write training sequence length, the optimization result needs to be combined with the hardware circuit implementation to form a complete write training circuit design. First, the determined optimal write training sequence length is configured as the counting end value of the counter module. The counting end value defines the number of data comparisons that need to be completed in a single write training operation, serving as the target value for the operation of the counter.

[0037] The data comparison module remains in a continuous working state during the write training process, and compares the write training data received from the memory controller with the internal expected data pattern in real time. The comparison result signal generated every clock cycle is sent to the counter module for statistics.

[0038] The counter module starts from zero and accumulatively counts the correct comparison result signals output by the data comparison module. When the current counting value of the counter reaches the preset counting end value, it indicates that the write training sequence of the specified length has been completed, and all data has been verified. At this time, the counter module outputs a write training completion signal.

[0039] The finally formed write training circuit design contains three key elements: the counter configured with the counting end value, the data comparison module continuously performing data comparison, and the write training completion signal generated based on the counting end value. These three elements together constitute an autonomous write training circuit that can independently complete the write training operation of the specified length and accurately determine the training completion time without the intervention of the controller.

[0040] To sum up, the embodiments of the present application have at least the following technical effects: Compared with the prior art, the present application first realizes adaptive adjustment of the write training sequence length by integrating a special hardware module in the dynamic memory and constructing a dynamic optimization mechanism, breaking through the inherent limitations of the traditional fixed length scheme. Secondly, the precision evaluation method based on multiple executions and statistical determination can more reliably reflect the signal timing margin, significantly enhancing the credibility of the training results. Thirdly, the iterative optimization process combined with the directional search strategy can automatically and efficiently determine the optimal sequence length with high precision and high speed. Finally, the optimization results are directly solidified as the configuration parameters of the hardware circuit, so that the finally designed write training circuit has excellent adaptive characteristics and can continuously maintain optimal performance under varying voltage, temperature and process conditions, thereby comprehensively improving the initialization efficiency, running stability and overall energy efficiency of the memory system.

[0041] It should be noted that the above-mentioned sequence of the embodiments of the present application is only for description, and does not represent the advantages and disadvantages of the embodiments. And the above describes the specific embodiments of the present application. In addition, the processes depicted in the drawings do not necessarily require the specific order or continuous order shown to achieve the desired results. In some embodiments, multi-task processing and parallel processing are also possible or can be advantageous.

[0042] The above only describes the preferred embodiments of the present application, and does not limit the present application. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application shall be included in the protection scope of the present application.

[0043] The present application and the drawings are only exemplary descriptions of the present application, and are considered to cover any and all modifications, changes, combinations or equivalents within the scope of the present application. Obviously, those skilled in the art can make various modifications and changes to the present application without departing from the scope of the present application. Thus, if these modifications and changes of the present application belong to the scope of the present application and its equivalent technology, the present application intends to include these modifications and changes.

Claims

1. An improved circuit design method for write training of DDR-type dynamic memory, characterized in that, include: A counter and a data comparison module are set up in the dynamic memory within the DDR-type dynamic memory; Randomly set the length of the write training sequence for write training; Obtain the precision and speed parameters for writing training according to the length of the writing training sequence, and calculate the writing training score; The length of the write training sequence is iteratively optimized to obtain the optimal write training sequence length. Combined with the counter and data comparison module, the design result of the write training circuit is obtained.

2. The method according to claim 1, characterized in that, include: The data comparison module is used to compare the received write training data with the preset expected data pattern in real time within the dynamic memory particle, and output the comparison result signal. The counter is used to continuously accumulate and count the alignment result signal, which represents the correctness of the data, output by the data comparison module during the writing of the training sequence, in order to record the total number of correct data alignments.

3. The method according to claim 1, characterized in that, The length of the training sequence for write training is randomly set, including: According to the protocol specification of the DDR-type dynamic memory, determine the effective range of values ​​for the write training sequence length; Within the valid value range, a candidate write training sequence length is randomly generated; The candidate write training sequence length value is configured into the controller to perform a write training operation according to the write training sequence length value.

4. The method according to claim 1, characterized in that, Obtain the accuracy and speed parameters for write training based on the stated write training sequence length, and calculate the write training score, including: Within a historical time period, write training is performed multiple times using the current write training sequence length, and the number of times the write training is successfully completed is counted. The ratio of the number of successful completions to the total number of completions is calculated, and this ratio is quantified as the accuracy parameter. Record the number of clock cycles consumed from the start to the end of the training, and quantify the clock cycles into the speed parameter. Based on the accuracy and speed parameters, the write training score is calculated using the preset scoring function, wherein the scoring function is used to comprehensively evaluate the performance of accuracy and speed.

5. The method according to claim 1, characterized in that, Iteratively optimizing the write training sequence length to obtain the optimal write training sequence length includes: Based on the current write training sequence length and its corresponding write training score, a targeted search strategy is used to automatically adjust and generate a new write training sequence length. Repeat the steps of setting the training sequence length, obtaining parameters, calculating scores, and automatic adjustment multiple times; When the preset number of iterations is reached or the improvement of the write training score is less than the preset threshold, the iteration is terminated, and the corresponding sequence length with the highest write training score among all iterations is selected as the optimal write training sequence length.

6. The method according to claim 5, characterized in that, Based on the current write training sequence length and its corresponding write training score, a targeted search strategy is used to automatically adjust and generate a new write training sequence length, including: Determine the gradient or trend of the scoring to determine the direction of optimization; In the optimization direction, the current write training sequence length is updated with a preset adjustment step size to generate the new write training sequence length.

7. The method according to claim 1, characterized in that, Combining the counter and data comparison module, the design results of the write training circuit are obtained, including: Configure the optimal write training sequence length as the final count value of the counter; The data comparison module is configured to continuously compare the received data with the expected data during the training process. When the counter reaches its final count value, a write training complete signal is generated. Based on the configured final count value, data comparison module, and write training completion signal, the final write training circuit design result is generated.

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