Digital phase-locked loop system and PLL output frequency modulation range real-time adjusting method thereof

Abstract

The invention discloses a digital phase-locked loop system and a PLL output frequency modulation range real-time adjusting method thereof. The digital phase-locked loop system digitally controls an oscillator. The digital control oscillator comprises a plurality of groups of macro cells, and each group of macro cells comprises at least one macro cell; and each group of macro units is used for being switched on or switched off according to a configurable control signal input by a user, so that the switched-on macro units determine a PLL output frequency modulation range, and the PLL output frequency modulation range is adjusted according to an adjusting instruction input by the user. The effective frequency modulation range of the digital phase-locked loop system can be changed on the premise that a hardware circuit is not changed, so that the digital phase-locked loop system can flexibly adapt to various application scenes with huge differences, and the maximum application flexibility is obtained while the advantages of a single hardware design are kept.

Description

Technical Field

[0001] This application relates to the field of circuit technology, specifically to a digital phase-locked loop system and a method for real-time adjustment of the PLL output frequency range. Background Technology

[0002] Phase-locked loops (PLLs) are core modules of modern electronic systems, widely used in clock generation, frequency synthesis, and clock recovery. Their performance directly determines communication quality, system speed, and stability. Traditional PLL circuits typically have their frequency modulation range determined during the design phase by hardware parameters (such as VCO inductor and capacitor values, loop filter bandwidth, etc.). Once the chip or circuit board is manufactured, its operating frequency range is fixed. This means that a system needing to handle multiple application scenarios (such as different communication standards) often requires integrating multiple PLLs in different frequency bands, or designing different hardware versions for different frequency requirements. This not only increases chip area, system complexity, and production costs, but also reduces design flexibility and versatility.

[0003] To address these issues, the industry has proposed the concept of reconfigurable PLLs. For example, in an FPGA, the PLL's divider counter and other components can be reset via a specific configuration port to change the output frequency. However, this reconfigurability is often limited. For instance, the configurable frequency range is still constrained by the hardware tuning range of the internal voltage-controlled oscillator (VCO). A PLL designed for low frequencies will find it difficult to cover very high frequency bands through simple configuration. In other words, the "programmability" of existing configurable PLLs is more about fine-tuning frequency points than fundamentally changing the frequency range. Furthermore, some implementation schemes may still be quite complex or unable to achieve truly real-time, dynamic switching. Therefore, traditional PLLs have limitations in practical applications. Summary of the Invention

[0004] In view of this, this application provides a digital phase-locked loop system and a method for real-time adjustment of the PLL output frequency modulation range, so as to solve the problem of limitations of traditional PLL in practical applications.

[0005] This application provides a digital phase-locked loop system, which includes a digitally controlled oscillator; the digitally controlled oscillator includes multiple sets of macrocells, and each set of macrocells includes at least one macrocell; Each macro unit group is used to turn on or off according to the configurable control signal input by the user, so as to determine the PLL output frequency modulation range by the number of macro unit groups turned on, and to adjust the PLL output frequency modulation range according to the adjustment command input by the user.

[0006] Optionally, the configurable control signal includes binary control bits corresponding to each group of macrocells; each group of macrocells is turned on when the corresponding binary control bit is 1, and turned off when the corresponding binary control bit is 0.

[0007] Optionally, the adjustment command includes a coarse adjustment command; the digital phase-locked loop system is further used to adjust the on / off state of each group of macrocells according to the coarse adjustment command, thereby adjusting the number of macrocells connected.

[0008] Optionally, each macro unit includes two groups of sub-units, and each group of sub-units includes multiple sub-units; the configurable control signal also includes a sub-unit control field corresponding to each sub-unit; each sub-unit in each group of sub-units is used to turn on or off according to the sub-unit control field to adjust the PLL output frequency modulation range corresponding to the macro unit.

[0009] Optionally, after determining the number of macrocell groups and the number of sub-units to be turned on, the digitally controlled oscillator turns on and off the corresponding macrocell groups and sub-units respectively to adjust the output frequency of the PLL.

[0010] Optionally, the sub-unit control field includes binary control bits corresponding to each sub-unit; each sub-unit is turned on when the corresponding binary control bit is 1, and turned off when the corresponding binary control bit is 0.

[0011] Optionally, the adjustment command includes a fine-tuning command; the digital phase-locked loop system is further configured to adjust the on / off state of each of the sub-units according to the fine-tuning command, thereby adjusting the number of sub-units connected in each macro-unit.

[0012] Optionally, each macrocell further includes a first NAND gate, a second NAND gate, a third NAND gate, and an inverter; the input terminal of the first group of sub-units serves as the first input terminal of the corresponding macrocell and is connected to the first output terminal of the previous macrocell; the control terminal is used to receive the configurable control signal and is respectively connected to the control terminal of the second group of sub-units, the first input terminal of the first NAND gate, and the input terminal of the inverter; the output terminal is respectively connected to the second input terminal of the first NAND gate and the first input terminal of the second NAND gate; the output terminal of the first NAND gate is connected to the first input terminal of the third NAND gate; the output terminal of the inverter is connected to the second input terminal of the second NAND gate; the output terminal of the second NAND gate serves as the first output terminal of the corresponding macrocell and is connected to the first input terminal of the next macrocell; the second input terminal of the third NAND gate serves as the second input terminal of the corresponding macrocell and is connected to the second output terminal of the next macrocell; the output terminal of the second group of sub-units serves as the second output terminal of the corresponding macrocell and is connected to the second input terminal of the previous macrocell.

[0013] Optionally, the digital phase-locked loop system further includes a time-to-digital converter circuit and a digital filter; the first terminal of the time-to-digital converter circuit is used to connect to a reference clock, the second terminal is connected to the output terminal of each group of macrocells, and the third terminal is connected to the input terminal of the digital filter; the output terminal of the digital filter is connected to the enable control terminal of the digitally controlled oscillator; the time-to-digital converter circuit is used to obtain the phase difference between the PLL output signal and the reference clock, and send the phase difference to the digital filter; the digital filter is used to perform digital signal processing on the phase difference, and output a control signal to adjust the digitally controlled oscillator according to the processing result.

[0014] This application also provides a method for real-time adjustment of the PLL output frequency modulation range of a digital phase-locked loop system, including the following steps: Obtain user input metrics; The PLL is used to design a database to parse the user input indicators and obtain the configurable control signals corresponding to the user input indicators. The PLL output frequency modulation range can be determined using any of the above-mentioned digital phase-locked loop systems.

[0015] Optionally, the process of determining the PLL design database includes: parsing each group of design indicators; constructing the PLL design database based on the parsed design indicators; performing verification analysis on each group of design indicators after chip fabrication; and updating the PLL design database using the verified design indicators.

[0016] In the aforementioned digital phase-locked loop system and its real-time adjustment method for the PLL output frequency modulation range, each group of macro units can be turned on or off according to a configurable control signal input by the user, thereby determining the PLL output frequency modulation range through the macro unit that is turned on. Each group of macro units can also adjust the PLL output frequency modulation range according to the adjustment command input by the user, so as to change the effective frequency modulation range of the digital phase-locked loop system without changing the hardware circuit, enabling it to flexibly adapt to a variety of vastly different application scenarios, thereby achieving maximum application flexibility while maintaining the advantages of a single hardware design. Attached Figure Description

[0017] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0018] Figure 1 This is a schematic diagram of a digital phase-locked loop system according to an embodiment of this application; Figure 2This is a schematic diagram of a digitally controlled vibrator structure according to an embodiment of this application; Figure 3 This is a schematic diagram of a macrocell structure according to an embodiment of this application; Figure 4 This is a schematic flowchart of a real-time adjustment method for the PLL output frequency modulation range of a digital phase-locked loop system according to an embodiment of this application; Figure 5 This is a schematic diagram of the working process of a digital phase-locked loop system according to an embodiment of this application; Figure 6 This is a schematic diagram of the silicon parameter determination process according to an embodiment of this application. Detailed Implementation

[0019] The technical solutions in the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of them. Based on the embodiments in this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application. In the absence of conflict, the following embodiments and their technical features can be combined with each other.

[0020] This application provides a digital phase-locked loop system that can be installed in a chip system such as a microprocessor.

[0021] refer to Figure 1 As shown, the digital phase-locked loop system includes a digitally controlled oscillator 100; the digitally controlled oscillator 100 includes multiple sets of macrocells, each set of macrocells including at least one macrocell.

[0022] Each group of macrocells is used to turn on or off according to configurable control signals input by the user, so that the digitally controlled oscillator 100 can subsequently determine the PLL output frequency modulation range based on the number of macrocell groups that are turned on. Each group of macrocells can also adjust the PLL output frequency modulation range according to adjustment commands input by the user, thereby changing the effective frequency modulation range of the digital phase-locked loop system without altering the hardware circuitry. This allows it to flexibly adapt to a variety of vastly different application scenarios, thus achieving maximum application flexibility while maintaining the advantages of a single hardware design.

[0023] Optionally, users can view the PLL output signal of the digital phase-locked loop system to determine whether the frequency and other characteristics of the PLL output signal match the current application requirements. If the characteristics of the PLL output signal are inconsistent with the current application requirements, users can input adjustment commands to the digital phase-locked loop system to adjust the PLL output frequency modulation range in real time. Optionally, refer to Figure 2As shown, each group of macrocells can include a first input terminal IN, a second input terminal INB, a first output terminal OUT, and a second output terminal OUTB. If the macrocell on the left is the previous macrocell and the macrocell on the right is the next macrocell, then the leftmost macrocell is the first macrocell and the rightmost macrocell is the last macrocell. The internal connection relationship of each group of macrocells includes: the first output terminal OUT of the previous macrocell is connected to the first input terminal IN of the next macrocell, and the second input terminal INB of the previous macrocell is connected to the second input terminal OUTB of the next macrocell.

[0024] Specifically, the configurable control signal includes a macrocell control field, which may include binary control bits corresponding to each group of macrocells. For example, if the digital phase-locked loop system includes 6 macrocells, the macrocell control field may include control fields such as 111100 or 111110. Each group of macrocells is turned on when the corresponding binary control bit is 1 and turned off when the corresponding binary control bit is 0, so as to turn on the corresponding macrocells according to the configurable control signal, and match the frequency adjustment capability of the turned-on macrocells with the corresponding frequency processing requirements.

[0025] In some examples, the adjustment instructions include coarse adjustment instructions; in the digital phase-locked loop system, the digitally controlled oscillator 100 is also used to adjust the on / off state of each group of macrocells according to the coarse adjustment instructions. For example, based on the macrocells that need to be turned on, a group of macrocells may be turned off or another group of macrocells may be turned on, thereby adjusting the number of macrocell groups that are turned on, so as to achieve the purpose of coarsely adjusting the frequency adjustment capability of the digital phase-locked loop system.

[0026] In some examples, reference Figure 3 As shown, each macrocell includes two sets of sub-units, namely a first set of sub-units 111 and a second set of sub-units 112, which have identical structures. Each set of sub-units includes multiple sub-units; each sub-unit can be implemented using an inverter or similar structure with an enable control terminal (such as an enable signal terminal). The configurable control signal also includes sub-unit control fields corresponding to each sub-unit; each sub-unit in each set is used to turn on or off according to the sub-unit control fields to adjust the PLL output frequency modulation range corresponding to its macrocell.

[0027] Specifically, configurable control signals are used to determine the number of macrocell groups to be turned on and off, and the number of sub-units to be turned on and off. After determining the number of macrocell groups to be turned on and the number of sub-units to be turned on, the digitally controlled oscillator turns on and off the corresponding macrocell groups and the corresponding macrocell group sub-units to be turned on and off, so as to adjust the output frequency of the PLL.

[0028] Specifically, the sub-unit control field includes binary control bits corresponding to each sub-unit; for example, if each group of sub-units includes 4 sub-units, the sub-unit control field may include control fields such as 1100 or 1110. If the digital phase-locked loop system includes 6 macro-units, the macro-unit control field includes 111100, the sub-unit control field includes 1100, and the configurable control signal includes 111100_1100.

[0029] Each subunit is turned on when the corresponding binary control bit is 1 and turned off when the corresponding binary control bit is 0, so as to turn the corresponding subunit on or off according to the subunit control field, thereby precisely adjusting the frequency adjustment capability of the corresponding macrounit.

[0030] In some examples, the adjustment command includes a fine-tuning command; in the digital phase-locked loop system, the digitally controlled oscillator 100 is also used to adjust the on / off state of each of the sub-units according to the fine-tuning command, for example, based on the currently connected sub-units, turning off one sub-unit or turning on another sub-unit, thereby adjusting the number of connected sub-units in each macro-unit, so as to achieve the purpose of fine-tuning the frequency adjustment capability of the digital phase-locked loop system.

[0031] In some examples, reference Figure 3 As shown, each of the macrocells further includes a first NAND gate 120, a second NAND gate 130, a third NAND gate 140, and an inverter 150.

[0032] The input terminal of the first group of subunits 111 serves as the first input terminal IN of the corresponding macrounit and is connected to the first output terminal of the previous macrounit. The control terminal of the first group of subunits 111 is used to input the configurable control signal CTRL and is connected to the control terminal of the second group of subunits 112, the first input terminal of the first NAND gate 120, and the input terminal of the inverter 150, respectively. The output terminal of the first group of subunits 111 is connected to the second input terminal of the first NAND gate 120 and the first input terminal of the second NAND gate 130, respectively. The output terminal of the first NAND gate 120 is connected to the first input terminal of the third NAND gate 140. The output terminal of the inverter 150 is connected to the second input terminal of the second NAND gate 130. The output terminal of the second NAND gate 130 serves as the first output terminal OUT of the corresponding macrounit and is connected to the first input terminal of the next macrounit; the second input terminal of the third NAND gate 140 serves as the second input terminal INB of the corresponding macrounit and is connected to the second output terminal of the next macrounit; the output terminal of the third NAND gate 140 is connected to the input terminal of the second group of subunits 112. The output terminal of the first group of sub-units 111 serves as the second output terminal OUTB of the corresponding macro-unit and is connected to the second input terminal of the previous macro-unit. The first group of sub-units 111 and 111 can be turned on or off according to the sub-unit control field in the configurable control signal CTRL.

[0033] In some examples, reference Figure 1 As shown, the digital phase-locked loop system also includes a time-to-digital converter circuit 210 and a digital filter 220. The first terminal of the time-to-digital converter circuit 210 is used to connect to a reference clock. The second terminal of the time-to-digital converter circuit 210 is connected to the output terminals of each group of macrocells; for example, the time-to-digital converter circuit 210 can be connected to the signal output terminals of each group of macrocells, and can also be connected to another output terminal of the first macrocell (such as the second output terminal). The third terminal of the time-to-digital converter circuit 210 is connected to the input terminal of the digital filter 220. The output terminal of the digital filter 220 is connected to the enable control terminal of the digitally controlled oscillator 100.

[0034] The time-to-digital converter circuit 210 is used to obtain the phase difference between the PLL output signal and the reference clock, and send the phase difference to the digital filter 220.

[0035] The digital filter 220 is used to perform digital signal processing on the phase difference and output a control signal to adjust the digitally controlled oscillator based on the processing result.

[0036] In the above digital phase-locked loop (PLL) system, each group of macrocells can be turned on or off according to configurable control signals input by the user. After determining the number of macrocell groups and sub-units to be turned on, the digitally controlled oscillator will turn on and off the corresponding macrocell groups and sub-units respectively to adjust the PLL output frequency. Each group of macrocells can also update the number of groups to be turned on and / or off according to the adjustment instructions input by the user to adjust the PLL output frequency range in real time. Without changing the hardware circuit, the effective frequency range of the digital PLL system can be changed, making it flexibly adaptable to a variety of vastly different application scenarios. This achieves maximum application flexibility while maintaining the advantages of a single hardware design.

[0037] This application also provides a method for real-time adjustment of the PLL output frequency modulation range of a digital phase-locked loop system, including the following steps S310 to S330.

[0038] S310, acquires user input metrics.

[0039] S320 uses a PLL to design a database to parse the user input indicators and obtain the configurable control signals corresponding to the user input indicators.

[0040] S330, the PLL output frequency modulation range is determined by the digital phase-locked loop system described in any of the above embodiments.

[0041] In some embodiments, the process of determining the PLL design database includes: Analyze each set of design indicators; each set of design indicators can be derived from design indicators and process library files input by the user according to the corresponding application scenario.

[0042] A PLL design database is constructed based on the analyzed design metrics.

[0043] After the chip is fabricated, the design metrics of each group are verified and analyzed to determine the design metrics that pass the verification analysis.

[0044] The PLL design database is updated using the design metrics from the verification analysis to ensure that the updated PLL design database passes the verification analysis during chip fabrication.

[0045] In some examples, the real-time adjustment method for the PLL output frequency modulation range of the digital phase-locked loop system further includes: inputting an adjustment command to the digital phase-locked loop system according to the PLL output signal, so as to enable the digital phase-locked loop system to adjust the PLL output frequency modulation range of the PLL output signal in real time without changing the hardware circuit.

[0046] Specifically, the adjustment commands can include coarse adjustment commands and fine adjustment commands. The coarse adjustment commands are used to adjust the on / off state of each group of macro units, thereby adjusting the number of macro units that are connected, so as to achieve the purpose of coarsely adjusting the frequency adjustment capability of the digital phase-locked loop system. The fine adjustment commands are used to adjust the on / off state of each sub-unit, thereby adjusting the number of sub-units that are connected in each macro unit, so as to achieve the purpose of finely adjusting the frequency adjustment capability of the digital phase-locked loop system.

[0047] In some examples, the inventors through Figure 5 A detailed explanation of the real-time adjustment method for the PLL output frequency modulation range of a digital phase-locked loop system is provided. (Reference) Figure 5 As shown, the real-time adjustment method for the PLL output frequency modulation range of a digital phase-locked loop system includes the following steps S411 to S426.

[0048] S411, users input design specifications and process library files according to application requirements.

[0049] S412, parse design specifications and process library files; for example, configurable control signals can be determined by parsing design specifications. <n:0>The number of N values ​​and their relationship with the indicators are used to obtain the analyzed design indicators for each group.

[0050] S413, Build the PLL design database.

[0051] S414, after chip tape-out, the design specifications of each group are verified and analyzed. The PLL design database is updated using the verified and analyzed design specifications to ensure that the updated PLL design database passes the chip tape-out verification analysis. Specifically, this can be achieved by inputting control signals multiple times, each time a single type, followed by simulation. After the simulation is completed, the obtained data is integrated into the PLL design database. Then, the PLL parameters are silicon verified, and the PLL design database is updated after obtaining the silicon parameters.

[0052] S421, the user inputs relevant control indicators based on the parameter range and other conditions recorded in the PLL design database to determine the user input indicators.

[0053] S422, parse the user input metrics according to the PLL design database.

[0054] S423, determine the configurable control signal corresponding to the user input indicator. This can be obtained by parsing the indicator. <n:0>This is to enable the digital phase-locked loop system to determine the corresponding silicon parameters.

[0055] S424 determines the PLL silicon parameters corresponding to the configurable control signal so that the digital phase-locked loop system can determine the PLL output frequency modulation range based on the PLL silicon parameters.

[0056] S425, the user inputs an adjustment command to adjust the PLL output frequency modulation range. Here, the user can input the adjustment command by viewing information such as the PLL output signal of the digital phase-locked loop system. Specifically, when the user wants to fine-tune the PLL output frequency modulation range, they can input a fine-tuning command; when they want to coarsely adjust the PLL output frequency modulation range, they can input a coarse-tuning command.

[0057] S426, if the adjustment command is a coarse adjustment command, then modify the macro cell control field in the configurable control signal accordingly, so as to redetermine the PLL silicon parameters according to the modified configurable control signal, and return to execute step S424, thereby realizing the adjustment of the PLL output frequency modulation range.

[0058] S427, if the adjustment command is a fine-tuning command, then modify the sub-unit control field in the configurable control signal accordingly, so as to redetermine the PLL silicon parameters according to the modified configurable control signal, and return to execute step S424, thereby realizing the adjustment of the PLL output frequency modulation range.

[0059] Specifically, the digital phase-locked loop system receives configurable control signals. <n:0>It can be based on each configurable control signal <n:0>The corresponding PLL parameters determine the corresponding silicon parameters, enabling the digital phase-locked loop system to determine the PLL output frequency modulation range using these silicon parameters. The PLL parameters can be determined through methods such as post-simulation. Optionally, the process for determining the silicon parameters can refer to... Figure 6 As shown, first determine the configurable control signals. <n:0>,like Figure 6 The first configurable control signal shown is <9:0>110000_1100, the second is <9:0>111100_1100, and the third is <10:0>111111_11100. The first configurable control signal corresponds to PLL parameter A. The silicon parameters can be determined through PLL parameter A: coarse tuning frequency: 2GHz-3GHz, fine tuning frequency: ±10MHz, phase noise: -100dBc / Hz, power consumption: 2.6mW. The second configurable control signal corresponds to PLL parameter B. The silicon parameters can be determined through PLL parameter B: coarse tuning frequency: 1GHz-2GHz, fine tuning frequency: ±10MHz, phase noise: -103dBc / Hz, power consumption: 1.8mW. The third configurable control signal corresponds to PLL parameter C. At this time, the corresponding silicon parameters can be determined through PLL parameter C: coarse adjustment frequency: 0.2G-1GHz, fine adjustment frequency: ±30MHz, phase noise: -98dBc / Hz, power consumption: 1.2mW.

[0060] When the aforementioned digital phase-locked loop (PLL) system is applied to a microprocessor chip, it provides three operating modes. After the PLL system and microprocessor are powered on, initial measurements and configurations are performed. The corresponding operating mode can be matched by measuring the frequencies of the three control signals. After the PLL system is configured and powered on again, the PLL can be in normal mode, where the control signal can be 111100_1100. When the microprocessor chip detects a large-scale task, its functional module modifies the configurable control signal <9:0>111111_1100, and the PLL enters high-frequency mode. When the microprocessor chip detects no task, its functional module modifies the configurable control signal <9:0>111111_1100, and the PLL enters low-frequency, low-power mode.

[0061] The inventors analyzed the application process of the digital phase-locked loop system and determined that the above-mentioned digital phase-locked loop system has the following advantages: (1) It improves the reusability and versatility of the hardware platform, realizes "one board for multiple uses" or "one chip for multiple uses", and significantly reduces the R&D and inventory costs for different market demands. (2) For new frequency requirements, developers do not need to carry out lengthy hardware iterations, but only need to update the software configuration or firmware program. (3) The configurable nature of the software enables the system to dynamically optimize performance according to the real-time working status. (4) The system can easily control the output frequency of the PLL to perform periodic modulation or adjust it in real time according to the load through software instructions, thereby improving the overall energy efficiency ratio and electromagnetic compatibility of the system, without increasing the additional hardware cost.

[0062] The real-time adjustment method for the PLL output frequency modulation range of the above-described digital phase-locked loop system, which determines the PLL output frequency modulation range through the digital phase-locked loop system described in any of the above embodiments, has all the beneficial effects of the digital phase-locked loop system described in any of the above embodiments, and will not be repeated here.

[0063] Although this application has been shown and described with respect to one or more implementations, equivalent variations and modifications will occur to those skilled in the art based on a reading and understanding of this specification and the accompanying drawings. This application includes all such modifications and variations and is limited only by the scope of the appended claims. In particular, with respect to the various functions performed by the aforementioned components, the terminology used to describe such components is intended to correspond to any component (unless otherwise indicated) that performs the specified function of said component (e.g., is functionally equivalent to it), even if structurally not equivalent to the disclosed structure performing the functions in the exemplary implementations of this specification shown herein.

[0064] That is, the above description is only an embodiment of this application and does not limit the patent scope of this application. Any equivalent structural or procedural changes made using the content of this application’s specification and drawings, such as the combination of technical features between different embodiments, or direct or indirect application in other related technical fields, are similarly included within the patent protection scope of this application.

[0065] Furthermore, it should be understood that in the description of this application, the terms "center," "longitudinal," "lateral," "length," "width," "thickness," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," and "outer," etc., indicating the orientation or positional relationship, are based on the orientation or positional relationship shown in the accompanying drawings, and are only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of this application. In addition, for structural elements with the same or similar characteristics, this application may use the same or different reference numerals for identification. Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Therefore, features defined with "first" and "second" may explicitly or implicitly include one or more features. In the description of this application, "multiple" means two or more, unless otherwise expressly and specifically defined.

[0066] In this application, the term "exemplary" is used to mean "serving as an example, illustration, or description." Any embodiment described as "exemplary" in this application is not necessarily to be construed as more preferred or advantageous than other embodiments. This application has been provided above to enable any person skilled in the art to implement and use it. Various details have been set forth in the above description for purposes of explanation. It should be understood that those skilled in the art will recognize that this application can be implemented without using these specific details. In other embodiments, well-known structures and processes are not described in detail to avoid obscuring the description of this application with unnecessary detail. Therefore, this application is not intended to be limited to the embodiments shown, but is consistent with the broadest scope of the principles and features disclosed herein.

Claims

1. A digital phase-locked loop system, characterized in that, The digital phase-locked loop system includes a digitally controlled oscillator; the digitally controlled oscillator includes multiple sets of macrocells, each set of macrocells including at least one macrocell; Each macro unit group is used to turn on or off according to the configurable control signal input by the user, so as to determine the PLL output frequency modulation range by the number of macro unit groups turned on, and to adjust the PLL output frequency modulation range according to the adjustment command input by the user.

2. The digital phase-locked loop system according to claim 1, characterized in that, The configurable control signals include binary control bits corresponding to each group of macrocells; Each macrocell in each group is turned on when the corresponding binary control bit is 1, and turned off when the corresponding binary control bit is 0.

3. The digital phase-locked loop system according to claim 2, characterized in that, The adjustment commands include coarse adjustment commands; The digital phase-locked loop system is also used to adjust the on / off state of each group of macrocells according to the coarse adjustment command, thereby adjusting the number of macrocells connected.

4. The digital phase-locked loop system according to claim 2, characterized in that, Each macro unit includes two sets of sub-units, and each set of sub-units includes multiple sub-units; the configurable control signal also includes sub-unit control fields corresponding to each sub-unit. Each subunit in each group of subunits is used to turn on or off according to the subunit control field to adjust the PLL output frequency modulation range corresponding to the macrounit.

5. The digital phase-locked loop system according to claim 4, characterized in that, After determining the number of macrocell groups and subcells to be turned on, the digitally controlled oscillator turns on and off the corresponding macrocell groups and subcells respectively to adjust the output frequency of the PLL.

6. The digital phase-locked loop system according to claim 4, characterized in that, The sub-unit control field includes the binary control bits corresponding to each sub-unit; Each of the sub-units is turned on when the corresponding binary control bit is 1, and turned off when the corresponding binary control bit is 0.

7. The digital phase-locked loop system according to claim 4, characterized in that, The adjustment commands include fine-tuning commands; The digital phase-locked loop system is also used to adjust the on / off state of each of the sub-units according to the fine-tuning instructions, thereby adjusting the number of sub-units connected in each macro-unit.

8. The digital phase-locked loop system according to claim 4, characterized in that, Each of the macrocells further includes a first NAND gate, a second NAND gate, a third NAND gate, and an inverter; The input terminals of the first group of sub-units serve as the first input terminals of the corresponding macro-units and are connected to the first output terminal of the previous macro-unit. The control terminal is used to receive the configurable control signal and is connected to the control terminal of the second group of sub-units, the first input terminal of the first NAND gate, and the input terminal of the inverter, respectively. The output terminals are connected to the second input terminals of the first NAND gate and the first input terminals of the second NAND gate, respectively. The output terminal of the first NAND gate is connected to the first input terminal of the third NAND gate. The output terminal of the inverter is connected to the second input terminal of the second NAND gate. The output terminal of the second NAND gate serves as the first output terminal of the corresponding macro-unit and is connected to the first input terminal of the next macro-unit. The second input terminal of the third NAND gate serves as the second input terminal of the corresponding macro-unit and is connected to the second output terminal of the next macro-unit. The output terminal of the second group of sub-units serves as the second output terminal of the corresponding macro-unit and is connected to the second input terminal of the previous macro-unit.

9. The digital phase-locked loop system according to claim 8, characterized in that, The digital phase-locked loop system also includes a time-to-digital conversion circuit and a digital filter; The first terminal of the time-to-digital conversion circuit is used to connect to a reference clock, the second terminal is connected to the output terminal of each group of macrocells, and the third terminal is connected to the input terminal of the digital filter; the output terminal of the digital filter is connected to the enable control terminal of the digitally controlled oscillator. The time-to-digital converter circuit is used to obtain the phase difference between the PLL output signal and the reference clock, and send the phase difference to the digital filter; The digital filter is used to perform digital signal processing on the phase difference, and outputs a control signal to adjust the digitally controlled oscillator based on the processing result.

10. A method for real-time adjustment of the PLL output frequency modulation range in a digital phase-locked loop system, characterized in that, Includes the following steps: Obtain user input metrics; The PLL is used to design a database to parse the user input indicators and obtain the configurable control signals corresponding to the user input indicators. The PLL output frequency modulation range is determined by the digital phase-locked loop system according to any one of claims 1 to 9.

11. The method for real-time adjustment of the PLL output frequency modulation range of a digital phase-locked loop system according to claim 10, characterized in that, The process of determining the PLL design database includes: Analyze the design indicators for each group; A PLL design database is constructed based on the analyzed design indicators of each group. After the chip is fabricated, the design specifications of each group are verified and analyzed. The PLL design database is updated using the design metrics from the validation analysis.

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