Local clock calibration method and time synchronization signal channel expansion system

Abstract

The invention relates to a local clock calibration method and a time synchronization signal channel expansion system, a timed device receives a PPS signal transmitted by a channel expansion device, and the method comprises the following steps: based on a received PPS output signal, measuring and determining a period deviation y of a local clock of the timed device relative to a standard time; dynamically generating a correction step z and a correction interval b based on the period deviation y according to an allowable error threshold value Q; and in the next time service period, taking the calibration time interval b as a period, and utilizing the calibration step z to carry out multiple times of incremental adjustment on a local calibratable time counter, so that the timing of the local calibratable time counter is close to the standard time. According to the invention, the problem of one-to-many signal distribution can be solved with low cost and high reliability, and a time service algorithm which is low in calculation overhead and easy to transplant and deploy on MCUs with various performance levels can be realized.

Description

Technical Field

[0001] This application relates to the field of time synchronization, and in particular to a local clock calibration method and a time synchronization signal channel extension system. Background Technology

[0002] In current industrial control, data acquisition, and distributed systems, accurate time synchronization of multiple devices is a critical technical requirement. The aim is to ensure the timing accuracy of event data and achieve higher-precision collaborative control. Existing technologies offer various time synchronization solutions, such as Ethernet-based precise time protocols (e.g., GPTP), synchronization techniques combining GPS-based pulse-per-second (PPS) synchronization with UART serial communication, and other synchronization methods that rely on specific timing device interfaces. While these solutions can effectively synchronize multiple devices in specific applications, they each have their advantages and disadvantages, typically placing higher demands on one or more aspects of the system, including operating environment, deployment costs, multi-device synchronization capabilities, and terminal device computing power.

[0003] Specifically, these higher requirements manifest in different aspects. For Ethernet-based protocols such as GPTP, to achieve sub-microsecond high-precision synchronization, all network nodes within the synchronization domain, including terminal devices and network switches, are typically required to have hardware timestamp functionality. This undoubtedly increases hardware costs and the complexity of network deployment. Simultaneously, a complete protocol stack also places certain demands on the processor performance and memory resources of the terminal devices. While GPS-based PPS plus serial port solutions offer high time synchronization accuracy, they suffer from bottlenecks in multi-device synchronization capabilities. The electrical drive capability of the PPS and RS232 signal output ports of a single time synchronization device is limited. If directly connected to multiple time-synchronized devices in parallel, issues such as increased load and impedance mismatch can cause signal reflection and waveform distortion, leading to significant changes in the physical characteristics of the signal and severely impacting time synchronization accuracy and communication reliability.

[0004] Furthermore, due to the diversity of application scenarios, the time-synchronized devices often employ microcontrollers (MCUs) with varying performance levels. The aforementioned existing technical solutions, especially those relying on complex algorithms or specific hardware functions, suffer from poor portability between MCUs of different performance levels. A synchronization algorithm designed for high-performance processors and consuming significant resources is difficult to directly migrate to a resource-constrained, low-cost MCU. Conversely, an extremely simplified solution may fail to meet the accuracy requirements of high-performance applications. Summary of the Invention

[0005] To address the problem of low-cost, highly reliable one-to-many signal distribution, and to implement a timing algorithm with low computational overhead that is easy to port and deploy on MCUs of various performance levels, this application provides a local clock calibration method and a time synchronization signal channel extension system.

[0006] Firstly, this application provides a local clock calibration method for a time-synchronized device, which adopts the following technical solution: A local clock calibration method for a time-synchronized device, the time-synchronized device receiving a PPS signal transmitted via a channel extension device, the method comprising the following steps: S1. Based on the received PPS output signal, measure and determine the period deviation y of the local clock of the time-synchronized device relative to the standard time; S2. Based on the periodic deviation y and according to the allowable error threshold Q, dynamically generate the correction step z and the correction interval b; S3. In the next timekeeping cycle, using the calibration time interval b as the period, the calibration step z is used to make multiple incremental adjustments to a local calibrable time counter so that its timing approaches the standard time.

[0007] By adopting the above technical solution, step S1 first involves real-time measurement to determine the period deviation y of the local clock of the time-synchronized device relative to the standard time. Step S2 then dynamically generates the calibration step z and calibration time interval b based on this period deviation y and a preset accuracy target. Since the calibration parameters are dynamically generated based on each measurement result, this method can adapt to clock drift caused by factors such as changes in operating temperature, without relying on a fixed compensation model. Furthermore, the process of generating calibration parameters can be implemented using low-complexity operations such as bitwise operations, requiring less processor resources, thus making it feasible to deploy on microcontrollers of different performance levels.

[0008] In time synchronization applications, a single, concentrated correction at the end of a cycle can cause a significant jump in the value of the local time counter. This discontinuity in time disrupts the monotonicity of the timing sequence, potentially leading to erroneous calculations or even system instability in systems requiring data interpolation, differentiation, or precise control logic. This solution distributes the total cycle deviation y into multiple tiny calibration steps z, adjusting them multiple times within a timing cycle at short calibration intervals b. This continuous, incremental correction method ensures that the value of the calibrable time counter changes smoothly and continuously, effectively guaranteeing the monotonically increasing time. Furthermore, this mechanism ensures that the local clock continuously converges to the standard time at any point within the entire second cycle, rather than aligning only at the second boundary. This not only improves the overall synchronization accuracy of the cycle but also significantly enhances the accuracy of the timestamp at any point within the second.

[0009] Optionally, S1 includes: S11. Based on the first counter X, measure the time interval between the rising edges of two consecutive PPS signals under the local system clock of the time-synchronized device to obtain the measurement period x; S12. Calculate the period deviation y based on the difference between the measurement period x and the standard second period.

[0010] By adopting the above technical solution, the measurement subject is first identified as the first counter X, the measurement reference is the local system clock of the time-synchronized device, and the start and end boundaries of the measurement are the rising edges of two consecutive PPS signals. Using the rising edge of the signal as the trigger boundary utilizes its physical characteristic of having the fastest rate of change, thereby achieving high-precision interval capture and ensuring the accuracy of the obtained measurement period x. Next, step S12 compares the measurement period x with the standard second period to directly quantify the period deviation y.

[0011] Optionally, S2 includes: S21. Set an allowable error threshold Q as the preset accuracy target; S22. The absolute value of the period deviation y is cyclically shifted to the right until the shift result is less than the allowable error threshold Q or the number of shifts reaches a preset maximum value, and the final number of shifts is recorded as n; wherein, the calibration step z is obtained by shifting the period deviation y to the right n times, and the calibration time interval b is obtained by shifting the measurement period x to the right n times, corresponding to dividing the next timing period into 2^n intervals.

[0012] By adopting the above technical solution, a configurable allowable error threshold Q is first introduced, making the accuracy target of this calibration method a configurable parameter, thus enhancing its applicability to applications with different accuracy levels. Then, a low-complexity operation, cyclic right shift, is used to dynamically determine the granularity of the calibration scheme. Using bitwise operations instead of conventional division significantly reduces the demand on processor computing resources, enabling the algorithm to run efficiently on low-cost microcontrollers with weak or even absent hardware dividers. Furthermore, the number of shifts, n, is dynamically determined based on the magnitude of the real-time error, y. This means that when the device clock drifts significantly, the algorithm automatically increases the number of divisions to correct with smaller steps, and vice versa. This adaptive adjustment mechanism ensures the smoothness and robustness of the calibration process, ultimately achieving the generation of optimal calibration parameters that precisely match the current device state with extremely low computational overhead.

[0013] Optionally, when x is not divisible by 2^n, the additional count corresponding to the remainder is evenly distributed to each calibration interval according to a predetermined allocation strategy.

[0014] By employing the above technical solution, a compensation mechanism is provided to address the quantization error generated when calculating calibration intervals using bitwise operations, thereby further improving the long-term accuracy of the synchronization algorithm. In digital circuits, a right shift operation is essentially an efficient integer division, which discards any remainders that do not result in a perfect division. Although this discarded remainder is small in a single cycle, it can create a small but persistent system error during long-term continuous system operation, accumulating over time and eventually leading to a considerable deviation between the local clock and the standard time. This solution captures this remainder and compensates for it in subsequent calibration intervals according to a predetermined strategy, ensuring that the sum of all calibration interval durations within a complete timing cycle is precisely equal to the initially measured cycle x. This eliminates a potential source of accumulated error, significantly enhancing the long-term stability and final synchronization accuracy of the entire time synchronization system.

[0015] Optionally, the preset maximum value is 10.

[0016] By adopting the above technical solution, a clear and reasonable computational boundary is provided for the generation process of calibration parameters, which helps to ensure the stability and predictable performance of the algorithm under extreme conditions. A preset maximum value is set to limit the number of times the algorithm divides the period deviation y when it is extremely large. This value is 10, meaning that a period is divided into a maximum of 1024 parts. This ensures that the algorithm has sufficient segmentation granularity to smoothly correct very large clock errors; on the other hand, it avoids excessively short calibration time intervals b and excessively frequent calibration events due to too many segments, thus avoiding unnecessary computational and interrupt overhead on the processor.

[0017] Optionally, S3 includes: S31. The calibration time interval b is timed based on a down counter Y, wherein the down counter Y is repeatedly loaded with the calibration time interval b and counts down; S32. Whenever the down counter Y counts to zero, the value of a second counter A, which serves as a calibrable time counter, is adjusted once; wherein the direction of the adjustment is determined based on the sign of the period deviation y, and the magnitude of the adjustment is the calibration step z.

[0018] By adopting the above technical solution, a dedicated down-counter Y is first used for periodic timing. This dedicated down-counter Y decouples the triggering of periodic events from the main program logic, effectively reducing software timing overhead and processor load, while ensuring the accuracy of the calibration time interval. Counter Y acts as a trigger, while a second counter A serves as the corrected time base, ensuring that the value of counter A, as the final time output, is stable and continuously increasing. Its value is only subjected to a discrete, minute step adjustment at the precise moment when the Y count reaches zero.

[0019] Optionally, after the temperature change of the time-synchronized device exceeds a preset amount, or after a preset time period, the calibration parameters are re-executed in steps S1 and S2 to recalculate and update the calibration parameters, wherein the calibration parameters include the values ​​of calibration step z and calibration time interval b.

[0020] By adopting the above technical solution, since the frequency drift of the local clock is significantly affected by temperature, if the calibration parameters are not updated after being generated once, the fixed calibration parameters will be unable to match the new drift rate when the device's operating temperature changes, leading to a decrease in synchronization accuracy. Therefore, this solution triggers the recalculation of calibration parameters by setting a temperature change threshold, enabling the method to actively adapt to the thermal dynamics of the external environment and ensuring that the calibration scheme is always based on the latest physical state of the device. In addition, by setting a preset time period as a supplementary trigger condition, slow and long-term drift caused by factors such as component aging can be periodically corrected.

[0021] Optionally, the allowable error threshold Q is set based on the MCU performance of the time-synchronized device and the required time synchronization accuracy, and is an integer beat of the local system clock of the time-synchronized device.

[0022] By adopting the above technical solution, firstly, defining the unit of Q as an integer step size of the local system clock ensures that the comparison operation is performed in a unified, dimensionless counting unit when determining the calibration granularity. This avoids introducing floating-point operations or unit conversions into the core algorithm, simplifying program implementation and improving computational efficiency. Secondly, it is explicitly stated that the value of Q must consider both the required timing accuracy and MCU performance. Developers can initially set the Q value based on the specific application's time accuracy requirements. Furthermore, if the MCU performance is limited, the Q value can be appropriately relaxed (i.e., accepting a slightly larger calibration step) to reduce the frequency of calibration events and reserve more computing resources for the MCU's main application tasks.

[0023] Secondly, this application provides a time synchronization signal channel extension system based on PPS and RS232, which adopts the following technical solution: A time synchronization signal channel extension system based on PPS and RS232 includes a channel extension device and at least one time synchronization device; The channel expansion device includes: A signal input module is used to receive a single PPS signal and a single RS232 data signal generated by a single timing device; a PPS signal processing module is configured with an active multiplexer to regenerate the single PPS signal into multiple PPS output signals with consistent physical characteristics. An RS232 signal processing module is used to regenerate the single-channel RS232 signal into multiple RS232 output signals; The time-synchronized device is used to receive one of the PPS output signals and the RS232 output signal from the channel extension device. The time-synchronized device includes: A processor; A memory containing instructions executable by the processor; When the instruction is executed, it enables the processor to perform the local clock calibration method for a time-synchronized device as described in any one of claims 1-6.

[0024] By adopting the above technical solution and configuring an active multiplexer and signal regeneration circuit, the device can replicate and distribute the PPS and RS232 signals from a single timing source to multiple timing devices with high quality, ensuring that each device receives an independent signal with consistent electrical characteristics and no distortion, thus overcoming the inherent problems of increased load and impedance mismatch in traditional signal splitting methods.

[0025] Secondly, the time-synchronized devices in the system execute a lightweight local clock calibration method through their built-in processors and instructions. This method works perfectly in synergy with the channel expansion device: the channel expansion device solves the problem of reliably delivering the standard time signal, while the time-synchronized devices solve the problem of efficiently utilizing this signal to accurately calibrate their local clocks under resource constraints. The clear and stable PPS signal provided by the hardware is a prerequisite for the software algorithm to perform accurate error measurement; the software algorithm fully utilizes this high-quality signal to transform precise second boundary information into continuous, smooth, high-resolution time within seconds. Therefore, as a whole, this system provides a comprehensive solution that combines high reliability, high precision, high scalability, and low cost, making it possible to deploy high-precision time synchronization networks in complex scenarios employing numerous low-performance microcontrollers.

[0026] Optionally, the RS232 signal processing module includes: a centralized RS232→TTL conversion channel and multiple independent TTL→RS232 driving channels, used to drive the upstream single-channel RS232 signal into independent multi-channel RS232 outputs.

[0027] In summary, this application includes at least one of the following beneficial technical effects: 1. By configuring hardware-level active drivers and signal regeneration circuits, the signal integrity degradation caused by increased load and impedance mismatch during one-to-many distribution of traditional PPS and RS232 signals is solved at the physical layer, realizing a reliable and high-precision physical synchronization link for multiple devices and enhancing the scalability of the system.

[0028] 2. A local clock calibration algorithm with low computational overhead and dynamic self-adaptation is provided. The core of this algorithm is mainly based on low-complexity operations such as bitwise operations, and it can dynamically adjust the calibration scheme according to the real-time measured clock deviation, thereby greatly reducing the requirements for the hardware performance of terminal devices. At the same time, it can cope with the influence of environmental factors such as temperature changes and has excellent portability and robustness.

[0029] 3. A multi-step, incremental smoothing calibration mechanism is adopted, distributing the total periodic deviation across multiple tiny steps for correction. This avoids drastic jumps in the time counter's value at calibration moments, ensuring the continuity and monotonicity of local time and significantly improving the accuracy and reliability of the timestamp at any point within a second. Attached Figure Description

[0030] Figure 1 A schematic diagram of a time synchronization signal channel extension system based on PPS and RS232 is shown in one embodiment of the present invention.

[0031] Figure 2 A flowchart illustrating a local clock calibration method for a time-synchronized device according to an embodiment of the present invention is shown.

[0032] Explanation of reference numerals in the attached figures: 1. Time synchronization device; 2. PPS signal input channel; 3. Multi-channel driver chip; 4. PPS signal output channel; 5. Device being synchronized; 6. RS232 signal input channel; 7. RS232 to TTL serial port chip; 8. TTL serial port signal; 9. TTL to RS232 serial port chip; 10. RS232 signal output channel. Detailed Implementation

[0033] The present application will be further described in detail below with reference to the accompanying drawings. It should be understood that the specific embodiments described herein are merely illustrative of the application and are not intended to limit the scope of the application.

[0034] In the following description, numerous specific details are set forth for purposes of explanation in order to provide a thorough understanding of the inventive concept. As part of this specification, some of the accompanying drawings of this disclosure are block diagrams illustrating structures and devices to avoid complicating the disclosed principles. For clarity, not all features of the actual embodiment need to be described. Furthermore, the language used in this disclosure has been primarily chosen for readability and instructional purposes and may not have been chosen to define or limit the subject matter of the invention, thus requiring the necessary claims to determine such inventive subject matter. References to “an embodiment” or “an embodiment” in this disclosure mean that a particular feature, structure, or characteristic described in connection with that embodiment is included in at least one embodiment, and multiple references to “an embodiment” or “an embodiment” should not be construed as necessarily referring to the same embodiment.

[0035] Unless explicitly defined, the terms “a,” “an,” and “the” are not intended to refer to a singular entity, but rather to include a general category whose specific examples can be used for illustration. Therefore, the use of the terms “a” or “an” can mean any number of at least one, including “a,” “one or more,” “at least one,” and “one or more.” The term “or” means any of the options and any combination of the options, including all options unless explicitly indicated that the options are mutually exclusive. The phrase “at least one of” when combined with a list of items refers to a single item in the list or any combination of items in the list. The phrase does not require all items listed unless explicitly defined as such.

[0036] In many technological fields such as modern industrial control, data acquisition, and distributed computing, accurate time synchronization of multiple devices or nodes within a system is a fundamental and critical technical requirement. A unified and accurate time reference ensures that the data acquired in a distributed manner has the correct temporal sequence during fusion analysis and provides reliable time assurance for collaborative control and scheduling among multiple agents. To achieve this, one or more time synchronization devices are typically introduced as the system's time reference source. Such time synchronization devices can provide high-precision time information, and their own time is usually traceable to a Global Navigation Satellite System (GNSS), such as the Global Positioning System (GPS), thus maintaining a high degree of consistency with Coordinated Universal Time (UTC).

[0037] A common time synchronization principle involves time synchronization devices using at least two different types of signals to collaboratively transmit time information. One is a pulse-second signal (PPS), typically a pulse-level signal with a period of one second. The rising or falling edge of this signal is precisely calibrated to the starting boundary of a standard second, serving as a high-precision physical time anchor. The other is a serial communication signal, such as a data frame transmitted via an RS-232 interface, which carries specific, human-readable absolute time stamp information, such as a UTC timestamp containing year, month, day, hour, minute, and second. Upon receiving these two signals, the device being synchronized uses the precise edge of the PPS signal to calibrate the phase of its local clock, while simultaneously using the serial communication signal to assign an absolute time stamp to that phase point. The combination of these two methods allows for the local reconstruction of a high-precision absolute time.

[0038] In modern industrial control systems, a one-to-many timing architecture is a common requirement for achieving large-scale, high-precision collaborative operations. For example, in distributed data acquisition systems deployed for large equipment (such as aircraft engine test benches and wind turbine generators) or complex production lines, hundreds or thousands of sensors are installed in different locations, and their data is processed by multiple distributed acquisition units. To accurately analyze and correlate this data, especially to reproduce the occurrence and propagation of transient events, the local clocks of all acquisition units must be synchronized with a common time reference. Furthermore, in the field of high-performance cooperative motion control, such as multi-joint robots or automated work units composed of multiple robots, the servo controllers of each motion axis or independent robot controllers also require strict time synchronization to ensure they can accurately execute complex linkage trajectories. Similarly, in power system automation, all intelligent electronic devices (IEDs) in substations, such as protective relays and fault recorders, must be synchronized to a unified time source so that the sequence of events can be accurately recorded when a power grid fault occurs, providing a basis for fault diagnosis and system recovery. In these scenarios, an authoritative time synchronization device typically acts as the master clock, providing time synchronization signals to multiple slave devices within the system, thus forming a one-to-many time synchronization topology.

[0039] Before the aforementioned one-to-many time synchronization scenarios became a common requirement, many time synchronization devices widely adopted the RS-232 interface for one-to-one time synchronization with individual time-receiving devices. RS-232 is a mature serial communication interface standard that defines the electrical characteristics, interface pin functions, and communication protocols for asynchronous serial communication between Data Terminal Equipment (DTE) and Data Communication Equipment (DCE). A significant physical layer feature of this standard is its signal level logic: it uses negative voltages to represent logic "1" (-3V to -15V) and positive voltages to represent logic "0" (+3V to +15V). Compared to the TTL or CMOS logic levels commonly used in microcontrollers, this larger voltage swing gives RS-232 signals stronger noise immunity and a longer effective transmission distance, thus leading to its long-term and widespread use in industrial environments. During data transmission, information is sent asynchronously in the form of data frames. Each frame typically contains a start bit, several data bits, an optional parity bit, and one or more stop bits. Through this interface, the time synchronization device can reliably send data packets containing absolute time information to a single time-receiving device.

[0040] However, while the RS-232 interface performs robustly in one-to-one configurations, attempting to directly distribute the RS-232 signal or its parallel PPS signal from a single timing device to multiple timing devices via simple physical splitting introduces serious and intractable signal integrity problems. These problems primarily stem from insufficient drive capability, increased load, and impedance mismatch. On one hand, standard signal drivers, whether RS-232 driver chips or PPS signal output stages, are typically designed to drive a single load with specific input impedance and capacitance. When the inputs of multiple devices are connected in parallel on the same line, the total load capacitance increases exponentially, requiring the driver to provide a larger instantaneous current to charge and discharge the line capacitance. With limited drive capability, this inevitably leads to longer signal rise and fall times, making the already steep digital signal edges more sluggish.

[0041] On the other hand, physical bifurcation points in signal lines can cause severe discontinuities in the characteristic impedance of the transmission line. According to transmission line theory, when a rapidly changing signal edge encounters an impedance discontinuity, some signal energy is reflected, forming a back-and-forth oscillating reflected wave in the transmission path. This reflected wave, superimposed on the original signal, can cause distortion phenomena such as overshoot, undershoot, and ringing. For RS-232 signals carrying time stamps, edge hysteresis and waveform oscillations can interfere with the correct sampling of data bits by the receiving UART, leading to communication errors and making it impossible to reliably transmit time information. For PPS signals, which serve as high-precision time anchors, edge hysteresis and jitter directly reduce the accuracy of time synchronization, and oscillations may be misinterpreted as multiple valid trigger events, thus rendering the synchronization reference completely ineffective.

[0042] To address the signal integrity challenges posed by the aforementioned one-to-many signal distribution, the channel expansion device proposed in this application employs a parallel processing architecture, processing and regenerating PPS and RS232 signals through their respective independent physical paths. Specifically, for the high-precision PPS signal, the device utilizes a dedicated low-latency multiplexer chip for fan-out, ensuring that the edge characteristics of each output PPS signal are preserved. Simultaneously, a separate signal regeneration link is used for the data-carrying RS232 signal. This parallel processing architecture is adopted because PPS and RS232 signals differ fundamentally in their physical form, timing characteristics, and the information they carry.

[0043] Specifically, the PPS signal is essentially a high-precision physical time stamp. It typically manifests as a logic level pulse with a nominal period of one second, whose steep rising or falling edge serves as a precise phase reference point marking the start of a standard second. The key advantage of this signal lies in its extremely low time jitter, providing timing accuracy on the order of nanoseconds. However, it carries almost no data information; it can only indicate when a whole second begins, not which second it is. In contrast, the core function of the RS232 signal is to transmit data content. As an asynchronous serial byte stream, it carries a complete absolute time stamp, such as a UTC timestamp containing year, month, day, hour, minute, and second, as well as other status information. However, limited by its communication protocol, baud rate, and processing latency, the RS232 signal is far less precise than the PPS signal. Therefore, these two signals are functionally complementary: the PPS signal provides a precise but unmarked time, while the RS232 signal provides a clear but somewhat ambiguous identity label for this precise time. The time-receiving device must receive and process both signals simultaneously in order to correctly associate the high-precision phase anchor with the absolute time tag, thereby recovering the complete, high-precision absolute time locally.

[0044] To more clearly illustrate the implementation of this application, the following description will be provided in conjunction with the accompanying drawings. Figure 1 A schematic diagram of a time synchronization signal channel extension system according to a specific embodiment of this application is shown. The system mainly includes a timing device 1, a channel extension device, and multiple timing-receiving devices 5. The channel extension device integrates two parallel processing links for processing PPS signals and RS232 signals.

[0045] In the PPS signal processing chain, the single-channel PPS signal from timing device 1 enters the channel expansion device through PPS signal input channel 2 and is sent to a multiplexer chip 3. This multiplexer chip 3 is the core of the PPS signal path; its responsibility is to receive a single input pulse signal, buffer and regenerate it internally, and finally generate multiple PPS output signals with highly consistent timing through multiple electrically isolated output ports. A driver chip with extremely low propagation delay and minimal inter-channel variation should be selected here to ensure that the time anchor points of the PPS signals distributed to different timing devices 5 remain strictly synchronized. The regenerated multiple PPS signals are then transmitted to their respective timing devices 5 through their respective PPS signal output channels 4.

[0046] In the RS232 signal processing link, a single RS232 signal from timing device 1 enters the channel expansion device through RS232 signal input channel 6. The signal is first sent to an RS232-to-TTL serial port chip 7, which is responsible for converting the RS232 level with a relatively high voltage swing into a standard TTL logic level that is easily processed within the circuit board, forming a TTL serial port signal 8. Subsequently, this TTL serial port signal 8 is distributed in parallel on the circuit board to multiple TTL-to-RS232 serial port chips 9 through short-distance wiring. Each TTL-to-RS232 serial port chip 9 independently converts the received TTL signal back into an RS232 signal with standard electrical characteristics and sufficient drive capability, and transmits it to the corresponding timing device 5 through its respective RS232 signal output channel 10.

[0047] The parallel processing architecture employed in this application effectively distributes and mitigates the risks encountered during signal distribution at the physical layer. For PPS signals with extremely stringent timing requirements, a dedicated multi-channel driver is used for fan-out, ensuring the steepness and integrity of the edges of each output signal, thus providing physical assurance for its use as a high-precision time reference. For RS232 data signals, a regeneration strategy of "centralized RS232→TTL conversion, on-board short-line allocation, and sequential TTL→RS232 conversion" avoids long-distance, multi-load RS232 bus applications, ensuring that each time-synchronized device obtains an independent, equivalent, and reliable timestamp link.

[0048] In summary, the channel extension device architecture proposed in this application, through its signal regeneration design, directly avoids the problem of insufficient driving capability of a single time synchronization device's RS232 signal, which prevents reliable communication with multiple time-synchronized devices after data line forks. The original RS232 signal only needs to drive a single, impedance-matched RS232-to-TTL serial port chip, while subsequent multiplexing is accomplished by multiple independent, newly generated RS232 signals. It is important to note that both the low-latency multiplexing driver chip used for distributing PPS signals and the TTL serial port signal used for distributing time stamp information have their critical signal distribution paths controlled within the limited physical space of a single circuit board. Due to the extremely short trace length on the circuit board, signal attenuation during transmission is negligible, and signal reflection effects caused by factors such as wiring forks are also minimized. Therefore, the physical characteristics of the signal can be highly faithfully reproduced and distributed during the regeneration process, ultimately enabling this solution to support one time synchronization device in providing highly reliable and accurate time synchronization to multiple time-synchronized devices.

[0049] Another beneficial effect of this application is that its software and hardware collaborative architecture enables the high-precision time synchronization function to be applied to a wide range of time-synchronized devices with diverse performance profiles. These devices typically use a microcontroller (MCU) as their core processing unit. The local time calibration method proposed in this application does not rely on complex network protocol stacks (such as PTP / NTP, etc.). Its time reference is directly derived from the PPS signal at the hardware level, and the core algorithm only involves integer and bit operations. This design greatly reduces the demand on MCU computing power and storage resources. Therefore, even on a low-performance MCU with only tens of kilobytes of memory, sub-millisecond or even microsecond-level local time correction can be easily achieved.

[0050] This solution demonstrates good portability across MCUs with varying performance levels. When the time synchronization device uses a high-performance MCU, its powerful processing capabilities support higher frequency calibration events. Developers can therefore set a smaller allowable error threshold Q. A smaller Q value results in a finer calibration step z and a shorter calibration time interval b when calculating calibration parameters, meaning more calibration actions with smaller amplitudes. In this way, the high-performance MCU can suppress local time drift errors within a smaller range, thereby achieving higher granularity synchronization accuracy.

[0051] For example, in a time-synchronization device designed for cost-sensitive applications, a low-cost MCU with a low clock speed and very limited memory resources (such as RAM) might be configured. Deploying a complete network time synchronization protocol stack on such devices is impractical. However, the lightweight algorithm presented in this application requires minimal code space and memory footprint to run. Developers can set a suitable Q value to achieve synchronization accuracy at the millisecond level, meeting application requirements, while ensuring that calibration tasks do not excessively consume processor resources and affect the operation of the main business logic. Conversely, in a high-performance time-synchronization device with extremely high time accuracy requirements, its high-speed MCU can instantly calculate calibration parameters and handle high-frequency calibration interruptions without difficulty. Therefore, developers can set a very small Q value to pursue sub-microsecond or even nanosecond synchronization accuracy, enabling this technical solution to flexibly meet the needs of different scenarios, from general industrial control to high-precision measurement.

[0052] Specifically, this application discloses a local clock calibration method for a time-synchronized device, wherein the time-synchronized device receives a PPS signal transmitted via a channel extension device, and refers to... Figure 2 The method includes the following steps S1-S3.

[0053] S1. Based on the received PPS output signal, measure and determine the period deviation y of the local clock of the time-synchronized device relative to the standard time.

[0054] The purpose of step S1 is to measure and determine the period deviation y of the local clock of the time-synchronized device relative to the standard time based on the received PPS output signal. In a more specific embodiment, step S1 can be broken down into steps S11 and S12.

[0055] S11. Based on the first counter X, measure the time interval between the rising edges of two consecutive PPS signals under the local system clock of the time-synchronized device to obtain the measurement period x.

[0056] In step S11, the MCU of the time-synchronized device uses an internal first counter X to perform the measurement. This first counter X is driven by the MCU's local system clock and accumulates a count for each tick of the system clock. When the MCU receives the rising edge of the first PPS signal, the first counter X is cleared or its initial value is recorded and it begins counting; when it receives the rising edge of the next PPS signal, the counting stops. The time interval between these two rising edges physically defines a standard second period. During this period, the accumulated count value of the first counter X is the measurement period x.

[0057] S12. Calculate the period deviation y based on the difference between the measurement period x and the standard second period.

[0058] In step S12, the MCU compares the obtained measurement period x with the theoretical count value of a standard second period to calculate the period deviation y. Here, the theoretical count value of a standard second period is not an external input signal, but a constant predetermined based on the MCU's own rated system clock frequency. For example, if the MCU's rated system clock is 100MHz, it should theoretically generate 100 million clock beats in a standard second; this "100 million" is the theoretical count value of a standard second period. Therefore, the period deviation y is the difference between the measurement period x and this theoretical count value. The value and sign of the period deviation y have a clear physical meaning: if y is positive, it means that the local clock has recorded more beats than the rated value in a standard second, indicating that the local clock is running too fast; conversely, if y is negative, it indicates that the local clock is running too slow. In other words, this period deviation y is a direct quantification of the current drift rate of the local clock.

[0059] S2. Based on the periodic deviation y and according to the allowable error threshold Q, dynamically generate the correction step z and the correction interval b.

[0060] After the period deviation y, step S2 dynamically generates a set of optimal calibration parameters for the next second calibration cycle based on the deviation y and a preset accuracy target, specifically including the calibration step z and the calibration time interval b.

[0061] In a specific embodiment, step S2 can be broken down into steps S21 and S22.

[0062] S21. Set an allowable error threshold Q as the preset accuracy target.

[0063] In step S21, an allowable error threshold Q is set based on the timing accuracy requirements of the application scenario of the time-synchronized device and the performance of its own MCU. This threshold Q serves as a preset accuracy target, and its unit is the integer number of clock ticks (i.e., clock cycles) of the local system clock. It defines the level of precision in calibration pursued by the algorithm.

[0064] S22. The absolute value of the period deviation y is cyclically shifted to the right until the shift result is less than the allowable error threshold Q or the number of shifts reaches a preset maximum value, and the final number of shifts is recorded as n; wherein, the calibration step z is obtained by shifting the period deviation y to the right n times, and the calibration time interval b is obtained by shifting the measurement period x to the right n times.

[0065] In step S22, the absolute value of the period deviation y is cyclically shifted right bit by bit. Each right shift is equivalent to an integer division by 2. This cyclic operation continues until the shifted result is less than a preset allowable error threshold Q, or the number of shifts reaches a preset maximum value (e.g., 10). The final number of shifts at the end of the loop is recorded as n. Here, n is a dynamically calculated key parameter that reflects the hierarchy at which the total error y needs to be divided to achieve the accuracy target Q. The calibration cycle of the next second will be divided into 2^n time periods.

[0066] After determining the segmentation level n, the two core parameters used for actual calibration can be calculated. The calibration step z is obtained by shifting the period deviation y to the right n times. It represents the magnitude of correction that should be made to the calibrable time counter in each subsequent incremental adjustment, and its unit is also the number of clock ticks. The calibration time interval b is obtained by shifting the measurement period x measured in step S11 to the right n times. It represents the duration that should be between two consecutive calibration actions, and its unit is also the number of clock ticks.

[0067] In a preferred embodiment, to further improve the accuracy of long-term timing, compensation can be made for the calculation of the calibration time interval b. Since right shifting is an integer division, when the measurement period x is not divisible by 2^n, the remainder is discarded when calculating b = x >> n. Although this remainder is small, it will cause cumulative error if left unprocessed. Therefore, the additional count value corresponding to the remainder (i.e., x % 2^n) can be evenly or quasi-evenly distributed into each calibration interval according to a predetermined allocation strategy (e.g., adding one beat in each of the first few calibration intervals b of the next cycle), thereby ensuring that the total duration of all calibration intervals is exactly equal to the measurement period x, eliminating the long-term cumulative effect of quantization error.

[0068] S3. In the next timekeeping cycle, using the calibration time interval b as the period, the calibration step z is used to make multiple incremental adjustments to a local calibrable time counter so that its timing approaches the standard time.

[0069] This step involves performing actual, multiple, and incremental calibration adjustments within the next timing cycle following the measurement cycle. The goal of this step is to smoothly and discretely compensate for the total cycle deviation y measured in step S1, thereby bringing the timing behavior of a local calibrable time counter closer to standard time.

[0070] In one specific embodiment, the execution of S3 relies on two counters: a calibrable time counter, referred to herein as the second counter A, which serves as the final precise time output; and a down counter Y used to periodically trigger the calibration action. Like the first counter X, the second counter A is driven by the local system clock and is reset to zero on the rising edge of each PPS signal. However, unlike the first counter X, which is used solely for measurement, the count value of the second counter A can be actively modified by the program. Its ultimate goal is to become a precise "local intrasecond clock," whose count value represents the calibrated, precise time elapsed since the previous second boundary. The down counter Y is a dedicated timer used to precisely time the calibration time interval b calculated by S2.

[0071] Specifically, S3 includes two sub-steps, S31 and S32.

[0072] S31. The calibration time interval b is timed based on a down counter Y, wherein the down counter Y is repeatedly loaded with the calibration time interval b and counts down.

[0073] S32. Whenever the down counter Y counts to zero, the value of a second counter A, which serves as a calibrable time counter, is adjusted once; wherein the direction of the adjustment is determined based on the sign of the period deviation y, and the magnitude of the adjustment is the calibration step z.

[0074] In step S31, the down counter Y is loaded with an initial value, which is the calibration time interval b. Y then begins counting down in sync with the local system clock. In step S32, when the count value of the down counter Y decreases to zero, it indicates that a calibration time interval of length b has elapsed. At this point, the MCU adjusts the value of the second counter A. The specific direction of the adjustment is determined by the sign of the period deviation y calculated in step S12: if y is positive (indicating the local clock is too fast), the adjustment direction is decrement; if y is negative (indicating the local clock is too slow), the adjustment direction is increment. The adjustment magnitude is constant at the calibration step z calculated in S22. After one adjustment is completed, the down counter Y is immediately reloaded with the calibration time interval b and begins the next countdown, repeating this cycle until the next PPS signal arrives. By performing multiple such small and precise adjustments throughout the entire one-second cycle, the accumulated count value of the second counter A can continuously converge towards the ideal value.

[0075] To further ensure the stability of this calibration method during long-term operation and its adaptability to environmental changes, in a preferred embodiment, the calculation of calibration parameters is not a one-time operation. The calibration parameters, including the values ​​of the calibration step z and the calibration time interval b, can be recalculated and updated when specific trigger conditions are met. These trigger conditions may include: the temperature change of the time-synchronized device exceeding a preset amount, or the expiration of a preset time period (e.g., several minutes or hours). When either condition is met, the MCU of the time-synchronized device will re-execute the aforementioned steps S1 and S2 to obtain the latest clock drift state and generate a new set of matching calibration parameters, thereby ensuring that the calibration effect is always maintained at an optimal level.

[0076] Furthermore, the settings of key parameters in the algorithm can be based on specific technical requirements. For example, the allowable error threshold Q can be set based on the MCU performance of the time-synchronized device and the timing accuracy required by the application. To facilitate calculation and improve efficiency, the unit of this threshold Q is defined as an integer number of clock cycles of the local system clock of the time-synchronized device. As an example, in a specific embodiment, the preset maximum value used to limit the number of cyclic shifts in step S22 can be set to 10.

[0077] To further clarify the specific process of the method described in this application, a specific numerical embodiment is given below.

[0078] Suppose a timing device 5 has an internal MCU with a rated system clock frequency of 100MHz. Therefore, one clock cycle of its local clock is 10 nanoseconds, and one standard second cycle corresponds to a theoretical count of 100,000,000 cycles. Suppose that under certain operating conditions, due to environmental factors such as temperature, the actual clock frequency of this MCU is 50ppm (parts per million) faster than the rated value.

[0079] In this state, when the MCU begins executing the calibration method, it first proceeds to step S1. In step S11, the first counter X counts between the rising edges of two consecutive PPS signals. Due to the local clock being ahead, X will count to a measurement period x greater than the theoretical value within a standard second of physical time. This value x is 100,000,000 + (100,000,000 * 50 / 1,000,000) = 100,050,000 beats. Next, in step S12, the period deviation y = x - 100,000,000 = +50,000 beats is calculated. y is a positive value, reflecting the local clock being ahead.

[0080] Subsequently, the calibration parameters are calculated. Assuming the required synchronization accuracy for this application scenario is better than 1 microsecond, in step S21, the allowable error threshold Q = 1000ns / 10ns / beat = 100 beats can be set. In step S22, the absolute value of the period deviation y, 50,000, is cyclically shifted right until the result is less than Q. Calculation shows that when the number of shifts n = 9, the shift result is 50000 >> 9 = 97, which is less than 100, so the loop terminates, and n = 9 is determined. Then, the calibration step z = y >> n = 50000 >> 9 = 97 beats and the calibration time interval b = x >> n = 100050000 >> 9 = 195,410 beats are calculated.

[0081] Finally, calibration is performed in the next second cycle. When the rising edge of the new PPS signal arrives, the second counter A is reset to zero. Simultaneously, the down counter Y is loaded with the initial value b = 195,410 and begins its countdown. Each time Y counts down to zero, the MCU adjusts the second counter A. Since the cycle deviation y is positive, indicating the clock is too fast, the adjustment direction is subtraction, and the adjustment magnitude is a calibration step z = 97 beats. Afterward, Y is reloaded with the b value and a new countdown begins. This process repeats 2^n = 512 times throughout the entire second cycle. Through these 512 small and uniform subtraction corrections, the total value of counter A, driven by the local fast clock, is continuously pulled back to the standard value, effectively compensating for the original deviation of 50,000 beats, ensuring that its final timing result is highly synchronized with the standard time.

[0082] Furthermore, the total compensation amount for 512 executions is 97 × 512 = 49,664, with a residual of 336 beats. In another embodiment, to achieve complete compensation for the period deviation y and eliminate the quantization error caused by the timing calculation of the calibration step z, a step jitter or quota allocation strategy can be adopted. In this strategy, a reference calibration step z0 = |y| >> n is first calculated. Subsequently, the total uncompensated margin d = |y| - z0·2 is calculated. n This margin d represents 2 in the next period. n The total number of clock cycles requiring additional compensation in this calibration event. Therefore, when performing step S3, in these 2 n In this adjustment, d adjustments use a calibration step of (z0+1), while the remaining (2n-d) adjustments use a calibration step of z0. The direction of the adjustment is still determined by the sign of y. In this way, it can be ensured that within a complete timing cycle, the sum of all calibration steps is precisely equal to the absolute value of the initially measured cycle deviation y, thus eliminating the calculation error of the calibration quantity in principle and further improving the synchronization accuracy.

[0083] In another embodiment, the rule used in S22 to determine the segmentation level n is further optimized to achieve a smaller residual error after a single calibration cycle. In this optimization rule, the selection of the value of n must simultaneously satisfy two constraints: first, the value of the single calibration step z = |y| >> n must be less than the allowable error threshold Q; second, the absolute value of the cumulative residual over the entire cycle caused by the quantization error of step z, i.e., |y| - 2 n The value of z must also be less than the allowable error threshold Q. The algorithm will search for an optimal value of n under these two constraints.

[0084] In another preferred embodiment, to achieve accurate timing while maintaining the majority of calibration steps constant, a final compensation adjustment strategy can be adopted. This strategy, during step S3, adjusts the first (k-1) calibration events within a time synchronization cycle using a constant calibration step z calculated in step S22 for the total k = 2n calibration events. However, during the kth, and final, adjustment, a specially calculated final calibration step z' is used. The value of this final step z' is the total deviation minus all deviations already performed, i.e., z' = |y| - (k-1)·z. By performing this compensation, it can be ensured that the cumulative effect of all k adjustments is exactly equal to the total cycle deviation y.

[0085] It should be understood that the sequence number of each step in the above embodiments does not imply the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of the present invention.

[0086] Those skilled in the art will clearly understand that, for the sake of convenience and brevity, the above-described division of functional units and modules is used as an example. In practical applications, the above functions can be assigned to different functional units and modules as needed, that is, the internal structure of the device can be divided into different functional units or modules to complete all or part of the functions described above.

[0087] The above embodiments are only used to illustrate the technical solutions of the present invention, and are not intended to limit it. Although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of the present invention, and should all be included within the protection scope of the present invention.

Claims

1. A method for local clock calibration of a time-served device, characterized in that, The time-served device receives the PPS signal transmitted via the channel expansion device, and the method comprises the following steps: S1. Based on the received PPS output signal, measure and determine the period deviation y of the local clock of the time-served device relative to the standard time; S2. Based on the period deviation y, and according to the allowable error threshold Q, dynamically generate the correction step z and the correction interval b; S3. In the next time-served period, periodically adjust a local correctable time counter by the calibration step z with the calibration interval b as the period, so that its timing approaches the standard time.

2. The method for local clock calibration of a time-synchronized device according to claim 1, wherein, The S1 comprises: S11. Based on the first counter X, measure the time interval between the rising edges of the two consecutive PPS signals at the local system clock of the time-served device to obtain the measurement period x; S12. Calculate the period deviation y according to the difference between the measurement period x and the standard second period.

3. The method for local clock calibration of a time-synchronized device according to claim 2, wherein, The S2 comprises: S21. Set an allowable error threshold Q as the preset accuracy target; S22. Perform a cyclic right shift operation on the absolute value of the period deviation y until the shift result is less than the allowable error threshold Q or the number of shifts reaches a preset maximum value, and record the final number of shifts as n; wherein the calibration step z is obtained by right shifting the period deviation y by n times, and the calibration time interval b is obtained by right shifting the measurement period x by n times, corresponding to dividing the next time-served period into 2^n intervals.

4. The method for local clock calibration of a time-synchronized device according to claim 3, wherein, When the measurement period x cannot be divided by 2^n, the remainder is uniformly distributed to each calibration interval according to a predetermined distribution strategy.

5. The method for local clock calibration of a time-synchronized device according to claim 3, wherein, The preset maximum value is 10.

6. The method for local clock calibration of a time-synchronized device according to claim 3, wherein, The S3 comprises: S31. Based on a downward counter Y, count the calibration time interval b, wherein the downward counter Y is repeatedly loaded with the calibration time interval b and counts down; S32. Adjust the value of a second counter A as a correctable time counter every time the downward counter Y counts to zero; wherein the direction of the adjustment is determined based on the sign of the period deviation y, and the amplitude of the adjustment is the calibration step z.

7. The method for local clock calibration of a time-synchronized device of claim 1, wherein, The calibration parameters are re-executed to recalculate and update the calibration parameters, including the values of the calibration step z and the calibration time interval b, after the temperature of the time-served device changes by more than a preset change amount, or after a preset time period.

8. The local clock calibration method for time-served devices according to claim 1, wherein the allowable error threshold Q is set based on the MCU performance of the time-served device and the required time-served accuracy, and is an integer beat of the local system clock of the time-served device.

9. A PPS and RS232 based time synchronization signal channel extension system, characterized in that, The channel expansion device and at least one time-served device are included; The channel expansion device comprises: A signal input module for receiving a single PPS signal and a single RS232 data signal generated by a single time-served device; A PPS signal processing module configured with a source multi-channel driver for regenerating the single PPS signal into multiple PPS output signals with consistent physical characteristics; A signal output module for outputting the multiple PPS output signals; An RS232 signal processing module is used to regenerate the single RS232 signal into multiple RS232 output signals; The time-servicing device is used to receive one of the PPS output signals and the RS232 output signal output by the channel expansion device, and the time-servicing device comprises: a processor; a memory in which instructions executable by the processor are stored; The instructions, when executed, enable the processor to perform the local clock calibration method for the time-servicing device according to any one of claims 1-6.

10. The PPS and RS232 based time synchronization signal channel extension system according to claim 9, wherein, It comprises: a centralized RS232-TTL conversion channel and multiple independent TTL-RS232 drive channels, which are used to drive the upstream single RS232 signal into multiple independent RS232 outputs.

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