Synchronization signal processing method and artificial intelligence chip

Abstract

The invention provides a synchronization signal processing method and an artificial intelligence chip. The synchronization signal processing method comprises the following steps: receiving a synchronization signal reading request with a prompt sign sent by a first processing core; confirming that the synchronization signal reading request is a synchronization operation according to the prompt sign; determining that storage addresses in an effective state exist, and determining whether a target storage address matched with the target program segment identifier and the target synchronous address identifier exists in the storage addresses in the effective state; if the target storage address exists, when the synchronization value in the target storage address is the same as the target synchronization value, returning a synchronization success message to the first processing core, and adjusting readable times in the target storage address; the time spent on reading the synchronizing signal is greatly shortened, the time is saved, the delay is reduced, and the processing efficiency of the processing core is improved; moreover, the bandwidth can be saved, the bandwidth waste is avoided, and the working efficiency of the whole system is improved.

Description

Technical Field

[0001] This application relates to the field of artificial intelligence chip technology, and in particular to a method for processing synchronization signals and an artificial intelligence chip. Background Technology

[0002] Currently, to improve parallelism and maximize computational throughput and data exchange efficiency, artificial intelligence chips generally employ an architecture where multiple processing cores are connected to a network-on-chip (NoC) via a crossbar, and then connected to memory or cache units via the NoC. In this architecture, when multiple processing cores need to synchronize, some cores must perform write barrier operations to ensure data has been written to memory or cache units and to write a synchronization signal. Other cores can only begin reading the data written to memory or cache units after receiving the synchronization signal. However, this overall process is time-consuming, hindering the support for large-scale parallel computing and failing to fully utilize the computational potential of the multi-core architecture. Summary of the Invention

[0003] This application provides a method for processing synchronization signals and an artificial intelligence chip to reduce the time spent reading or writing synchronization signals, thereby saving time, reducing latency, and improving the processing efficiency of the processing core. In a first aspect, embodiments of this application provide a method for processing a synchronization signal, comprising: Receive a synchronization signal read request with a prompt flag sent by the first processing core. The synchronization signal read request carries the target program segment identifier, the target synchronization address identifier, and the target synchronization value. The prompt flag confirms that the synchronization signal reading request is a synchronization operation; Confirm the existence of valid storage addresses, and determine from the valid storage addresses whether there is a target storage address that matches the target program segment identifier and the target synchronization address identifier; If the target storage address exists, when the synchronization value in the target storage address is the same as the target synchronization value, a synchronization success message is returned to the first processing core, and the number of readable values ​​in the target storage address is adjusted; wherein, the synchronization value represents the number of second processing cores that have completed data writing, and the number of readable values ​​is the number of readable values ​​of the synchronization value.

[0004] Optionally, when the number of readable accesses is adjusted to 0, the target storage address is set to an invalid state.

[0005] Optionally, when the synchronization value in the target storage address is different from the target synchronization value, a synchronization failure message is returned to the first processing core.

[0006] Optionally, it further includes: if the target storage address does not exist, distributing the synchronization signal read request to the data scheduling unit, and the synchronization signal read request being distributed to the storage unit through the data scheduling unit.

[0007] Optionally, it further includes: receiving a synchronization signal write request with a prompt flag sent by the second processing core, wherein the synchronization signal write request carries a program segment identifier, a synchronization address identifier, the synchronization value, and the number of times it can be read; Based on the prompt flag, the synchronization signal write request is confirmed to be a synchronization operation. An invalid storage address is allocated to the synchronization signal write request. The program segment identifier, the synchronization address identifier, the synchronization value, and the number of readable items in the synchronization signal write request are written to the storage address, and the storage address is adjusted from an invalid state to an valid state.

[0008] Optionally, it further includes: simultaneously distributing the synchronization signal write request to the data scheduling unit, wherein the synchronization signal write request is distributed to the storage unit through the data scheduling unit.

[0009] Optionally, it further includes: receiving a clear instruction for the target program segment identifier, determining from the valid storage addresses whether there is a target storage address that matches the target program segment identifier, and if so, adjusting the target storage address to an invalid state.

[0010] Secondly, embodiments of this application provide an artificial intelligence chip, including: multiple processing cores, a data distribution unit, a data scheduling unit, and a storage unit; The plurality of processing cores includes: a first processing core; the first processing core is configured to read target data from the storage unit through the data distribution unit and the data scheduling unit, and to send a synchronization signal reading request with a prompt flag before reading the target data; The data distribution unit is configured to confirm that the synchronization signal read request is a synchronization operation based on the prompt flag, and to confirm that there is a valid storage address. From the valid storage addresses, it is determined whether there is a target storage address that matches the target program segment identifier and the target synchronization address identifier. The data distribution unit is further configured to confirm the existence of the target storage address, and when the synchronization value in the target storage address is the same as the target synchronization value, return a synchronization success message to the first processing core and adjust the number of readable values ​​in the target storage address.

[0011] Optionally, the data distribution unit is further configured to adjust the target storage address to an invalid state when it is confirmed that the number of readable accesses is adjusted to 0.

[0012] Optionally, the data distribution unit is further configured to return a synchronization failure message to the first processing core when it confirms that the synchronization value in the target storage address is different from the target synchronization value.

[0013] Optionally, the plurality of processing cores further includes: a second processing core; the second processing core is configured to write the target data into the storage unit through the data distribution unit and the data scheduling unit, and after confirming that the target data has been written, send a synchronization signal with a prompting flag to request a write operation; The data distribution unit includes a synchronization signal caching module, which includes multiple rows of storage addresses configured to store the synchronization signal write request. The data distribution unit is further configured to confirm that the synchronization signal write request is a synchronization operation according to the prompt flag, allocate an invalid storage address to the synchronization signal write request, write the program segment identifier, the synchronization address identifier, the synchronization value and the number of reads in the synchronization signal write request to the storage address, and adjust the storage address from an invalid state to an valid state.

[0014] Thirdly, embodiments of this application provide a computer device, including a memory, an artificial intelligence chip, and a computer program stored in the memory and executable on the artificial intelligence chip, wherein the artificial intelligence chip executes the computer program to implement the steps of the above-described instruction synchronization method.

[0015] This application embodiment achieves the writing and reading of target data through the cooperation of multiple processing cores, a data distribution unit, a data scheduling unit, and a storage unit. The data distribution unit confirms the synchronization signal read request as a synchronization operation based on a prompt flag, and verifies the existence of a valid storage address. It then determines from the valid storage addresses whether a target storage address exists that matches the target program segment identifier and the target synchronization address identifier. Upon confirming the existence of a target storage address and determining that the synchronization value in the target storage address is the same as the target synchronization value, the data distribution unit returns a synchronization success message to the first processing core and adjusts the readable count in the target storage address. In other words, by determining whether the synchronization value matches the target synchronization value within the data distribution unit, synchronous processing by multiple processing cores is achieved, and the path for the first processing core to read the synchronization signal is shortened. The first processing core can directly read the synchronization signal from the data distribution unit, avoiding the need for each first processing core to read the synchronization signal from the storage unit through the data scheduling unit. This saves time, reduces the latency of synchronization signal transmission, and improves the processing efficiency of the processing cores. Furthermore, since the data distribution unit confirms that the synchronization signal read request is a synchronization operation based on the prompt flag, it can ensure that it does not need to access the data scheduling unit and the storage unit again, but can directly access the storage address in the data distribution unit. This can save the bandwidth of the data scheduling unit and the storage unit, avoid bandwidth waste, and thus improve the working efficiency of the entire system. Attached Figure Description

[0016] Figure 1 This application provides schematic diagrams of the structures of some artificial intelligence chips in its embodiments. Figure 2 Schematic diagrams of other artificial intelligence chips provided in the embodiments of this application; Figure 3 This application provides further structural schematic diagrams of some artificial intelligence chips in its embodiments; Figure 4 This application provides further structural schematic diagrams of some artificial intelligence chips in its embodiments; Figure 5 A flowchart illustrating some synchronization signal processing methods provided in the embodiments of this application; Figure 6 A flowchart illustrating other methods for processing synchronization signals provided in embodiments of this application; Figure 7 This application provides further structural schematic diagrams of some artificial intelligence chips in its embodiments; Figure 8 The diagram shows the structure of some computer devices provided in the embodiments of this application. Detailed Implementation

[0017] To make the objectives, technical solutions, and advantages of the embodiments of this application clearer, the technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this application. Furthermore, the embodiments and features in the embodiments of this application can be combined with each other without conflict. All other embodiments obtained by those skilled in the art based on the described embodiments of this application without creative effort are within the scope of protection of this application.

[0018] Unless otherwise defined, the technical or scientific terms used in this application shall have the ordinary meaning understood by one of ordinary skill in the art to which this application pertains. The terms "first," "second," and similar terms used in this application do not indicate any order, quantity, or importance, but are merely used to distinguish different components. Terms such as "comprising" or "including" mean that the element or object preceding the word encompasses the elements or objects listed following the word and their equivalents, without excluding other elements or objects. Furthermore, in the description of the embodiments in this application, unless otherwise stated, "a plurality of" means two or more.

[0019] Under related technologies, such as Figure 1 As shown, to improve parallelism and maximize computational throughput and data exchange efficiency, current AI chips typically employ an architecture where multiple processing cores are connected to a network-on-chip (NoC) via crossbars, and connected to memory units or cache units via the same network. For example, when processing cores 1 and 2 jointly execute a program instruction, processing core 1 will act as the producer, and processing core 2 as the consumer. After processing core 1 completes the data calculation, it needs to write the data to the shared memory unit or cache unit through the crossbar switch and on-chip network, and perform a write barrier operation to ensure that the data is visible to processing core 2. After waiting to receive the response of all write operations and confirming that the data has been persistently written to the memory unit or cache unit, it also needs to write the synchronization signal to the memory unit or cache unit through the crossbar switch and on-chip network to indicate that the data is ready. Similarly, processing core 2 also needs to poll the synchronization signal from the memory cell or cache cell via the crossbar switch and on-chip network. Once it is determined that the synchronization signal is set, it begins to read the data written by processing core 1 to the shared memory cell or cache cell. However, the above solution has at least the following problems: First, the process of processing core 1 writing the synchronization signal to the memory unit or cache unit M through the crossbar switch and on-chip network, and processing core 2 polling the synchronization signal from the memory unit or cache unit through the crossbar switch and on-chip network, both take a long time. This results in a delay in processing core 2 reading the synchronization signal written by processing core 1, which in turn reduces the processing efficiency of the processing core. Second, the need for core 2 to repeatedly read synchronization signals will frequently occupy the bandwidth of the on-chip network, which may affect the memory access requests of other processing cores; and in cross-chip read scenarios, it may occupy a large amount of bandwidth between artificial intelligence chips, resulting in bandwidth waste and affecting the working efficiency of the entire system.

[0020] In view of the above problems, this application provides an artificial intelligence chip 100, such as Figure 2 As shown, it specifically includes: multiple processing cores 10, a data distribution unit 20, a data scheduling unit 30, and a storage unit 40; The multiple processing cores 10 include: first processing cores 101 and 102; the first processing cores 101 and 102 are configured to read target data from storage unit 40 through data distribution unit 20 and data scheduling unit 30, and to send a synchronization signal with prompt flag to read the target data before reading the target data. The data distribution unit 20 is configured to confirm that the synchronization signal read request is a synchronization operation based on the prompt flag, and to confirm that there is a valid storage address. From the valid storage addresses, it determines whether there is a target storage address that matches the target program segment identifier and the target synchronization address identifier. The data distribution unit 20 is also configured to confirm the existence of a target storage address, and when it determines that the synchronization value in the target storage address is the same as the target synchronization value, return a synchronization success message to the first processing cores 101 and 102, and adjust the number of readable values ​​in the target storage address.

[0021] This application embodiment achieves the writing and reading of target data through the cooperation of multiple processing cores, a data distribution unit, a data scheduling unit, and a storage unit. The data distribution unit confirms the synchronization signal read request as a synchronization operation based on a prompt flag, and verifies the existence of a valid storage address. It then determines from the valid storage addresses whether a target storage address exists that matches the target program segment identifier and the target synchronization address identifier. Upon confirming the existence of a target storage address and determining that the synchronization value in the target storage address is the same as the target synchronization value, the data distribution unit returns a synchronization success message to the first processing core and adjusts the readable count in the target storage address. In other words, by determining whether the synchronization value matches the target synchronization value within the data distribution unit, synchronous processing by multiple processing cores is achieved, and the path for the first processing core to read the synchronization signal is shortened. The first processing core can directly read the synchronization signal from the data distribution unit, avoiding the need for each first processing core to read the synchronization signal from the storage unit through the data scheduling unit. This saves time, reduces the latency of synchronization signal transmission, and improves the processing efficiency of the processing cores. Furthermore, since the data distribution unit confirms that the synchronization signal read request is a synchronization operation based on the prompt flag, it can ensure that it does not need to access the data scheduling unit and the storage unit again, but can directly access the storage address in the data distribution unit. This can save the bandwidth of the data scheduling unit and the storage unit, avoid bandwidth waste, and thus improve the working efficiency of the entire system.

[0022] For example, the artificial intelligence chip 100 may include a graphics processing unit (GPU), a general-purpose graphics processing unit (GPGPU), a domain-specific architecture (DSA), etc.

[0023] For example, the processing core 10 is highly specialized for artificial intelligence chips and typically has the ability to perform AI-related calculations, such as matrix multiplication and convolution operations. These operations are common computational operations in artificial intelligence models, and a single processing core can achieve extremely high computational density.

[0024] For example, the data distribution unit 20 includes a crossbar, which provides the shortest data path and extremely high internal bandwidth for multiple processing cores, memory controllers, and other units in the artificial intelligence chip, and is key to achieving high-speed data sharing between cores; the crossbar provides non-blocking full connectivity between the ports it connects to. This means that at any given time, as long as the input and output ports are idle, multiple data streams can pass through the crossbar simultaneously and in parallel without waiting.

[0025] For example, the data scheduling unit 30 can be a network-on-chip (NoC). The network-on-chip connects all components on the entire artificial intelligence chip (including the processing core cluster, high-bandwidth memory controller, off-chip interfaces, etc.) to form a "system-on-chip network". When the number of processing cores is very large, a fully connected cross switch becomes physically infeasible (due to wiring complexity and power consumption). In this case, a network-on-chip (such as Mesh, Torus, Fat-Tree, etc.) provides a more scalable interconnection solution.

[0026] For example, storage unit 40 can be a memory unit or a cache unit, both used for storing data. The specific choice between a memory unit and a cache unit can be adjusted according to design requirements and is not specifically limited here.

[0027] In this embodiment of the application, the data distribution unit 20 is also configured to adjust the target storage address to an invalid state when it is confirmed that the number of readable times has been adjusted to 0.

[0028] In this embodiment of the application, the data distribution unit 20 is further configured to return a synchronization failure message to the first processing cores 101 and 102 when it is confirmed that the synchronization value in the target storage address is different from the target synchronization value.

[0029] In the embodiments of this application, such as Figure 2 As shown, the multiple processing cores 10 also include: second processing cores 103 and 104; the second processing cores 103 and 104 are configured to write target data into storage unit 40 through data distribution unit 20 and data scheduling unit 30, and after confirming the writing of target data, send a synchronization signal with prompt flag to write the request.

[0030] In the embodiments of this application, such as Figure 3 As shown, the data distribution unit 20 includes a synchronization signal buffer module 201, which includes multiple storage addresses 2010. The storage addresses 2010 are configured to store synchronization signal write requests. The data distribution unit 20 is also configured to confirm that the synchronization signal write request is a synchronization operation according to the prompt flag, allocate an invalid state storage address 2010 to the synchronization signal write request, write the program segment identifier (kernel id), synchronization address identifier (addr), synchronization value (value), and number of reads in the synchronization signal write request to the storage address 2010, and adjust the storage address 2010 from an invalid state to an valid state.

[0031] This application shortens the path for the second processing core to write the synchronization signal by storing the synchronization signal write request in the storage address of the data distribution unit. That is, the second processing core can directly write the synchronization signal in the data distribution unit without having to write the synchronization signal to the storage unit through the data scheduling unit, which saves time, reduces the delay in the transmission of the synchronization signal, and improves the processing efficiency of the processing core.

[0032] Furthermore, since the storage address is only used to store synchronization signal write requests, the area overhead is very small and it will not occupy much space.

[0033] For example, the kernel ID is used to distinguish different computing tasks; the synchronization address ID (addr) indicates the location of the data that the second processing core needs to write to the storage unit; the synchronization value (value) indicates the value to be written or added; and the number of reads indicates how many first processing cores need to read the synchronization signal.

[0034] For example, such as Figure 3 As shown, each storage address 2010 is configured with a valid bit; different values ​​of the valid bit represent different meanings; for example, when the valid bit is 1, it means that the storage address 2010 is in a valid state and cannot be used to store a synchronization signal write request; when the valid bit is 0, it means that the storage address 2010 is in an invalid state and can be used to store a synchronization signal write request.

[0035] In the embodiments of this application, such as Figure 4 As shown, it also includes: processor 50, which is used to send the clear instruction of the target program segment identifier to the data distribution unit 20; The data distribution unit 20 can determine whether there is a target storage address that matches the target program segment identifier from the storage addresses that are in a valid state, based on the clear instruction of the target program segment identifier. If there is, the target storage address is adjusted to an invalid state.

[0036] In addition to the structures described above, the artificial intelligence chip in this application may also include other structures, and this application does not specifically limit such structures.

[0037] The following will combine, for example, Figures 2 to 4 The diagram shows the architecture of the artificial intelligence chip. A detailed explanation of the flow of a synchronization signal processing method provided in this application can be found in the attached diagram. Figure 5 This method is executed by a data distribution unit in an artificial intelligence chip, and includes the following steps: S100: Receive a synchronization signal reading request with a prompt flag sent by the first processing core; Specifically, the first processing core first processes the synchronization signal read request, sets a prompt flag for the synchronization signal read request, and then sends a synchronization signal read request carrying the target program segment identifier, the target synchronization address identifier, and the target synchronization value.

[0038] S200: Confirm the synchronization signal reading request as a synchronization operation based on the prompt indicator; Specifically, the data distribution unit receives a synchronization signal read request and detects that the synchronization signal read request has a prompt flag, thereby determining that the synchronization signal read request sent by the first processing core is a synchronization operation. Then, the data distribution unit first searches for a valid storage address in the multi-line storage address in the synchronization signal buffer module, that is, determines the value of the valid bit of the multi-line storage address. When the valid bit is detected as 1, the storage address is determined to be in a valid state; when the valid bit is detected as 0, the storage address is determined to be in an invalid state.

[0039] S300: Confirm the existence of a valid storage address, and determine from the valid storage addresses whether there is a target storage address that matches the target program segment identifier and the target synchronization address identifier; Specifically, when the data distribution unit determines that there is a valid storage address, that is, when it determines that there is a storage address with a valid bit of 1, it means that a second processing core has completed the data writing operation. However, these second processing cores that have completed the data writing operation may not be the ones that the first processing core needs to synchronize. Furthermore, there may be multiple rows of valid storage addresses. In this case, the data distribution unit needs to further determine the program segment identifier and synchronization address identifier in each row of storage addresses. If it is determined that the program segment identifier and synchronization address identifier in a certain row of storage addresses can match the target program segment identifier and target synchronization address identifier in the synchronization signal read request, then the data distribution unit determines that row of storage addresses as the target storage address. In some embodiments, if no target storage address exists, the synchronization signal read request is distributed to the data scheduling unit, and the synchronization signal read request is written to the storage unit through the data scheduling unit.

[0040] Specifically, if the data distribution unit determines that there is no valid storage address, it determines that there is no target storage address, indicating that none of the second processing cores has completed the data writing operation in the storage unit; or, if the data distribution unit determines that there is a valid storage address, but fails to find a storage address that matches both the target program segment identifier and the target synchronization address identifier in the synchronization signal read request, it determines that there is no target storage address, indicating that the synchronization signal to be read by the first processing core has not been written to the storage address, but rather to the storage unit; then the data distribution unit needs to distribute the synchronization signal read request to the data scheduling unit, which in turn distributes the synchronization signal read request to the storage unit, allowing the data scheduling unit to further determine whether the synchronization signal required by the second processing core exists in the storage unit. This setting ensures the accuracy of the synchronization signal reading and avoids the situation where the storage address in the data distribution unit is incorrect, resulting in the inability to store the synchronization signal and thus storing the synchronization signal in the storage unit.

[0041] S400. If a target storage address exists, when the synchronization value in the target storage address is the same as the target synchronization value, return a synchronization success message to the first processing core and adjust the number of readable values ​​in the target storage address. Specifically, the synchronization value represents the number of second processing cores that have completed data writing, and the number of readable counts is the number of readable counts of the synchronization value; Specifically, when the data distribution unit determines that a target storage address exists, it further determines the synchronization value in the target storage address and whether the synchronization value in the target storage address is the same as the target synchronization value in the synchronization signal read request. If the data distribution unit determines that the synchronization value in the target storage address is the same as the target synchronization value, it means that all second processing cores have completed the data writing operation in the storage unit. Therefore, the data distribution unit returns a synchronization success message to the first processing core. The data distribution unit also needs to adjust the number of readable items in the target storage address, for example, by performing an atomic decrement operation on the number of readable items in the target storage address. In some embodiments, when the synchronization value in the target storage address is different from the target synchronization value, a synchronization failure message is returned to the first processing core; Specifically, if the data distribution unit determines that the synchronization value in the target storage address is different from the target synchronization value, it means that some of the second processing cores have not completed the data writing operation in the storage unit. Therefore, the data distribution unit returns a synchronization failure message to the first processing core.

[0042] In this embodiment of the application, after the first processing core sends a synchronization signal read request with a prompt flag, the data distribution unit can determine that the synchronization signal read request is a synchronization operation based on the prompt flag. Thus, it can directly determine whether the target storage address exists in the storage address and confirm whether the synchronization is successful through the synchronization signal in the target storage address, instead of confirming whether the synchronization is successful through the synchronization signal in the storage unit. This greatly reduces the time spent reading the synchronization signal, which can save time, reduce latency, and improve the processing efficiency of the processing core. Furthermore, it can minimize the need to access the data scheduling unit and storage unit multiple times, thereby saving bandwidth in the data scheduling unit and storage unit, avoiding bandwidth waste, and thus improving the overall system efficiency.

[0043] In some embodiments, when the number of reads is adjusted to 0, the target storage address is adjusted to an invalid state.

[0044] Specifically, when the data distribution unit determines that the number of readable times in the storage address is 0, it means that the first processing core of all synchronization signals to be read has completed the synchronization signal reading operation, that is, all synchronization is successful. Then the data distribution unit automatically adjusts the target storage address to an invalid state, that is, adjusts the value of the valid bit in the target storage address to 0, and automatically releases the target storage address to facilitate subsequent storage operations.

[0045] In some embodiments, a clear instruction for the target program segment identifier is received, and it is determined from the valid storage addresses whether there is a target storage address that matches the target program segment identifier. If there is, the target storage address is adjusted to an invalid state.

[0046] Specifically, the processor sends a clear instruction for the target program segment identifier to the data distribution unit. The data distribution unit receives the clear instruction and, based on it, determines from the valid memory addresses whether a target memory address matching the target program segment identifier exists. If such an address exists, it sets the target memory address to an invalid state. This configuration ensures that after a program segment has finished executing and synchronization is successful, errors in the data distribution unit that might prevent the automatic release of the target memory address are avoided. Therefore, by having the processor issue a clear instruction for the target program segment identifier, the data distribution unit can release the target memory address, further ensuring the accuracy of the memory address status within the data distribution unit.

[0047] In some embodiments, such as Figure 6 As shown, the method also includes: S500: Receives a write request with a prompt flag sent by the second processing core; Specifically, the second processing core first processes the synchronization signal write request, sets a prompt flag for the synchronization signal write request, and then sends a synchronization signal write request carrying the program segment identifier, synchronization address identifier, synchronization value, and number of reads. Specifically, synchronization values ​​can be achieved by setting a synchronization value or by atomic addition. For example, when there is only one second processing core, the synchronization value can be set in the memory address, i.e., directly writing the synchronization value as 1. When there are three second processing cores, after the first second processing core finishes writing data to the memory unit, it can perform an atomic addition operation in the synchronization signal buffer to increase the synchronization value from 0 to 1. After the second second processing core finishes writing data to the memory unit, it can perform an atomic addition operation in the synchronization signal buffer to increase the synchronization value from 1 to 2. After the third second processing core finishes writing data to the memory unit, it can perform an atomic addition operation in the synchronization signal buffer to increase the synchronization value from 2 to 3.

[0048] S600: Confirm that the synchronization signal write request is a synchronization operation according to the prompt flag, allocate an invalid storage address to the synchronization signal write request, write the program segment identifier, synchronization address identifier, synchronization value and read count in the synchronization signal write request to the storage address, and adjust the storage address from invalid to valid. Specifically, the data distribution unit receives a synchronization signal write request and detects that the synchronization signal write request has a prompt flag, thus determining that the synchronization signal write request sent by the second processing core is a synchronization operation. The data distribution unit first searches for an invalid storage address in the multiple rows of storage addresses in the synchronization signal buffer module. If an invalid storage address exists, the data distribution unit randomly assigns an invalid storage address to the synchronization signal write request, writes the program segment identifier, synchronization address identifier, synchronization value, and number of reads in the synchronization signal write request to the storage address, and adjusts the storage address from an invalid state to a valid state, that is, adjusts the valid bit value of the storage address to 1. Specifically, if there is no valid storage address, the data distribution unit cannot allocate an invalid storage address for the synchronization signal write request. In this case, the data distribution unit sends the synchronization signal write request to the data scheduling unit, which then distributes the synchronization signal write request to the storage unit, thereby storing the synchronization signal write request in the storage unit. This ensures that the synchronization signal write request will not be discarded when there is no invalid storage address, thus avoiding synchronization failure.

[0049] In some embodiments, a synchronization signal write request is simultaneously distributed to a data scheduling unit, and the synchronization signal write request is distributed to a storage unit through the data scheduling unit.

[0050] Specifically, while the data distribution unit assigns the synchronization signal to the storage address in the invalid state, it also needs to distribute the synchronization signal to the data scheduling unit. The synchronization signal to the storage unit is then distributed to the storage unit through the data scheduling unit. This configuration allows the synchronization signal to be executed in the storage unit, avoiding the situation where storage fails at the storage address, and thus preventing some synchronization operations from being missing.

[0051] For example, such as Figure 7 As shown, the GPGPU configuration includes: a first processing core 101, a first processing core 102, a second processing core 103, a second processing core 104, a data distribution unit 20, a data scheduling unit 30, and a storage unit 40. First, when neither the second processing core 103 nor the second processing core 104 has completed writing the target data into the storage unit 40 through the data distribution unit 20 and the data scheduling unit 30, the multiple storage addresses 2010 in the synchronization signal cache module 201 are not the target storage addresses; both the first processing core 101 and the first processing core 102 set a prompt flag for the synchronization signal read request, and the first processing core 101 and the first processing core 102 send the synchronization signal read request carrying the target program segment identifier, the target synchronization address identifier, and the target synchronization value to the data distribution unit 20, where the target synchronization value is 2; if the data distribution unit 20 does not find the target storage address, it routes the synchronization signal read request to the data scheduling unit 30, and the data scheduling unit 30 then routes the synchronization signal read request to the storage unit 40. If there is no synchronization signal in the storage unit 40, it returns a synchronization failure message to the first processing core 101 and the first processing core 102; Secondly, when the second processing core 103 has completed writing the target data into the storage unit 40 through the data distribution unit 20 and the data scheduling unit 30, but the second processing core 104 has not completed writing the target data into the storage unit 40 through the data distribution unit 20 and the data scheduling unit 30, the second processing core 103 sets a prompt flag for the synchronization signal write request, and sends the synchronization signal write request carrying the program segment identifier, synchronization address identifier, synchronization value, and number of readable counts to the data distribution unit 20; the data distribution unit 20 randomly assigns the invalid state storage address 2010-1 in the synchronization signal cache module 201. A synchronization signal write request is allocated. At this time, the value of the valid bit in storage address 2010-1 is 0. After allocation, the synchronization signal write request sent by the second processing core 103 is written to storage address 2010-1, and storage address 2010-1 is adjusted to a valid state, that is, the value of the valid bit in storage address 2010-1 is set to 1. Here, storage address 2010-1 is the target storage address. The synchronization signal write request sent by the second processing core 103 is written to storage address 2010-1. At this time, the valid bit in storage address 2010-1 is 1, the synchronization value is adjusted to 1 through atomic addition operation, and the number of reads is 2. Both the first processing core 101 and the first processing core 102 set a prompt flag for the synchronization signal reading request. The first processing core 101 and the first processing core 102 send the synchronization signal reading request carrying the target program segment identifier, the target synchronization address identifier, and the target synchronization value to the data distribution unit 20, wherein the target synchronization value is 2. The data distribution unit 20 determines that the storage address 2010-1 is the target storage address by matching the target program segment identifier and the target synchronization address identifier, and determines that the synchronization value 1 in the storage address 2010-1 is not the same as the target synchronization value 2 in the synchronization signal reading request. Then, the data distribution unit 20 returns a synchronization failure message to the first processing core 101 and the first processing core 102. Finally, when both the second processing core 103 and the second processing core 104 have completed writing the target data into the storage unit 40 through the data distribution unit 20 and the data scheduling unit 30, the second processing core 104 sets a prompt flag on the synchronization signal write request. The second processing core 104 sends the synchronization signal write request carrying the program segment identifier, synchronization address identifier, synchronization value, and number of reads to the data distribution unit 20. The data distribution unit 20 finds the same program segment identifier and synchronization address identifier in the storage address 2010-1 of the synchronization signal cache module 201 based on the program segment identifier and synchronization address identifier in the synchronization signal write request sent by the second processing core 104. Then, it writes the synchronization signal write request sent by the second processing core 104 into the storage address 2010-1. At this time, the valid bit in the storage address 2010-1 is 1, the synchronization value is adjusted from 1 to 2 through an atomic addition operation, and the number of reads is 2. The first processing core 101 first sets a prompt flag on the synchronization signal read request. The first processing core 101 sends the synchronization signal read request carrying the target program segment identifier, the target synchronization address identifier, and the target synchronization value to the data distribution unit 20, where the target synchronization value is 2. The data distribution unit 20 determines that the storage address 2010-1 is the target storage address by matching the target program segment identifier and the target synchronization address identifier. If the synchronization value 2 in the storage address 2010-1 is the same as the target synchronization value 2 in the synchronization signal read request, the data distribution unit 20 returns a synchronization success message to the first processing core 101 and decrements the number of readable items 2 in the storage address 2010-1 by 1, so the number of readable items in the storage address 2010-1 is 1. After receiving the synchronization success message, the first processing core 101 can perform subsequent operations, such as reading the data written to the storage unit 40 by the second processing core 103 and the second processing core 104 through the data distribution unit 20 and the data scheduling unit 30. The first processing core 102 first sets a prompt flag on the synchronization signal read request. The first processing core 102 then sends the synchronization signal read request, carrying the target program segment identifier, the target synchronization address identifier, and the target synchronization value, to the data distribution unit 20, where the target synchronization value is 2. The data distribution unit 20 determines that storage address 2010-1 is the target storage address by matching the target program segment identifier and the target synchronization address identifier. If the synchronization value 2 in storage address 2010-1 is the same as the target synchronization value 2 in the synchronization signal read request, the data distribution unit 20 returns a synchronization success message. The message is sent to the first processing core 102, and the number of readable bits in storage address 2010-1 is decremented by 1, so the number of readable bits in storage address 2010-1 is 0. Storage address 2010-1 is then set to an invalid state, that is, the valid bits in storage address 2010-1 are changed from 1 to 0. After receiving the synchronization success message, the first processing core 102 can perform subsequent operations, such as reading the data written to storage unit 40 by the second processing core 103 and the second processing core 104 through data distribution unit 20 and data scheduling unit 30. Once it is determined that both the first processing core 101 and the first processing core 102 have completed reading the data written by the second processing core 103 and the second processing core 104 to the storage unit 40 through the data distribution unit 20 and the data scheduling unit 30, the processor 50 sends a clear instruction for the target program segment identifier to the data distribution unit 20. The data distribution unit 20 receives the clear instruction for the target program segment identifier and, based on the clear instruction, determines from the valid storage addresses 2010 whether there is a target storage address that matches the target program segment identifier (e.g., storage address 2010-1 has not been adjusted to an invalid state). If there is, the data distribution unit 20 adjusts the target storage address (e.g., storage address 2010-1) to an invalid state.

[0052] In this embodiment of the application, after the first processing core sends a synchronization signal read request with a prompt flag, the data distribution unit can determine that the synchronization signal read request is a synchronization operation based on the prompt flag. Thus, it can directly determine whether the target storage address exists in the storage address and confirm whether the synchronization is successful through the synchronization signal in the target storage address, instead of confirming whether the synchronization is successful through the synchronization signal in the storage unit. This greatly reduces the time spent reading the synchronization signal, which can save time, reduce latency, and improve the processing efficiency of the processing core. Furthermore, it can minimize the need to access the data scheduling unit and storage unit multiple times, thereby saving bandwidth in the data scheduling unit and storage unit, avoiding bandwidth waste, and thus improving the overall system efficiency.

[0053] Based on the same technical concept, embodiments of this application provide a computer device, such as... Figure 8 As shown, it includes at least one artificial intelligence chip 100 and a memory 200 connected to at least one artificial intelligence chip 100. In this embodiment, the specific connection medium between the artificial intelligence chip 100 and the memory 200 is not limited. Figure 8 Taking the connection between the AI ​​chip 100 and the memory 200 via a bus as an example, the bus can be divided into address bus, data bus, control bus, etc.

[0054] In this embodiment of the application, the memory 200 stores instructions that can be executed by at least one artificial intelligence chip 100. By executing the instructions stored in the memory 200, at least one artificial intelligence chip 100 can perform the steps of the above-mentioned instruction synchronization method. Among them, the artificial intelligence chip 100 is the control center of the computer device. It can connect to various parts of the computer device through various interfaces and lines, and realize instruction synchronization by running or executing instructions stored in the memory 200 and calling data stored in the memory 200.

[0055] Optionally, the artificial intelligence chip 100 may include one or more processing units. The artificial intelligence chip 100 may integrate an application processor and a modem processor, wherein the application processor primarily handles the operating system, user interface, and applications, while the modem processor primarily handles wireless communication. It is understood that the modem processor may not be integrated into the artificial intelligence chip 100. In some embodiments, the artificial intelligence chip 100 and the memory 200 may be implemented on the same chip; in some embodiments, they may be implemented separately on independent chips.

[0056] The artificial intelligence chip 100 can be a general-purpose processor, such as a graphics processing unit (GPU), a general-purpose graphics processing unit (GPGPU), a digital signal processor, an application-specific integrated circuit (ASIC), a field-programmable gate array (FPGA), or other programmable logic devices, discrete gate or transistor logic devices, or discrete hardware components, capable of implementing or executing the methods, steps, and logic block diagrams disclosed in the embodiments of this application. The general-purpose processor can be a microprocessor or any conventional processor. The steps of the methods disclosed in the embodiments of this application can be directly manifested as being executed by a hardware processor, or executed by a combination of hardware and software modules within the processor.

[0057] Memory 200, as a non-volatile computer-readable storage medium, can be used to store non-volatile software programs, non-volatile computer-executable programs, and modules. Memory 200 may include at least one type of storage medium, such as flash memory, hard disk, multimedia card, card-type memory, random access memory (RAM), static random access memory (SRAM), programmable read-only memory (PROM), read-only memory (ROM), electrically erasable programmable read-only memory (EEPROM), magnetic storage, magnetic disk, optical disk, etc. Memory 200 can be any other medium capable of carrying or storing desired program code in the form of instructions or data structures and accessible by a computer device, but is not limited thereto. In the embodiments of this application, memory 200 may also be a circuit or any other device capable of implementing storage functions for storing program instructions and / or data.

[0058] Based on the same concept, embodiments of this application provide a computer-readable storage medium storing a computer program executable by a computer device, which, when run on the computer device, causes the computer device to execute the steps of the above-described instruction synchronization method.

[0059] Those skilled in the art will understand that embodiments of this application can be provided as methods or computer program products. Therefore, this application can take the form of a completely hardware embodiment, a completely software embodiment, or an embodiment combining software and hardware aspects. Furthermore, this application can take the form of a computer program product embodied on one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) containing computer-usable program code.

[0060] This application is described with reference to flowchart illustrations and / or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of this application. It will be understood that each block of the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, special-purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer apparatus or other programmable data processing apparatus, generate instructions for implementing the flowchart... Figure 1One or more processes and / or boxes Figure 1 A device that provides the functions specified in one or more boxes.

[0061] These computer program instructions may also be stored in a computer-readable storage medium that can direct a computer device or other programmable data processing device to function in a particular manner, such that the instructions stored in the computer-readable storage medium produce an article of manufacture including instruction means, which are implemented in a process Figure 1 One or more processes and / or boxes Figure 1 The function specified in one or more boxes.

[0062] These computer program instructions may also be loaded onto a computer device or other programmable data processing equipment to cause a series of operational steps to be performed on the computer device or other programmable equipment to produce a process implemented by the computer device, thereby providing instructions that execute on the computer device or other programmable equipment for implementing the process. Figure 1 One or more processes and / or boxes Figure 1 The steps of the function specified in one or more boxes.

[0063] Although preferred embodiments of this application have been described, those skilled in the art, upon learning the basic inventive concept, can make other changes and modifications to these embodiments. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments as well as all changes and modifications falling within the scope of this application.

[0064] Obviously, those skilled in the art can make various modifications and variations to this application without departing from the spirit and scope of this application. Therefore, if such modifications and variations fall within the scope of the claims of this application and their equivalents, this application also intends to include such modifications and variations.

Claims

1. A method of processing a synchronization signal, characterized by, Comprising: receiving a synchronization signal read request with a prompt flag sent by a first processing core, the synchronization signal read request carrying a target program segment identifier, a target synchronization address identifier and a target synchronization value; confirming that the synchronization signal read request is a synchronization operation according to the prompt flag; confirming that there is a storage address in a valid state, and determining whether there is a target storage address matching the target program segment identifier and the target synchronization address identifier from the storage address in the valid state; if there is the target storage address, returning a synchronization success message to the first processing core when the synchronization value in the target storage address is the same as the target synchronization value, and adjusting the number of readable times in the target storage address; wherein the synchronization value represents the number of second processing cores that have completed data writing, and the number of readable times is the number of readable times of the synchronization value.

2. The method of claim 1, wherein, When the number of readable times is adjusted to 0, the target storage address is adjusted to an invalid state.

3. The method of claim 1, wherein, When the synchronization value in the target storage address is different from the target synchronization value, a synchronization failure message is returned to the first processing core.

4. The method according to any one of claims 1 to 3, characterized in that, Further comprising: if there is no target storage address, distributing the synchronization signal read request to a data scheduling unit, and the synchronization signal read request is distributed to a storage unit through the data scheduling unit.

5. The method of claim 4, wherein, Further comprising: receiving a synchronization signal write request with a prompt flag sent by a second processing core, the synchronization signal write request carrying a program segment identifier, a synchronization address identifier, the synchronization value and the number of readable times; confirming that the synchronization signal write request is a synchronization operation according to the prompt flag, allocating an invalid storage address to the synchronization signal write request, writing the program segment identifier, the synchronization address identifier, the synchronization value and the number of readable times in the synchronization signal write request into the storage address, and adjusting the storage address from an invalid state to a valid state.

6. The method of claim 5, wherein, Further comprising: distributing the synchronization signal write request to the data scheduling unit at the same time, and the synchronization signal write request is distributed to the storage unit through the data scheduling unit.

7. The method according to any one of claims 1 to 3, wherein the method is performed in a single step. Further comprising: receiving a clear instruction of the target program segment identifier, determining whether there is a target storage address matching the target program segment identifier from the storage address in the valid state, and adjusting the target storage address to an invalid state if there is.

8. An artificial intelligence chip, characterized by, Comprising: a plurality of processing cores, a data distribution unit, a data scheduling unit and a storage unit; the plurality of processing cores include a first processing core; the first processing core is configured to read target data from the storage unit through the data distribution unit and the data scheduling unit, and send a synchronization signal read request with a prompt flag before reading the target data; wherein the synchronization signal read request carries a target program segment identifier, a target synchronization address identifier and a target synchronization value; The data distribution unit is configured to confirm, according to the prompt flag, that the synchronization signal reading request is a synchronization operation, and that there is a storage address in an active state, and determine whether there is a target storage address matching the target program segment identifier and the target synchronization address identifier in the storage address in the active state. The data distribution unit is further configured to confirm that there is the target storage address, determine that the synchronization value in the target storage address is the same as the target synchronization value, return a synchronization success message to the first processing core, and adjust the number of readable times in the target storage address.

9. The artificial intelligence chip of claim 8, wherein, The data distribution unit is further configured to confirm that the number of readable times is adjusted to 0, and adjust the target storage address to an invalid state.

10. The artificial intelligence chip of claim 8, wherein, The data distribution unit is further configured to confirm that the synchronization value in the target storage address is different from the target synchronization value, and return a synchronization failure message to the first processing core.

11. The artificial intelligence chip of any one of claims 8-10, wherein, The plurality of processing cores further include a second processing core, and the second processing core is configured to write the target data into the storage unit through the data distribution unit and the data scheduling unit, and send a synchronization signal writing request with a prompt flag after confirming that the target data is written. The data distribution unit includes a synchronization signal cache module, and the synchronization signal cache module includes a plurality of storage addresses, which are configured to store the synchronization signal writing request. The data distribution unit is further configured to confirm, according to the prompt flag, that the synchronization signal writing request is a synchronization operation, assign an invalid storage address to the synchronization signal writing request, write the program segment identifier, the synchronization address identifier, the synchronization value and the number of readable times in the synchronization signal writing request into the storage address, and adjust the storage address from the invalid state to the active state.

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