Reduced strain and stop layer for Si / SiGe EPI stacks

Abstract

The invention provides a semiconductor device and a manufacturing method thereof. A substrate is provided. At least one silicon layer is formed on top of a substrate. At least one silicon germanium layer is formed on top of the at least one silicon layer. The at least one silicon germanium layer includes at least one n-type dopant. A semiconductor device having at least one silicon layer and at least one silicon germanium layer is formed.

Description

TECHNICAL FIELD

[0001] This application claims priority to U.S. Provisional Patent Application No. 63 / 522,113 to Hao et al., filed June 20, 2023, entitled “Reduced Strain and Stop Layer for Si / SiGe EPI Stack,” the disclosure of which is hereby incorporated by reference in its entirety.

[0002] The present disclosure relates generally to semiconductor devices, and in particular to semiconductor devices employing heteroepitaxial structures and related processes that can reduce strain that can be caused by a mismatch in lattice elements. BACKGROUND

[0003] Epitaxial layer growth can represent crystal growth and / or material deposition, whereby a new crystalline layer can be formed using a predetermined orientation with respect to a crystalline seed layer, where the deposited film is referred to as an epitaxial layer. The orientation of the epitaxial layer and seed layer can be determined using the lattice orientation of each material. Epitaxial growth processes are used in the manufacture of semiconductors, where a semiconductor film is grown epitaxially on a substrate. Heteroepitaxial growth involves the epitaxial growth of materials that are different from each other. However, during such heteroepitaxial growth processes (e.g., using Si / SiGe films), strain can be introduced due to a mismatch in the lattice elements of the Si lattice and the Ge lattice. As a result, wafer bowing can occur. While for thin layer growth, wafer bowing can be managed using various known processes, this is not the case for thicker layers, where wafer bowing requires bow compensation. SUMMARY

[0004] In some implementations, the subject innovation is directed to a method for fabricating a semiconductor device. The method can include providing a substrate, forming at least one silicon layer on top of the substrate, forming at least one silicon germanium layer on top of the at least one silicon layer, where the at least one silicon germanium layer can include at least one n-type dopant, and forming a semiconductor device having the at least one silicon layer and the at least one silicon germanium layer.

[0005] In some implementations, the subject innovation can include one or more of the following optional features. The method can further include stacking a plurality of the at least one silicon germanium layer formed on top of the at least one silicon layer. The semiconductor device can include a stacked plurality of the at least one silicon germanium layer formed on top of the at least one silicon layer.

[0006] In some implementations, a thickness of the at least one silicon layer can be greater than a thickness of the at least one silicon germanium layer.

[0007] In some implementations, the method can also include forming at least one p-type doped region within the at least one silicon layer. The at least one p-type doped region can be disposed adjacent to the at least one silicon germanium layer. The method can further include stacking a plurality of the at least one silicon germanium layer formed on top of the at least one silicon layer. The at least one silicon layer can have at least one p-type doped region formed within the at least one silicon layer. The semiconductor device can include a stacked plurality of the at least one silicon germanium layer formed on top of the at least one silicon layer. One or more of the stacked plurality of the at least one silicon germanium layer formed on top of the at least one silicon layer can be configured to be adjacent to one or more p-type doped regions formed within a silicon layer adjacent to the one or more silicon germanium layers. The one or more p-type doped regions can include one or more p-type dopants. The one or more p-type dopants can include at least one of boron, carbon, boron and carbon, and any combination thereof.

[0008] In some implementations, the method can also include forming at least one tensile layer on a bottom of the at least one silicon layer. Forming the at least one tensile layer can include forming at least one n-type doped silicon layer on top of a substrate, forming at least one p-type stop layer on top of the n-type doped silicon layer, and removing at least a portion of the n-type doped silicon layer. The method can also include removing the substrate and reducing a germanium concentration in the silicon germanium layer, thereby reducing a curvature of the substrate.

[0009] In some implementations, a thickness of the at least one p-type stop layer can be less than a thickness of the at least one n-type doped silicon layer.

[0010] In some implementations, the n-type dopant can include at least one of phosphorous, arsenic, antimony, bismuth, lithium, and any combination thereof.

[0011] In some implementations, the subject matter is about a semiconductor device. The device can include a substrate, at least one silicon layer formed on top of the substrate, at least one silicon germanium layer formed on top of the at least one silicon layer, wherein the at least one silicon germanium layer can include at least one n-type dopant.

[0012] In some implementations, the device can also include a stacked plurality of the at least one silicon germanium layer formed on top of the at least one silicon layer. A thickness of the at least one silicon layer can be greater than a thickness of the at least one silicon germanium layer. The device can further include at least one p-type doped region formed within the at least one silicon layer, wherein the at least one p-type doped region can be disposed adjacent to the at least one silicon germanium layer. In some implementations, the device can include a stacked plurality of the at least one silicon germanium layer formed on top of the at least one silicon layer, wherein the at least one silicon layer can have at least one p-type doped region formed within the at least one silicon layer.

[0013] In some implementations, in a semiconductor device, one or more silicon germanium layers of a stacked plurality of at least one silicon germanium layer formed on top of at least one silicon layer can be adjacent to one or more p-type doped regions formed within a silicon layer adjacent to the one or more silicon germanium layers. The one or more p-type doped regions can include one or more p-type dopants including at least one of: boron, carbon, boron and carbon, and any combination thereof.

[0014] In some implementations, a semiconductor device can include at least one tensile layer formed on a bottom of at least one silicon layer. The at least one tensile layer can be formed by forming at least one n-type doped silicon layer on a top of a substrate, forming at least one p-type stop layer on a top of the n-type doped silicon layer, and removing at least a portion of the n-type doped silicon layer.

[0015] In some implementations, in a semiconductor device, a thickness of the at least one p-type stop layer can be less than a thickness of the at least one n-type doped silicon layer. The n-type dopant can include at least one of: phosphorous, arsenic, antimony, bismuth, lithium, and any combination thereof.

[0016] The details of one or more variations of the subject matter described herein are set forth in the accompanying drawings and the description below. Other features and advantages of the subject matter described herein will be apparent from the description and drawings, and from the claims. BRIEF DESCRIPTION OF DRAWINGS

[0017] The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate certain aspects of the subject matter disclosed herein and, together with the description, help explain some of the principles associated with the disclosed implementations. The drawings are schematic in nature and are not drawn to scale. In the drawings,

[0018] Figures la to lc FIGS. 1-3 respectively illustrate example semiconductor devices according to some implementations of the subject matter of the present application;

[0019] Figures 2a to 2b FIGS. 4-6 illustrate, according to some implementations of the subject matter of the present application, structures used during formation of a tensile layer for inclusion in a Figures la to lc FIG. 7 illustrates an example structure used during formation of a tensile layer in one or more semiconductor devices shown;

[0020] Figure 3 FIG. 8 illustrates an example process for forming a tensile layer according to some implementations of the subject matter of the present application; and

[0021] Figure 4 FIG. 9 illustrates an example process according to some implementations of the subject matter of the present application. DETAILED DESCRIPTION

[0022] To address these and potential other deficiencies in currently available solutions, one or more implementations of the inventive subject matter are directed to methods, systems, articles of manufacture, and the like, that can provide semiconductor devices using heteroepitaxial structures and associated processes that can reduce strain that can be caused by a mismatch in one or more lattice elements.

[0023] In some implementations, the inventive subject matter is directed to the ability to compensate for and / or reduce wafer bow in a semiconductor device that has been heteroepitaxially grown, such as for the purpose of producing a dynamic random-access memory (DRAM) device. A typical DRAM device can include alternating layers of silicon (Si) and silicon germanium (SiGe) that can be epitaxially grown from a crystalline silicon substrate. A mismatch can occur in the lattice between the Si and Ge, which can result in strain, which in turn can result in wafer bow. As noted above, such wafer bow is less of a problem in thin layers than in thick layers. To address this problem, compensation and / or reduction of the inventive subject matter can be performed during one or more stages of the heteroepitaxial growth process and / or after one or more stages and / or after the growth process is complete. Compensation can be performed via one or more of the following: adding n-type dopants in the SiGe layers, adding carbon and / or carbon boron on either side of the SiGe layers to be selectively etched, and / or adding a tensile Si layer to the front side prior to the memory stack epitaxy process. Each of these will be discussed in further detail below.

[0024] Adding n-type dopants to the SiGe layers can be helpful during the selective removal of the SiGe layers. In addition, this operation can result in a reduction of the Ge concentration in the SiGe layers, which can have a further benefit for reducing wafer bow. As a non-limiting example, the n-type dopants can be phosphorous, which has a smaller lattice constant. Thus, the combination of the added phosphorous and the resulting reduction in the Ge concentration in the SiGe layers can help reduce bow in the wafer. It can be appreciated that any other n-dopant material can be used.

[0025] Adding carbon and / or a combination of carbon and boron on one or both sides of the selectively etched SiGe layer can be configured to result in a reduction in the etch rate of Si that can be exposed during the selective etching process. In particular, using carbon and / or a carbon boron combination can help to increase the SiGe layer etch while reducing the Si layer etch. This in turn can also help to compensate for wafer bowing. The smaller lattice constant of carbon (e.g., less than the lattice constant of silicon) can be used to offset any lattice mismatch with germanium, which has a larger lattice constant. For example, the lattice constant of germanium is approximately 1.04 times the lattice constant of silicon, while the lattice constant of carbon is 0.66 times the lattice constant of silicon. For example, in a layer stack, carbon can be added to a silicon layer, resulting in a SiC layer. The silicon layer that receives the carbon can be, for example, approximately 15 nanometers (nm) thick, and the added carbon can have a concentration of 0.5%. Adding carbon to the silicon layer can be performed on one or both sides of a silicon germanium layer that is doped with an n-dopant (e.g., phosphorus (SiGe-Phos)), which is sandwiched between silicon layers in the stack. For example, the SiGe-Phos layer can have a thickness of 10 nm and a germanium concentration of 13%. The resulting combination can be configured to substantially completely compensate for the stress from the presence of germanium, and thus reduce wafer bowing. Further, as indicated above, boron and / or a carbon boron combination can be added to the silicon layers surrounding the SiGe-Phos layer instead of carbon. The concentration of the added element(s) can be selected based on the desired degree of reduction in wafer bowing, as well as, for example, the particular design specifications of any final product, layer thicknesses, layer arrangements, etc. It can be appreciated that the numerical examples provided above are for illustrative purposes only, and are not intended to limit the scope of the subject matter described herein.

[0026] Alternatively or in addition, one or more tensile silicon layers can be added to the front side prior to the memory stack epitaxy process. The tensile silicon layers can be doped with carbon, boron, phosphorus, and / or any combination thereof, and have a sufficient thickness to not only provide sufficient compensation but also prevent crystal defect relaxation. In one example, non-limiting implementation, a thick phosphorus-doped silicon epitaxial layer can be followed by a thin boron-doped epitaxial layer, which can be helpful during a later stage backside silicon removal process.

[0027] It should be noted that as used herein, a substrate can represent any substrate and / or material surface formed on a substrate on which film processing can be performed during a fabrication process. The substrate material can include, for example and without limitation, silicon, silicon oxide, strained silicon, silicon on insulator (SOI), carbon doped silicon oxides, amorphous silicon, doped silicon, germanium, gallium arsenide, glass, sapphire, and / or any other material such as metals, metal nitrides, metal alloys, and / or any other conductive material, etc. that can be specific to a particular implementation, application, use, etc. The substrate can also include a semiconductor wafer. The substrate can be exposed to one or more pretreatment processes such as grinding, etching, reducing, oxidizing, hydroxylating, annealing, UV curing, e-beam curing, and / or baking the substrate surface. The substrate surface and / or substrate can include an underlying layer such as, for example, an exposed surface of a deposited film / layer becomes the substrate surface when a film / layer and / or partial film / layer is deposited onto the substrate surface.

[0028] Figures la to lc Example semiconductor devices 100-120 in accordance with some implementations of the present subject matter are respectively illustrated. The devices 100-120 can be used to form dynamic random access memory (DRAM) devices and / or any other type of memory device. The devices 100-120 can be configured to include a plurality of stacked layers and / or groups of layers that can be arranged directly on top of one another and / or side-by-side. For ease of illustration, Figures la to lc Only a limited number of such layers are shown. It can be appreciated that any number of layers can be stacked directly on top of one another. As used herein, the term "on" as used with respect to a film and / or layer of a film can include a film and / or layer arranged directly on a surface, and / or on one or more underlying layers between the film and / or layer and the surface.

[0029] A layer can represent a single crystalline layer of a material and / or a plurality of crystalline layers of the same material that, when combined, can form a single crystalline layer. The devices 100-120 can include, for example, a plurality of alternating silicon (Si) and silicon germanium (SiGe) layers, where a thickness or height of each Si layer can be greater than a thickness or height of a SiGe layer. Alternatively or additionally, at least one Si layer can have a thickness or height that can be less than a thickness or height of at least one SiGe layer. It can be appreciated that any combination of thicknesses / heights of layers is possible.

[0030] Additionally, as described herein, one or more SiGe and / or Si layers of the devices 100-120 can be doped with and / or include at least one dopant. Some non-limiting examples of dopants can include carbon, boron, phosphorus, oxygen, nitrogen, and / or any other type of dopant and / or any combination thereof. Further, the devices 100-120 can be configured to include any combination of doped and undoped Si layers and / or doped SiGe layers. For example, a doped Si layer can be disposed adjacent to and / or on each side of a doped and / or undoped SiGe layer. Alternatively or additionally, a doped SiGe layer can be disposed adjacent to and / or on each side of a doped and / or undoped Si layer. Each doped and / or undoped layer can have a respective thickness and / or height, which can be selected according to design requirements and / or characteristics of the devices 100-120. Further, each doped layer can have a particular desired doping concentration (e.g., of one or more dopants), which can again be selected according to particular requirements / characteristics of the devices 100-120. The doping concentration can be configured to be uniform throughout the layer stack. Alternatively or additionally, the doping concentration can be non-uniform and can vary between doped layers in the stack, e.g., the doping concentration can vary from a bottom doped layer in the stack to a top layer in the stack (if desired). Such non-uniform doping can facilitate the formation of uniform recesses of SiGe layers (depending on the recess etch conditions).

[0031] Referring to Figure la , the device 100 can include silicon layers 102a, 102b, 102c and one or more silicon germanium layers 104a, 104b, which can be doped with n-dopants. As described above, any number of silicon layers 102 and silicon germanium layers 104 can be used. The silicon germanium layers 104 can be configured to alternate with the silicon layers 102. For example, the silicon germanium layer 104a can be disposed between the silicon layer 102a and the silicon layer 102b, where the silicon germanium layer 104a can be disposed on top of the silicon layer 102a and the silicon layer 102b can be disposed on top of the silicon germanium layer 104a. Similarly, the silicon germanium layer 104b can be disposed between the silicon layer 102b and the silicon layer 102c, where the silicon germanium layer 104b can be disposed on top of the silicon layer 102b and the silicon layer 102c can be disposed on top of the silicon germanium layer 104b.

[0032] As shown in Figure la , the thickness or height of the silicon layers 102 can be greater than the thickness or height of the silicon germanium layers 104. Alternatively or additionally, the thickness / height of at least one silicon germanium layer 104 can be greater than the thickness / height of at least one silicon layer 102. Further, although the thicknesses of the silicon layers 102 and the silicon germanium layers 104 are shown as being uniform, the thicknesses of the silicon layers 102 and the silicon germanium layers 104 can be non-uniform. For example, the thickness of the silicon layers 102 and / or the silicon germanium layers 104 can vary from a bottom layer in the stack to a top layer in the stack (if desired). Figure laThe uniform thickness / height of each silicon layer 102 is illustrated, and similarly, for each silicon germanium layer 104, it is to be understood that the thickness / height of such respective layers 102, 104 can not be uniform. For example, the thickness / height of layer 102a can be greater than the thickness / height of layer 102b, etc. (similarly for layers 104). The disposition or growth of each respective layer 102 and 104 can be performed in accordance with any existing technology.

[0033] In some implementations, one or more of the silicon germanium layers 104 can be doped with a dopant, such as, for example, an n-dopant, for the purpose of reducing wafer bow and enhancing the selective etch process. It is noted that SiGe layers are generally selectively etched compared to Si layers. Thus, adding n-type dopants to the SiGe layers can be configured to increase the availability of electrons, thereby increasing the etch rate of the SiGe layers. The increase in etch rate can result in a further reduction in the concentration of germanium in the SiGe layers, thereby reducing the impact of the SiGe layers on wafer bow.

[0034] In some example, non-limiting implementations, the concentration of the n-type dopant can be approximately less than or equal to 0.01%. The concentration of the n-type dopant can be selected based on the particular dopant and the desired strain reduction effect. For example, a higher doping level of phosphorous dopants, which have a smaller lattice constant compared to silicon, can be effective in reducing strain. In contrast, the use of arsenic and / or antimony dopants can result in lower diffusivity and an increase in strain, as each of these dopants has a larger lattice constant compared to silicon. It is to be understood that any type of n-type dopant can be used, where examples of such n-type dopants can include, but are not limited to, phosphorous, arsenic, antimony, bismuth, lithium, and / or any other n-type dopant and / or any combination thereof. As noted above, the doping of the layers can be uniform and / or non-uniform (e.g., varying) in the stack.

[0035] Figure lcAn example device 110 is illustrated that can include one or more regions that can be doped with p-type dopants to further improve the selective etch process and reduce bow compensation in accordance with some implementations of the present subject matter. In non-limiting implementations, the addition of p-type dopants and / or carbon to the silicon layer disposed next to the silicon germanium layer can be configured to lower the silicon layer etch rate, which in turn can help remove the SiGe layer relative to the silicon layer loss. The use of carbon and the absence of electrons in the silicon layer can be configured to lower the etch rate of the silicon layer. This can be configured to allow a more aggressive SiGe layer etch process during which a higher etch rate can be used to result in a reduction of the germanium concentration in the SiGe layer, thereby reducing the impact of the SiGe layer on wafer bow. While the resulting p-type and / or carbon-doped silicon layer can not be conducive to DRAM device tunnels, the thickness of this layer can be kept within the thickness of the silicon layer, which can be later removed when the silicon is thinned to form the final thickness of silicon for the semiconductor device (e.g., transistors). In addition, a gradual and / or thin silicon transition layer can be added to buffer the transition from a compressive film to a tensile film in the epitaxial layer, which can help reduce the formation of crystal defects.

[0036] As Figure lc shown, similar to the device 100 shown in Figure la , the device 110 can include silicon layers 102a, 102b, 102c and one or more silicon germanium layers 104a, 104b, which can be doped with n-dopants. Again, any number of silicon layers 102 and silicon germanium layers 104 can be used. The silicon germanium layers 104 can be configured to alternate with the silicon layers 102.

[0037] In addition to the layers 102 and 104, one or more of the silicon layers 102 can be configured to include one or more doped regions 106 (a, b, c, d). The regions 106 can be doped with p-type dopants. Such p-type dopants can include, but are not limited to, carbon, boron, carbon and boron, and / or any other p-type dopants, and / or any combination thereof. For example, the silicon layer 102a can be configured to include the doped region 106a, the silicon layer 102b can be configured to include the doped regions 106b and 106c, and the silicon layer 102c can include the doped region 106d. It can be appreciated that the silicon layers 102 can include any number of doped regions 106.

[0038] Additionally, doped regions 106 can be disposed within respective silicon layers 102 and adjacent to each side of respective n-type doped layers 104. For example, doped region 106a disposed within silicon layer 102a can be disposed adjacent to the bottom of silicon germanium layer 104a; doped region 106b disposed within silicon layer 102b can be disposed adjacent to the top of silicon germanium layer 104a; doped region 106c disposed within silicon layer 102b can be disposed adjacent to the bottom of silicon germanium layer 104b; and doped region 106d disposed within silicon layer 102c can be disposed adjacent to the top of silicon germanium layer 104b. The thickness, height, and / or concentration of each doped region 106 can be determined according to the particular characteristics of device 110, one or more intended uses of device 110, and / or a particular application. For example, the thickness and / or height of layers 104 can be comparable to the thickness and / or height of regions 106. Alternatively or additionally, each region 106 can have the same or different thickness and / or height as another region 106 and / or one or more layers 104.

[0039] Figure lc Some embodiments according to the inventive subject matter illustrate an example device 120 that can include layers and regions of one or more devices 100 and 110 as shown in Figure la and Figure lc shown above, also include an additional tensile layer disposed on the front side of the device. As shown in Figure lc , device 120 can include silicon layers 102 having one or more n-type doped regions 106, and one or more silicon germanium layers 104 doped with n-type dopants, similar to device 100 and device 110 shown in Figures la to lc . Again, any number of silicon layers 102 and silicon germanium layers 104 can be used. Silicon germanium layers 104 can be configured to alternate with silicon layers 102.

[0040] In addition to layers 102 and 104, a tensile layer 108 can be added to the front side of device 120 and adjacent to, for example, silicon layer 102a. Layer 108 can be added prior to the memory stack process. Layer 108 can be a silicon layer doped with p-dopants, such as, for example, boron. Alternatively or additionally, layer 108 can be one or more layers, a bilayer, and / or a combination of any other type of layer. For example, layer 108 can include a combination of layers, such as a thick n-type doped (e.g., phosphorous doped) silicon layer followed by a thin p-type doped (e.g., boron) silicon layer. Layer 108 can be further configured to facilitate a backside silicon removal process. Additionally, as discussed herein, layer doping can be uniform and / or non-uniform between layers in the stack.

[0041] Figures 2a to 2b Example structures 200(a, b) used during formation of a tensile layer are illustrated, which are used in devices including one or more n-type doped regions 106 and one or more p-type doped regions 108 according to some embodiments of the inventive subject matter, respectively.Figures la to lc one or more devices 100-120 shown. Figure 3 An example process 300 for forming a stretch layer is illustrated in accordance with some implementations of the present subject matter.

[0042] Referring to Figures 2a to 2b and Figure 3 At 302, a process of forming a stretch layer can be initiated by providing a silicon wafer 202. In some example, non-limiting implementations, the silicon wafer 202 can be about 750 microns (um) thick. As background, after a memory device process is completed on a front side of a wafer, it can be desirable to remove backside silicon to access memory cells from the backside. Typically, this can involve removing more than 750 um of silicon to a very small thickness (e.g., less than 0.1 um) of silicon remaining before the memory cell array. Such removal can be aided by adding a thin p-type wet etch stop layer over a thick n-type silicon wet etch layer. Backside grinding of silicon can stop within the n-type region. A wet silicon etch can then be used to easily remove the n-type silicon and stop the etch on the thin p-type silicon. The thin stop layer can be removed uniformly using a known etch process.

[0043] At 304 (as Figure 3 shown), an n-type doped silicon layer 204a can be grown on top of the silicon wafer 202, as Figure 2a shown. The n-type (e.g., N+) doped silicon layer 204a can be configured to have a thickness of 10-20 um. The dopant can be phosphorous and / or any other type of dopant material.

[0044] At 306 (as Figure 3 shown), a stop layer 206 can be formed on top of the doped silicon layer 204a. The thickness of the stop layer 206 can be less than and / or substantially less than the thickness of the doped silicon layer 204a. The stop layer can be p-type (P+) doped. The dopant can be boron and / or any other type of dopant material.

[0045] At 308, one or more silicon silicon germanium layer combinations 208 (e.g., memory stacks) can be formed on top of the stop layer 206. As Figures la to lc shown, the layer combinations 208 can be similar to a combination of the layers 102 (whether or not including the region 106) and / or 104. The formation of the memory stacks (i.e., the layer combinations 208) can complete Figure 2a the device 202a shown.

[0046] At 310 (as Figure 3 shown), to complete the formation of the memory device, a removal 210 of the silicon wafer 202 and at least a portion of the n-type doped layer 204a can be performed. As Figure 2bAs shown, removing at least a portion of the n-type doped layer 204a results in the formation of an n-type doped layer 204b. The removal of the portion of the silicon wafer and layer 204a can be accomplished by any known process, such as, for example, backgrinding. The removal 210 can be configured to stop when and / or before reaching the thin p-type stop layer 206. The resulting n-type doped layer 204b can have any desired shape, such as, for example, the arcuate shape shown. It can be appreciated that any desired shape of the layer 204b can be achieved and used in the device 202b. Figure 2b

[0047] Further, in some implementations, the remaining stop layer 206 and layer 204b can be used to reduce the bow of the silicon germanium layer before any silicon silicon germanium layers can be formed. It can be appreciated that the stop layer 206 can also be removed using any known etching process.

[0048] Figure 4 FIG. 4 illustrates an example process 400 for fabricating a semiconductor device in accordance with some implementations of the present subject matter. The process 400 can include any of the components and / or operations discussed herein with respect to Figures la to 3 At 402, a substrate (e.g., the substrate or silicon wafer 202) can be provided. At 404, at least one silicon layer can be formed on top of the substrate. At 406, at least one silicon germanium layer can be formed on top of the silicon layer. One silicon germanium layer can include at least one n-type dopant.

[0049] At 408, at least one p-type doped region can be formed within the silicon layer. The p-type doped region can be disposed adjacent to the silicon germanium layer. At 412, at least one tensile layer can be formed on a bottom of the silicon layer. At 414, a semiconductor device having one or more of the above-described layers can be formed.

[0050] In some implementations, the present subject matter can have one or more of the following optional features. For example, the process 400 can include a plurality of silicon germanium layers formed on top of the silicon layer, where the semiconductor device can include a plurality of one or more silicon germanium layers formed on top of one or more silicon layers.

[0051] In some implementations, a thickness of the at least one silicon layer can be greater than a thickness of the at least one silicon germanium layer.

[0052] ​In some implementations, the process 400 can include forming a plurality of silicon germanium layers stacked on top of a silicon layer, where the silicon layer can have at least one p-type doped region formed therein. Further, one or more silicon germanium layers of the stacked plurality of at least one silicon germanium layers formed on top of the at least one silicon layer are configured to be adjacent to one or more p-type doped regions formed within the silicon layer adjacent to the one or more silicon germanium layers. The one or more p-type doped regions can include one or more p-type dopants. The one or more p-type dopants can include at least one of boron, carbon, boron and carbon, and any combination thereof.

[0053] In some implementations, forming the tensile layer can include forming at least one n-type doped silicon layer on top of a substrate, forming at least one p-type stop layer on top of the n-type doped silicon layer, and removing at least a portion of the n-type doped silicon layer. In some implementations, the process 400 can also include removing the substrate and reducing a germanium concentration in the silicon germanium layer, thereby reducing a curvature of the substrate (e.g., wafer bow).

[0054] In some implementations, a thickness of the at least one p-type stop layer is less than a thickness of the at least one n-type doped silicon layer. The n-type dopant can include at least one of phosphorous, arsenic, antimony, bismuth, lithium, and any combination thereof.

[0055] It is to be understood that the example devices shown in the above block diagrams can represent one functional descriptive example of many potential implementations. Thus, the division, omission or inclusion of block functions depicted in the accompanying figures does not infer that the hardware components, circuits, software and / or elements for implementing these functions would necessarily be divided, omitted, or included in implementations in this manner.

[0056] Some implementations can be described using the expression "one or more implementation" or "one or more implementations" along with their derivatives. Such phrases indicate that implementations include one or more implementations. The use of the terms "one or more" with reference to implementations indicates that a particular feature, structure, or characteristic can be included in one or more implementations. The occurrence of the phrase "in one implementation" in various places in the specification does not necessarily all refer to the same implementation. In addition, the various identified features are believed to be applicable in any combination to one or more implementations. Accordingly, any feature or combination of features described herein are not necessarily limited to the combination with other features unless the combination of features are expressly noted as being critical for the feature or critical for the particular implementation.

[0057] In one aspect, a method for manufacturing a semiconductor device can include providing a substrate, forming at least one silicon layer on top of the substrate, forming at least one silicon germanium layer on top of the at least one silicon layer, the at least one silicon germanium layer including at least one n-type dopant, and forming a semiconductor device having the at least one silicon layer and the at least one silicon germanium layer.

[0058] The method can also include stacking a plurality of the at least one silicon germanium layer formed on top of the at least one silicon layer, the semiconductor device including the stacked plurality of the at least one silicon germanium layer formed on top of the at least one silicon layer.

[0059] The method can also include where a thickness of the at least one silicon layer is greater than a thickness of the at least one silicon germanium layer.

[0060] The method can also include forming at least one p-type doped region within the at least one silicon layer, the at least one p-type doped region arranged adjacent to the at least one silicon germanium layer.

[0061] The method can also include stacking a plurality of the at least one silicon germanium layer formed on top of the at least one silicon layer, the at least one silicon layer having the at least one p-type doped region formed within the at least one silicon layer; the semiconductor device including the stacked plurality of the at least one silicon germanium layer formed on top of the at least one silicon layer.

[0062] The method can also include where one or more silicon germanium layers of the stacked plurality of the at least one silicon germanium layer formed on top of the at least one silicon layer are configured to be adjacent to one or more p-type doped regions formed within a silicon layer adjacent to the one or more silicon germanium layers.

[0063] The method can also include where the one or more p-type doped regions include one or more p-type dopants including at least one of: boron, carbon, boron and carbon, and any combination thereof.

[0064] The method can also include forming at least one tensile layer on a bottom of the at least one silicon layer.

[0065] The method can also include where forming the at least one tensile layer includes forming at least one n-type doped silicon layer on top of the substrate; forming at least one p-type stop layer on top of the n-type doped silicon layer; and removing at least a portion of the n-type doped silicon layer.

[0066] The method can also include removing the substrate.

[0067] The method can also include reducing a germanium concentration in the silicon germanium layer, thereby reducing a curvature of the substrate.

[0068] The method can also include where a thickness of the at least one p-type stop layer is less than a thickness of the at least one n-type doped silicon layer.

[0069] The method can also include where the n-type dopant includes at least one of: phosphorous, arsenic, antimony, bismuth, lithium, and any combination thereof.

[0070] In one aspect, a semiconductor device can include a substrate; at least one silicon layer formed on a top of the substrate; and at least one silicon germanium layer formed on a top of the at least one silicon layer, the at least one silicon germanium layer including at least one n-type dopant.

[0071] The semiconductor device can also include a plurality of the at least one silicon germanium layer formed on the top of the at least one silicon layer.

[0072] The semiconductor device can also include a thickness of the at least one silicon layer is greater than a thickness of the at least one silicon germanium layer.

[0073] The semiconductor device can also include at least one p-type doped region formed within the at least one silicon layer, the at least one p-type doped region arranged adjacent to the at least one silicon germanium layer.

[0074] The semiconductor device can also include a plurality of the at least one silicon germanium layer formed on the top of the at least one silicon layer, the at least one silicon layer having at least one p-type doped region formed within the at least one silicon layer.

[0075] The semiconductor device can also include one or more silicon germanium layers of the plurality of the at least one silicon germanium layer formed on the top of the at least one silicon layer configured to be adjacent to one or more p-type doped regions formed within a silicon layer adjacent to the one or more silicon germanium layers.

[0076] The semiconductor device can also include the one or more p-type doped regions include one or more p-type dopants including at least one of: boron, carbon, boron and carbon, and any combination thereof.

[0077] The semiconductor device can also include at least one tensile layer formed on a bottom of the at least one silicon layer.

[0078] The semiconductor device can also include the at least one tensile layer formed by: forming at least one n-type doped silicon layer on a top of the substrate; forming at least one p-type stop layer on a top of the n-type doped silicon layer; and removing at least a portion of the n-type doped silicon layer.

[0079] The semiconductor device can also include a thickness of the at least one p-type stop layer is less than a thickness of the at least one n-type doped silicon layer.

[0080] The semiconductor device can also include the n-type dopant includes at least one of: phosphorous, arsenic, antimony, bismuth, lithium, and any combination thereof.

[0081] It should be emphasized that the summary of the disclosure provided herein is intended to allow the reader to quickly determine the nature of the technical disclosure. It is submitted with the understanding that the present disclosure will not be used to interpret or limit the scope or meaning of the claims. In addition, in the foregoing detailed description, for purposes of simplicity, various features are grouped together in individual implementations. The methods of the disclosure should not be construed as reflecting an intention that the claimed implementations require more features than are explicitly recited in each claim. Rather, the inventive subject matter is defined by the scope of the claims and the specification, viewed in the light most favorable to the present disclosure, taken together with their entire teachings. Accordingly, the following claims are hereby incorporated into the detailed description, where each claim by itself is a separate implementation. In the following claims, the terms "including", "includes", "having" and "has" are used as simple determinations — "comprising" and "wherein" and "whereby", respectively. Moreover, the term "first", "second", "third", etc., are used merely as labels, and are not intended to impose numerical requirements on their objects.

[0082] The above description includes examples of the disclosed architecture. Of course, it is not possible to describe every conceivable combination of components and / or methods, but one of ordinary skill in the art will recognize that many further combinations and permutations of the disclosed architecture are possible. Accordingly, the novel architecture is intended to embrace all such alterations, modifications, and variations that fall within the spirit and scope of the appended claims.

[0083] The foregoing description of the example implementations has been presented for the purposes of illustration and description. It is not intended to be exhaustive or to limit the disclosure to the precise form disclosed. Many modifications and variations are possible in light of this disclosure. The scope of the disclosure is intended to be limited only by the claims appended hereto, and it is expressly intended that all such modifications and variations are within the scope of the disclosure. Future filed applications claiming priority to this application can claim the disclosed subject matter in different ways and generally can include any set of one or more limitations as variously disclosed or otherwise taught herein.

Claims

1. A method for fabricating a semiconductor device, comprising the steps of: providing a substrate; forming at least one silicon layer on top of the substrate; forming at least one silicon germanium layer on top of the at least one silicon layer, the at least one silicon germanium layer comprising at least one n-type dopant; and forming the semiconductor device with the at least one silicon layer and the at least one silicon germanium layer. stacking a plurality of the at least one silicon germanium layer formed on top of the at least one silicon layer, the semiconductor device comprising the stacked plurality of the at least one silicon germanium layer formed on top of the at least one silicon layer.

2. The method of claim 1, further comprising the step of:

3. The method of any one of the preceding claims, wherein a thickness of the at least one silicon layer is greater than a thickness of the at least one silicon germanium layer. forming at least one p-type doped region within the at least one silicon layer, the at least one p-type doped region arranged adjacent to the at least one silicon germanium layer.

4. The method of any of the preceding claims, further comprising the step of: stacking a plurality of the at least one silicon germanium layer formed on top of the at least one silicon layer, the at least one silicon layer having the at least one p-type doped region formed within the at least one silicon layer; 5. The method of claim 4, further comprising the step of: the semiconductor device comprising the stacked plurality of the at least one silicon germanium layer formed on top of the at least one silicon layer.

6. The method of claim 5, wherein one or more silicon germanium layers of the stacked plurality of the at least one silicon germanium layer formed on top of the at least one silicon layer are configured to be adjacent to one or more p-type doped regions formed within a silicon layer adjacent to the one or more silicon germanium layers.

7. The method of claim 6, wherein the one or more p-type doped regions comprise one or more p-type dopants comprising at least one of: boron, carbon, boron and carbon, and any combination thereof. forming at least one tensile layer on a bottom of the at least one silicon layer.

8. The method of claim 4, further comprising the step of:

9. The method of claim 8, wherein the forming the at least one tensile layer comprises the steps of: forming at least one n-type doped silicon layer on top of the substrate; forming at least one p-type stop layer on top of the n-type doped silicon layer; and removing at least a portion of the n-type doped silicon layer. removing the substrate.

10. The method of claim 9, further comprising the step of: lowering a germanium concentration in the silicon germanium layer, thereby lowering a curvature of the substrate.

11. The method of claim 10, further comprising the step of:

12. The method of claim 9, wherein a thickness of the at least one p-type stop layer is less than a thickness of the at least one n-type doped silicon layer.

13. The method of any one of the preceding claims, wherein the n-type dopant comprises at least one of: phosphorous, arsenic, antimony, bismuth, lithium, and any combination thereof.

14. A semiconductor device, comprising: a substrate; at least one silicon layer formed on top of the substrate; and at least one silicon germanium layer formed on top of the at least one silicon layer, the at least one silicon germanium layer comprising at least one n-type dopant.

15. The semiconductor device of claim 14, further comprising a stacked plurality of the at least one silicon germanium layer formed on top of the at least one silicon layer. ​ ​ 16. The semiconductor device of any of the preceding claims 14-15, wherein a thickness of the at least one silicon layer is greater than a thickness of the at least one silicon germanium layer.

17. The semiconductor device of any of the preceding claims 14-16, further comprising at least one p-type doped region formed within the at least one silicon layer, the at least one p-type doped region disposed adjacent to the at least one silicon germanium layer.

18. The semiconductor device of claim 17, further comprising a stacked plurality of the at least one silicon germanium layer formed on top of the at least one silicon layer, the at least one silicon layer having the at least one p-type doped region formed within the at least one silicon layer.

19. The semiconductor device of claim 18, wherein one or more silicon germanium layers of the stacked plurality of the at least one silicon germanium layer formed on top of the at least one silicon layer are configured to be adjacent to one or more p-type doped regions formed within a silicon layer adjacent to the one or more silicon germanium layers.

20. The semiconductor device of claim 19, wherein the one or more p-type doped regions comprise one or more p-type dopants comprising at least one of: boron, carbon, boron and carbon, and any combination thereof.

21. The semiconductor device of claim 17, further comprising at least one tensile layer formed on a bottom of the at least one silicon layer.

22. The semiconductor device of claim 21, wherein the at least one tensile layer is formed by: forming at least one n-type doped silicon layer on top of the substrate; forming at least one p-type stop layer on top of the n-type doped silicon layer; and removing at least a portion of the n-type doped silicon layer.

23. The semiconductor device of claim 22, wherein a thickness of the at least one p-type stop layer is less than a thickness of the at least one n-type doped silicon layer.

24. The semiconductor device of any of the preceding claims 14-23, wherein the n-type dopants comprise at least one of: phosphorous, arsenic, antimony, bismuth, lithium, and any combination thereof.

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