Verification method and system thereof, equipment, storage medium and computer program product

Abstract

The invention discloses a verification method and system, equipment, a storage medium and a computer program product, and the verification method comprises the steps: obtaining first configuration information which comprises a distance design inspection rule of adjacent metal wires with a connection relation in a to-be-tested metal layer; second configuration information is obtained, the second configuration information comprises a parameterization unit, parameters comprise metal layer options with the connection relation to be verified and the distance between metal wires in a metal layer to be tested, the metal layers corresponding to the metal layer options have the connection relation, and one layer is the metal layer to be tested; performing verification operation according to the design rule detection file, the first configuration information, the second configuration information and the assignment of each parameter; the verification operation comprises the following steps: traversing assignment values of the spacing to obtain a plurality of unit patterns, metal layers to be tested of the unit patterns comprising adjacent metal wires, and the assignment values of the spacing comprise values which meet the spacing requirement and values which do not meet the spacing requirement; and performing design rule detection on the unit graph through the design rule detection file. The verification efficiency can be improved, and the verification cost can be reduced.

Description

TECHNICAL FIELD

[0001] Embodiments of the present application relate to the field of semiconductor manufacturing, and in particular, to a verification method and system, device, storage medium and computer program product. BACKGROUND

[0002] In the field of integrated circuits, it is often necessary to perform design rule checking (DRC) on a layout, through which portions of the layout that do not meet the requirements of the manufacturing process (for example, process design rules that violate minimum line width or minimum spacing, etc.) can be found, so that potential manufacturing problems can be avoided.

[0003] After developing a design rule checking file, a large number of test patterns are usually manually established to verify the accuracy of the design rule checking file, and PDK (Process Design Kit) files of different process platforms often correspond to different design rules, and accordingly corresponding test patterns are required. Moreover, due to different product design requirements, the number of metal layers in the product is large, and there are many types of combinations of inner metal layers and top metal layers, and the verification of the back-end connection in the design rule checking is also particularly important.

[0004] Therefore, the current verification of the design rule checking file consumes a large amount of verification cost and has low verification efficiency. SUMMARY

[0005] The problem solved by embodiments of the present application is to provide a verification method and system, device, storage medium and computer program product, which improves verification efficiency and reduces verification cost.

[0006] To solve the above problems, the embodiment of the present application provides a verification method of a design rule detection file, comprising: obtaining first configuration information, including a spacing design checking rule used for performing design rule detection, the spacing design checking rule including spacing requirements between adjacent metal lines having a connection relationship in a metal layer to be detected; obtaining second configuration information, including a parameterized unit, parameters in the parameterized unit including a metal layer option of a connection relationship to be verified and a spacing between adjacent metal lines in the metal layer to be detected, the metal layer option corresponding to multiple metal layers having a connection relationship, one of the multiple metal layers being the metal layer to be detected; performing a verification operation on the design rule detection file according to the design rule detection file, the first configuration information, the second configuration information and assignment of each parameter in the parameterized unit; wherein the verification operation comprises: traversing assignment of the spacing in the parameterized unit to obtain multiple unit patterns having a preset detection result, the metal layer to be detected of the unit pattern including adjacent metal lines, and the assignment of the spacing including a value satisfying the spacing requirement and a value not satisfying the spacing requirement; performing design rule detection on the multiple unit patterns based on the spacing design checking rule through the design rule detection file to obtain an actual detection result.

[0007] Correspondingly, the embodiment of the present application also provides a verification system of a design rule detection file, comprising: a first configuration module configured to obtain first configuration information, including a spacing design checking rule used for performing design rule detection, the spacing design checking rule including spacing requirements between adjacent metal lines having a connection relationship in a metal layer to be detected; a second configuration module configured to obtain second configuration information, including a parameterized unit, parameters in the parameterized unit including a metal layer option of a connection relationship to be verified and a spacing between adjacent metal lines in the metal layer to be detected, the metal layer option corresponding to multiple metal layers having a connection relationship, one of the multiple metal layers being the metal layer to be detected; and a verification module configured to perform a verification operation on the design rule detection file according to the design rule detection file, the first configuration information, the second configuration information and assignment of each parameter in the parameterized unit; wherein the verification operation comprises: traversing assignment of the spacing in the parameterized unit to obtain multiple unit patterns having a preset detection result, the metal layer to be detected of the unit pattern including adjacent metal lines, and the assignment of the spacing including a value satisfying the spacing requirement and a value not satisfying the spacing requirement; performing design rule detection on the multiple unit patterns based on the spacing design checking rule through the design rule detection file to obtain an actual detection result.

[0008] Correspondingly, the embodiment of the present application also provides a device comprising at least one memory and at least one processor, the memory storing one or more computer instructions, wherein the one or more computer instructions are executed by the processor to implement the verification method of the design rule detection file provided by any embodiment of the present application.

[0009] Correspondingly, the embodiment of the present application also provides a storage medium storing one or more computer instructions, the one or more computer instructions being used to implement the verification method of the design rule detection file provided by any embodiment of the present application.

[0010] Correspondingly, the embodiment of the present application also provides a computer program product comprising computer instructions, the computer instructions being executed by a processor to implement the verification method of the design rule detection file provided by any embodiment of the present application.

[0011] Compared with the prior art, the technical scheme of the embodiment of the present application has the following advantages:

[0012] The verification method of the design rule detection file provided in the embodiment of the present application comprises the following steps: obtaining first configuration information and second configuration information, the first configuration information comprising a space design checking rule used for performing design rule detection, the space design checking rule comprising a space requirement between adjacent metal lines having a connection relationship in a metal layer to be detected, the second configuration information comprising a parameterized cell (Pcell), parameters in the parameterized cell comprising a metal layer option of a connection relationship to be verified and a space between adjacent metal lines in the metal layer to be detected, the metal layer option corresponding to a plurality of metal layers having a connection relationship, one of the plurality of metal layers being the metal layer to be detected, and performing a verification operation according to the design rule detection file, the first configuration information, the second configuration information and the assignment of each parameter in the parameterized cell, the verification operation comprising: traversing the assignment of the space in the parameterized cell to obtain a plurality of cell patterns having a preset detection result, and the assignment of the space containing a value meeting the space requirement and a value not meeting the space requirement; and performing design rule detection on the plurality of cell patterns based on the space design checking rule through the design rule detection file to obtain an actual detection result. The embodiment of the present application can realize batch assignment, calling and verification according to verification requirements by pre-configuring the parameterized cell and the space design checking rule. Compared with the scheme of manually selecting from a large number of test patterns, the embodiment of the present application can obtain the cell pattern in a shorter time, can significantly reduce the probability of human operation errors and the requirement for maintaining the pattern set, and can facilitate subsequent verification of the design rule detection file according to the actual detection result and the corresponding preset detection result because the preset detection result contains two situations of meeting the design rule and violating the design rule. In summary, the verification method of the embodiment of the present application can realize overall verification of the connection relationship of the later-stage metal layer in the design rule detection, improve the verification efficiency and reliability and reduce the verification cost. BRIEF DESCRIPTION OF DRAWINGS

[0013] Figure 1 is a flowchart of a verification method of a design rule detection file according to an embodiment of the present application;

[0014] Figure 2 is a schematic diagram of a metal layer layout corresponding to a metal layer option of a connection relationship to be verified according to an embodiment of the verification method of the design rule detection file of the present application;

[0015] Figure 3 is Figure 1 is a flowchart of each step in step S3 in

[0016] Figure 4It is a schematic diagram of unit patterns corresponding to different connected layers in a verification method of a design rule detection file according to an embodiment of the present application.

[0017] Figure 5 It is a partial schematic diagram of an error mark appearing in a result judgment layer in a verification method of a design rule detection file according to an embodiment of the present application.

[0018] Figure 6 It is a schematic diagram of a verification system of a design rule detection file according to an embodiment of the present application.

[0019] Figure 7 It is a hardware structure diagram of an electronic device according to an embodiment of the present application. DETAILED DESCRIPTION

[0020] As known from the background, the verification of the design rule detection file currently consumes a large amount of verification cost and has low verification efficiency.

[0021] It is found through research that a commonly used method is to collect a large number of test patterns together, and then manually select the required test patterns according to different process platforms.

[0022] However, due to different product design requirements, there are many types of metal layer options, and there are commonly used 30-40 types, and the metal layer options of each platform are not completely the same, and the test patterns of the corresponding back-end connection relationship need to be established one by one for each platform, which will occupy a lot of time and manpower.

[0023] Moreover, due to the large number of test patterns established, the manual selection of the required test patterns is prone to human operation errors, and often needs to be manually verified again.

[0024] In addition, as the number of process platforms increases, the accumulated test patterns also increase, and the time for manually selecting test patterns also increases.

[0025] Therefore, it is urgent to provide a verification method of a design rule detection file to improve the verification efficiency and reduce the verification cost.

[0026] In order to solve the technical problem, an embodiment of the present application provides a verification method of a design rule detection file. Figure 1, the flowchart of the verification method of the design rule detection file according to an embodiment of the present application is shown. The verification method of the design rule detection file according to the embodiment of the present application includes the following basic steps:

[0027] Step S1: obtaining first configuration information, including spacing design checking rules for performing design rule detection, the spacing design checking rules including spacing requirements between adjacent metal lines having a connection relationship in a metal layer to be detected;

[0028] Step S2: obtaining second configuration information, including a parameterized unit, parameters in the parameterized unit including metal layer options of a connection relationship to be verified and spacing between adjacent metal lines in the metal layer to be detected, the metal layer options corresponding to multiple metal layers having a connection relationship, one of the multiple metal layers being the metal layer to be detected;

[0029] Step S3: performing a verification operation on the design rule detection file according to the design rule detection file, the first configuration information, the second configuration information, and the assignment of each parameter in the parameterized unit.

[0030] In step S3, the verification operation includes: traversing the assignment of the spacing in the parameterized unit to obtain multiple unit patterns having a preset detection result, the metal layer to be detected of the unit pattern including adjacent metal lines, and the assignment of the spacing including values satisfying the spacing requirements and values not satisfying the spacing requirements; performing design rule detection on the multiple unit patterns based on the spacing design checking rules through the design rule detection file to obtain actual detection results.

[0031] The verification method according to the embodiment of the present application can realize overall verification work on the connection relationship of the back-end metal layer in the design rule detection, improve the verification efficiency, and reduce the verification cost.

[0032] In order to make the above-mentioned purposes, features and advantages of the present application more obvious and easy to understand, the specific embodiments of the present application will be described in detail below with reference to the accompanying drawings.

[0033] For reference Figure 1 and Figure 2 , Figure 2 is a schematic diagram of an embodiment of a metal layer layout corresponding to metal layer options of a connection relationship to be verified, step S1 is performed to obtain first configuration information, including spacing design checking rules for performing design rule detection, the spacing design checking rules including spacing requirements between adjacent metal lines having a connection relationship in a metal layer to be detected (such as Figure 2 shown).

[0034] The verification method of the embodiment is used for verifying the design rule detection file, and the connection relationship of the back-end metal layer is mainly checked by the design rule, therefore, the spacing design checking rule adopted includes the spacing requirement between the adjacent metal lines having the connection relationship in the metal layer to be tested, so that whether the design rule detection file defines the connection between the metal layers can be verified in the design rule detection process.

[0035] It should be noted that in the back-end metal layer layout, if the connection relationship exists between any multiple metal layers, the multiple metal layers can constitute a same wire Net (for example, as shown in Figure 2 ).

[0036] In the multiple metal layers, if the metal layers except the topmost metal layer each include the adjacent metal lines arranged side by side, and the connection relationship exists between the metal layers, the multiple metal layers except the topmost metal layer can constitute two wires arranged side by side, that is, a first wire Net1 (for example, as shown in Figure 2 ) and a second wire Net2 (for example, as shown in Figure 2 ). The topmost metal layer acts as a communication layer, when the communication layer connects the first wire Net1 and the second wire Net2, the first wire Net1, the second wire Net2 and the communication layer constitute a same wire Net.

[0037] Therefore, in the case that the first wire Net1, the second wire Net2 and the communication layer can constitute a same wire, it means that the adjacent metal lines of the metal layer to be tested Mt (for example, as shown in Figure 2 ) have the connection relationship, and the adjacent metal lines of the metal layer to be tested Mt satisfy the prerequisite condition (that is, the adjacent metal lines having the connection relationship) of the spacing design checking rule, so that when the spacing S (for example, as shown in Figure 2 ) of the adjacent metal lines of the metal layer to be tested Mt does not satisfy the spacing requirement of the spacing design checking rule, it is determined that the adjacent metal lines of the metal layer to be tested Mt violate the spacing design checking rule.

[0038] In other words, only for the adjacent metal lines having the connection relationship, in the case that the spacing requirement is not satisfied, it is determined that the adjacent metal lines violate the spacing design checking rule.

[0039] Therefore, the verification method can verify whether the design rule detection file can identify the connection relationship of the back-end metal layer, so as to realize the verification of the connection relationship of the back-end metal layer in the design rule detection.

[0040] It should be noted that the metal layer to be tested Mt is any metal layer in the same wire Net except the communication layer.

[0041] Correspondingly, the embodiment first acquires a spacing design checking rule used for performing the design rule detection, so as to prepare for a subsequent verification operation on the design rule detection file.

[0042] The verification method of the embodiment is used for performing the design rule detection on a metal layer layout including multiple metal layers. For example, as shown in Figure 2 The metal layer layout includes a first metal layer M1, a second metal layer M2, a third metal layer M3, a fourth metal layer M4, and a top metal layer TM.

[0043] The first metal layer M1 and the second metal layer M2 are connected through a first via structure V1 located between the first metal layer M1 and the second metal layer M2, the second metal layer M2 and the third metal layer M3 are connected through a second via structure V2 located between the second metal layer M2 and the third metal layer M3, the third metal layer M3 and the fourth metal layer M4 are connected through a third via structure V3 located between the third metal layer M3 and the fourth metal layer M4, and the fourth metal layer M4 and the top metal layer TM are connected through a fourth via structure V4 located between the fourth metal layer M4 and the top metal layer TM. Therefore, the first metal layer M1, the second metal layer M2, the third metal layer M3, the fourth metal layer M4, and the top metal layer TM have a connection relationship and constitute a same wire Net.

[0044] In addition, in the metal layer layout as shown in Figure 2 The fourth metal layer M4 located adjacent to and spaced from each other is connected through the top metal layer TM. Therefore, the top metal layer TM is a communication layer. In other words, the communication layer is a metal layer located at the top in the same wire Net.

[0045] It can be understood that according to different product design requirements, the metal layer layout can have different types of metal layer options.

[0046] In the embodiment, the metal layer to be detected Mt is the first metal layer M1 in the metal layer layout.

[0047] For any metal layer layout, the first metal layer M1 is usually provided. Therefore, selecting the first metal layer M1 as the metal layer to be detected Mt is beneficial to reduce variable parameters in a subsequent parameterized unit, and the same spacing design checking rule can be used for different metal layer options, so as to improve the verification efficiency.

[0048] In addition, the first metal layer M1 is the bottommost metal layer in the back-end-of-line process. Whether the connection relationship of the back-end metal layer is complete can be reflected on the first metal layer M1. Therefore, selecting the first metal layer M1 as the metal layer to be detected Mt is also beneficial to verify the connection relationship of the back-end metal layer in the design rule detection.

[0049] In other embodiments, the metal layer to be tested can also be a metal layer of other layers in the metal layer layout, for example, a second metal layer, according to actual needs.

[0050] As an example, the spacing design checking rule is that the spacing S (as shown in Figure 2 ) between adjacent metal lines having a connection relationship in the metal layer to be tested Mt is greater than a first preset value (for example, in microns). It can be understood that the first preset value can be set according to actual conditions.

[0051] Continuing to refer to Figure 1 , a second configuration information is obtained in step S2, including a parameterization unit, parameters in the parameterization unit including a metal layer option of a connection relationship to be verified, and a spacing S (as shown in Figure 2 ) between adjacent metal lines in the metal layer to be tested Mt (as shown in Figure 2 ), the metal layer option corresponding to multiple metal layers having a connection relationship, one of the multiple metal layers being the metal layer to be tested.

[0052] The metal layer option is used to represent the metal layers having a connection relationship contained in the same wire, for example, the same wire can contain an inner metal layer and a top metal layer, and therefore, the metal layer option can represent the total number of metal layers and the number of layers of the top metal layer.

[0053] The parameterization unit is used to generate a unit pattern, and therefore, the parameters contained in the parameterization unit are configured in advance, so that the parameters of the parameterization unit include the metal layer option and the spacing, and the corresponding unit pattern can be obtained by assigning values to each parameter in the parameterization unit.

[0054] The parameterization unit is a parameterized layout file, and the parameterization unit is mounted inside the electronic design automation (EDA) software and is a core part of the PDK, and is usually implemented by using a programming language to automatically generate a unit pattern (for example, by using skill language programming). Different variable parameters are contained in the parameterization unit, so that a plurality of unit patterns can be formed by different combinations of parameter assignment, so as to realize batch verification operation according to verification needs, thereby effectively reducing the need for combination processing of different variable parameters by manual assignment, and making the verification method applicable to more process platforms, and even applicable to all process platforms.

[0055] By configuring the parameterized unit, a plurality of unit patterns can be obtained by traversing the assignment of the parameters in the parameterized unit and cross-combining when the types of the parameters are multiple, so that repeated creation of the unit pattern can be avoided; compared with the scheme of manually selecting from a pattern set containing a large number of test patterns, the need for maintaining the pattern set is reduced, and the unit pattern used as the test pattern can be quickly obtained, thereby improving the verification efficiency and reducing the verification cost.

[0056] In addition, compared with the scheme of manually selecting from a pattern set containing a large number of test patterns, the probability of human operation error can also be significantly reduced, which is beneficial to improving the reliability of verification.

[0057] Thirdly, by pre-configuring the parameterized unit, the subsequent batch assignment, calling and verification can be implemented in an automatic verification mode.

[0058] In the embodiment, in the step of obtaining the second configuration information, any metal layer above the metal layer to be tested Mt is used as a communication layer.

[0059] The parameterized unit defines the number of metal layers that can be contained in the unit pattern, any metal layer above the metal layer to be tested Mt is used as a communication layer, and the spacing S between adjacent metal lines in the communication layer and the metal layer to be tested Mt is a variable, so that the plurality of assignments of the communication layer (i.e. the plurality of selection results of the communication layer) and the plurality of assignments of the spacing can be cross-combined, thereby obtaining a plurality of unit patterns to meet the verification requirements of different product designs.

[0060] In the embodiment, in the step of obtaining the second configuration information, the metal layer options of the connection relationship to be verified include the first metal layer to the top metal layer in the metal layer layout, so that more selection results of the communication layer are obtained to meet the verification requirements of different product designs.

[0061] It should be noted that in other embodiments, the metal layers included in the metal layer options can be configured according to actual needs.

[0062] In the embodiment, in the step of obtaining the second configuration information, the parameters in the parameterized unit further include a result judgment layer, the result judgment layer is used to cover the metal layer to be tested Mt when the metal layer to be tested Mt does not meet the spacing design checking rule, and is used to cover any remaining metal layer except the metal layer to be tested Mt in the plurality of metal layers having the connection relationship when the metal layer to be tested Mt meets the spacing design checking rule.

[0063] The plurality of metal layers corresponding to the metal layer options of the connection relationship to be verified have the connection relationship, and when the spacing S of the adjacent metal lines of the metal layer to be tested Mt (such as Figure 2When the spacing design check rule is violated, an error mark is usually displayed in the area where the metal layer Mt to be detected is located (for example, the error mark is displayed at the spacing of the adjacent metal lines and has an overlap with the adjacent metal lines), so by adding a result judgment layer for covering the metal layer Mt to be detected that does not meet the spacing design check rule, the actual detection result of the unit pattern and the corresponding preset detection result can be compared by judging whether there is only an error mark in the result judgment layer, thereby reducing the complexity of the verification.

[0064] Therefore, the result judgment layer can also be regarded as an error mark layer.

[0065] In other embodiments, according to the comparison manner of the actual detection result and the corresponding preset detection result, the parameters in the parameterized unit can also not include the result judgment layer.

[0066] With reference to Figure 1 , step S3 is performed to verify the design rule detection file according to the design rule detection file, the first configuration information, the second configuration information, and the assignment of each parameter in the parameterized unit.

[0067] In this embodiment, the verification instruction for performing the verification operation is generated according to the design rule detection file, the first configuration information, the second configuration information, and the assignment of each parameter in the parameterized unit, so as to perform the verification operation on the design rule detection file.

[0068] Specifically, the design rule detection file, the first configuration information, the second configuration information, and the assignment of each parameter in the parameterized unit are bound, so that the verification instruction can be used to perform the verification operation, and the assignment of each parameter in the design rule detection file, the first configuration information, the second configuration information, and the parameterized unit can be called when the verification operation is performed.

[0069] Specifically, in the step of generating the verification instruction for performing the verification operation, the verification instruction for performing the verification operation is generated according to the design rule detection file, the first configuration information, the second configuration information, the assignment of each parameter in the parameterized unit, and the output path information of the design rule detection result, so as to perform the verification operation on the design rule detection file.

[0070] By pre-configuring the output path information, the result can be automatically exported to the target position after the subsequent verification operation is performed, so as to realize the automatic verification operation in the whole process.

[0071] With reference to Figure 3 , Figure 3 is Figure 1 a flowchart of an embodiment of each step in step S3.

[0072] In this embodiment, the verification operation includes: performing step S31, traversing the assignment of the spacing in the parameterized cell to obtain a plurality of cell patterns with a preset detection result, the metal layer to be tested of the cell pattern includes adjacent metal lines, and the assignment of the spacing includes a value satisfying the spacing requirement and a value not satisfying the spacing requirement.

[0073] In this embodiment, the spacing design checking rule is that the spacing S (as shown in Figure 2 ) between the adjacent metal lines having a connection relationship in the metal layer to be tested Mt is greater than a first preset value (for example, in microns), therefore, the assignment of the spacing S of the adjacent metal lines in the metal layer to be tested Mt needs to include a value satisfying the spacing requirement and a value not satisfying the spacing requirement, so as to verify the accuracy of the design rule detection file.

[0074] For example, the assignment of the spacing S of the adjacent metal lines in the metal layer to be tested Mt can include a first preset value and a second preset value, the second preset value is greater than the first preset value.

[0075] It should be noted that in other embodiments, the assignment of the spacing of the adjacent metal lines in the metal layer to be tested can also include a third preset value, the third preset value is less than the first preset value.

[0076] In this embodiment, the combination of the assignment of the spacing in the parameterized cell and the assignment of the connected layer is traversed to obtain a plurality of cell patterns with a preset detection result.

[0077] It should be noted that the same cell pattern includes a connected layer located at the topmost layer, a first connection line connected to one end of the connected layer, and a second connection line connected to the other end of the connected layer, the first connection line and the second connection line are arranged side by side, and the first connection line and the second connection line each include the remaining metal layers below the connected layer, and the first connection line includes one of the metal lines in the metal layer to be tested Mt, and the second connection line includes another metal line in the metal layer to be tested Mt.

[0078] In this embodiment, in the step of traversing the combination of the assignment of the spacing in the parameterized cell and the assignment of the connected layer, each metal layer above the metal layer to be tested Mt is respectively taken as a connected layer.

[0079] For example, as shown in Figure 4 , the Figure 4 is a schematic diagram of the cell pattern corresponding to different connected layers in the design rule detection file verification method of an embodiment of the present application.

[0080] Figure 4(a) The unit pattern shown is a first unit pattern CP1, and the connected layer of the first unit pattern CP1 is the topmost metal layer TM, that is, the first unit pattern CP1 includes the first metal layer M1, the second metal layer M2, the third metal layer M3, the fourth metal layer M4 and the topmost metal layer TM having a connection relationship.

[0081] Figure 4 (b) The unit pattern shown is a second unit pattern CP2, and the connected layer of the second unit pattern CP2 is the fourth metal layer M4, that is, the second unit pattern CP2 includes the first metal layer M1, the second metal layer M2, the third metal layer M3 and the fourth metal layer M4 having a connection relationship.

[0082] Figure 4 (c) The unit pattern shown is a third unit pattern CP3, and the connected layer of the third unit pattern CP3 is the third metal layer M3, that is, the third unit pattern CP3 includes the first metal layer M1, the second metal layer M2 and the third metal layer M3 having a connection relationship.

[0083] Figure 4 (d) The unit pattern shown is a fourth unit pattern CP4, and the connected layer of the fourth unit pattern CP4 is the second metal layer M2, that is, the fourth unit pattern CP4 includes the first metal layer M1 and the second metal layer M2 having a connection relationship.

[0084] Therefore, each metal layer above the metal layer to be tested Mt is selected as the connected layer, and more selection results of the connected layer are obtained to meet the verification requirements of different product designs.

[0085] For example, Figure 4 (a) Taking the first unit pattern CP1 shown as an example, the first unit pattern CP1 can include a case where the spacing S of adjacent metal lines in the metal layer to be tested Mt meets the spacing requirement and a case where the spacing S does not meet the spacing requirement, and thus multiple different first unit patterns CP1 can be obtained.

[0086] Similarly, multiple different second unit patterns CP2, multiple different third unit patterns CP3 and multiple different fourth unit patterns CP4 can be obtained.

[0087] Meanwhile, the selection of the connected layer also has different cases, and thus in this embodiment, multiple different unit patterns can be obtained by cross-combining the assignment of the connected layer and the assignment of the spacing.

[0088] It should be noted that, since the unit pattern is used to verify the design rule detection file, specifically, the verification method is used to verify the connectivity of the metal layer by spacing, therefore, as an example, when the number of metal layers contained in the same unit pattern is greater than two, in the same unit pattern, the extension direction of each metal layer other than the connected layer is consistent, and each metal layer other than the connected layer is sequentially connected along the extension direction, so that each metal layer other than the connected layer adopts the same spacing, thereby reducing the variables of the parameterized unit.

[0089] It should also be noted that, since the parameters in the parameterized unit also include the result judgment layer M, in the step of obtaining a plurality of unit patterns with a preset detection result, each unit pattern has a result judgment layer M (as shown in Figure 4 ), and the result judgment layer M covers the to-be-tested metal layer Mt of the unit pattern that does not meet the spacing design checking rule, and covers any remaining metal layer other than the to-be-tested metal layer Mt in the unit pattern that meets the spacing design checking rule.

[0090] It should be noted that, Figure 4 Only the case where the result judgment layer M covers the to-be-tested metal layer Mt of the unit pattern that does not meet the spacing design checking rule is shown.

[0091] With reference to Figure 3 , the verification operation further includes: before the design rule detection (i.e. step S33) of the plurality of unit patterns based on the spacing design checking rule by the design rule detection file, performing step S32, grouping the plurality of unit patterns, grouping the unit patterns that meet the spacing design checking rule into a first type of pattern, and grouping the unit patterns that do not meet the spacing design checking rule into a second type of pattern.

[0092] The first type of pattern is a correct pattern (i.e. a pattern that will not report an error when design rule detection is performed), and the second type of pattern is an error pattern (i.e. a pattern that will report an error when design rule detection is performed), therefore, by classifying the unit patterns, the subsequent design rule detection of the unit patterns in the first type of pattern and the second type of pattern is prepared.

[0093] Correspondingly, before the grouping of the plurality of unit patterns (i.e. step S32), the verification operation can further include: performing step S30, establishing a first type of pattern library and a second type of pattern library, the first type of pattern library is used to collect the first type of pattern, and the second type of pattern library is used to collect the second type of pattern.

[0094] Correspondingly, in the step of grouping the plurality of unit patterns, the first type of pattern is grouped into the first type of pattern library, and the second type of pattern is grouped into the second type of pattern library.

[0095] The unit patterns in the first type of pattern library are all correct patterns, and the unit patterns in the second type of pattern library are all incorrect patterns. The unit patterns are classified and grouped into the corresponding pattern library, thereby preparing for subsequent design rule detection of the unit patterns in the first type of pattern library and the second type of pattern library.

[0096] Specifically, before obtaining the plurality of unit patterns with the preset detection results (i.e., before step S31 is performed), step S30 is performed, so that after the unit patterns are obtained, the unit patterns are grouped into the corresponding pattern library, and the verification efficiency is improved.

[0097] It should be noted that in this embodiment, the unit patterns are classified in the manner of establishing the pattern library. In other embodiments, according to actual conditions, the first type of pattern and the second type of pattern can also be distinguished by other manners, for example, the first type of pattern and the second type of pattern can be distinguished by pattern type identification.

[0098] With reference to Figure 3 , the verification operation further includes: performing step S33, and detecting the plurality of unit patterns based on the spacing design inspection rule by using the design rule detection file to obtain actual detection results.

[0099] In this embodiment, the verification instruction can call the design rule detection file, the first configuration information, the second configuration information, the assignment of each parameter in the parameterized unit, and the output path information of the design rule detection result, so that the plurality of unit patterns are automatically detected by the design rule detection file.

[0100] Specifically, the unit patterns in the first type of pattern library and the second type of pattern library are respectively detected by the design rule detection file based on the spacing design inspection rule.

[0101] With reference to Figure 3 , the verification operation further includes: performing step S34, and verifying the design rule detection file according to the actual detection results of the unit patterns and the corresponding preset detection results.

[0102] Specifically, the design rule detection file is verified according to the consistency of the actual detection results of the unit patterns and the corresponding preset detection results.

[0103] Since the plurality of unit patterns are obtained by traversing according to the assignment of the spacing, and the preset detection results of the unit patterns are known, if the actual detection results of each unit pattern and the corresponding preset detection results are consistent, it indicates that the design rule detection file is correct, otherwise, it indicates that the design rule detection file is incorrect.

[0104] In this embodiment, each unit pattern has a result judging layer M (as shown in Figure 4 The result judging layer M covers the metal layer Mt to be tested of the unit pattern that does not meet the spacing design checking rule, and covers any other metal layer of the unit pattern that meets the spacing design checking rule. Therefore, according to the actual detection result and the corresponding preset detection result of the unit pattern, the step of verifying the design rule detection file includes: judging whether there is an error mark inside the result judging layer M. If there is only an error mark inside the result judging layer M, it is determined that the design rule detection file is correct. If there is no error mark inside the result judging layer M covering the metal layer Mt to be tested or there is an error mark outside the result judging layer M, it is determined that the design rule detection file is incorrect.

[0105] For example, as shown in Figure 5 Figure 5 A partial schematic view of an embodiment in which an error mark appears in the result judging layer M is shown.

[0106] For the unit pattern that does not meet the spacing design checking rule, the spacing S of the adjacent metal lines of the metal layer Mt to be tested does not meet the spacing requirement, and an error mark should appear in the position of the metal layer Mt to be tested. Since the result judging layer M covers the metal layer Mt to be tested of the unit pattern that does not meet the spacing design checking rule, an error mark should appear inside the result judging layer M covering the metal layer Mt to be tested. Therefore, if an error mark appears inside the result judging layer M corresponding to the unit pattern that does not meet the spacing design checking rule, it is determined that the actual detection result meets the expectation, indicating that the design rule detection file is correct. If no error mark appears inside the result judging layer M corresponding to the unit pattern that does not meet the spacing design checking rule, it is determined that the actual detection result does not meet the expectation, indicating that the design rule detection file is incorrect.

[0107] Similarly, for the unit pattern that meets the spacing design checking rule, the spacing S of the adjacent metal lines of the metal layer Mt to be tested meets the spacing requirement, and no error mark should appear in the position of the metal layer Mt to be tested. Since the result judging layer M covers any other metal layer of the unit pattern that meets the spacing design checking rule except the metal layer Mt to be tested, if no error mark appears outside the result judging layer M corresponding to the unit pattern that meets the spacing design checking rule, it is determined that the actual detection result meets the expectation, indicating that the design rule detection file is correct. If an error mark appears outside the result judging layer M corresponding to the unit pattern that meets the spacing design checking rule, it is determined that the actual detection result does not meet the expectation, indicating that the design rule detection file is incorrect. ​

[0108] In summary, if the error flag appears in the result judgment layer M and does not appear outside the result judgment layer M, it is determined that the design rule detection file is correct, otherwise, it is determined that the design rule detection file is incorrect.

[0109] Therefore, by judging whether the error flag appears in the result judgment layer M, the complexity of comparing the actual detection result with the preset detection result is reduced, and the automation verification is facilitated.

[0110] In this embodiment, the design rule detection file performs design rule detection on the unit patterns in the first type of pattern library and the second type of pattern library based on the spacing design checking rule.

[0111] The step of verifying the design rule detection file according to the actual detection result and the corresponding preset detection result of the unit pattern includes: judging whether the first type of pattern all conforms to the spacing design checking rule and the second type of pattern all does not conform to the spacing design checking rule, if yes, it is determined that the design rule detection file is correct, otherwise, it is determined that the design rule detection file is incorrect.

[0112] If the first type of pattern is all the unit pattern conforming to the spacing design checking rule, the to-be-tested metal layer Mt of the unit pattern does not violate the spacing design checking rule and does not report an error during the design rule detection. Therefore, theoretically, after the design rule detection on the unit pattern in the first type of pattern, there is no pattern violating the spacing design checking rule, and once there is a pattern violating the spacing design checking rule, it means that the design rule detection file is incorrect, and a false positive situation occurs.

[0113] Similarly, if the second type of pattern is all the unit pattern not conforming to the spacing design checking rule, theoretically, after the design rule detection on the unit pattern in the second type of pattern, there is no pattern conforming to the spacing design checking rule, and once there is a pattern conforming to the spacing design checking rule, it means that the design rule detection file is incorrect, and a false positive situation occurs.

[0114] Therefore, by classifying the unit patterns first and then performing the design rule detection on the unit patterns in the first type of pattern and the second type of pattern respectively, if the detection result of any of the first type of pattern and the second type of pattern is abnormal, it is determined that the design rule detection file is incorrect, thereby reducing the complexity of judging whether the design rule detection file is correct, and facilitating the automation verification.

[0115] In the embodiment, in the step of verifying the design rule detection file according to the actual detection result of the unit pattern and the corresponding preset detection result, only whether the error mark appears outside the result judgment layer M of the first type of pattern and whether the error mark appears inside the result judgment layer M of the second type of pattern is judged, and any one of the error mark appearing outside the result judgment layer M of the first type of pattern and the error mark not appearing inside the result judgment layer M of the second type of pattern indicates that the design rule detection file is incorrect.

[0116] Specifically, the manner of judging whether the first type of pattern all meets the spacing design checking rule and the second type of pattern all does not meet the spacing design checking rule includes: judging whether the error mark appears inside the result judgment layer M, if only the error mark appears inside the result judgment layer M, it is determined that the design rule detection file is correct, if the error mark does not appear inside the result judgment layer M or the error mark appears outside the result judgment layer M, it is determined that the design rule detection file is incorrect.

[0117] In the embodiment, in the step of generating the verification instruction for performing the verification operation, the verification instruction is recorded in the verification script. The verification script is an automatic processing script, so that the automatic mode of the whole process of parameterized unit assignment, unit pattern generation, unit pattern layout, design rule detection, result analysis and result analysis export can be performed to reduce manual intervention.

[0118] Therefore, the verification work of the connection relationship of the back-end metal layer in the DRC is completed by the automatic script, so that the time of human investment and the risk of error are effectively reduced. For example, the work time of one day can be reduced to within half an hour.

[0119] Correspondingly, the embodiment of the present application also provides a design rule detection file verification system. For reference Figure 6 , Figure 6 is a schematic diagram of a design rule detection file verification system of an embodiment of the present application.

[0120] For reference Figure 2 , Figure 2 is a schematic diagram of a metal layer layout corresponding to a metal layer option of a connection relationship to be verified. The design rule detection file verification system of the embodiment includes: a first configuration module 10, configured to obtain first configuration information, including a spacing design checking rule for performing design rule detection, the spacing design checking rule including a metal layer to be detected Mt (such as Figure 2a spacing requirement between adjacent metal lines having a connection relationship in the metal layer option corresponding to the multiple metal layers; the second configuration module 20 is configured to obtain second configuration information, including a parameterization unit, parameters in the parameterization unit including a metal layer option to be verified for the connection relationship, and a spacing S between adjacent metal lines in the metal layer Mt to be tested (as shown in FIG. 2), the multiple metal layers corresponding to the metal layer option have a connection relationship, and one of the multiple metal layers is the metal layer Mt to be tested; and the verification module 30 is configured to perform a verification operation on the design rule detection file according to the design rule detection file, the first configuration information, the second configuration information, and the assignment of each parameter in the parameterization unit. Figure 2 The metal layer option corresponds to multiple metal layers having a connection relationship, and one of the multiple metal layers is the metal layer Mt to be tested; and the verification module 30 is configured to perform a verification operation on the design rule detection file according to the design rule detection file, the first configuration information, the second configuration information, and the assignment of each parameter in the parameterization unit.

[0121] The verification operation includes: traversing the assignment of the spacing in the parameterization unit to obtain multiple unit patterns having a preset detection result, the metal layer to be tested of the unit pattern including adjacent metal lines, and the assignment of the spacing including a value satisfying the spacing requirement and a value not satisfying the spacing requirement; and performing design rule detection on the multiple unit patterns based on the spacing design checking rule in the design rule detection file to obtain an actual detection result.

[0122] In the verification system of the design rule detection file in this embodiment, the first configuration information and the second configuration information are obtained first, the first configuration information includes the spacing design checking rule, the spacing design checking rule includes a spacing requirement between adjacent metal lines having a connection relationship in the metal layer to be tested, the second configuration information includes a parameterization unit, parameters in the parameterization unit including a metal layer option to be verified for the connection relationship and a spacing between adjacent metal lines in the metal layer to be tested, the metal layer option corresponding to multiple metal layers having a connection relationship, and one of the multiple metal layers being the metal layer to be tested, and a verification operation is performed according to the design rule detection file, the first configuration information, the second configuration information, and the assignment of each parameter in the parameterization unit. The present embodiment can realize batch assignment, calling, and verification according to verification requirements by pre-configuring the parameterization unit and the spacing design checking rule. Compared with the scheme of manually selecting from a large number of test patterns, the present embodiment requires less time to obtain unit patterns, can significantly reduce the probability of human operation errors and the demand for maintenance of the pattern set, and since the preset detection result includes both the case of conforming to the design rule and the case of violating the design rule, it is convenient to verify the design rule detection file according to the actual detection result and the corresponding preset detection result subsequently. In summary, the verification method of the present embodiment can realize overall verification of the connection relationship of the later-stage metal layer in the design rule detection, improve the verification efficiency and reliability, and reduce the verification cost.

[0123] The spacing design checking rule includes spacing requirements between adjacent metal lines having a connection relationship in the metal layer to be tested, so as to verify the connection between the metal layers in the design rule detection process.

[0124] It should be noted that only for the adjacent metal lines having a connection relationship, if the spacing requirements are not met, it is determined that the adjacent metal lines violate the spacing design checking rule. Therefore, the verification method can verify whether the design rule detection file can identify the connection relationship of the metal layer in the later stage, so as to realize the verification of the connection relationship of the metal layer in the later stage in the design rule detection.

[0125] It should be further noted that the metal layer to be tested Mt is any metal layer in the same wire Net (as shown in Figure 2 ) except the connection layer, and the connection layer is the metal layer located at the top layer in the same wire Net.

[0126] Correspondingly, the spacing design checking rule used for performing the design rule detection is acquired first, so as to prepare for the subsequent verification operation.

[0127] The verification system of the embodiment is used for performing the design rule detection on the metal layer layout, and the metal layer layout includes multiple metal layers. For example, as shown in Figure 2 , the metal layer layout includes a first metal layer M1, a second metal layer M2, a third metal layer M3, a fourth metal layer M4 and a top metal layer TM.

[0128] Among them, the first metal layer M1 and the second metal layer M2 are connected through the first via structure V1 located between them, the second metal layer M2 and the third metal layer M3 are connected through the second via structure V2 located between them, the third metal layer M3 and the fourth metal layer M4 are connected through the third via structure V3 located between them, and the fourth metal layer M4 and the top metal layer TM are connected through the fourth via structure V4 located between them. Therefore, the first metal layer M1, the second metal layer M2, the third metal layer M3, the fourth metal layer M4 and the top metal layer TM have a connection relationship, and constitute the same wire Net.

[0129] Moreover, in the metal layer layout shown in Figure 2 , the adjacent and spaced fourth metal layer M4 is connected through the top metal layer TM, so the top metal layer TM is the connection layer.

[0130] It can be understood that according to different product design requirements, the metal layer layout can have different types of metal layer options.

[0131] In this embodiment, the metal layer Mt to be tested is the first metal layer M1 in the metal layer layout. For any metal layer layout, there is usually a first metal layer M1, and selecting the first metal layer M1 as the metal layer Mt to be tested can reduce the variable parameters in the subsequent parameterization unit, and the same spacing design checking rule can be used for different metal layer options, thereby improving the verification efficiency. Moreover, the first metal layer M1 is the bottommost metal layer in the back-end-of-line process, and whether the connection relationship of the back-end metal layer is complete can be reflected on the first metal layer M1. Therefore, selecting the first metal layer M1 as the metal layer Mt to be tested also facilitates the verification of the connection relationship of the back-end metal layer in the design rule detection.

[0132] In other embodiments, according to actual needs, the metal layer to be tested can also be a metal layer of other layers in the metal layer layout, for example, a second metal layer.

[0133] As an example, the spacing design checking rule is that the spacing S (as shown in FIG. 1) between adjacent metal lines having a connection relationship in the metal layer Mt to be tested is greater than a first preset value (for example, in microns). It can be understood that the first preset value can be set according to actual conditions. Figure 2

[0134] The parameterization unit is used to generate a unit pattern, and therefore, the parameters included in the parameterization unit are configured in advance, so that the parameters of the parameterization unit include the metal layer option and the spacing. Then, the corresponding unit pattern can be obtained by assigning values to each parameter in the parameterization unit.

[0135] By configuring the parameterization unit, a plurality of unit patterns can be obtained by traversing the assignment of the parameters in the parameterization unit and cross-combining when the type of the parameters is multiple, thereby avoiding repeated creation of unit patterns. Compared with the scheme of manually selecting from a large number of test patterns in a pattern set, the demand for maintaining the pattern set is reduced, and the unit pattern used as a test pattern can be quickly obtained, thereby improving the verification efficiency and reducing the verification cost. In addition, compared with the scheme of manually selecting from a large number of test patterns in a pattern set, the probability of human operation errors can be significantly reduced, which is beneficial to improving the reliability of the verification. Furthermore, by configuring the parameterization unit in advance, the automatic verification mode of subsequent batch assignment, calling and verification can be facilitated.

[0136] In this embodiment, in the second configuration module 20, any metal layer above the metal layer Mt to be tested is used as a connection layer in the step of obtaining the second configuration information.

[0137] ​The parameterized unit defines the number of metal layers that the unit pattern can contain. Any metal layer above the metal layer under test Mt is used as a connected layer. The spacing S between adjacent metal lines in the connected layer and the metal layer under test Mt are variables. Then, multiple assignments of the connected layer (i.e., multiple selection results of the connected layer) and multiple assignments of the spacing can be cross-combined to obtain a variety of unit patterns to meet the verification needs of different product designs.

[0138] In this embodiment, the metal layer options for verifying the connectivity relationships include the first metal layer to the topmost metal layer in the metal layer layout, thereby obtaining a wider range of connected layer selection results to meet the verification needs of different product designs. In other embodiments, the metal layers included in the metal layer options can be configured according to actual needs.

[0139] In this embodiment, the parameters in the parameterization unit also include a result judgment layer. The result judgment layer is used to cover the metal layer Mt under test when the metal layer Mt under test does not meet the spacing design inspection rules. It is also used to cover any other metal layer in the multi-layer metal layers with connection relationship, except for the metal layer Mt under test, when the metal layer Mt under test meets the spacing design inspection rules.

[0140] The multilayer metal layers corresponding to the metal layer option whose connectivity needs to be verified have connectivity relationships. When the spacing S between adjacent metal lines of the metal layer Mt under test (e.g., Figure 2 As shown, when the spacing design check rules are violated, error marks are usually displayed in the area where the tested metal layer Mt is located (for example, error marks are displayed at the intervals between adjacent metal lines and overlap with adjacent metal lines). Therefore, by adding a result judgment layer to cover the tested metal layer Mt that does not comply with the spacing design check rules, the actual detection result of the unit pattern and the corresponding preset detection result can be compared by determining whether error marks exist only within the result judgment layer, thus reducing the complexity of verification. Therefore, the result judgment layer can also be regarded as an error mark layer.

[0141] In other embodiments, the parameters in the parameterization unit may not include the result judgment layer, depending on the comparison method between the actual detection results and the corresponding preset detection results.

[0142] In this embodiment, in the verification module 30, a verification instruction for performing verification operations is generated based on the design rule detection file, the first configuration information, the second configuration information, and the values ​​of each parameter in the parameterization unit, so as to perform verification operations on the design rule detection file.

[0143] Specifically, the design rule detection file, the first configuration information, the second configuration information, and the assignment of each parameter in the parameterized cell are bound, so that the verification instruction can be used to perform the verification operation, and when the verification operation is performed, the design rule detection file, the first configuration information, the second configuration information, and the assignment of each parameter in the parameterized cell can be called.

[0144] Specifically, the verification module 30 generates a verification instruction for performing a verification operation according to the design rule detection file, the first configuration information, the second configuration information, the assignment of each parameter in the parameterized cell, and the output path information of the design rule detection result, so as to perform a verification operation on the design rule detection file. By pre-configuring the output path information, the verification result can be automatically exported to the target position after the subsequent verification operation is performed, so as to realize automatic verification operation in the whole process.

[0145] In this embodiment, the verification module 30 includes a cell pattern generation unit (not shown in the figure) configured to traverse the assignment of the spacing in the parameterized cell to obtain a plurality of cell patterns with a preset detection result. The metal layer to be tested of the cell pattern includes adjacent metal lines, and the assignment of the spacing includes a value satisfying the spacing requirement and a value not satisfying the spacing requirement.

[0146] In this embodiment, the spacing design checking rule is that the spacing S (as shown in Figure 2 ) between the adjacent metal lines having a connection relationship in the metal layer to be tested Mt is greater than a first preset value (for example, in microns), and therefore, the assignment of the spacing S of the adjacent metal lines in the metal layer to be tested Mt needs to include a value satisfying the spacing requirement and a value not satisfying the spacing requirement, so as to verify the accuracy of the design rule detection file. For example, the assignment of the spacing S of the adjacent metal lines in the metal layer to be tested Mt can include a first preset value and a second preset value, and the second preset value is greater than the first preset value. It should be noted that in other embodiments, the assignment of the spacing of the adjacent metal lines in the metal layer to be tested can also include a third preset value, and the third preset value is less than the first preset value.

[0147] In this embodiment, the cell pattern generation unit is configured to traverse the combination of the assignment of the spacing and the assignment of the connected layer in the parameterized cell to obtain a plurality of cell patterns with a preset detection result.

[0148] In this embodiment, the cell pattern generation unit is configured to take each metal layer above the metal layer to be tested Mt as a connected layer, respectively. For example, as shown in Figure 4 , Figure 4 is a schematic diagram of the cell patterns corresponding to different connected layers in the verification method of the design rule detection file according to an embodiment of the present application.

[0149] Figure 4(a) the unit pattern shown is a first unit pattern CP1, and the connected layer of the first unit pattern CP1 is the topmost metal layer TM; Figure 4 (b) the unit pattern shown is a second unit pattern CP2, and the connected layer of the second unit pattern CP2 is the fourth metal layer M4; Figure 4 (c) the unit pattern shown is a third unit pattern CP3, and the connected layer of the third unit pattern CP3 is the third metal layer M3; Figure 4 (d) the unit pattern shown is a fourth unit pattern CP4, and the connected layer of the fourth unit pattern CP4 is the second metal layer M2.

[0150] Therefore, each metal layer above the metal layer to be tested Mt is selected as the connected layer, and more selection results of the connected layer are obtained to meet the verification requirements of different product designs.

[0151] For example, Figure 4 (a) taking the first unit pattern CP1 shown as an example, the first unit pattern CP1 can include a case where the spacing S of adjacent metal lines in the metal layer to be tested Mt meets the spacing requirement and a case where the spacing S of adjacent metal lines in the metal layer to be tested Mt does not meet the spacing requirement, and thus multiple different first unit patterns CP1 can be obtained. Similarly, multiple different second unit patterns CP2, multiple different third unit patterns CP3, and multiple different fourth unit patterns CP4 can be obtained.

[0152] Meanwhile, the selection of the connected layer also has different cases, and thus the assignment of the connected layer and the assignment of the spacing are cross-combined to obtain multiple different unit patterns.

[0153] It should be noted that as an example, when the number of metal layers contained in the same unit pattern is greater than two, in the same unit pattern, the extension directions of the remaining metal layers except the connected layer are consistent, and the remaining metal layers are sequentially connected along the extension directions, so that the remaining metal layers except the connected layer adopt the same spacing, thereby reducing the variables of the parameterized unit.

[0154] It should be further noted that since the parameters in the parameterized unit also include the result judgment layer M, in the unit pattern generation unit, in the step of obtaining multiple unit patterns with the preset detection result, the result judgment layer M is obtained on each unit pattern (as shown in Figure 4 The result judgment layer M covers the metal layer to be tested Mt of the unit pattern that does not meet the spacing design inspection rule, and covers any remaining metal layer except the metal layer to be tested Mt in the unit pattern that meets the spacing design inspection rule. It should be noted that Figure 4 Only the case where the result judgment layer M covers the metal layer to be tested Mt of the unit pattern that does not meet the spacing design inspection rule is shown.

[0155] In this embodiment, the verification module 30 further comprises a grouping unit (not shown in the figure) configured to group the plurality of unit patterns before the design rule detection is performed on the plurality of unit patterns based on the spacing design rule check rule in the design rule detection file, and group the unit patterns that meet the spacing design rule check rule into a first type of patterns, and group the unit patterns that do not meet the spacing design rule check rule into a second type of patterns.

[0156] The first type of patterns are correct patterns (i.e., patterns that will not cause errors during the design rule detection), and the second type of patterns are error patterns (i.e., patterns that will cause errors during the design rule detection). Therefore, by classifying the unit patterns, the first type of patterns and the second type of patterns are prepared for subsequent design rule detection.

[0157] Correspondingly, the verification module 30 further comprises a pattern library establishing unit (not shown in the figure) configured to establish a first type of pattern library and a second type of pattern library before the plurality of unit patterns are grouped, the first type of pattern library is configured to collect the first type of patterns, and the second type of pattern library is configured to collect the second type of patterns.

[0158] Correspondingly, when the grouping unit groups the plurality of unit patterns, the first type of patterns are grouped into the first type of pattern library, and the second type of patterns are grouped into the second type of pattern library.

[0159] The unit patterns in the first type of pattern library are all correct patterns, and the unit patterns in the second type of pattern library are all error patterns. By classifying the unit patterns and grouping them into corresponding pattern libraries, the first type of pattern library and the second type of pattern library are prepared for subsequent design rule detection.

[0160] Specifically, the pattern library establishing unit is configured to establish the first type of pattern library and the second type of pattern library before the plurality of unit patterns with the preset detection results are obtained, so that after the unit patterns are obtained, the unit patterns can be grouped into corresponding pattern libraries, and the verification efficiency is improved.

[0161] It should be noted that in this embodiment, the unit patterns are classified by establishing pattern libraries. In other embodiments, according to actual conditions, the verification module can not include the pattern library establishing unit, but can distinguish the first type of patterns and the second type of patterns by other ways, for example, the verification module can include a marking unit configured to add a pattern type identifier to the unit patterns to distinguish the first type of patterns and the second type of patterns.

[0162] In this embodiment, the verification module 30 further comprises a design rule detection unit (not shown in the figure) configured to perform design rule detection on the plurality of unit patterns based on the spacing design rule check rule in the design rule detection file, and obtain actual detection results.

[0163] In the embodiment, the verification instruction can call the design rule detection file, the first configuration information, the second configuration information, the assignment of each parameter in the parameterized cell, and the output path information of the design rule detection result, so that the design rule detection file is used to automatically detect the design rule of each cell pattern in the plurality of cell patterns.

[0164] Specifically, the design rule detection file is used to detect the design rule of each cell pattern in the first type of cell library and the second type of cell library based on the spacing design checking rule.

[0165] The verification module 30 further comprises a verification unit (not shown in the figure) configured to verify the design rule detection file according to the actual detection result of the cell pattern and the corresponding preset detection result.

[0166] Specifically, the verification unit verifies the design rule detection file according to the consistency of the actual detection result of the cell pattern and the corresponding preset detection result.

[0167] Since the plurality of cell patterns are obtained by traversing according to the assignment of the spacing, and the preset detection result of each cell pattern is known, if the actual detection result of each cell pattern and the corresponding preset detection result are consistent, it indicates that the design rule detection file is correct, otherwise, it indicates that the design rule detection file is incorrect.

[0168] In the embodiment, each cell pattern has a result judgment layer M (as shown in Figure 4 , and the result judgment layer M covers the to-be-tested metal layer Mt of the cell pattern that does not meet the spacing design checking rule, and covers any remaining metal layer of the cell pattern that meets the spacing design checking rule except the to-be-tested metal layer Mt, therefore, the step of verifying the design rule detection file according to the actual detection result of the cell pattern and the corresponding preset detection result comprises: judging whether an error mark appears inside the result judgment layer M, if only the error mark appears inside the result judgment layer M, it is determined that the design rule detection file is correct, if the error mark does not appear inside the result judgment layer M covering the to-be-tested metal layer Mt or the error mark appears outside the result judgment layer M, it is determined that the design rule detection file is incorrect. For example, as shown in Figure 5 , a partial schematic view of an embodiment in which an error mark appears in the result judgment layer M is shown. Figure 5

[0169] ​For the unit pattern whose preset detection result is that the spacing design checking rule is not met, the spacing S of the adjacent metal lines of the metal layer Mt to be detected does not meet the spacing requirement, and error marks should appear on the position processing theory of the metal layer Mt to be detected. Since the unit pattern whose spacing design checking rule is not met is covered with the result judgment layer M, error marks should appear in the result judgment layer M covering the metal layer Mt to be detected. Therefore, if error marks appear in the result judgment layer M corresponding to the unit pattern whose spacing design checking rule is not met, it means that the actual detection result meets the expectation, indicating that the design rule detection file is correct; if error marks do not appear in the result judgment layer M corresponding to the unit pattern whose spacing design checking rule is not met, it means that the actual detection result does not meet the expectation, indicating that the design rule detection file is incorrect.

[0170] Similarly, for the unit pattern whose preset detection result is that the spacing design checking rule is met, the spacing S of the adjacent metal lines of the metal layer Mt to be detected meets the spacing requirement, and error marks should not appear on the position processing theory of the metal layer Mt to be detected. Since the result judgment layer M covers any remaining metal layer other than the metal layer Mt to be detected in the unit pattern whose spacing design checking rule is met, if error marks do not appear outside the result judgment layer M corresponding to the unit pattern whose spacing design checking rule is met, it means that the actual detection result meets the expectation, indicating that the design rule detection file is correct; if error marks appear outside the result judgment layer M corresponding to the unit pattern whose spacing design checking rule is met, it means that the actual detection result does not meet the expectation, indicating that the design rule detection file is incorrect.

[0171] In summary, if error marks appear inside the result judgment layer M and no error marks appear outside the result judgment layer M, it is determined that the design rule detection file is correct, otherwise it is determined that the design rule detection file is incorrect.

[0172] Therefore, the verification unit adopts the way of judging whether error marks appear in the result judgment layer M, which reduces the complexity of comparing the actual detection result with the preset detection result, and facilitates automatic verification.

[0173] In this embodiment, the design rule detection unit detects the unit patterns in the first type of pattern library and the second type of pattern library based on the spacing design checking rule through the design rule detection file.

[0174] The step of verifying the design rule detection file according to the actual detection result of the unit pattern and the corresponding preset detection result comprises: judging whether the first type of pattern all conforms to the spacing design checking rule and the second type of pattern all does not conform to the spacing design checking rule, if yes, determining that the design rule detection file is correct, otherwise, determining that the design rule detection file is incorrect.

[0175] The first type of pattern is all the unit pattern conforming to the spacing design checking rule, so when the design rule detection is performed, the to-be-detected metal layer Mt of the unit pattern does not violate the spacing design checking rule and does not occur error. Therefore, theoretically, after the design rule detection is performed on the unit pattern in the first type of pattern, there is no pattern violating the spacing design checking rule, and once the pattern violating the spacing design checking rule occurs, it means that the design rule detection file is incorrect, and a false alarm occurs.

[0176] Similarly, the second type of pattern is all the unit pattern not conforming to the spacing design checking rule, and theoretically, after the design rule detection is performed on the unit pattern in the second type of pattern, there is no pattern conforming to the spacing design checking rule, and once the pattern conforming to the spacing design checking rule occurs, it means that the design rule detection file is incorrect, and a false alarm occurs.

[0177] Therefore, by classifying the unit pattern first and then performing the design rule detection on the unit pattern in the first type of pattern and the second type of pattern respectively, if the detection result of any one of the first type of pattern and the second type of pattern is abnormal, it is determined that the design rule detection file is incorrect, thereby reducing the complexity of judging whether the design rule detection file is correct, and facilitating automatic verification.

[0178] In the embodiment, the verification unit only needs to judge whether the error mark appears outside the result judgment layer M of the first type of pattern and whether the error mark appears inside the result judgment layer M of the second type of pattern according to the actual detection result of the unit pattern and the corresponding preset detection result. If any one of the error mark appearing outside the result judgment layer M of the first type of pattern and the error mark not appearing inside the result judgment layer M of the second type of pattern is correct, it means that the design rule detection file is incorrect.

[0179] Specifically, the way of judging whether the first type of pattern all conforms to the spacing design checking rule and the second type of pattern all does not conform to the spacing design checking rule comprises: judging whether the error mark appears inside the result judgment layer M, if the error mark only appears inside the result judgment layer M, it is determined that the design rule detection file is correct, if the error mark does not appear inside the result judgment layer M covering the to-be-detected metal layer Mt or the error mark appears outside the result judgment layer M, it is determined that the design rule detection file is incorrect.

[0180] In the embodiment, the verification instruction is recorded in a verification script. The verification script is an automatic processing script, and thus can perform the full-process automation mode of parameterized unit assignment, unit pattern generation, unit pattern layout, design rule detection, result analysis, and result analysis export, so as to reduce manual intervention.

[0181] Therefore, the verification work of the connection relationship of the back-end metal layer in the DRC is completed by the automatic script, and the human input time and the error risk are effectively reduced. For example, the work time of one day can be reduced to within half an hour.

[0182] It should be noted that, as an example, the design rule detection file verification system is used to execute the design rule detection file verification method provided in the foregoing embodiments, and thus the specific description of the design rule detection file verification system can refer to the related description of the foregoing embodiments.

[0183] Correspondingly, the embodiment of the present application also provides an electronic device, which can load the design rule detection file verification method in the form of a program to implement the design rule detection file verification method provided in the embodiment of the present application.

[0184] Reference Figure 7 , a hardware structure diagram of an electronic device provided by an embodiment of the present application is shown. The device in the embodiment includes at least one processor 01, at least one communication interface 02, at least one memory 03, and at least one communication bus 04.

[0185] In the embodiment, the number of the processor 01, the communication interface 02, the memory 03, and the communication bus 04 is at least one, and the processor 01, the communication interface 02, and the memory 03 complete the communication with each other through the communication bus 04.

[0186] The communication interface 02 can be an interface of a communication module for network communication, for example, an interface of a GSM module.

[0187] The processor 01 can be a central processing unit CPU, or an application specific integrated circuit ASIC, or one or more integrated circuits configured to implement the design rule detection file verification method of the embodiment.

[0188] The memory 03 can include a high-speed RAM memory and can also include a non-volatile memory, such as at least one disk memory. The memory 03 stores one or more computer instructions, which are executed by the processor 01 to implement the verification method of the design rule check file provided by the foregoing embodiments.

[0189] It should be noted that the above-mentioned electronic device can further include other devices (not shown) which can not be necessary for the disclosure of the embodiments of the present application; since these other devices can not be necessary for understanding the disclosure of the embodiments of the present application, the embodiments of the present application do not introduce them one by one.

[0190] The embodiments of the present application also provide a storage medium, which stores one or more computer instructions, the one or more computer instructions being used to implement the verification method of the design rule check file provided by the foregoing embodiments.

[0191] The embodiments of the present application also provide a computer program product, which includes computer instructions, the computer instructions being executed by a processor to implement the verification method of the design rule check file provided by the foregoing embodiments.

[0192] The above-described embodiments of the present application are combinations of elements and features of the present application. Unless otherwise mentioned, elements or features can be considered selective. Each element or feature can be practiced without being combined with other elements or features. Also, the embodiments of the present application can be constructed by combining some of the elements and / or features. The order of the operations described in the embodiments of the present application can be changed. Some constructions of any of the embodiments can be included in another embodiment and can substitute corresponding constructions of another embodiment. It is apparent that the claims that are not explicitly cited in this patent are combinable with each other in the embodiments of the present application, or can be included as new claims after the amendment of the present application.

[0193] The embodiments of the present application can be implemented by various means, for example, hardware, firmware, software, or a combination thereof. In a hardware configuration, the method according to the exemplary embodiments of the present application can be implemented by one or more application specific integrated circuits (ASICs), digital signal processors (DSPs), digital signal processing devices (DSPDs), programmable logic devices (PLDs), field programmable gate arrays (FPGAs), processors, controllers, micro-controllers, microprocessors, etc.

[0194] In firmware or software configurations, embodiments of the application can be implemented as modules, procedures, functions, and so on. Software code can be stored in memory units and executed by processors. The memory unit is located in the processor internally or externally, and can transmit data to and receive data from the processor via various known means.

[0195] The above description of disclosed embodiments of the application allows skilled persons in the art to carry out or use the application. Various modifications to these embodiments will be apparent to those skilled in the art, and the general principles defined herein can be applied to other embodiments without departing from the spirit or scope of the application. Therefore, the application will not be limited to the embodiments shown herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

[0196] Although the present application has been disclosed in its generic form, it is not to be limited to the specific aspects disclosed. Various modifications in form and details of the application as described herein can be made to the application without departing from the spirit and the scope of the application as described herein. The scope of the application is therefore defined by the scope of the appended claims.

Claims

1. A method of verifying a design rule detection file, characterized by, The method comprises the following steps: obtaining first configuration information, including a spacing design checking rule for performing design rule detection, wherein the spacing design checking rule comprises spacing requirements between adjacent metal lines having a connection relationship in a metal layer to be detected; obtaining second configuration information, including a parameterized unit, wherein parameters in the parameterized unit comprise a metal layer option of a connection relationship to be verified and spacing between adjacent metal lines in the metal layer to be detected, the metal layer option corresponds to multiple metal layers having a connection relationship, and one of the multiple metal layers is the metal layer to be detected; performing a verification operation on the design rule detection file according to the design rule detection file, the first configuration information, the second configuration information, and assignment of each parameter in the parameterized unit; wherein the verification operation comprises: traversing assignment of spacing in the parameterized unit to obtain multiple unit patterns having a preset detection result, the metal layer to be detected of the unit pattern comprises adjacent metal lines, and the assignment of spacing comprises a value satisfying the spacing requirement and a value not satisfying the spacing requirement; and performing design rule detection on the multiple unit patterns based on the spacing design checking rule through the design rule detection file to obtain an actual detection result.

2. The method of claim 1, wherein the design rule check file is a design rule check (DRC) file. In the step of obtaining the second configuration information, any metal layer above the metal layer to be detected is used as a connection layer; In the verification operation, combinations of assignment of spacing in the parameterized unit and assignment of the connection layer are traversed to obtain multiple unit patterns having a preset detection result.

3. The method of claim 2, wherein the design rule check file is a design rule check (DRC) file. In the step of traversing combinations of assignment of spacing in the parameterized unit and assignment of the connection layer, each of the metal layers above the metal layer to be detected is used as a connection layer.

4. The method of claim 1, wherein the design rule check file is a design rule check (DRC) file. In the step of obtaining the second configuration information, any metal layer above the metal layer to be detected is used as a connection layer; In the same unit pattern, the extension directions of the remaining metal layers except the connection layer are the same.

5. The method of claim 1, wherein the design rule check file is a design rule check (DRC) file. In the step of obtaining the second configuration information, the parameters in the parameterized unit further comprise a result judgment layer, which is used to cover the metal layer to be detected when the metal layer to be detected does not meet the spacing design checking rule, and is used to cover any remaining metal layer of the multiple metal layers having a connection relationship except the metal layer to be detected when the metal layer to be detected meets the spacing design checking rule. In the step of obtaining multiple unit patterns having a preset detection result, each unit pattern has a result judgment layer, and the result judgment layer covers the metal layer to be detected of the unit pattern not meeting the spacing design checking rule and covers any remaining metal layer of the unit pattern meeting the spacing design checking rule except the metal layer to be detected.

6. The method of verifying a design rule check file according to claim 5, wherein, The verification operation further comprises: verifying the design rule detection file according to the actual detection result of the unit pattern and the corresponding preset detection result. The step of verifying the design rule detection file according to the actual detection result of the unit pattern and the corresponding preset detection result comprises: judging whether an error mark appears in the result judgment layer, if only the error mark appears in the result judgment layer, it is determined that the design rule detection file is correct, if no error mark appears in the result judgment layer or an error mark appears outside the result judgment layer, it is determined that the design rule detection file is incorrect.

7. The method of claim 1, wherein the design rule check file is a design rule check (DRC) file. The metal layer to be detected is a first metal layer in a metal layer layout.

8. The method of claim 1, wherein the design rule check file is a design rule check (DRC) file. In the step of obtaining the second configuration information, the metal layer option of the connection relationship to be verified comprises a first metal layer to a top metal layer in a metal layer layout.

9. The method of claim 1, wherein the design rule check file is a design rule check (DRC) file. The verification operation further comprises: grouping the unit patterns before the design rule detection file based on the spacing design checking rule detects the unit patterns, unit patterns meeting the spacing design checking rule are classified as a first type of pattern, and unit patterns not meeting the spacing design checking rule are classified as a second type of pattern; The design rule detection file based on the spacing design checking rule detects the unit patterns in the first type of pattern and the second type of pattern.

10. The method of verifying a design rule check file according to claim 9, wherein, The verification operation further comprises: verifying the design rule detection file according to the actual detection result of the unit pattern and the corresponding preset detection result; In the step of verifying the design rule detection file according to the actual detection result of the unit pattern and the corresponding preset detection result, if the first type of pattern meets the spacing design checking rule and the second type of pattern does not meet the spacing design checking rule, it is determined that the design rule detection file is correct, otherwise, it is determined that the design rule detection file is incorrect.

11. The method of verifying a design rule check file according to claim 10, wherein, In the step of obtaining the second configuration information, the parameter in the parameterized unit further comprises a result judgment layer, the result judgment layer is used to cover the metal layer to be detected when the metal layer to be detected does not meet the spacing design checking rule, and is used to cover any remaining metal layer except the metal layer to be detected in the multiple metal layers having the connection relationship when the metal layer to be detected meets the spacing design checking rule; In the step of obtaining the multiple unit patterns having the preset detection result, each unit pattern has a result judgment layer, and the result judgment layer covers the metal layer to be detected of the unit pattern not meeting the spacing design checking rule, and covers any remaining metal layer except the metal layer to be detected in the unit pattern meeting the spacing design checking rule; The manner of judging whether the first type of patterns all meet the spacing design checking rule and the second type of patterns all do not meet the spacing design checking rule comprises judging whether an error mark appears inside the result judging layer, if the error mark only appears inside the result judging layer, it is determined that the design rule detection file is correct, if no error mark appears inside the result judging layer or an error mark appears outside the result judging layer, it is determined that the design rule detection file is incorrect.

12. The method of verifying a design rule check file of claim 9, wherein, The verification operation further comprises: before grouping the multiple unit patterns, establishing a first type of pattern library and a second type of pattern library, the first type of pattern library is used to collect the first type of patterns, and the second type of pattern library is used to collect the second type of patterns. In the step of grouping the multiple unit patterns, the first type of patterns are classified into the first type of pattern library, and the second type of patterns are classified into the second type of pattern library.

13. The verification method of a design rule check file according to any one of claims 1 to 12, wherein, Verification instructions for performing the verification operation are generated according to the design rule detection file, the first configuration information, the second configuration information, the assignment of each parameter in the parameterized unit, and output path information of the design rule detection result, so as to perform the verification operation on the design rule detection file.

14. The design rule check file verification method of claim 13, wherein, In the step of generating the verification instructions for performing the verification operation, the verification instructions are recorded in a verification script.

15. A verification system of a design rule check file, characterized by, Comprise: A first configuration module is configured to obtain first configuration information, including a spacing design checking rule used for performing design rule detection, the spacing design checking rule including spacing requirements between adjacent metal lines having a connection relationship in a metal layer to be tested; A second configuration module is configured to obtain second configuration information, including a parameterized unit, parameters in the parameterized unit including a metal layer option of a connection relationship to be verified and spacing between adjacent metal lines in the metal layer to be tested, the metal layer option corresponding to multiple metal layers having a connection relationship, one of the multiple metal layers being the metal layer to be tested; A verification module is configured to perform a verification operation on a design rule detection file according to the design rule detection file, the first configuration information, the second configuration information, and assignment of each parameter in the parameterized unit. The verification operation comprises: traversing assignment of spacing in the parameterized unit to obtain multiple unit patterns having a preset detection result, the metal layer to be tested of the unit pattern including adjacent metal lines, and the assignment of spacing including a value meeting the spacing requirement and a value not meeting the spacing requirement; and performing design rule detection on the multiple unit patterns based on the spacing design checking rule by the design rule detection file to obtain an actual detection result.

16. The design rule check file verification system of claim 15, wherein, In the verification module, the verification operation further comprises: verifying the design rule detection file according to the actual detection result of the unit pattern and the corresponding preset detection result.

17. An apparatus, comprising: An apparatus comprising at least one memory and at least one processor, the memory storing one or more computer instructions, wherein the one or more computer instructions are executable by the processor to implement the method of verifying a design rule check file of any one of claims 1-14.

18. A storage medium, characterized by A storage medium storing one or more computer instructions, the one or more computer instructions being used to implement the method of verifying a design rule check file of any one of claims 1-14.

19. A computer program product, characterised in that, A computer program product comprising computer instructions, the computer instructions being executed by a processor to implement the method of verifying a design rule check file of any one of claims 1-14.

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