Balanced three-valued dynamic logic gate implementation circuit based on memristor

Abstract

The invention discloses a balanced three-valued dynamic logic gate implementation circuit based on memristors. The balanced three-valued dynamic logic gate implementation circuit comprises a balanced three-valued dynamic NOT gate circuit, a balanced three-valued dynamic NOR gate circuit and a balanced three-valued dynamic NAND gate circuit which are implemented according to the memristors. The dynamic logic circuit provided by the invention is widely applied to the design of a super-large-scale integrated circuit, and can reduce the circuit area and improve the circuit speed.

Description

TECHNICAL FIELD

[0001] The application belongs to the technical field of circuit design, and particularly relates to a balanced ternary dynamic circuit based on a memristor. BACKGROUND

[0002] Chua proposed the concept of memristor according to the completeness of circuit theory. He pointed out that voltage, current, charge and magnetic flux are four basic variables in electrical theory, and there are six mathematical relationships between any two of them. However, only five of them are used in modern circuits. According to the completeness and symmetry of the circuit variables, it is inferred that there should be another element besides resistance, capacitance and inductance to represent the corresponding relationship between magnetic flux and charge, which is named as memristor. The memristor is a new type of circuit element with memory characteristics and non-linear characteristics, which is the fourth basic circuit element parallel to the traditional circuit elements of resistance, capacitance and inductance. Until 2008, HP laboratory successfully prepared the first memristor physical device, which promoted the "memristor" from a theoretical concept to a physical realization, and aroused widespread attention in the academic community to the related research on memristor.

[0003] Compared with binary logic, ternary logic can increase the data processing capacity per unit area, reduce power consumption, and reduce the number of active elements. At the same time, the ternary logic with a base of 3 is close to the exponential base (e=2.718), which helps to achieve more compact and energy-efficient information coding mode. In addition, the information carrying capacity of each wire is enhanced on the same wire or for the same bit. For example, a 3-bit counter using binary logic has a total of 8 possible states, while for ternary logic, the total number of possible states is 27. Ternary logic includes balanced and unbalanced types, and unbalanced ternary logic is divided into positive ternary {0, 1, 2} and negative ternary {0, -1, -2}. Since the two have symmetry in logic states, the methods used in digital logic circuit design are similar. Balanced ternary {-1, 0, 1} combines positive ternary logic "1" and negative ternary logic "-1", so it can directly represent negative numbers without additional symbols.

[0004] Dynamic logic circuits are widely used in very large scale integrated circuit design to reduce circuit area and improve circuit speed. In binary digital systems, dynamic logic circuits can reduce the number of transistors compared to traditional static CMOS circuits. By removing a CMOS logic network and adding a clock-controlled PMOS and NMOS, the number of transistors is reduced from 2N in static to N+2. Due to the reduction in the number of transistors and the absence of short-circuit current in dynamic gates, dynamic logic circuits have faster switching speed. In addition, in digital circuits, dynamic circuits can make the circuit not work at a certain time by introducing a clock pulse to achieve the purpose of reducing circuit power consumption. SUMMARY

[0005] The present application provides a balanced ternary dynamic logic gate implementation circuit based on a memristor, which comprises a balanced ternary dynamic NOT gate circuit, a balanced ternary dynamic NOR gate circuit and a balanced ternary dynamic NAND gate circuit realized based on a memristor.

[0006] A balanced ternary dynamic NOT gate circuit based on a memristor comprises a dynamic standard ternary inverter (STI), a dynamic positive ternary inverter (PTI) and a dynamic negative ternary inverter (NTI).

[0007] The dynamic standard ternary inverter (STI) comprises a first memristor M1, three NMOS tubes and two PMOS tubes and a capacitor C L ;

[0008] The three NMOS tubes are a first NMOS tube N1, a second NMOS tube N2 and a third NMOS tube N3 respectively;

[0009] The two PMOS tubes are a first PMOS tube P1 and a second PMOS tube P2 respectively;

[0010] The source (S) of the first PMOS tube P1 is connected with a power supply V DD , the gate (G) of the first PMOS tube P1 is connected with a clock control signal CP, and the drain (D) of the first PMOS tube P1 is connected with the source (S) of the second PMOS tube P2;

[0011] The drain (D) of the second PMOS tube P2 is connected with the negative electrode of the first memristor M1;

[0012] The gate (G) of the second PMOS tube P2 and the gate (G) of the second NMOS tube N2 are connected with an input terminal V in respectively;

[0013] The positive electrode of the first memristor M1 is connected with the drain (D) of the second NMOS tube N2;

[0014] The gate (G) of the first NMOS tube N1 is connected with a clock control signal , and the source (S) of the first NMOS tube N1 is connected with a power supply-V DD ;

[0015] The source (S) of the second NMOS tube N2 is connected with the drain (D) of the first NMOS tube N1;

[0016] The drain (D) of the third NMOS tube N3 is connected with the drain (D) of the second PMOS tube P2, the negative electrode of the first memristor M1 and one end of the capacitor C L respectively, and serves as an output terminal Vout The gate (G) of the third NMOS transistor N3 is connected with the clock control signal CP, the source (S) of the third NMOS transistor N3 is connected with one end of the capacitor C L , and the other end is connected with the ground.

[0017] The dynamic positive ternary inverter (PTI) comprises two memristors, three NMOS transistors, a third PMOS transistor P3 and a capacitor C L .

[0018] The two memristors are respectively a second memristor M2 and a third memristor M3; the three NMOS transistors are respectively a fourth NMOS transistor N4, a fifth NMOS transistor N5 and a sixth NMOS transistor N6.

[0019] The anode of the second memristor M2 is connected with the drain (D) of the fifth NMOS transistor N5.

[0020] The cathode of the third memristor M3 is connected with the drain (D) of the fourth NMOS transistor N4.

[0021] The gate (G) of the fourth NMOS transistor N4 is connected with the clock control signal , and the source (S) of the fourth NMOS transistor N4 is connected with the power supply-V DD .

[0022] The gate (G) of the fifth NMOS transistor N5 is connected with the input end V in , and the source (S) of the fifth NMOS transistor N5 is connected with the anode of the third memristor M3.

[0023] The drain (D) of the sixth NMOS transistor N6 is connected with the anode of the second memristor M2 and one end of the capacitor C L respectively, and serves as an output end V out , the gate (G) of the sixth NMOS transistor N6 is connected with the clock control signal CP, and the source (S) of the sixth NMOS transistor N6 is connected with the other end of the capacitor C L and the ground.

[0024] The source (S) of the third PMOS transistor P3 is connected with the power supply V DD , the gate (G) of the third PMOS transistor P3 is connected with the clock control signal CP, and the drain (D) of the third PMOS transistor P3 is connected with the cathode of the second memristor M2.

[0025] The dynamic negative ternary inverter (NTI) comprises two memristors, two NMOS transistors, two PMOS transistors and a capacitor C L .

[0026] The two memristors are the fourth memristor M4 and the fifth memristor M5; the two NMOS transistors are the seventh NMOS transistor N7 and the eighth NMOS transistor N8; and the two PMOS transistors are the fourth PMOS transistor P4 and the fifth PMOS transistor P5.

[0027] The negative terminal of the fourth memristor M4 is connected to the source (S) of the fifth PMOS transistor P5.

[0028] The positive terminal of the fifth memristor M5 is connected to the drain (D) of the seventh NMOS transistor N7;

[0029] The gate (G) of the seventh NMOS transistor N7 is connected to the clock control signal. The source (S) of the seventh NMOS transistor N7 is connected to the power supply -V. DD Connected;

[0030] The drain (D) of the eighth NMOS transistor N8 is connected to the drain (D) of the fifth PMOS transistor P5, the negative terminal of the fifth memristor M5, and the capacitor C, respectively. L One end is connected and serves as the output terminal V. out The gate (G) of the eighth NMOS transistor N8 is connected to the clock control signal CP, and the source (S) of the eighth NMOS transistor N8 is connected to the capacitor C. L The other end is connected to the ground;

[0031] The source (S) of the fourth PMOS transistor P4 is connected to the power supply V. DD The gate (G) of the fourth PMOS transistor P4 is connected to the clock control signal CP, and the drain (D) of the fourth PMOS transistor P4 is connected to the positive terminal of the fourth memristor M4.

[0032] The gate (G) of the fifth PMOS transistor P5 is connected to the input terminal V. in The drain (D) of the fifth PMOS transistor P5 is connected to the negative terminal of the fifth memristor M5.

[0033] The present invention also provides a balanced ternary dynamic NOR gate circuit based on memristors, comprising two memristors, three PMOS transistors, four NMOS transistors, and a capacitor C. L ;

[0034] The two memristors are respectively the first memristor M 10 Second memristor M 11 The three PMOS transistors are the first PMOS transistor P8, the second PMOS transistor P9, and the third PMOS transistor P... 10 The four NMOS transistors are respectively the first NMOS transistor N 12 The second NMOS transistor N 13 The third NMOS transistor N14 and the fourth NMOS transistor N 15 ;

[0035] the positive electrode of the first memristor M 10 is connected with the drain (D) of the second PMOS transistor P9 and the drain (D) of the third PMOS transistor P 10 , and the negative electrode of the first memristor M 10 is connected with the negative electrode of the second memristor M 11 ;

[0036] the positive electrode of the second memristor M 11 is connected with the drain (D) of the second NMOS transistor N 13 and the drain (D) of the third NMOS transistor N 14 ;

[0037] the source (S) of the first PMOS transistor P8 is connected with the power supply V DD , the gate (G) of the first PMOS transistor P8 is connected with the clock control signal CP, and the drain (D) of the first PMOS transistor P8 is connected with the source (S) of the second PMOS transistor P9 and the source (S) of the third PMOS transistor P 10 ;

[0038] the gate (G) of the second PMOS transistor P9 is connected with the input end B;

[0039] the gate (G) of the third PMOS transistor P 10 is connected with the input end A;

[0040] the drain (D) of the first NMOS transistor N 12 is connected with the source (S) of the second NMOS transistor N 13 and the source (S) of the third NMOS transistor N 14 , the gate (G) of the first NMOS transistor N 12 is connected with the clock signal , the source (S) of the first NMOS transistor N 12 is connected with the power supply -V DD ;

[0041] the gate (G) of the second NMOS transistor N 12 is connected with the input end A;

[0042] the gate (G) of the third NMOS transistor N 14 is connected with the input end B;

[0043] the drain (D) of the fourth NMOS transistor N 15 is connected with the positive electrode of the first memristor M 10 , the negative electrode of the second memristor M 11negative electrode of the first memristor M6 and the negative electrode of the second memristor M7 are connected with the gate (G) of the second PMOS tube P7, the positive electrode of the first memristor M6 and the positive electrode of the second memristor M7 are connected with the input end A and the input end B respectively. L One end is connected, and the fourth NMOS tube N 15 The gate (G) of the fourth NMOS tube N 14 The source (S) of the fourth NMOS tube N L The other end is connected with the ground.

[0044] The application also provides a balanced ternary dynamic NAND gate circuit based on a memristor, comprising four memristors, two PMOS tubes, three NMOS tubes and a capacitor C L ;

[0045] The four memristors are a first memristor M6, a second memristor M7, a third memristor M8 and a fourth memristor M9 respectively.

[0046] The two PMOS tubes are a first PMOS tube P6 and a second PMOS tube P7 respectively.

[0047] The three NMOS tubes are a first NMOS tube N9, a second NMOS tube N 10 and a third NMOS tube N 11 ;

[0048] The negative electrode of the first memristor M6 and the negative electrode of the second memristor M7 are connected with the gate (G) of the second PMOS tube P7, the positive electrode of the first memristor M6 and the positive electrode of the second memristor M7 are connected with the input end A and the input end B respectively.

[0049] The positive electrode of the third memristor M8 and the positive electrode of the fourth memristor M9 are connected with the gate (G) of the second NMOS tube N 10 , the negative electrode of the third memristor M8 and the negative electrode of the fourth memristor M9 are connected with the input end A and the input end B respectively.

[0050] The source (S) of the first PMOS tube P6 is connected with the power supply V DD , the gate (G) of the first PMOS tube P6 is connected with the clock control signal CP, the drain (D) of the first PMOS tube P6 is connected with the source (S) of the second PMOS tube P7,

[0051] The drain (D) of the second PMOS tube P7 is connected with the drain (D) of the second NMOS tube N 10 .

[0052] The gate (G) of the first NMOS tube N9 is connected with the clock signal , the source (S) of the first NMOS tube N9 is connected with the power supply-V DD .

[0053] The gate (G) of the second NMOS tube N10 The source (S) of the first NMOS transistor N9 is connected with the drain (D) of the source (S) of the first NMOS transistor N9;

[0054] The third NMOS transistor N 11 The drain (D) of the second NMOS transistor N 10 The drain (D) of the second PMOS transistor P7 and the capacitor C L One end is connected with the drain (D) of the second PMOS transistor P7 and the capacitor C 11 The gate (G) of the third NMOS transistor N 11 The source (S) of the third NMOS transistor N L The other end is connected with the ground.

[0055] The present application has the advantages that:

[0056] The present application combines the advantages of the memristor and the ternary logic, and provides a balanced ternary dynamic logic circuit scheme based on a binary memristor, specifically including a balanced ternary dynamic NOT gate (STI, PTI and NTI), a dynamic NAND gate (TNAND) and a dynamic NOR gate (TNOR) circuit, which provides a certain reference for the design of the ternary dynamic logic circuit. The dynamic logic circuit provided by the present application is widely applied to the design of a very large scale integrated circuit, and can reduce the circuit area and improve the circuit speed. In a digital circuit, the dynamic circuit can be inactivated at a certain time by introducing a clock pulse, so as to reduce the power consumption of the circuit. BRIEF DESCRIPTION OF DRAWINGS

[0057] The above and / or other aspects of the present application will become apparent and more readily appreciated from the following description, taken in conjunction with the accompanying drawings, in which:

[0058] Fig. 1(a) is a dynamic standard ternary inverter circuit diagram in a balanced ternary dynamic NOT gate circuit;

[0059] Fig. 1(b) is a dynamic positive ternary inverter circuit diagram in a balanced ternary dynamic NOT gate circuit;

[0060] Fig. 1(c) is a dynamic negative ternary inverter circuit diagram in a balanced ternary dynamic NOT gate circuit;

[0061] Figure 2 is a balanced ternary dynamic NOR gate circuit based on a memristor;

[0062] Figure 3 is a balanced ternary dynamic NAND gate circuit based on a memristor. DETAILED DESCRIPTION

[0063] In a specific embodiment of the present application, the voltage V DD1V, corresponding to logic 1, voltage -1V, corresponding to logic -1, ground GND 0V, corresponding to logic 0. Clock signal CP is a binary signal (-1, 1). Balanced ternary dynamic circuit works in two stages, one is precharge stage, two is evaluation stage. DD 1V, corresponding to logic 1, voltage -1V, corresponding to logic -1, ground GND 0V, corresponding to logic 0. Clock signal CP is a binary signal (-1, 1). Balanced ternary dynamic circuit works in two stages, one is precharge stage, two is evaluation stage.

[0064] A balanced ternary dynamic NOT gate circuit based on memristor designed in this embodiment is shown in Figure 1(a), Figure 1(b), Figure 1(c), wherein Figure 1(a) is a dynamic standard ternary inverter (STI) circuit diagram. In the STI circuit, the threshold voltage v N1 of the first NMOS tube N1 and the threshold voltage v N3 of the third NMOS tube N3 satisfy 0V < v N1 ≤ V DD , 0V < v N3 ≤ V DD , the threshold voltage v N2 of the second NMOS tube N2 satisfies V DD < v N2 ≤ 2V DD ; the threshold voltage v P1 of the first PMOS tube P1 satisfies -V DD ≤ v P1 < 0V, and the threshold voltage of the second PMOS tube P2 satisfies -2V DD ≤ v P2 < -V DD . Figure 1(b) is a dynamic positive ternary inverter (PTI) circuit;

[0065] In the PTI circuit, the threshold voltage v N5 of the fifth NMOS tube N5 and the threshold voltage v N6 of the sixth NMOS tube N6 satisfy 0 < v N5 ≤ V DD , 0 < v N6 ≤ V DD , the threshold voltage v N4 of the fourth NMOS tube N4 satisfies V DD < v N4 ≤ 2V DD ; the threshold voltage v P3 of the third PMOS tube P3 satisfies -V DD ≤ v P3 < 0V.

[0066] Figure 1(c) is a dynamic negative ternary inverter (NTI) circuit, in which the threshold voltage v N7 of the seventh NMOS tube N7 and the threshold voltage v N8 of the eighth NMOS tube N8 satisfy 0 < v N7 ≤ VDD , 0 < v N8 < V DD ; the threshold voltage of the fourth PMOS transistor P4 satisfies -2V DD ≤ v P4 < 0V, the threshold voltage of the fifth PMOS transistor P5 satisfies -2V DD ≤ v P5 < -V DD .

[0067] The truth table of the balanced ternary NOT gate is shown in Table 1 below, wherein v in represents the input signal of the NOT gate, STI, PTI and NTI represent the outputs of the three NOT gates respectively.

[0068] Table 1

[0069]

[0070] From the input and output relationship of the above truth table and the diagram 1(a), the working principle of the dynamic STI circuit is as follows:

[0071] (1) Pre-charge phase: when CP = V DD (logical "1"), the pre-charge transistor N3 is turned on, the evaluation transistors P1 and N1 are turned off, and the output v out passes through N3 and is connected to the ground terminal GND, i.e. the output v out = 0.

[0072] (2) Evaluation phase: when CP = -V DD (logical "-1"), the pre-charge transistor N3 is turned off, the evaluation transistors P1 and N1 are turned on, and the output v out is determined by the input signal v in .

[0073] When the input v in = -1, the second NMOS transistor N2 is turned off, the second PMOS transistor P2 is turned on, and the output v out passes through the first PMOS transistor P1 and the second PMOS transistor P2 and is connected to V DD , i.e. the output v out = 1.

[0074] When the input v in = 0, the second NMOS transistor N2 and the second PMOS transistor P2 are both turned off, at this time the output terminal is discharged to the ground terminal GND through the capacitor C L , the output pre-charge state "0" is output, i.e. v out = 0;

[0075] When the input v in = 1, the second NMOS transistor N2 is turned on, the second PMOS transistor P2 is turned off, and the output v outThrough the first memristor M1 and the first NMOS tube N1, the second NMOS tube N2 and the -V DD Connected, that is, v out =-1.

[0076] From the above truth table input and output relationship combined with Fig. 1(b), the working principle of the dynamic PTI circuit is as follows:

[0077] (1) Precharge phase: when CP=V DD (Logical "1"), the precharge tube N3 is turned on, the evaluation tube P3, N4 is cut off, and the output v out Through the sixth NMOS tube N6 connected with the ground terminal GND, that is, the output v out =0.

[0078] (2) Evaluation phase: when CP=-V DD (Logical "-1"), the precharge tube N6 is cut off, the evaluation tube P3, N4 is turned on, and the output v out Is determined by the input signal v in .

[0079] When the input v in =-1, the fifth NMOS tube N5 is cut off, and the output v out Through the pull-up resistor composed of the second memristor M2 and V DD Connected, that is, v out =1;

[0080] When the input v in =-0, the fifth NMOS tube N5 is cut off, and the output v out Through the pull-up resistor composed of the second memristor M2 and V DD Connected, that is, v out =1;

[0081] When the input v in =1, the fifth NMOS tube N5 is turned on, and the current in the circuit flows from VDD to -V DD Through the second memristor M2 and the third memristor M3, because the positive poles of the second memristor M2 and the third memristor M3 in the circuit are connected to form a "minimum value" circuit, according to the working principle of the "minimum value" circuit, when the input is V DD And -V DD , the output minimum voltage is -V DD , so the output voltage of v out -VDD, that is, v out =-1.

[0082] From the above truth table input and output relationship combined with Fig. 1(c), the working principle of the dynamic NTI circuit is as follows:

[0083] (1) Precharge phase: when CP=VDD (Logic "1"), the pre-charge tube N8 is turned on, the evaluation tube P4, N7 is turned off, and the output is connected to the ground terminal GND, that is, the output vout=0.

[0084] (2) Evaluation stage: when CP=-V DD (Logic "-1"), the pre-charge tube N8 is turned off, the evaluation tube P4, N7 is turned on, and the output v out . in is determined by the input signal v in .

[0085] When the input v DD =-1, the fifth PMOS tube P5 is turned on, and the current flows from V DD to-V DD through the fourth memistor M4 and the fifth memistor M5. DD Since the fourth memistor M4 and the fifth memistor M5 are connected at the negative terminal to form a "maximum" circuit in the circuit, according to the working principle of the "maximum" circuit, when the input is V DD and-V out , the maximum output voltage V DD is output, so the output v out =1.

[0086] When the input v in =0, the fifth PMOS tube P5 is turned off, and the output v out is connected to-V DD through the fifth memistor M5 and the seventh NMOS tube N7, that is, the output v out =-1.

[0087] When the input v in =1, the fifth PMOS tube P5 is turned off, and the output v out is connected to-V DD through the fifth memistor M5 and the seventh NMOS tube N7, that is, the output v out =-1.

[0088] In the embodiment of the present application, a balanced ternary dynamic or non-inverter circuit based on a memistor is provided, as shown in FIG. Figure 2 The truth table of the balanced ternary or non-inverter is shown in Table 2, wherein A and B represent the input signals of the non-inverter, and TNOR represents the output of the non-inverter. In the circuit, the threshold voltage v P1 of the first PMOS tube P8 satisfies-V DD ≤v P1 <0V, the threshold voltage v P2 of the second PMOS tube P9 and the threshold voltage v 10 of the third PMOS tube P P3 satisfy-2V DD ≤vP2 <-V DD -2V DD ≤v P3 <-V DD ; First NMOS transistor N 12 Threshold voltage v N1 and the fourth NMOS transistor N 15 Threshold voltage v N4 Satisfy 0 <v N1 ≤V DD 0 <v N4 ≤V DD The second NMOS transistor N 13 Threshold voltage v N2 and the third NMOS transistor N 14 Threshold voltage v N3 Satisfy V DD <v N2 ≤2V DD V DD <v N3 ≤2V DD .

[0089] Table 2

[0090]

[0091] According to the truth table of a balanced ternary NOR gate, different combinations of input signals "-1", "0", and "1" will result in corresponding outputs of logic "-1", "0", and "1". The input and output relationships described in the truth table can then be combined... Figure 3 It can be seen that the working principle of the balanced three-valued dynamic NOR gate is as follows:

[0092] (1) Pre-charge stage: when CP = V DD When (logic "1"), the precharge transistor N 15 Conducting, evaluating transistors P8 and N 12 Cutoff, output after N 15 When connected to the ground terminal GND, the output is logic "0".

[0093] (2) Evaluation stage: When CP = -V DD When (logic "-1"), the precharge transistor N 15 Deadline: Values ​​are being evaluated on pipes P8 and N. 12 When the circuit is on, the output TNOR is determined by the input signals A and B.

[0094] When input A = -1 and B = -1, the second PMOS transistor P9 and the third PMOS transistor P... 10 Turn on, the second NMOS transistor N 13 and the third NMOS transistor N 14 Cut off, the output is connected to the power supply V via a pull-up network.DD connected, output is logic "1".

[0095] When input A = -1, B = 0, the second PMOS P9 is off, the third PMOS P 10 is on, the second NMOS N 13 and the third NMOS N 14 are off, the output is connected to the power supply V DD through the pull-up network, and the output is logic "1".

[0096] When input A = -1, B = 1, the second PMOS P9 is on, the third PMOS P 10 is off, the second NMOS N 13 is off, the third NMOS N 14 is on, the circuit passes through the second PMOS P9 and the third NMOS N 14 to connect V DD to -V DD to form a path, and the current flows from the first memristor M 10 to the second memristor M 11 , and the resistance is switched to R OFF state. The output end outputs 0V after voltage division by the two memristors, that is, the output is logic "0".

[0097] When input A = 0, B = -1, the second PMOS P9 is off, the third PMOS P 10 is on, the second NMOS N 13 and the third NMOS N 14 are off, the output is connected to the power supply V DD through the pull-up network, and the output is logic "1".

[0098] When input A = 0, B = 0, the second PMOS P9, the third PMOS P 10 , the second NMOS N 13 and the third NMOS N 14 are all off, and the output end is discharged to the ground end GND through the capacitor, that is, the output is logic "0".

[0099] When input A = 0, B = 1, the PMOS P9, the third PMOS P 10 and the second NMOS N 13 are all off, the third NMOS N 14 is on, and the output is connected to the power supply -V DD through the pull-down network, and the output is logic "-1".

[0100] When input A = 1, B = -1, the second PMOS P9 is off, the third PMOS P 10On, the second NMOS transistor N 13 On, the third NMOS transistor N 14 Off, the circuit passes through the third PMOS transistor P 10 and the second NMOS transistor N 13 On, the current from V DD to -V DD forms a path, the current from the first memristor M 10 flows to the second memristor M 11 , and the resistance switches to R OFF State. The output is 0V after being divided by the two memristors, that is, the output is logic "0".

[0101] When the input A=1, B=0, the second PMOS transistor P9, the third PMOS transistor P 10 and the third NMOS transistor N 14 are all off, the second NMOS transistor N 13 is on, and the output is connected to the power supply -V DD through the pull-down network, and the output is logic "-1".

[0102] When the input A=1, B=1, the second PMOS transistor P9 and the third PMOS transistor P 10 are off, the third NMOS transistor N 14 and the second NMOS transistor N 13 are on, and the output is connected to the power supply -V DD through the pull-down network, and the output is logic "-1".

[0103] An embodiment of the present application provides a balanced ternary dynamic NAND gate circuit based on a memristor, as shown in Figure 3 The truth table of the balanced ternary NAND gate is shown in Table 3, where A and B represent the input signals of the NAND gate, and TNAND represents the output of the NAND gate. In the circuit, the threshold voltage v P1 of the first PMOS transistor P6 satisfies -V DD ≤v P1 <0V, the threshold voltage v P2 of the second PMOS transistor P7 satisfies -2V DD ≤v P2 <-V DD , the threshold voltage v N1 of the first NMOS transistor N9 and the threshold voltage v 11 of the third NMOS transistor N N3 satisfy 0<v N1 ≤V DD , 0<v N3 ≤V DD , and the threshold voltage v 10 of the second NMOS transistor N N2 satisfies V DD<v N2 ≤2V DD .

[0104] Table 3

[0105]

[0106] According to the balanced ternary "NAND" gate truth table, it can be known that different input signal "-1", "0" and "1" combinations can make the corresponding output end be logic "-1", "0" and "1". The input and output relationship of the above truth table is combined Figure 2 It can be known that the working principle of the balanced ternary dynamic NAND gate circuit is as follows:

[0107] (1) Precharge stage: when CP = V DD (logic "1"), the precharge tube N 11 is turned on, the evaluation tube P6, N9 is cut off, and the output is connected to the ground end GND through N 11 , that is, the output is logic "0".

[0108] (2) Evaluation stage: when CP = -V DD (logic "-1"), the precharge tube N 11 is cut off, the evaluation tube P6, N9 is turned on, and the output TNAND is determined by the input signals A and B.

[0109] When input A = -1, B = -1, the "maximum" gate and "minimum" gate composed of the first memistor M6, the second memistor M7, the third memistor M8 and the fourth memistor M9 output "-1". At this time, according to the threshold voltage of the transistor, the PMOS tube P7 is turned on, the NMOS tube N 10 is cut off, the output is connected to the power supply V DD through PMOS tubes P6 and P7, and the output is logic "1".

[0110] When input A = -1, B = 0, the "maximum" gate and "minimum" gate composed of the memristors M6 and M7, M8 and M9 output "0" and "-1" respectively. At this time, according to the threshold voltage of the transistor, the PMOS tube P7 is cut off, the NMOS tube N 10 is cut off, and at this time the circuit does not form a path, and the output is discharged through the capacitor C L , and the output is the precharge value logic "0".

[0111] When input A = -1, B = 1, the "maximum" gate and "minimum" gate composed of the memristors M6 and M7, M8 and M9 output "1" and "-1" respectively. At this time, according to the threshold voltage of the transistor, the PMOS tube P7 is cut off, the NMOS tube N 10 is cut off, and at this time the circuit does not form a path, and the output is discharged through the capacitor C LDischarge, output is pre-charge value logic "0".

[0112] When input A=0, B=-1, the "max" gate and "min" gate composed of memristors M6 and M7, M8 and M9 output "0" and "-1" respectively. At this time, according to the threshold voltage of the transistor, PMOS P7 is off, NMOS N 10 off, at this time the circuit does not form a path, the output through the capacitor C L Discharge, output is pre-charge value logic "0".

[0113] When input A=0, B=0, the "max" gate and "min" gate composed of memristors M6 and M7, M8 and M9 output "0" and "0" respectively. At this time, according to the threshold voltage of the transistor, PMOS P7 is off, NMOS N 10 off, at this time the circuit does not form a path, the output through the capacitor C L Discharge, output is pre-charge value logic "0".

[0114] When input A=0, B=1, the "max" gate and "min" gate composed of memristors M6 and M7, M8 and M9 output "1" and "0" respectively. At this time, according to the threshold voltage of the transistor, PMOS P7 is off, NMOS N 10 off, at this time the circuit does not form a path, the output through the capacitor C L Discharge, output is pre-charge value logic "0".

[0115] When input A=1, B=-1, the "max" gate and "min" gate composed of memristors M6 and M7, M8 and M9 output "1" and "-1" respectively. At this time, according to the threshold voltage of the transistor, PMOS P7 is off, NMOS N 10 off, at this time the circuit does not form a path, the output through the capacitor C L Discharge, output is pre-charge value logic "0".

[0116] When input A=1, B=0, the "max" gate and "min" gate composed of memristors M6 and M7, M8 and M9 output "1" and "0" respectively. At this time, according to the threshold voltage of the transistor, PMOS P7 is off, NMOS N 10 off, at this time the circuit does not form a path, the output through the capacitor C L Discharge, output is pre-charge value logic "0".

[0117] When input A=1, B=1, the "max" gate and "min" gate composed of memristors M6 and M7, M8 and M9 output "1". At this time, PMOS P7 is off, NMOS N 10Conduct, output through N9, N 10 Connected with power supply-V DD Connected with power supply-V

[0118] The application provides a balanced ternary dynamic circuit based on a memristor. There are many methods and approaches to realize the technical scheme, and the above description is only the preferred embodiment of the application. It should be pointed out that, for ordinary skilled persons in the technical field, some improvements and refinements can be made without departing from the principle of the application, and these improvements and refinements should also be regarded as the protection scope of the application. The components not explicitly described in the embodiment can be realized by using the existing technology.

Claims

1. A memristor-based balanced ternary dynamic logic gate implementation circuit, characterized in that, The balanced ternary dynamic NOT gate circuit, the balanced ternary dynamic OR gate circuit and the balanced ternary dynamic NAND gate circuit are realized according to a memristor.

2. The memristor-based balanced ternary dynamic logic gate implementation circuit according to claim 1, characterized in that, The balanced ternary dynamic NOT gate circuit comprises a dynamic standard ternary inverter STI, a dynamic positive ternary inverter PTI and a dynamic negative ternary inverter NTI.

3. The memristor-based balanced ternary dynamic logic gate implementation circuit of claim 2, wherein, The dynamic standard ternary inverter STI is specifically implemented as follows: The source of the first PMOS transistor P1 is connected to a power supply V DD The gate of the first PMOS transistor P1 is connected to a clock control signal CP, and the drain of the first PMOS transistor P1 is connected to the source of the second PMOS transistor P2. The drain of the second PMOS transistor P2 is connected to the negative electrode of the first memristor Ml; the gate of the second PMOS transistor P2 and the gate of the second NMOS transistor N2 are respectively connected to the input end V in in. The positive electrode of the first memristor M1 is connected with the drain electrode of the second NMOS transistor N2; the gate electrode of the first NMOS transistor N1 is connected with a clock control signal CP, the source electrode of the first NMOS transistor N1 is connected with a power supply-V DD are connected together. The source of the second NMOS transistor N2 is connected with the drain of the first NMOS transistor N1; the drain of the third NMOS transistor N3 is respectively connected with the drain of the second PMOS transistor P2, the negative electrode of the first memristor M1 and one end of the capacitor C L connected with each other and as an output terminal V out The gate of the third NMOS transistor N3 is connected with a clock control signal CP, and the source of the third NMOS transistor N3 is connected with the capacitor C L The other end of the capacitor C is connected with the ground.

4. The memristor-based balanced ternary dynamic logic gate implementation circuit of claim 2, wherein, The dynamic positive ternary inverter PTI is specifically implemented as follows: The positive electrode of the second memristor M2 is connected with the drain electrode of the fifth NMOS tube N5, and the negative electrode of the third memristor M3 is connected with the drain electrode of the fourth NMOS tube N4; The gate of the fourth NMOS transistor N4 is connected with the clock control signal CP, and the source of the fourth NMOS transistor N4 is connected with the power supply-V DD are connected together. The gate of the fifth NMOS transistor N5 is connected to the input terminal V in The source of the fifth NMOS transistor N5 is connected to the anode of the third memristor M3, The drain of the sixth NMOS transistor N6 is connected with the anode of the second memristor M2 and the capacitor C L One end is connected and serves as an output terminal V out The gate of the sixth NMOS transistor N6 is connected with a clock control signal CP, and the source of the sixth NMOS transistor N6 is connected with the capacitor C L The other end is connected with the ground The source of the third PMOS transistor P3 is connected to the power supply V DD The gate of the third PMOS transistor P3 is connected to the clock control signal CP, and the drain of the third PMOS transistor P3 is connected to the negative electrode of the second memristor M2.

5. The memristor-based balanced ternary dynamic logic gate implementation circuit of claim 2, wherein, The dynamic negative ternary inverter NTI is specifically implemented as follows: The negative electrode of the fourth memristor M4 is connected with the source electrode of the fifth PMOS tube P5, and the positive electrode of the fifth memristor M5 is connected with the drain electrode of the seventh NMOS tube N7; The gate of the seventh NMOS transistor N7 is connected with the clock control signal CP, and the source of the seventh NMOS transistor N7 is connected with the power supply-V DD are connected together; The drain of the eighth NMOS transistor N8 is connected with the drain of the fifth PMOS transistor P5, the negative pole of the fifth memristor M5 and the capacitor C L One end is connected and serves as an output terminal V out The gate of the eighth NMOS transistor N8 is connected with a clock control signal CP, and the source of the eighth NMOS transistor N8 is connected with the capacitor C L The other end is connected with the ground The source of the fourth PMOS transistor P4 is connected with the power supply V DD The gate of the fourth PMOS transistor P4 is connected with the clock control signal CP, and the drain of the fourth PMOS transistor P4 is connected with the anode of the fourth memristor M4. The gate of the fifth PMOS transistor P5 is connected to the input terminal V in are connected.

6. The memristor-based balanced ternary dynamic logic gate implementation circuit of claim 1, wherein, The balanced ternary dynamic OR gate circuit is specifically implemented as follows: The positive electrode of the first memristor M 10 is connected with the drain electrode of the second PMOS tube P9 and the drain electrode of the third PMOS tube P 10 , and the negative electrode of the first memristor M 10 is connected with the positive electrode of the second memristor M 11 . The second memistor M 11 The anode of the second NMOS transistor N 13 The drain of the third NMOS transistor N 14 is connected with the drain of the second NMOS transistor N The source of the first PMOS transistor P8 is connected to the power supply V DD The gate of the first PMOS transistor P8 is connected to the clock control signal CP, and the drain of the first PMOS transistor P8 is connected to the source of the second PMOS transistor P9 and the source of the third PMOS transistor P 10 10 respectively. The gate of the second PMOS transistor P9 is connected with the input terminal B; the gate of the third PMOS transistor P 10 is connected with the input terminal A; The drain of the first NMOS transistor N 12 is connected with the source of the second NMOS transistor N 13 and the source of the third NMOS transistor N 14 respectively, the gate of the first NMOS transistor N 12 is connected with the clock signal CP, the source of the first NMOS transistor N 12 is connected with the power supply-V DD . The gate of the second NMOS transistor N 12 is connected to the input terminal A; the gate of the third NMOS transistor N 14 is connected to the input terminal B; The drain of the fourth NMOS transistor N 15 is connected with the positive pole of the first memristor M 10 , the negative pole of the second memristor M 11 and one end of the capacitor C L , and serves as an output terminal TNOR. The gate of the fourth NMOS transistor N 15 is connected with a clock signal CP. The source of the fourth NMOS transistor N 14 is connected with the other end of the capacitor C L and the ground.

7. The memristor-based balanced ternary dynamic logic gate implementation circuit of claim 1, wherein, The balanced ternary dynamic NAND gate circuit is specifically implemented as follows: The negative electrode of the first memristor M6 and the negative electrode of the second memristor M7 are respectively connected with the gate electrode of the second PMOS tube P7, and the positive electrode of the first memristor M6 and the positive electrode of the second memristor M7 are respectively connected with the input end A and the input end B. The positive electrode of the third memristor M8 and the positive electrode of the fourth memristor M9 are connected with the gate of the second NMOS tube N 10 , respectively, and the negative electrode of the third memristor M8 and the negative electrode of the fourth memristor M9 are connected with the input end A and the input end B, respectively. The source of the first PMOS transistor P6 is connected to a power supply V DD The gate of the first PMOS transistor P6 is connected to a clock control signal CP, and the drain of the first PMOS transistor P6 is connected to the source of the second PMOS transistor P7. The drain of the second PMOS transistor P7 is connected to the drain of the second NMOS transistor N 10 . The gate of the first NMOS transistor N9 is connected with the clock signal CP, and the source of the first NMOS transistor N9 is connected with the power supply -V DD The gate of the second NMOS transistor N 10 10 is connected with the source of the first NMOS transistor N9, and the source of the second NMOS transistor N10 is connected with the power supply -V The drain of the third NMOS transistor N 11 is connected with the drain of the second NMOS transistor N 10 , the drain of the second PMOS transistor P7 and one end of the capacitor C L , and serves as an output terminal TNAND. The gate of the third NMOS transistor N 11 is connected with the clock signal CP. The source of the third NMOS transistor N 11 is connected with the other end of the capacitor C L and the ground.

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