A semiconductor device, a method of fabricating the same, and a semiconductor apparatus

Abstract

The application relates to the technical field of semiconductor manufacturing, in particular to a semiconductor device and a preparation method thereof, which comprises a semiconductor substrate, a first transistor and a second transistor, the first transistor and the second transistor are sequentially arranged above the semiconductor substrate along the thickness direction of the semiconductor substrate from bottom to top, the first transistor comprises a first gate stack structure and a first source / drain region located on both sides of the first gate stack structure, the second transistor comprises a second gate stack structure and a second source / drain region located on both sides of the second gate stack structure, a gate isolation structure is arranged between the first gate stack structure and the second gate stack structure, and a source / drain isolation region is arranged between the first source / drain region and the second source / drain region; wherein, in the width direction of the channel, the width of the gate isolation structure and the width of the source / drain isolation region are the same; and the first source / drain region and the second source / drain region are respectively located below and above the source / drain isolation region. The application significantly reduces the process integration difficulty of the device.

Description

Technical Field

[0001] This invention relates to the field of semiconductor manufacturing technology, and in particular to a semiconductor device and its preparation method, as well as semiconductor equipment. Background Technology

[0002] As semiconductor process nodes continue to shrink to 3nm and below, traditional planar transistors and FinFET structures face increasingly severe short-channel effects and integration density bottlenecks due to physical limitations. To continue Moore's Law, the industry has proposed the revolutionary Complementary Field-Effect Transistor (CFET) architecture. The core idea of ​​CFET is to stack N-type and P-type transistors vertically, thereby halving the area of ​​logic cells within the same footprint, greatly improving chip integration density.

[0003] However, the practical application of CFET structures faces several severe process integration challenges, mainly in the following aspects: 1. Current mainstream CFET integration schemes typically employ high-Ge-concentration GeSi as a sacrificial layer for the middle dielectric isolation (MDI) layer of vertically stacked N-type and P-type transistor gates, achieving separation between the upper and lower transistor layers. However, high-Ge-concentration GeSi has an extremely thin critical thickness, and its inherent lattice mismatch stress makes this layer highly susceptible to defects during fabrication, resulting in high reliability risks. More critically, this sacrificial layer exhibits poor thermal stability and a very low thermal budget, severely limiting subsequent high-temperature process steps and posing a significant obstacle to device performance optimization and process integration flexibility.

[0004] 2. Within the vertically stacked nanoscale space, it is necessary to simultaneously achieve perfect electrical isolation between the source / drain (S / D) regions of the upper and lower transistors, non-interference between NMOS and PMOS (N / P isolation), and their respective gate threshold voltages (V). t The independent and precise control of these processes is crucial. These process steps are highly complex and interconnected, and any deviation can lead to crosstalk or failure of the performance of upper and lower layer devices, significantly increasing the difficulty of process integration and reducing the process yield.

[0005] 3. Currently, most CFET structures employ a gate self-alignment process, meaning the gates of the upper and lower transistors are defined in the same process step. While this method ensures alignment accuracy, it forces the gates of the upper and lower transistors to be strictly aligned vertically. This fixed architecture deprives the circuit design stage of the flexibility to independently adjust the dimensions of the upper and lower devices to optimize performance and power consumption, failing to meet the urgent need for refined and customized circuit design in advanced processes.

[0006] To address the aforementioned issues, existing technologies employ either monolithic integration (MSI) with high-Ge-concentration SiGe as a sacrificial layer for MDI or sequential integration (SII) with direct bonding of SiGe / Si stacks. While these strategies partially resolve interlayer interference, reliance on traditional front-side power supply networks exacerbates congestion on front-side metal interconnects, hindering performance improvements. Furthermore, while sequential integration (e.g., fabricating the bottom PMOS and some circuitry before the top NMOS and circuitry) simplifies the process, its advantages are limited if the thermal buildup and performance degradation experienced by bottom-layer devices during top-layer fabrication are not effectively addressed, and if coupled with innovative interconnect technologies.

[0007] In view of this, the present invention is proposed. Summary of the Invention

[0008] The purpose of this invention is to provide a semiconductor device and its fabrication method, which aims to improve the stability of the device under high-frequency operation.

[0009] In a first aspect, the present invention provides a semiconductor device, including a semiconductor substrate; A first transistor and a second transistor are sequentially disposed above the semiconductor substrate from bottom to top along the thickness direction of the semiconductor substrate. The first transistor includes a first gate stack structure and a first source / drain region located on both sides of the first gate stack structure. The second transistor includes a second gate stack structure and a second source / drain region located on both sides of the second gate stack structure. A gate isolation structure is disposed between the first gate stack structure and the second gate stack structure; A source / drain isolation region is provided between the first source / drain region and the second source / drain region; In the width direction of the channel, the gate isolation structure and the source / drain isolation region have the same width; The first source / drain region is located below the source / drain isolation region, and the second source / drain region is located above the source / drain isolation region.

[0010] In a preferred embodiment of this technical solution, the gate isolation structure and the source / drain isolation region have the same width.

[0011] As a preferred embodiment of this technical solution, the gate isolation structure and the source / drain isolation region are integrally formed.

[0012] As a preferred embodiment of this technical solution, the first transistor is an NMOS, and the first source / drain region includes a Si / SiC source / drain epitaxial layer; The second transistor is a PMOS, and the second source / drain region contains a GeSi source / drain epitaxial layer.

[0013] In a preferred embodiment of this technical solution, the bottom of the GeSi source / drain epitaxial layer is the same width as the source / drain isolation region along the length of the channel.

[0014] In a preferred embodiment of this technical solution, the bottom of the GeSi source / drain epitaxial layer is the same width as the source / drain isolation region in the width direction of the channel.

[0015] As a preferred embodiment of this technical solution, the first gate stack structure and the second gate stack structure are independent patterned structures.

[0016] As a preferred embodiment of this technical solution, the first gate stack structure and the second gate stack structure are completely overlapping, partially overlapping, or completely non-overlapping in the horizontal projection direction of the semiconductor substrate.

[0017] As a preferred embodiment of this technical solution, the gate isolation structure includes a support structure and isolation bodies located on both sides of the support structure. One end of the support structure is in contact with the first gate stack structure, and the other end is in contact with the second gate stack structure. The isolation bodies are integrally formed with the source / drain isolation region.

[0018] In a preferred embodiment of this technical solution, the side of the supported structure is either separated from or connected to the inner wall of the isolation body.

[0019] As a preferred embodiment of this technical solution, the supporting structure is an intrinsic silicon layer.

[0020] In a preferred embodiment of this technical solution, the bottom of the GeSi source / drain epitaxial layer has the same shape as the top of the source / drain isolation region.

[0021] Secondly, the present invention also discloses a method for preparing the above-mentioned semiconductor, comprising the following steps: S1. A first stacked structure, a gate isolation structure sacrificial layer, and a second stacked structure are sequentially formed on a semiconductor substrate, wherein the first stacked structure includes a first semiconductor layer and a first sacrificial layer arranged alternately in sequence, and the second stacked structure includes a second semiconductor layer and a second sacrificial layer arranged alternately in sequence. S2. The second stack structure is graphically processed to form a second channel stack, and a second source / drain region is formed on both sides of the second channel stack. S3. Bond the second substrate above the second source / drain region, flip and thin the semiconductor substrate; S4. The first stacked structure is patterned to form a first channel stack, the gate isolation structure sacrificial layer is released, and the first source / drain regions are formed on both sides of the first channel stack. S5. Etch the first sacrificial layer to form a first trench between the first semiconductor layers in the first stacked structure; S6. A first gate stack structure is formed in the first trench, and then the first gate stack structure and the first source / drain region are metal interconnected. S7. Bond the third substrate above the first source / drain region, flip and thin the second substrate; S8. Etch the second sacrificial layer to form a second trench between the second semiconductor layers in the second stacked structure; S9. Form a second gate stack structure in the second trench, and then perform metal interconnection between the second gate stack structure and the second source / drain region; The gate isolation structure sacrificial layer is intrinsic silicon.

[0022] As a preferred embodiment of this technical solution, step S1 further includes: selectively etching back the first stacked structure, the gate isolation structure sacrificial layer and the second stacked structure to form a fin stacked structure, and then forming a shallow trench isolation region between two adjacent fins; The upper surface of the shallow trench isolation region is lower than, flush with, or higher than the upper surface of the gate isolation structure sacrificial layer.

[0023] As a preferred embodiment of this technical solution, step S2 specifically includes: forming a dummy gate on the exposed fin surface, depositing sidewall media on both sides of the dummy gate and performing anisotropic etching to form an outer wall, using the dummy gate and the outer wall as a mask to etch the fin stack structure to form a second channel stack; laterally etching the second sacrificial layer to form a groove, and forming an inner sidewall in the groove; forming a second source / drain region on both sides of the second channel stack.

[0024] As a preferred embodiment of this technical solution, in step S3, when thinning the semiconductor substrate, the process stops at the bottom of the shallow trench isolation region, and then the silicon fins embedded in the shallow trench isolation region are removed.

[0025] As a preferred embodiment of this technical solution, step S4 specifically includes: forming a dummy gate on the exposed fin surface; depositing sidewall dielectric on both sides of the dummy gate and performing anisotropic etching to form an outer wall; using the dummy gate and the outer wall as a mask, etching the fin stack structure to form a first channel stack; depositing temporary sidewall dielectric on the surface of the first channel stack and the gate isolation structure sacrificial layer, and etching the temporary sidewall dielectric to expose the gate isolation structure sacrificial layer; releasing the gate isolation structure sacrificial layer and filling it with isolation dielectric; laterally etching the first sacrificial layer to form a groove, and forming an inner sidewall in the groove; forming a first source / drain region on both sides of the first channel stack.

[0026] In a preferred embodiment of this technical solution, in step S4, the release of the gate isolation structure sacrificial layer includes both complete release and partial release. Preferably, when the portion is released, a portion of the intrinsic silicon is retained as a support structure.

[0027] Thirdly, the present invention also discloses an electronic device including the above-mentioned semiconductor devices, wherein the electronic device includes a smartphone, personal computer, tablet computer, artificial intelligence device, wearable device or power bank, which should also fall within the protection scope of the present invention.

[0028] The semiconductor device of the present invention has at least the following beneficial effects: 1. In the semiconductor device of the present invention, intrinsic silicon is used as the sacrificial layer of the gate isolation structure. Its thickness can be freely adjusted according to process requirements, avoiding the limitations of traditional high Ge sacrificial layers in thickness control and etching processes. At the same time, intrinsic silicon material is compatible with existing GAA processes, requiring no additional equipment or materials, reducing process complexity and cost, and improving the epitaxial quality and thermal budget of the device channel layer. 2. In the semiconductor device of the present invention, the first source / drain region of the first transistor and the second source / drain region of the second transistor are vertically layered and distributed. Combined with the gate isolation structure and the one-time molding design of the source / drain isolation region, the parasitic capacitance between the upper and lower transistors is reduced, the signal transmission delay is reduced, and the stability of the device under high frequency operation is improved. 3. In the semiconductor device of the present invention, the upper and lower transistors adopt independent patterned gate technology, and the gates can be fully overlapped, partially overlapped or not overlapped at all in the horizontal projection direction, which facilitates the integration of Split Gate technology; in addition, the position of the upper and lower gates can be adjusted according to the circuit design requirements to optimize the interconnection path, reduce the interconnection resistance, and meet the different requirements of different circuits for device performance. Attached Figure Description

[0029] To more clearly illustrate the specific embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the specific embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of the present invention. For those skilled in the art, other drawings can be obtained from these drawings without creative effort.

[0030] Figure 1 This is a top view of the semiconductor device of the present invention; Figure 2 This is one of the schematic cross-sectional views of the semiconductor device of the present invention; Figure 3 This is the second schematic diagram of the AA' cross-section of the semiconductor device of the present invention; Figure 4 This is the third schematic diagram of the AA' cross-section of the semiconductor device of the present invention; Figure 5 This is the fourth schematic cross-sectional view of the semiconductor device of the present invention (BB'). Figure 6 This is the fifth schematic cross-sectional view of the semiconductor device of the present invention (BB'). Figure 7 This is the sixth schematic cross-sectional view of the semiconductor device of the present invention (BB'). Figure 8 This is the seventh schematic diagram of the BB' cross-section of the semiconductor device of the present invention; Figure 9 This is the eighth schematic diagram of the BB' cross-section of the semiconductor device of the present invention; Figure 10 This is the ninth schematic cross-sectional view of the semiconductor device of the present invention (BB'). Figure 11 This is the tenth schematic diagram of the BB' cross-section of the semiconductor device of the present invention; Figure 12 This is eleventh of the schematic diagrams of the BB' cross-section of the semiconductor device of the present invention; Figure 13 This is the 12th schematic cross-sectional view of the semiconductor device of the present invention (BB'). Figure 14 This is the thirteenth schematic diagram of the BB' cross-section of the semiconductor device of the present invention; Figure 15 This is the fourteenth schematic diagram of the BB' cross-section of the semiconductor device of the present invention; Figure 16 This is the fifteenth schematic cross-sectional view of the semiconductor device of the present invention (AA'). Figure 17 This is the sixteenth schematic diagram of the BB' cross-section of the semiconductor device of the present invention; Figure 18 This is the seventeenth schematic diagram of the BB' cross-section of the semiconductor device of the present invention; Figure 19 This is the eighteenth schematic cross-sectional view of the semiconductor device of the present invention (AA'). Figure 20 This is the nineteenth schematic cross-sectional view of the semiconductor device of the present invention (BB'). Figure 21 This is the twentieth schematic diagram of the BB' cross-section of the semiconductor device of the present invention; Figure 22 This is the twenty-first schematic diagram of the BB' cross-section of the semiconductor device of the present invention; Figure 23 This is the twenty-second schematic diagram of the BB' cross-section of the semiconductor device of the present invention; Figure 24 This is the twenty-third schematic cross-sectional view of the semiconductor device of the present invention (BB'). Figure 25 This is the twenty-fourth schematic cross-sectional view of the semiconductor device of the present invention (BB'). Figure 26 This is the twenty-fifth schematic cross-sectional view of the semiconductor device of the present invention (BB'). Figure 27 This is the twenty-sixth schematic cross-sectional view of the semiconductor device of the present invention (BB'). Figure 28 This is the twenty-seventh schematic cross-sectional view of the semiconductor device of the present invention (BB'). Figure 29 This is the twenty-eighth schematic diagram of the BB' cross-section of the semiconductor device of the present invention; Figure 30 This is the twenty-ninth schematic cross-sectional view of the semiconductor device of the present invention (BB'). Figure 31 This is the thirtieth schematic diagram of the BB' cross-section of the semiconductor device of the present invention; Figure 32 This is the thirty-first schematic diagram of the BB' cross-section of the semiconductor device of the present invention; Figure 33 This is 32nd schematic cross-sectional view of the semiconductor device of the present invention (BB'). Figure 34 This is the thirty-third schematic cross-sectional view of the semiconductor device of the present invention (BB'). Figure 35 Thirty-fourth schematic cross-sectional view of the semiconductor device of the present invention (BB'). Figure 36 This is the thirty-fifth schematic diagram of the BB' cross-section of the semiconductor device of the present invention; Figure 37 This is the thirty-sixth schematic cross-sectional view of the semiconductor device of the present invention (BB'). Figure 38 This is the thirty-seventh schematic diagram of the BB' cross-section of the semiconductor device of the present invention; Figure 39 This is the thirty-eighth schematic cross-sectional view of the semiconductor device of the present invention (BB'). Figure 40 This is the 39th schematic cross-sectional view of the semiconductor device of the present invention (BB'). Figure 41 This is the fortieth schematic diagram of the BB' cross-section of the semiconductor device of the present invention; Figure 42 This is schematic diagram of the BB' cross-section of the semiconductor device of the present invention, number forty-one. Figure 43 This is schematic diagram of the BB' cross-section of the semiconductor device of the present invention, number forty-two. Figure 44 This is schematic diagram of the BB' cross-section of the semiconductor device of the present invention, number forty-three. Figure 45 This is the forty-fourth schematic cross-sectional view of the semiconductor device of the present invention (BB'). Figure 46This is schematic diagram of the DD' cross-section of the semiconductor device of the present invention, number forty-five; Figure 47 This is schematic diagram of the BB' cross-section of the semiconductor device of the present invention, number forty-five. Figure 48 This is schematic diagram of the CC' cross-section of the semiconductor device of the present invention, number forty-five.

[0031] Explanation of reference numerals in the attached figures: 1: Semiconductor substrate; 2: First transistor; 3: Second transistor; 4: Gate isolation structure; 5: Source / drain isolation region; 6: Support structure; 7: First stacked structure; 8: Gate isolation structure sacrificial layer; 9: Second stacked structure; 10: First semiconductor layer; 11: First sacrificial layer; 12: Second semiconductor layer; 13: Second sacrificial layer; 14: Shallow trench isolation region; 15: Gate dielectric oxide layer; 16: Dummy gate layer; 17: Dummy gate hard mask layer; 18: Outer wall; 19: Trench; 20: Inner wall; 21: GeSi source / drain epitaxial layer; 22: Isolation layer; 23: Second substrate; 24: Si / SiC source / drain epitaxial layer; 25: Metal gate; 26: Third substrate; 27: Source / drain region. Detailed Implementation

[0032] The technical solution of the present invention will be clearly and completely described below with reference to the embodiments. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0033] In the description of this invention, it should be understood that the terms "center," "longitudinal," "lateral," "length," "width," "thickness," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," "outer," "clockwise," and "counterclockwise," etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are used only for the convenience of describing this invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limiting this invention.

[0034] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of the stated features. In the description of this invention, "a plurality of" means two or more, unless otherwise explicitly specified. Furthermore, the terms "installed," "connected," and "linked" should be interpreted broadly; for example, they may refer to a fixed connection, a detachable connection, or an integral connection; they may refer to a mechanical connection or an electrical connection; they may refer to a direct connection or an indirect connection through an intermediate medium; and they may refer to the internal connection of two components. Those skilled in the art can understand the specific meaning of the above terms in this invention based on the specific circumstances.

[0035] Example 1 like Figure 1-48 As shown, this embodiment provides a semiconductor device, including a semiconductor substrate 1; a first transistor 2 and a second transistor 3, the first transistor 2 and the second transistor 3 being sequentially disposed above the semiconductor substrate 1 from bottom to top along the thickness direction of the semiconductor substrate 1; the first transistor 2 including a first gate stack structure and first source / drain regions located on both sides of the first gate stack structure; the second transistor 3 including a second gate stack structure and second source / drain regions located on both sides of the second gate stack structure; a gate isolation structure 4 disposed between the first gate stack structure and the second gate stack structure; and a source / drain isolation region 5 disposed between the first source / drain region and the second source / drain region. In the width direction of the channel, the gate isolation structure 4 and the source / drain isolation region 5 have the same width; The first source / drain region is located below the source / drain isolation region 5, and the second source / drain region is located above the source / drain isolation region 5.

[0036] In the semiconductor device of the present invention, a first transistor 2 and a second transistor 3 are spaced apart along the thickness direction of the semiconductor substrate 1. The first transistor 2 and the second transistor 3 can constitute a three-dimensional stacked transistor (CFET device) to improve the integration density of the semiconductor device. Furthermore, intrinsic silicon is used as the sacrificial layer of the gate isolation structure 4, and its thickness can be freely adjusted according to process requirements, avoiding the limitations of traditional high-Ge sacrificial layers in thickness control and etching processes. Simultaneously, intrinsic silicon material is compatible with existing GAA processes, requiring no additional equipment or materials, reducing process complexity and cost, and improving the epitaxial quality and thermal budget of the device channel layer. Moreover, there is no contact interface between the gate isolation structure 4 and the source / drain isolation region 5, avoiding interface defects and leakage risks caused by multiple etching processes in conventional processes, enhancing the electrical isolation performance of the device, and extending its lifespan. Therefore, the first source / drain region 27 of the first transistor 2 and the second source / drain region of the second transistor 3 are vertically layered, and combined with the one-time molding design of the gate isolation structure 4 and the source / drain isolation region 5, the parasitic capacitance between the upper and lower transistor layers is reduced, signal transmission delay is lowered, and the stability of the device under high-frequency operation is improved.

[0037] Based on the above technical solution, it is further preferred that the gate isolation structure 4 and the source / drain isolation region 5 have the same width along the length of the channel.

[0038] Based on the above technical solution, and further preferably, the gate isolation structure 4 and the source / drain isolation region 5 are integrally formed. Integrating the gate isolation structure 4 and the source / drain isolation region 5 firstly reduces at least 2-3 etching steps and related auxiliary steps such as photolithography and cleaning, shortening the overall process by approximately 30%. Simultaneously, it avoids alignment errors during multiple etching processes, improving process yield; the yield is expected to increase by 15%-20%, significantly reducing production costs and cycle time. Secondly, the integrally formed gate isolation structure 4 and source / drain isolation region 5 eliminate interface defects and gaps caused by multiple etching and deposition processes in traditional methods, reducing leakage risk and improving the electrical isolation performance of the device. Furthermore, the seamless connection of the structure enhances overall mechanical strength, better resisting stress changes during subsequent processes such as bonding and thinning, reducing the possibility of structural damage, and improving the long-term reliability of the device. Finally, the integrated forming solution provides more possibilities for device design. Due to reduced process limitations, the shape, size, and material properties of the gate isolation structure 4 and the source / drain isolation region 5 can be flexibly adjusted according to different performance requirements. For example, in high-frequency applications, the shape of the isolation region can be optimized to reduce parasitic capacitance; in high-power applications, the strength and heat dissipation performance of the gate isolation structure 4 can be enhanced to meet diverse market demands.

[0039] Based on the above technical solution, more preferably, the first transistor 2 is an NMOS, and the first source / drain region includes a Si / SiC source / drain epitaxial layer 24; the second transistor 3 is a PMOS, and the second source / drain region includes a GeSi source / drain epitaxial layer 21.

[0040] The top-layer PMOS uses a GeSi source / drain epitaxial layer, which utilizes the compressive stress characteristics of Ge to significantly improve hole mobility; the bottom-layer NMOS uses a Si / SiC source / drain, which leverages the high electron mobility of SiC to optimize electron transport efficiency, enabling CFET devices to achieve a significant improvement in complementary performance, effectively reducing on-resistance and increasing switching speed.

[0041] Based on the above technical solution, it is further preferred that, in the length direction of the channel, the bottom of the GeSi source / drain epitaxial layer is the same as the width of the source / drain isolation region; and in the width direction of the channel, the bottom of the GeSi source / drain epitaxial layer is the same as the width of the source / drain isolation region.

[0042] The GeSi source / drain epitaxial layers adopt a shape distribution that is narrow at the top and wide at the bottom, which is the opposite of the conventional structure. This design not only adapts to the vertically layered source / drain structure, making it easy to achieve one-time molding isolation in conjunction with the gate isolation structure 4, but also optimizes the carrier injection path in a limited space, further improving device performance.

[0043] Based on the above technical solution, more preferably, the first gate stack structure and the second gate stack structure are independent patterned structures, and the first gate stack structure and the second gate stack structure are completely overlapping, partially overlapping or completely non-overlapping in the horizontal projection direction of the semiconductor substrate 1.

[0044] The upper and lower transistors use independent patterned gate technology, and the first gate stack structure and the second gate stack structure can achieve complete overlap in the horizontal projection direction. Figures 44-46 ), partially overlapping or not overlapping at all ( Figures 47-48 This facilitates the integration of SplitGate technology; by adjusting the positions of the upper and lower gates according to circuit design requirements, the interconnect path can be optimized, the interconnect resistance reduced, and the different requirements of different circuits for device performance can be met.

[0045] Based on the above technical solution, and further preferably, the gate isolation structure 4 includes a support structure 6 and an isolation body located on both sides of the support structure 6. One end of the support structure 6 is in contact with the first gate stack structure, and the other end is in contact with the second gate stack structure. The isolation body is integrally formed with the source / drain isolation region 5.

[0046] When a support structure 6 is provided inside the gate isolation structure 4, the two ends of the support structure 6 are connected to the upper and lower gate stack structures, which can effectively support the upper device and prevent the three-dimensional structure from collapsing during thinning, bonding and other processes. It is especially suitable for ultra-thin channel scenarios and improves the stability of device structure.

[0047] Based on the above technical solution, it is further preferred that the side of the supported structure 6 is separated from or connected to the inner wall of the gate isolation structure 4.

[0048] Based on the above technical solution, and further preferably, the support structure 6 in this embodiment can be columnar, strip-shaped, block-shaped or grid-shaped. Different shapes can be adapted to devices of different sizes. For example, small-sized devices can use columnar shapes, and large-sized devices can use grid-shaped shapes. The present invention does not strictly limit its shape.

[0049] Based on the above technical solution, and more preferably, the support structure 6 is an intrinsic silicon layer.

[0050] Based on the above technical solution, it is further preferred that the bottom of the GeSi source / drain epitaxial layer has the same shape as the top of the source / drain isolation region.

[0051] Example 2 This embodiment provides a method for fabricating a semiconductor device, including the following steps: S1, such as Figure 2 As shown, a first stacked structure 7, a gate isolation structure sacrificial layer 8, and a second stacked structure 9 are sequentially formed on a semiconductor substrate 1 by epitaxy. The first stacked structure 7 includes a first semiconductor layer 10 and a first sacrificial layer 11 arranged alternately in sequence. The second stacked structure 9 includes a second semiconductor layer 12 and a second sacrificial layer 13 arranged alternately in sequence. The number of cycles of each of them is ≥1. The first semiconductor layer 10 and the second semiconductor layer 12 are both Si layers. The first sacrificial layer 11 and the second sacrificial layer 13 are both SiGe sacrificial layers. The gate isolation structure sacrificial layer 8 is intrinsic silicon. Specifically, the semiconductor substrate 1 can be a substrate made of any semiconductor material such as silicon, silicon germanium, or germanium, or a substrate made of insulating material such as silicon oxide or ceramic. The embodiments of the present invention do not specifically limit the structure and material of the semiconductor substrate 1, as long as it can be applied to the semiconductor device provided in the embodiments of the present invention. The first sacrificial layer 11 and the second sacrificial layer 13 are generally made of SiGe, and the first semiconductor layer 10 and the second semiconductor layer 12 are generally made of Si. The first sacrificial layer 11, the second sacrificial layer 13, the first semiconductor layer 10 and the second semiconductor layer 12 are all superlattice structures. The Si layer determines the number of subsequent nanowires. The number of Si layers is ≥1, and each layer is less than 30nm. The final thickness directly determines the height of the nanosheet channel and the electrical performance.

[0052] Furthermore, such as Figure 3 As shown, the first stacked structure 7, the gate isolation structure sacrificial layer 8, and the second stacked structure 9 are selectively etched back to form a fin stacked structure; then a shallow trench isolation region 14 is formed between two adjacent fins. Specifically, firstly, a hard mask layer is deposited above the topmost second semiconductor layer 12. After patterning, the epitaxially grown superlattice stack is etched into multiple periodically distributed fins. The height of the fins is 10nm-400nm and the width is 1-100nm. The etching stops at or below the substrate. Then, an insulating dielectric material is deposited and planarized to expose the hard mask layer. The hard mask layer is then removed by wet or dry etching. The insulating dielectric material is then selectively etched back to expose the three-dimensional fin stack structure. Shallow trench isolation regions 14 are formed between adjacent fin stacks. The upper surface of the shallow trench isolation region 14 is lower than, flush with, or higher than the upper surface of the gate isolation structure sacrificial layer 8, which is used to define the well region of the semiconductor substrate 1, reduce the risk of leakage current, and further improve the yield and performance of the semiconductor device. Its material may include any insulating material such as silicon oxide, silicon oxynitride, or silicon oxynitride, without specific limitation here. S2. A dummy gate is formed on the exposed fin surface. Sidewall media is deposited on both sides of the dummy gate and anisotropically etched to form an outer wall 18. Using the dummy gate and the outer wall 18 as a mask, the fin stack structure is etched to form a second channel stack. The second sacrificial layer 13 is laterally etched to form a groove 19, and an inner sidewall 20 is formed in the groove 19. A second source / drain region is formed on both sides of the second channel stack. Specifically, such as Figure 4-5 As shown, a gate dielectric oxide layer 15 and a dummy gate layer 16 are sequentially deposited above the shallow trench isolation region 14, and CMP is performed. Then, a dummy gate hard mask layer 17 is deposited. The material of the dummy gate layer 16 is polycrystalline silicon or amorphous silicon. The material of the dummy gate hard mask layer 17 can be oxide, carbide, organic material, etc., and no specific limitation is made here. Furthermore, such as Figure 6 As shown, anisotropic etching of amorphous or polycrystalline dummy gates is performed and stopped at the top of the fin stack. After etching, the dummy gate hard mask layer 17 above the dummy gate structure is retained. Furthermore, such as Figure 7 As shown, gate sidewall dielectric is deposited on both sides of the dummy gate structure, and then the gate sidewall dielectric in the horizontal direction is etched, leaving only the dielectric of the dummy gate and the hard mask layer sidewall to form the outer sidewall 18. The material of the gate sidewall dielectric can be silicon nitride, nitrogen-doped silicon oxide, nitrogen-doped silicon carbide, etc., and no specific limitation is made here. Furthermore, such as Figure 8As shown, the gate dielectric oxide layer 15 on the fin surface is removed, and anisotropic precision etching is performed on the second source / drain region to remove the second stacked structure 9 of the second source / drain region, with a depth to the surface of the shallow trench isolation region 14, which can be slightly higher or lower than the upper surface of the gate isolation structure sacrificial layer 8 to form a second channel stack. Furthermore, such as Figure 9 As shown, the second sacrificial layer 13 of the fin is selectively etched isotropically and precisely in the center direction of the source / drain region 27 to form a groove 19, wherein the depth of the groove 19 can be set to 2-10 nm, and preferably 5 nm; Furthermore, such as Figure 10 As shown, the inner sidewall 20 is deposited with a dielectric material. The material of the inner sidewall 20 dielectric material can be silicon nitride, nitrogen-doped silicon oxide, nitrogen-doped silicon carbide, etc., and no specific limitation is made here. Furthermore, such as Figure 11 As shown, the medium of the inner wall 20 is etched to form the inner wall 20 of the second source / drain region; Furthermore, such as Figure 12 As shown, SiGe epitaxy of the second source / drain region is performed on both sides of the second channel stack using similar methods such as metal-organic chemical vapor deposition, molecular beam epitaxy, liquid phase epitaxy, vapor phase epitaxy, selective epitaxial growth, or combinations thereof. The resulting SiGe source / drain epitaxial layer 21 has a shape that is narrower at the top and wider at the bottom, with its bottom in contact with the source / drain isolation region 5 and its top close to the top of the second stack structure 9. Furthermore, such as Figure 13 As shown, an isolation layer 22 dielectric is deposited above the SiGe source / drain epitaxial layer 21, and the isolation layer 22 dielectric is chemically and mechanically polished to planarize it, thus obtaining the isolation layer 22. The dielectric of the isolation layer 22 is a commonly used film layer with excellent insulation performance and stability, or a composite film. In practical applications, the appropriate material of the isolation layer 22 can be selected according to the specific process and design requirements, and no specific limitation is made here. S3. Bond the second substrate 23 above the second source / drain region, and flip and thin the semiconductor substrate 1. Specifically, such as Figure 14 As shown, a second substrate 23 is bonded above the isolation layer 22. A corresponding dielectric material can be deposited on the surface of the wafer of the second substrate 23 to match the warpage and deformation when the two layers are bonded. The second substrate 23 is generally a silicon substrate. Furthermore, such as Figure 15 As shown, the wafer of semiconductor substrate 1 is flipped and thinned. Furthermore, such as Figure 16-17As shown, after the semiconductor substrate 1 wafer is thinned, it is planarized and stops at the bottom of the shallow trench isolation region 14. Then, the silicon fins embedded in the shallow trench isolation region 14 are removed by a dry or wet method with a high selectivity. S4. A dummy gate is formed on the exposed fin surface. Sidewall dielectric is deposited on both sides of the dummy gate and anisotropically etched to form an outer wall 18. Using the dummy gate and outer wall 18 as a mask, the fin stack structure is etched to form a first channel stack. Temporary sidewall dielectric is deposited on the surface of the first channel stack and the gate isolation structure sacrificial layer 8, and the temporary sidewall dielectric is etched to expose the gate isolation structure sacrificial layer 8. The gate isolation structure sacrificial layer 8 is released and filled with isolation dielectric. The first sacrificial layer 11 is laterally etched to form a groove 19, and an inner sidewall 20 is formed in the groove 19. First source / drain regions are formed on both sides of the first channel stack. Specifically, such as Figure 18 As shown, the shallow trench isolation region 14 is precisely etched in reverse down to the height of the gate isolation structure sacrificial layer 8, exposing the fins of the first transistor 2, which can be slightly higher or lower than the interface between the gate isolation structure sacrificial layer 8 and the first sacrificial layer 11. Furthermore, such as Figures 19-20 As shown, a gate dielectric oxide layer 15 and a dummy gate layer 16 are sequentially deposited on the exposed fin surface, and CMP is performed. Then, a dummy gate hard mask layer 17 is deposited. The dummy gate layer 16 is made of polycrystalline silicon or amorphous silicon. The dummy gate hard mask layer 17 can be made of oxides, carbides, organic materials, etc., without specific limitations. Furthermore, such as Figure 21 As shown, anisotropic etching of amorphous or polycrystalline dummy gates is performed and stopped at the top of the fin stack. After etching, the dummy gate hard mask layer 17 above the dummy gate structure is retained. Furthermore, such as Figure 22 As shown, gate sidewall dielectric is deposited on both sides of the dummy gate structure, and then the gate sidewall dielectric in the horizontal direction is etched, leaving only the dielectric of the dummy gate and the hard mask layer sidewall to form the outer sidewall 18. Furthermore, such as Figure 23-24 As shown, the gate dielectric oxide layer 15 on the fin surface is removed, and anisotropic precision etching is performed on the first source / drain region to remove the first stacked structure 7 of the first source / drain region, with a depth to the surface of the gate isolation structure sacrificial layer 8, which may be slightly higher or lower than the upper surface of the first sacrificial layer 11 to form the first channel stack. Furthermore, such as Figure 25 As shown, a temporary sidewall medium is deposited. The material of the temporary sidewall medium can be silicon nitride, nitrogen-doped silicon oxide, nitrogen-doped silicon carbide, etc., and no specific limitation is made here. Furthermore, such as Figure 26 As shown, the temporary sidewall dielectric is etched to expose the gate isolation structure sacrificial layer 8; Furthermore, such as Figure 27-29 As shown, the gate isolation structure sacrificial layer 8 is released and filled with isolation dielectric; In this step, when releasing the gate isolation structure sacrificial layer 8, either full release or partial release can be selected. When full release is used, the intrinsic silicon of the gate isolation structure sacrificial layer 8 is removed using a high selectivity removal process (wet or dry) for SiGe and dielectric. Figure 27 When partial release is used, the intrinsic silicon of the gate isolation structure sacrificial layer 8 is first etched using anisotropic etching, stopping at the bottom of the SiGe source / drain of the top-layer device. Then, isotropic etching is used for precise etching, retaining a portion of the intrinsic silicon of the gate isolation structure sacrificial layer 8 as the support structure 6. Figure 29 ).

[0053] Furthermore, such as Figure 28 As shown, remove the temporary sidewall medium; Furthermore, such as Figure 30 As shown, the insulating medium material is filled and planarized. Similarly, the insulating layer 22 medium is a commonly used film layer with excellent insulation performance and stability, or a composite film. In practical applications, the appropriate material of the insulating layer 22 can be selected according to the specific process and design requirements. No specific limitation is made here. Furthermore, such as Figure 31 As shown, the isolation dielectric material is precisely etched back onto the top of the gate isolation structure 4 to form the first channel stack; Furthermore, such as Figure 32 As shown, the first sacrificial layer 11 is selectively etched in an isotropic manner to form a groove 19, wherein the depth of the groove 19 can be set to 2-10 nm, and preferably 5 nm; Furthermore, such as Figure 33 As shown, the inner sidewall 20 is deposited with a dielectric material. The material of the inner sidewall 20 dielectric material can be silicon nitride, nitrogen-doped silicon oxide, nitrogen-doped silicon carbide, etc., and no specific limitation is made here. Furthermore, such as Figure 34 As shown, the medium of the inner wall 20 is etched to form the inner wall 20 of the first source / drain region; Furthermore, such as Figure 35 As shown, Si / SiC epitaxy of the first source / drain region is performed on both sides of the first channel stack using similar methods such as metal-organic chemical vapor deposition, molecular beam epitaxy, liquid phase epitaxy, vapor phase epitaxy, selective epitaxial growth, or combinations thereof, to obtain Si / SiC source / drain epitaxial layer 24. Furthermore, such as Figures 36-37As shown, an isolation layer 22 dielectric is deposited above the Si / SiC source / drain epitaxial layer 24, and the isolation layer 22 dielectric is chemically and mechanically polished to planarize it until the polycrystalline silicon or amorphous silicon dummy gate is exposed, thus obtaining the isolation layer 22. The dielectric of the isolation layer 22 is a commonly used film layer with excellent insulation performance and stability, or a composite film. In practical applications, the appropriate material of the isolation layer 22 can be selected according to the specific process and design requirements, and no specific limitation is made here. S5. Etch the first sacrificial layer 11 to form a first trench between the first semiconductor layers 10 in the first stacked structure 7; Specifically, such as Figure 38 As shown, firstly, the aforementioned dummy gate layer 16 formed by polycrystalline silicon or amorphous silicon is etched away by selective etching or etching processes; Furthermore, the interface gate oxide layer is removed, and the first sacrificial layer 11 in the superlattice stack is released by selective etching to release the nanosheet channel and form a first trench between the first semiconductor layers 10 in the first stacked structure 7. S6, such as Figure 39 As shown, a high-k metal gate 25 is filled in the first trench, and CMP is performed to form a first gate stack structure surrounding the nanosheet channel. Then, as... Figure 40 As shown, metal interconnection is performed on the first gate stack structure and the first source / drain region. Specifically, the signal interconnection of part of the gate and the wiring from the source / drain region 27 to the relevant power rail are completed by using the contact holes to the contact holes of the source / drain region 27, the contact holes of the gate top M0 and Metal 0. The metal interconnection process in this embodiment can refer to the prior art, and will not be described in detail here.

[0054] S7. Bond the third substrate 26 wafer above the first source / drain region, flip and thin the second substrate 23; Specifically, such as Figure 41 As shown, a third substrate 26 is bonded above the metal interconnect structure. The surface of the wafer of the third substrate 26 can be deposited with a corresponding dielectric material to match the warpage and deformation during the bonding of the two layers. The third substrate 26 is generally a silicon substrate. Furthermore, such as Figure 42 As shown, the wafer is flipped over, thinned, and completely removed from the second substrate 23. Furthermore, such as Figure 43 As shown, the dielectric of the isolation layer 22 is chemically and mechanically polished until the polycrystalline silicon or amorphous silicon dummy gate is exposed; S8. Etch the second sacrificial layer 13 to form a second trench between the second semiconductor layers 12 in the second stacked structure 9; Specifically, firstly, the aforementioned dummy gate layer 16 formed by polycrystalline silicon or amorphous silicon is etched away by selective etching or etching processes; Furthermore, the interface gate oxide layer is removed, and the second sacrificial layer 13 in the superlattice stack is released by selective etching to release the nanosheet channel and form a second trench between the second semiconductor layers 12 in the second stacked structure 9. S9, such as Figures 44-46 As shown, the metal gate 25 is filled in the second trench to form a second gate stack structure. Then, the second gate stack structure and the second source / drain region are interconnected by metal. Specifically, the signal interconnection of part of the gate and the wiring from the source / drain region 27 to the relevant power rail are completed by using the contact holes to the contact holes of the source / drain region 27, the contact holes of the gate top M0 and Metal 0. The metal interconnection process of this embodiment can refer to the prior art, and will not be described in detail here.

[0055] The structure of the semiconductor device formed by the manufacturing method provided in this embodiment is the same as that of the semiconductor device provided in Embodiment 1. Therefore, the beneficial effects of this embodiment can be referred to the beneficial effect analysis in Embodiment 1 and its various implementations, and will not be repeated here.

[0056] Example 3 This embodiment provides an electronic device including the above-described semiconductor devices. The electronic device includes a smartphone, personal computer, tablet computer, artificial intelligence device, wearable device, or power bank.

[0057] The beneficial effects of this embodiment can be found in the analysis of the beneficial effects in Embodiment 1 and its various implementations, and will not be repeated here.

[0058] The above description does not provide detailed explanations of the technical aspects of each layer's patterning and etching. However, those skilled in the art should understand that various technical means can be used to form layers and regions of the desired shape. Furthermore, to create the same structure, those skilled in the art can design methods that are not entirely identical to those described above.

[0059] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, and not to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A semiconductor device, characterized in that, Including semiconductor substrates; A first transistor and a second transistor are sequentially disposed above the semiconductor substrate from bottom to top along the thickness direction of the semiconductor substrate. The first transistor includes a first gate stack structure and a first source / drain region located on both sides of the first gate stack structure. The second transistor includes a second gate stack structure and a second source / drain region located on both sides of the second gate stack structure. A gate isolation structure is disposed between the first gate stack structure and the second gate stack structure; A source / drain isolation region is provided between the first source / drain region and the second source / drain region; In the width direction of the channel, the gate isolation structure and the source / drain isolation region have the same width; The first source / drain region is located below the source / drain isolation region, and the second source / drain region is located above the source / drain isolation region; The gate isolation structure and the source / drain isolation region are integrally formed.

2. The semiconductor device according to claim 1, characterized in that, Along the length of the channel, the gate isolation structure and the source / drain isolation region have the same width.

3. The semiconductor device according to claim 1, characterized in that, The first transistor is an NMOS, and the first source / drain region contains a Si / SiC source / drain epitaxial layer; The second transistor is a PMOS, and the second source / drain region contains a GeSi source / drain epitaxial layer.

4. The semiconductor device according to claim 3, characterized in that, Along the length of the channel, the bottom of the GeSi source / drain epitaxial layer is the same width as the source / drain isolation region.

5. The semiconductor device according to claim 3, characterized in that, In the width direction of the channel, the bottom of the GeSi source / drain epitaxial layer is the same width as the source / drain isolation region.

6. The semiconductor device according to claim 1, characterized in that, The first gate stack structure and the second gate stack structure are independent graphical structures.

7. The semiconductor device according to claim 1, characterized in that, The first gate stack structure and the second gate stack structure are completely overlapping, partially overlapping, or completely non-overlapping in the horizontal projection direction of the semiconductor substrate.

8. The semiconductor device according to claim 1, characterized in that, The gate isolation structure includes a support structure and isolation bodies located on both sides of the support structure. One end of the support structure is in contact with the first gate stack structure, and the other end is in contact with the second gate stack structure. The isolation bodies are integrally formed with the source / drain isolation region.

9. The semiconductor device according to claim 8, characterized in that, The side of the supported structure is either separated from or connected to the inner wall of the isolation body.

10. The semiconductor device according to claim 8, characterized in that, The supporting structure is an intrinsic silicon layer.

11. The semiconductor device according to claim 3, characterized in that, The bottom of the GeSi source / drain epitaxial layer has the same shape as the top of the source / drain isolation region.

12. A method for fabricating a semiconductor device, characterized in that, Includes the following steps: S1. A first stacked structure, a gate isolation structure sacrificial layer, and a second stacked structure are sequentially formed on a semiconductor substrate, wherein the first stacked structure includes a first semiconductor layer and a first sacrificial layer arranged alternately in sequence, and the second stacked structure includes a second semiconductor layer and a second sacrificial layer arranged alternately in sequence. S2. The second stack structure is graphically processed to form a second channel stack, and a second source / drain region is formed on both sides of the second channel stack. S3. Bond the second substrate above the second source / drain region, flip and thin the semiconductor substrate; S4. The first stacked structure is patterned to form a first channel stack, the gate isolation structure sacrificial layer is released, and the first source / drain regions are formed on both sides of the first channel stack. S5. Etch the first sacrificial layer to form a first trench between the first semiconductor layers in the first stacked structure; S6. A first gate stack structure is formed in the first trench, and then the first gate stack structure and the first source / drain region are metal interconnected. S7. Bond the third substrate above the first source / drain region, flip and thin the second substrate; S8. Etch the second sacrificial layer to form a second trench between the second semiconductor layers in the second stacked structure; S9. Form a second gate stack structure in the second trench, and then perform metal interconnection between the second gate stack structure and the second source / drain region; The gate isolation structure sacrificial layer is intrinsic silicon, and the gate isolation structure between the first gate stack structure and the second gate stack structure and the source / drain isolation region between the first source / drain region and the second source / drain region are integrally formed.

13. The preparation method according to claim 12, characterized in that, Step S1 further includes: selectively etching back the first stacked structure, the gate isolation structure sacrificial layer, and the second stacked structure to form a fin stacked structure, and then forming a shallow trench isolation region between two adjacent fins; The upper surface of the shallow trench isolation region is lower than, flush with, or higher than the upper surface of the gate isolation structure sacrificial layer.

14. The preparation method according to claim 12, characterized in that, Step S2 specifically includes: forming a dummy gate on the exposed fin surface; depositing sidewall media on both sides of the dummy gate and performing anisotropic etching to form an outer wall; using the dummy gate and the outer wall as a mask, etching the fin stack structure to form a second channel stack; laterally etching the second sacrificial layer to form a groove, and forming an inner sidewall in the groove; forming a second source / drain region on both sides of the second channel stack.

15. The preparation method according to claim 12, characterized in that, In step S3, when thinning the semiconductor substrate, the process stops at the bottom of the shallow trench isolation region, and then the silicon fins embedded in the shallow trench isolation region are removed.

16. The preparation method according to claim 12, characterized in that, Step S4 specifically includes: forming a dummy gate on the exposed fin surface; depositing sidewall dielectric on both sides of the dummy gate and performing anisotropic etching to form outer walls; using the dummy gate and outer walls as masks, etching the fin stack structure to form a first channel stack; depositing temporary sidewall dielectric on the surface of the first channel stack and the gate isolation structure sacrificial layer, and etching the temporary sidewall dielectric to expose the gate isolation structure sacrificial layer; releasing the gate isolation structure sacrificial layer and filling it with isolation dielectric; laterally etching the first sacrificial layer to form a groove, and forming an inner sidewall in the groove; forming a first source / drain region on both sides of the first channel stack.

17. The preparation method according to claim 12, characterized in that, In step S4, the release of the gate isolation structure sacrificial layer includes full release and partial release; When the portion is released, a portion of intrinsic silicon is retained as a support structure.

18. An electronic device, characterized in that, Includes the semiconductor device according to any one of claims 1-11; The electronic devices include smartphones, personal computers, tablets, artificial intelligence devices, wearable devices, or power banks.

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