Memory allocation system, method and device based on multi-core processor and medium

Abstract

The invention relates to the technical field of memory allocation of a multi-core processor architecture, and relates to a memory allocation system, method and device based on a multi-core processor and a medium. The system comprises a main processing core used for executing a general-purpose computing task of a user application program; the special allocation processing unit is used for intensively processing all dynamic memory allocation and release requests initiated by the main processing core; the private metadata storage area is used for storing all metadata required by memory allocation, and the metadata are only accessed by the special allocation processing unit; the on-chip network bus is connected with the main processing core, the special distribution processing unit and the main memory DRAM, and is used for realizing data transmission and ensuring cache consistency; the DRAM, the common main memory of the processor and the main processing core apply for a memory area on the DRAM through the memory allocation core. Complete separation of metadata operation and a main core computing task is realized, and cache pollution and cross-core synchronization overhead are eliminated.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of memory allocation of multi-core processor architecture, and relates to a memory allocation system and method, device and medium based on a multi-core processor. BACKGROUND

[0002] In modern computer architecture, multi-core processors have become mainstream, which realize significant improvement of computing power by integrating multiple processing cores on the same chip. However, with the continuous increase of the number of processor cores, how to efficiently manage dynamic memory allocation has become a key problem to be solved. Dynamic memory allocation is the basis for all upper-layer application programs to run, which is directly related to the overall performance and scalability of the system. The traditional memory allocation mechanism exposes a series of performance bottlenecks in the multi-core, multi-thread environment, mainly in the following two aspects: Cache pollution problem: The traditional memory allocator usually mixes the metadata used to manage the memory state with the user data of the application program in the shared cache and main memory. When multiple threads are concurrently executed, the memory allocation operation needs to frequently read and write its metadata, which will occupy and replace the application program data in the main processing core cache. This process causes the cache hit rate of the main core to decrease significantly when executing the computing task, because the useful data replaced needs to be reloaded from the main memory, thereby seriously slowing down the execution speed of the program. In addition, since the metadata and user data are not effectively separated in the access path, data consistency and integrity problems may also be caused.

[0003] Cross-core synchronization overhead problem: In order to ensure the consistency and integrity of the metadata in the multi-thread environment, the traditional memory allocator must use a complex synchronization mechanism, such as atomic instructions or locks. When multiple cores simultaneously initiate memory requests, they will compete for access to shared metadata. This competition causes a large number of cores to be in a waiting state, which cannot work effectively in parallel, thereby reducing the overall throughput and response speed of the system. Especially in high-concurrency scenarios, cross-core synchronization overhead becomes a key factor restricting system performance.

[0004] In view of the above problems, the industry and academia have carried out a lot of research and exploration, and have put forward a series of improvement schemes. However, these schemes often need to make a trade-off between performance improvement and implementation complexity, and it is difficult to guarantee high performance while maintaining the simplicity and maintainability of the system. Therefore, it is of great significance to develop an efficient and low-overhead memory allocation system and method for improving the execution performance and scalability of multi-core processors in a multi-thread environment.

[0005] It should be noted that the information disclosed in the above background section is only used to strengthen the understanding of the background of the present application, and therefore can include information that does not constitute prior art known to those skilled in the art. SUMMARY

[0006] The following presents a simplified summary in order to provide a basic understanding of some aspects of the disclosed embodiments. The summary is not an extensive overview of the embodiments and is not intended to identify key / critical elements or to delineate the scope of the embodiments. Its sole purpose is to present some concepts of the embodiments in a simplified form as a prelude to the more detailed description that is presented later.

[0007] The embodiments of the present disclosure provide a memory allocation system and method based on a multi-core processor, a device and a medium. By introducing a dedicated lightweight memory allocation processing unit and a private cache inside the unit, the embodiments realize complete separation of metadata operations and main core computing tasks, eliminate cache pollution and cross-core synchronization overhead, and do not need to use expensive atomic instructions or locks, thereby significantly improving the execution performance and scalability of multi-threaded application programs in a multi-core environment.

[0008] In some embodiments, the system comprises: a main processing core for performing general computing tasks of a user application program; a dedicated allocation processing unit for centralized processing of all dynamic memory allocation and release requests initiated by the main processing core; a private metadata storage area for storing all metadata required for memory allocation, and the metadata is only accessed by the dedicated allocation processing unit; an on-chip network bus connecting the main processing core, the dedicated allocation processing unit, and a main memory DRAM, for realizing data transmission and ensuring cache consistency; a DRAM, a common main memory of a processor, and the main processing core applies a memory region on the DRAM through a memory allocation core.

[0009] Preferably, the dedicated allocation processing unit comprises: a distributor for receiving and parsing request data packets from the on-chip network bus and distributing according to the request type; a hardware request queue for receiving and buffering concurrent requests from the distributor without locking; a scheduler for monitoring the state of the request queue and selecting a request to be processed according to a preset strategy; a memory allocation unit for accessing the private metadata storage area to execute a memory allocation or release algorithm according to the instruction of the scheduler; a response logic unit for packaging and returning the result address after the memory allocation operation to the main processing core initiating the request.

[0010] Preferably, the private metadata storage area is a physical region in main memory DRAM, mapped and cached in the cache inside the dedicated allocation processing unit, the main processing core only receives and operates pointers to user data area, completely separating the access path of metadata and user data.

[0011] Preferably, the hardware request queue is a hardware-implemented FIFO queue, including an allocation queue for caching allocation requests and a release queue for caching release requests.

[0012] In some embodiments, the memory allocation method based on a multi-core processor, the method comprising: When the main processing core encounters a memory allocation or release instruction during the execution of an application, it initiates a request; The main processing core sends a request data packet containing the request type and size parameters to the dedicated allocation processing unit through the communication interface, and continues to execute other instructions that are independent of the memory request; The dedicated allocation processing unit receives the request and places it in the internal hardware request queue; The scheduler in the dedicated allocation processing unit takes the request from the queue according to a predetermined strategy and accesses its private metadata storage area to perform the actual memory allocation or release operation; For a memory allocation request, after the operation is completed, the dedicated allocation processing unit returns the allocated memory block address to the main processing core that initiated the request through the communication interface; The main processing core receives the returned address and uses the memory block.

[0013] Preferably, the step of initiating a request specifically includes: the main processing core executes a memory allocation start instruction in the extended instruction set architecture, and the hardware logic automatically packs the parameters in the instruction and the context information of the current thread into a data packet, which is directly routed to the hardware request queue of the dedicated allocation processing unit through the coherent interconnection network.

[0014] Preferably, the memory allocation start instruction is: mem_alloc_start rd,rs1,rs2, where rd is the target register used to receive the allocated memory address, rs1 is the source register storing the memory size to be allocated, and rs2 is the source register storing the entry address of the specific allocation function determined by the linker that should be executed on the dedicated allocation processing unit.

[0015] Preferably, after the main processing core receives the returned address, it uses the memory block through the newNode pointer.

[0016] In some embodiments, the multi-core processor-based memory allocation apparatus comprises a processor and a memory storing program instructions, the processor being configured to execute the multi-core processor-based memory allocation method when running the program instructions.

[0017] In some embodiments, the storage medium stores program instructions, which, when running, execute the multi-core processor-based memory allocation method.

[0018] The multi-core processor-based memory allocation system and method, apparatus and medium provided by the embodiments of the present disclosure can achieve the following technical effects: Advantages The multi-core processor-based memory allocation system and method proposed by the present disclosure has the following significant advantages compared with the traditional technology: The present disclosure introduces a dedicated memory allocation processing unit and its internal private metadata storage area, which completely separates metadata from user data. This design avoids the cache pollution problem caused by the mixed storage of metadata and user data in the traditional memory allocation mechanism. When the main processing core executes the computing task, its cache is no longer occupied and replaced by the metadata of memory allocation, thereby significantly improving the cache hit rate, reducing the number of data reloading from the main memory due to cache miss, and speeding up the program execution.

[0019] The traditional memory allocator needs to use a complex synchronization mechanism to ensure the consistency and integrity of the metadata in a multi-threaded concurrent environment, which results in high cross-core synchronization overhead. The present disclosure processes all memory allocation requests through a dedicated memory allocation processing unit and only accesses and updates metadata in its internal private cache, thereby completely avoiding the contention and synchronization problem of shared metadata by multiple threads. This innovation significantly reduces the cross-core synchronization overhead, enabling multiple processing cores to work more efficiently in parallel, improving the overall throughput and response speed of the system.

[0020] To achieve the consistency and integrity of the metadata, the traditional memory allocator often needs to use expensive atomic instructions or lock mechanisms, which not only increases the implementation complexity, but also may have a negative impact on system performance. The present disclosure fundamentally eliminates the dependence on atomic instructions or locks through hardware design and the introduction of private cache, simplifying the implementation complexity of memory allocation while ensuring the high performance and scalability of the system.

[0021] Due to the elimination of cache pollution and cross-core synchronization overhead, the memory allocation system and method of the present application significantly improves the execution performance of multi-threaded application programs in a multi-core environment. At the same time, the design has good scalability and can maintain efficient memory allocation capability as the number of processor cores increases, providing strong support for the development of future multi-core processors.

[0022] The foregoing general description and the following description are merely exemplary and explanatory and are not intended to limit the present application. BRIEF DESCRIPTION OF DRAWINGS

[0023] One or more embodiments are illustrated by way of example, in reference to the accompanying drawings, which are schematic and not intended to be limiting of the embodiments, and in which like numerals refer to like elements throughout the drawings, the drawings are not necessarily to scale, and in which: Figure 1 is a schematic diagram of the system structure of the present application; Figure 2 is a schematic diagram of the structure of the special memory allocation processing unit provided by the embodiment of the present application; Figure 3 is a schematic diagram of the memory allocation method flow based on a multi-core processor provided by the embodiment of the present application; Figure 4 is a schematic diagram of the device structure of the embodiment of the present application. DETAILED DESCRIPTION

[0024] In order to enable a more detailed understanding of the features and technical contents of the embodiments of the present application, the implementation of the embodiments of the present application will be described in detail below in conjunction with the drawings, which are only used for reference and do not limit the embodiments of the present application. In the following technical description, a plurality of details are provided to facilitate a full understanding of the disclosed embodiments. However, one or more embodiments can still be implemented without these details. In other cases, well-known structures and devices can be simplified for the sake of the drawings.

[0025] The terms "first", "second", and the like in the specification and claims of the embodiments of the present application and the above drawings are used to distinguish similar objects and do not necessarily describe a specific order or sequence. It should be understood that the data thus used can be interchanged under appropriate circumstances to implement the embodiments of the present application described herein. In addition, the terms "include" and "have" and any variations thereof are intended to cover non-exclusive inclusion.

[0026] Unless otherwise specified, the term "a plurality of" means two or more.

[0027] In the embodiments of the present application, the character " / " represents an "or" relationship between the objects before and after it. For example, A / B means A or B.

[0028] The term "and / or", means a relation of association, can exist three kinds of relations. For example, A and / or B, means: A or B, or, A and B three kinds of relations.

[0029] The term "corresponding" can refer to a kind of association or binding relationship, A and B corresponding to A and B between a kind of association or binding relationship.

[0030] Embodiment 1 As Figures 1-2 A memory allocation system based on multi-core processor, the system comprises: The main processing core is used for executing the general computing task of user application program; The special allocation processing unit is used for centralized processing of all dynamic memory allocation and release requests initiated by the main processing core; Private metadata storage area is used for storing all metadata required for memory allocation, and the metadata is only accessed by the special allocation processing unit; Network on chip bus, connecting the main processing core, the special allocation processing unit and the main memory DRAM, for realizing data transmission and ensuring cache consistency; DRAM, common main memory of processor, main processing core applies memory region on DRAM through memory allocation core.

[0031] As a refinement of the above embodiment, the cache (L1Cache) built-in the special allocation processing unit is specially used for storing all metadata required for memory allocation. These data will not be loaded into the cache of the main processing core, and the main processing core finally only receives a pointer to the user data area and directly operates the memory region corresponding to the address, and the metadata and user data are completely separated in the access path. The region is a physical region in the main memory DRAM, when any core needs to perform memory allocation, it will load this region from the main memory into the cache to speed up the access.

[0032] Specifically, it comprises: The distributor is used for receiving and analyzing the request data packet from the network on chip bus, and the distributor analyzes the data packet type and pushes the allocation request into the allocation request queue and the release request into the release request queue.

[0033] Hardware request queue is used for receiving and buffering the concurrent requests from the distributor without lock; The scheduler is used for monitoring the state of the request queue and selecting the request to be processed according to the preset strategy; a memory allocation unit, for accessing the private metadata storage area to execute memory allocation or deallocation algorithm according to the instruction of the scheduler; a response logic unit, for packing and returning the result address after the completion of memory allocation operation to the main processing core that initiates the request. When the allocation operation is completed, the processing core puts the result (allocated address) into the response queue, and the response logic unit is responsible for packing and sending the completion signal back to the main core.

[0034] As a refinement of the above embodiment, the private metadata storage area is a physical area in the main memory DRAM, which is mapped and cached in the cache built-in the dedicated allocation processing unit, and the main processing core only receives and operates the pointer pointing to the user data area, completely separating the access path of metadata and user data.

[0035] As a refinement of the above embodiment, the hardware request queue is a hardware-implemented FIFO queue, including an allocation queue for caching allocation requests and a deallocation queue for caching deallocation requests.

[0036] As a refinement of the above embodiment, a special communication system inside the multi-core processor chip realizes basic data transmission and ensures that the data between the cache (Cache) of all processor cores and the main memory are consistent and synchronized, which is realized through the cache coherence protocol.

[0037] As a refinement of the above embodiment, when the memory allocation unit receives a memory allocation request from the main computing core, it will send the request to different hardware request queues (allocation queue mallocqueue and deallocation queue freequeue) according to the request type (allocation or deallocation), and the scheduler will extract the request from the queue according to the established strategy and execute it by the internal lightweight processing core. The processing core only accesses its private metadata cache to find or update memory block information during execution. The processing result (allocated address) is returned to the corresponding main processing core through the response logic unit.

[0038] Embodiment 2 As shown in Figure 3 A memory allocation method based on a multi-core processor, the method comprising: S1: When a main processing core executes an application program, it encounters a memory allocation or deallocation instruction, and then initiates a request; S2: The main processing core sends a request data packet containing the request type and size parameters to the dedicated allocation processing unit through a communication interface, and continues to execute other instructions that are independent of the memory request; S3: The dedicated allocation processing unit receives the request and puts it into the internal hardware request queue; S4: The scheduler in the dedicated allocation processing unit takes the request from the queue according to a predetermined strategy, and accesses its private metadata storage area to perform the actual memory allocation or release operation; S5: For a memory allocation request, after the operation is completed, the dedicated allocation processing unit returns the allocated memory block address to the main processing core initiating the request through the communication interface; S6: After the main processing core receives the returned address, the memory block is used.

[0039] As a refinement of the above embodiment, the step of initiating the request specifically includes: the main processing core executes a memory allocation start instruction in an extended instruction set architecture, and hardware logic automatically packs the parameters in the instruction and the context information of the current thread into a data packet, and routes the data packet to the hardware request queue of the dedicated allocation processing unit through the coherent interconnection network.

[0040] As a refinement of the above embodiment, in order to realize low-delay communication, the instruction set architecture (ISA) of the processor is extended, and a new instruction is added. The allocation start (mem_alloc_start) instruction is added. When the main processing core executes this instruction, the hardware will automatically pack the parameters (request size) in the instruction and the context information (process ID) of the current thread into a data packet, and route the data packet to the hardware request queue of the dedicated allocation processing unit through the coherent interconnection network. This process can bypass the traditional memory access and cache hierarchy, and the delay is extremely low.

[0041] The memory allocation start instruction is: mem_alloc_start rd, rs1, rs2, where rd is the target register used to receive the allocated memory address, rs1 is the source register storing the memory size to be allocated, and rs2 is the source register storing the entry address of the specific allocation function determined by the linker and which should be executed on the dedicated allocation processing unit.

[0042] As a refinement of the above embodiment, after the main processing core receives the returned address, the memory block is used through the newNode pointer.

[0043] The above method will be explained in combination with specific embodiments: Step 1: Execution of application code and conversion during compilation GraphNode* newNode = new GraphNode(node_id, initial_data); The above C++ code performs a memory allocation operation. The compiler and linker convert the above code into the extended instruction defined in the present application: mem_alloc_start rd, rs1, rs2, rd is the target register, which receives the allocated memory address (i.e. the newNode pointer) rs1: source register, which stores the size of the memory to be allocated (sizeof(GraphNode)) rs2: source register, which stores the entry address of the specific allocation function determined by the linker and to be executed on the memory processing unit.

[0044] Step 2: The main core initiates a memory allocation request When the instruction stream of the main processing core executes to this mem_alloc_start instruction, the hardware logic automatically performs the following operations: Packing the call data to generate a data packet including the request type, request size, initiator process ID, current process PID, and memory processing unit function address.

[0045] Packet sending: the data packet is injected into the on-chip coherent interconnection network, and its target address is routed to the memory processing unit.

[0046] Parallel execution. After sending the data packet, the main processor continues to execute the subsequent instructions that do not depend on the newNode pointer Step 3: The memory processing unit receives the data packet and processes the request Request queuing. The distributor parses the data packet and pushes it into the allocation request queue Task scheduling. The scheduler uses a custom strategy (such as polling) to sequentially take out tasks Execute the allocation algorithm. The processing unit accesses the private metadata storage area, executes memory allocation, and then updates the metadata.

[0047] Step 4: Result return and task completion Packing and sending response: the memory processing unit packs the allocated address 0xABCD1234 into a response data packet and sends it back to the main processing core through the interconnection network.

[0048] Main core execution. When the main core execution stream needs to use the newNode pointer, it checks whether the allocation task is completed, and after the allocation is completed, the newNode pointer in the application now holds a valid address.

[0049] Example 3 Combination Figure 4As shown, the embodiment of the present disclosure provides a memory allocation apparatus 300 based on a multi-core processor, which comprises a processor 304 and a memory 301. Optionally, the apparatus can further comprise a communication interface 302 and a bus 303. The processor 304, the communication interface 302 and the memory 301 can complete communication with each other through the bus 303. The communication interface 302 can be used for information transmission. The processor 304 can invoke the logic instructions in the memory 301 to execute the memory allocation method based on a multi-core processor of the above-mentioned embodiment.

[0050] In addition, the logic instructions in the memory 301 described above can be realized in the form of a software functional unit and sold or used as an independent product, which can be stored in a computer readable storage medium.

[0051] The memory 301 as a computer readable storage medium can be used to store software programs, computer executable programs, such as program instructions / modules corresponding to the method in the embodiment of the present disclosure. The processor 304 executes the program instructions / modules stored in the memory 301, thereby performing functional applications and data processing, i.e. realizing the memory allocation method based on a multi-core processor in the above-mentioned embodiment.

[0052] The memory 301 can include a program storage area and a data storage area, wherein the program storage area can store an operating system and at least one application required by a function; the data storage area can store data created according to the use of the terminal device, etc. In addition, the memory 301 can include a high-speed random access memory, and can further include a non-volatile memory.

[0053] The embodiment of the present disclosure provides a computer readable storage medium, which stores computer executable instructions, and the computer executable instructions are set to execute the memory allocation method based on a multi-core processor.

[0054] The computer readable storage medium described above can be a transitory computer readable storage medium or a non-transitory computer readable storage medium.

[0055] The technical solutions of the embodiments of the present disclosure can be embodied in the form of a software product. The computer software product is stored in a storage medium and includes one or more instructions for causing a computer device (which can be a personal computer, a server, or a network device, etc.) to execute all or part of the steps of the method disclosed in the embodiments of the present disclosure. The aforementioned storage medium can be a non-transitory storage medium, including: a U disk, a mobile hard disk, a read-only memory (ROM), a random access memory (RAM), a magnetic disk or an optical disk, and various media that can store program codes, or can be a transitory storage medium.

[0056] The above description and drawings sufficiently illustrate the embodiments of the present disclosure to enable one skilled in the art to practice them. Other embodiments can include structural, logical, electrical, process, and other changes. The embodiments represent only a few of the possible variations. Individual components and functions are optional unless explicitly required, and the order of operations can be changed. Parts and features of some embodiments can be included in or replace parts and features of other embodiments. Also, the words used in this application are used only to describe the embodiments and not to limit the claims. As used in the description of the embodiments and the claims, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. Similarly, the term "and / or" as used in this application means to include one or more associated listed items in any and all possible combinations. In addition, when used in this application, the term "comprise" and its variants "comprises" and / or comprises" and the like mean the presence of stated features, integers, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof. Without more limitations, the element defined by the phrase "comprising a" does not exclude the presence of additional identical elements in the process, method, or device that includes the stated element. In this document, each embodiment focuses on the differences from other embodiments, and the same or similar parts between various embodiments can be referred to each other. For the method, product, etc. disclosed in the embodiments, if it corresponds to the method part disclosed in the embodiments, the relevant part can be referred to the description of the method part.

[0057] Those skilled in the art can understand that the units and algorithm steps of each example described in combination with the embodiments disclosed herein can be realized by electronic hardware or a combination of computer software and electronic hardware. Whether the functions are realized in hardware or software depends on the specific application and design constraints of the technical solution. The skilled person can use different methods for each specific application to realize the described functions, but such implementation should not be considered beyond the scope of the embodiments of the present disclosure. The skilled person can clearly understand that, for the convenience and brevity of description, the specific working processes of the above-described system, device and unit can refer to the corresponding processes in the foregoing method embodiments, which will not be repeated here.

[0058] In the embodiments disclosed herein, the disclosed methods, products (including but not limited to devices, equipment, etc.) can be implemented in other ways. For example, the above-described device embodiments are only schematic, for example, the division of the units can only be a logical function division, and actual implementation can have another division manner, for example, a plurality of units or components can be combined or integrated into another system, or some features can be ignored or not executed. In addition, the coupling or direct coupling or communication connection between the units shown or discussed can be indirect coupling or communication connection through some interface, device or unit, and can be electrical, mechanical or other forms. The units described as separate components can or can not be physically separate, and the components shown as units can or can not be physical units, that is, they can be located in one place, or can be distributed on a plurality of network units. Part or all of the units can be selected according to actual needs to implement the embodiments. In addition, each functional unit in the embodiments of the present disclosure can be integrated in one processing unit, or each unit can be a physically independent unit, or two or more units can be integrated in one unit.

[0059] The computer program instructions can also be loaded onto a computer, other programmable data processing apparatus, or other processing device to cause a series of operational steps to be performed on the computer, other programmable apparatus or other processing device to produce a computer implemented process such that the instructions which execute on the computer or other programmable apparatus provide processes for implementing the functions / acts specified in the flowchart and / or block diagram block or blocks.

Claims

1. A memory allocation system based on a multi-core processor, characterized in that, include: The main processing core is used to execute general computing tasks for user applications; A dedicated allocation processing unit is used to centrally process all dynamic memory allocation and release requests initiated by the main processing cores; A private metadata storage area is used to store all metadata required for memory allocation, and the metadata is only accessed by the dedicated allocation processing unit; An on-chip network bus connects the main processing core, the dedicated allocation processing unit, and the main memory DRAM, and is used to realize data transmission and ensure cache consistency. DRAM is the processor's common main memory. The main processing core requests memory regions on DRAM through the memory allocation core.

2. The memory allocation system based on a multi-core processor according to claim 1, characterized in that, The dedicated allocation processing unit includes: A distributor is used to receive and parse request packets from the on-chip network bus and distribute them according to the request type. A hardware request queue is used to receive and cache concurrent requests from the dispatcher without locking; The scheduler is used to monitor the status of the request queue and select requests to be processed according to a preset strategy; The memory allocation unit is used to access the private metadata storage area to execute memory allocation or release algorithms according to the instructions of the scheduler; The response logic unit is used to package the result address after the memory allocation operation is completed and return it to the main processing core that initiated the request.

3. The memory allocation system based on a multi-core processor according to claim 1, characterized in that, The private metadata storage area is a physical region in the main memory DRAM, which is mapped and cached in the high-speed cache built into the dedicated allocation processing unit. The main processing core only receives and operates pointers to the user data area, completely separating the access paths of metadata and user data.

4. The memory allocation system based on a multi-core processor according to claim 2, characterized in that, The hardware request queue is a hardware-implemented FIFO queue, including an allocation queue for cache allocation requests and a release queue for cache release requests.

5. A memory allocation method based on a multi-core processor, applied to the system as described in any one of claims 1-4, characterized in that, The method includes: When the main processing core encounters a memory allocation or deallocation instruction while executing an application, it initiates a request. The main processing core sends a request data packet containing request type and size parameters to the dedicated allocation processing unit through the communication interface, and continues to execute other instructions that are not dependent on the memory request; The dedicated allocation processing unit receives the request and puts it into its internal hardware request queue; The scheduler in the dedicated allocation processing unit retrieves requests from the queue according to a predetermined strategy and accesses its private metadata storage area to perform actual memory allocation or release operations. For memory allocation requests, after the operation is completed, the dedicated allocation processing unit returns the allocated memory block address to the main processing core that initiated the request through the communication interface; After receiving the returned address, the main processing core uses the memory block.

6. The memory allocation method based on a multi-core processor according to claim 5, characterized in that, The steps for initiating the request specifically include: the main processing core executes the memory allocation start instruction in the extended instruction set architecture, the hardware logic automatically packages the parameters in the instruction and the context information of the current thread into a data packet, and routes it directly to the hardware request queue of the dedicated allocation processing unit through the consistent interconnect network.

7. The memory allocation method based on a multi-core processor according to claim 6, characterized in that, The memory allocation start instruction is: mem_alloc_start rd,rs1,rs2, where rd is the destination register used to receive the memory address to be allocated, rs1 is the source register storing the size of the memory to be allocated, and rs2 is the source register storing the entry address of the specific allocation function to be executed on the dedicated allocation processing unit, as determined by the linker.

8. The memory allocation method based on a multi-core processor according to claim 6, characterized in that, After receiving the returned address, the main processing core uses the memory block through the newNode pointer.

9. A memory allocation device based on a multi-core processor, comprising a processor and a memory storing program instructions, characterized in that, The processor is configured to perform the memory allocation method based on a multi-core processor as described in any one of claims 5 to 8 when executing the program instructions.

10. A storage medium storing program instructions, characterized in that, When the program instructions are executed, they perform the memory allocation method based on a multi-core processor as described in any one of claims 5 to 8.

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