Test vector construction method

Abstract

The invention provides a test vector construction method, which is used for constructing a test vector set required by a to-be-tested digital circuit, and comprises the following steps: S1, obtaining the to-be-tested digital circuit and a to-be-tested fault list corresponding to the to-be-tested digital circuit, the to-be-tested fault list comprising a plurality of circuit faults; s2, multiple rounds of simplification operation are executed until the number of circuit faults which can be detected by all the obtained test vectors is larger than or equal to a preset threshold value, all the test vectors obtained by each round of simplification operation are stored in a variable-capacity vector pool, the capacity of the vector pool corresponding to each round is a preset multiple of the capacity of the vector pool corresponding to the previous round, and the test vectors are stored in the variable-capacity vector pool; wherein each round of simplification operation comprises a static simplification stage and a dynamic simplification stage, the static simplification stage repeatedly fills a vector pool and reduces the number of test vectors in the vector pool, and the dynamic simplification stage fills a part of the uncertain items in the test vectors with the uncertain items obtained in the static simplification stage as 0 or 1.

Description

Technical Field

[0001] This invention relates to the field of design-for-testability of digital integrated circuits, more specifically to test vector construction technology in the field of design-for-testability of digital integrated circuits, and more specifically, to a test vector construction method. Background Technology

[0002] Digital integrated circuit testing is a crucial step in the chip design process. In recent years, with the increasing scale and complexity of chip designs, the complexity of Automatic Test Pattern Generation (ATPG) and the size of test vector sets have expanded dramatically, continuously driving up testing costs. Therefore, efficiently testing chips remains a significant challenge.

[0003] Test simplification is an effective way to reduce test vectors. Test vectors generated after testing generally contain definite bits (0 and 1) and indefinite bits (X). However, test vectors often contain a large number of indefinite bits (X), allowing for compatibility and merging between different vectors, such as... Figure 1 As shown, uncertain bits X and 0 can be merged into 0, and uncertain bits X and 1 can be merged into 1, greatly expanding the possibilities for test vector simplification. Traditionally, there are two test simplification methods: static simplification and dynamic simplification. Static simplification refers to the process of deleting redundant test vectors from the test set after test vector generation. The static simplification process performs compatibility processing on the uncertain bits (X bits) in the test vectors, without changing the definite bits (0 and 1) in the test vectors. Dynamic simplification refers to the process of merging test vectors generated for different faults into a single test vector as much as possible during the test vector generation process. There are also methods that combine dynamic and static simplification. Generally, during test generation, test vectors with a large number of X bits are generated first, and then dynamic simplification is performed on these, filling in more X bits to make them definite bits 0 or 1, detecting more faults. Finally, after all test vectors are generated, static simplification is performed on all test vectors to delete redundant test vectors.

[0004] Existing static test simplification methods mainly fall into two categories. The first is a simplification strategy based on reverse fault simulation: after generating the complete test vector set, fault simulation is performed again on the test vectors in reverse order, eliminating redundant vectors that haven't activated any new faults. While simple to implement, this method requires additional execution of the complete fault simulation process, resulting in high computational overhead and long processing time. Furthermore, the compression ratio is limited by the initial vector order, making it unsuitable for large-scale designs. The second is the SAT / MaxSAT method based on compatibility modeling: by constructing a "fault-vector" mapping dictionary, the compression problem is transformed into a set coverage or maximum satisfiability problem, and then a solver is used to identify merging compatible vectors. However, constructing a complete fault dictionary requires cross-simulation of all faults and all vectors, resulting in extremely high time complexity. Simultaneously, general-purpose SAT / MaxSAT solvers are inefficient when handling large-scale industrial instances, failing to obtain the optimal solution within a reasonable timeframe, severely limiting the practicality of this method.

[0005] Existing dynamic test simplification methods mostly employ an incremental ATPG strategy: first, a test vector with a large number of X bits is generated for the target fault; then, under the assignment constraints of this vector, compatible tests are attempted to be generated for other remaining faults to achieve single-vector multi-fault coverage. While this method theoretically has high compression potential, it faces two major bottlenecks in practical applications: first, the incremental process is computationally expensive, especially when the faults being attempted to fill are incompatible with the current constraints, leading to ineffective searches and wasting significant computational resources; second, the lack of an effective pre-screening mechanism for fault compatibility judgment results in numerous invalid attempts, further slowing down the overall process. Furthermore, existing methods often use static and dynamic compression separately, lacking a mechanism for adaptive switching and collaborative optimization based on the characteristics of the test generation stage, making it difficult to achieve the optimal balance between compression ratio and operational efficiency.

[0006] Although existing test simplification methods can reduce test vectors to some extent, they still suffer from long test times, redundant test vectors, and high test costs when dealing with larger-scale circuit designs.

[0007] It should be noted that the background information presented here is only for illustrating relevant information about the present invention to aid in understanding the technical solutions of the present invention, and does not imply that the relevant information is necessarily prior art. In the absence of evidence indicating that the relevant information was disclosed before the filing date of this invention, the relevant information should not be considered prior art. Summary of the Invention

[0008] Therefore, the purpose of this invention is to overcome the shortcomings of the prior art and provide a test vector construction method.

[0009] The objective of this invention is achieved through the following technical solutions.

[0010] This invention provides a test vector construction method for constructing a test vector set required for a digital circuit under test. The test vector set includes multiple test vectors. The method includes: Step S1, obtaining the digital circuit under test and its corresponding list of faults to be tested, wherein the list of faults to be tested includes multiple circuit faults; Step S2, performing multiple rounds of simplification operations until the number of circuit faults that can be detected by all obtained test vectors is greater than or equal to a preset threshold. All test vectors obtained in each round of simplification operations are stored in a variable-capacity vector pool. The capacity of the vector pool for each round is a preset multiple of the capacity of the vector pool for the previous round. Each round of simplification operations is performed as follows: Static simplification stage: Selecting any fault that cannot be detected by the current round from the list of faults to be tested. The test vectors detect multiple circuit faults and generate a test vector for each fault to fill the vector pool corresponding to the current round. A static simplification method is used to reduce the number of test vectors in the filled vector pool of the current round. This process of filling and reducing the vector pool continues until the number of test vectors in the current round cannot be reduced further and the number of test vectors equals a preset value. Each test vector includes multiple logic values, with each bit being 0, 1, or an uncertain term. In the dynamic simplification phase, all test vectors obtained in the static simplification phase are processed using a dynamic simplification method to fill some uncertain terms in test vectors with 0 or 1, until the number of circuit faults detected by all test vectors no longer increases.

[0011] According to some embodiments of the present invention, the method further includes: in the static simplification phase of each round of simplification operation, the static simplification method is to reduce the number of test vectors in the vector pool corresponding to the current round that is filled by following the steps of: performing a compatibility check on any two test vectors in the vector pool corresponding to the current round that is filled to determine whether the two test vectors are compatible, and merging the two compatible test vectors into a new test vector and storing it in the vector pool, until there are no compatible test vectors in the vector pool.

[0012] According to some embodiments of the present invention, the method further includes: performing a compatibility check on any two test vectors in the following manner: analyzing whether the logical values ​​of each identical bit in the two test vectors are compatible; if the logical values ​​of each identical bit in the two test vectors are compatible, then the two test vectors are compatible; otherwise, the two test vectors are incompatible.

[0013] According to some embodiments of the present invention, the method further includes: analyzing whether the logical values ​​of each corresponding bit in two test vectors are compatible in the following manner: if the logical values ​​of the corresponding bits in the two test vectors are the same, or if the logical value of the corresponding bit in one of the test vectors is an uncertain term, then the logical values ​​of the corresponding bits in the two test vectors are compatible; otherwise, the logical values ​​of the corresponding bits in the two test vectors are incompatible.

[0014] According to some embodiments of the present invention, the method further includes: merging two compatible test vectors into a new test vector in the following manner: determining the logical value of each common bit in the two test vectors; if the logical values ​​of the common bits of the two test vectors are the same, then keeping the logical value of the common bits unchanged; if the logical value of the common bit of one test vector is an indeterminate term, and the logical value of the common bit of the other test vector is 0 or 1, then setting the logical value of the common bit to 0 or 1.

[0015] According to some embodiments of the present invention, the method further includes: in each round of simplification, the dynamic simplification is performed by processing all test vectors obtained in the static simplification stage according to the following steps: determining all circuit faults in the circuit fault list that cannot be detected by any test vector obtained in the static simplification stage to obtain the current round fault detection set; analyzing all circuit faults in the current round fault detection set that are compatible with all test vectors obtained in the static simplification stage to obtain the current round dynamic simplification set; based on all circuit faults in the current round dynamic simplification set, filling some uncertain terms in the test vectors with uncertain terms with 0 or 1, until the number of circuit faults that can be detected by all test vectors in the vector pool corresponding to the current round no longer increases.

[0016] According to some embodiments of the present invention, the digital circuit under test includes multiple logic gates, each logic gate having an input pin and an output pin. Each circuit fault in the fault list indicates that the logic value of the corresponding logic gate's input pin or output pin is always 0 or always 1. The method further includes: analyzing all circuit faults in the current round of fault detection set that are compatible with all test vectors obtained in the static simplification stage in the following manner: injecting each circuit fault in the current round of fault detection set into the corresponding input or output pin of the digital circuit under test, filling all test vectors obtained in the static simplification stage into a fixed-bit machine word, and performing logic simulation using the machine word and the digital circuit under test after injecting different circuit faults. If the logic simulation result shows that the logic value of the input or output pin with the circuit fault is different from the logic value without the circuit fault, it indicates that one or more test vectors obtained in the static simplification stage are compatible with the corresponding circuit fault; otherwise, it indicates that one or more test vectors obtained in the static simplification stage are not compatible with the corresponding circuit fault.

[0017] According to some embodiments of the present invention, the preset value is 64.

[0018] Compared with the prior art, the advantages of the present invention are: (1) Through multiple rounds of simplification operations in coordination of static simplification and dynamic simplification, the simplification efficiency of test vectors can be significantly improved while ensuring circuit fault coverage, thereby solving the problems of test vector expansion and high test costs; (2) The static simplification stage in each round of simplification operations can automatically increase the size of the vector pool to accommodate more test vectors, thereby improving the possibility of test vector compatibility; (3) The dynamic simplification stage in each round of simplification operations uses fault blocking analysis to eliminate circuit faults that cannot be compatible with the current round of simplification operations, and optimizes the performance of fault blocking analysis through machine word parallelism, thereby improving the efficiency of dynamic simplification. Attached Figure Description

[0019] The embodiments of the present invention will be further described below with reference to the accompanying drawings, wherein:

[0020] Figure 1 This is a schematic diagram illustrating a simplified test vector example according to an embodiment of the present invention;

[0021] Figure 2 This is a schematic diagram of the test vector construction method according to an embodiment of the present invention;

[0022] Figure 3 This is an example schematic diagram of test vector and circuit fault compatibility analysis according to an embodiment of the present invention;

[0023] Figure 4 A schematic diagram illustrating an example of test vector filling according to an embodiment of the present invention;

[0024] Figure 5 This is a schematic diagram of the execution flow of the test vector construction method according to an embodiment of the present invention. Detailed Implementation

[0025] To make the objectives, technical solutions, and advantages of this invention clearer, the invention will be further described in detail below with reference to the accompanying drawings and specific embodiments. It should be understood that the specific embodiments described herein are merely illustrative and are not intended to limit the invention.

[0026] As mentioned in the background section, although existing test simplification methods can reduce test vectors to some extent, they still suffer from long test times, redundant test vectors, and high test costs when dealing with larger-scale circuit designs.

[0027] To address the aforementioned issues, the inventors analyzed existing test simplification methods and discovered that digital integrated circuit testing involves both easily testable and difficult-to-test faults. The vast majority of easily testable faults are quickly covered in the early stages of testing (e.g., within the first 64-128 vectors), contributing over 60%-70% of the fault coverage. While the remaining difficult-to-test faults constitute a smaller proportion, they often require the generation of numerous incompatible test vectors to cover, becoming the main cause of test set expansion. Further analysis revealed that while static simplification methods can increase merging opportunities and reduce the final number of vectors by expanding the vector pool, they also decrease fault coverage. Dynamic simplification methods, while reducing the number of vectors while maintaining coverage through incremental test generation, rely on fault-by-fault attempts and constraint propagation, resulting in significant computational overhead. This is particularly problematic when dealing with difficult-to-test faults, easily leading to inefficient searches and significantly slowing down the overall process.

[0028] Based on the above analysis, this invention proposes a novel test vector construction method for rapidly constructing the test vector set required for a digital circuit under test. Specifically, this method first obtains the digital circuit under test and its corresponding list of faults to be tested, which includes multiple circuit faults. Then, multiple rounds of simplification operations are performed until the number of circuit faults detectable by all obtained test vectors is greater than or equal to a preset threshold. All test vectors obtained in each round of simplification are stored in a variable-capacity vector pool. Each round of simplification includes a static simplification stage and a dynamic simplification stage. In the static simplification stage, the vector pool is repeatedly filled and the number of test vectors in the pool is reduced. In the dynamic simplification stage, some uncertain terms in the test vectors with uncertain terms obtained in the static simplification stage are filled with 0 or 1. Through multiple rounds of simplification operations combining static and dynamic simplification, the simplification efficiency of test vectors can be significantly improved while ensuring circuit fault coverage, thereby solving the problems of test vector bloat and high testing costs.

[0029] In summary, such as Figure 2As shown, a test vector construction method is provided for constructing a test vector set required for a digital circuit under test. The test vector set includes multiple test vectors. The method includes: Step S1, obtaining the digital circuit under test and its corresponding list of faults to be tested, wherein the list of faults to be tested includes multiple circuit faults; Step S2, performing multiple rounds of simplification operations until the number of circuit faults that can be detected by all the obtained test vectors is greater than or equal to a preset threshold. All test vectors obtained in each round of simplification operations are stored in a vector pool with variable capacity. The capacity of the vector pool corresponding to each round is a preset multiple of the capacity of the vector pool corresponding to the previous round. Each round of simplification operations is performed as follows: Static simplification stage: Selecting any fault that cannot be detected by the current round from the list of faults to be tested. The test vectors detect multiple circuit faults and generate a test vector for each fault to fill the vector pool corresponding to the current round. A static simplification method is used to reduce the number of test vectors in the filled vector pool of the current round. This process of filling and reducing the vector pool continues until the number of test vectors in the current round cannot be reduced further and the number of test vectors equals a preset value. Each test vector includes multiple logic values, with each bit being 0, 1, or an uncertain term. In the dynamic simplification phase, all test vectors obtained in the static simplification phase are processed using a dynamic simplification method to fill some uncertain terms in test vectors with 0 or 1, until the number of circuit faults detected by all test vectors no longer increases.

[0030] To better understand the present invention, each step will be described in detail below with reference to specific embodiments.

[0031] I. Step S1

[0032] In step S1, the digital circuit under test (DUT) and its corresponding fault list are obtained, where the fault list includes multiple circuit faults. For the DUT, the corresponding fault list can be obtained as follows: First, read the Verilog gate-level design netlist of the DUT (this netlist is represented by synthesized logic gates, such as AND, OR, NOT, etc.) and parse the netlist to connect all logic gates in the DUT to form a directed acyclic graph data structure; then, set faults on the input / output pins of each logic gate, including two types of faults: Stuck-At 0 (SA0) and Stuck-At 1 (SA1), where Stuck-At 0 (SA0) indicates that the logic value on the pin is always 0, and Stuck-At 1 (SA1) indicates that the logic value on the pin is always 1; finally, summarizing the faults on the input / output pins of each logic gate yields the fault list corresponding to the DUT.

[0033] II. Step S2

[0034] In step S2, multiple rounds of simplification are performed until the number of circuit faults detectable by all the obtained test vectors is greater than or equal to a preset threshold. All test vectors obtained in each round of simplification are stored in a variable-capacity vector pool. The capacity of the vector pool for each round is a preset multiple of the capacity of the vector pool for the previous round. Each round of simplification is performed as follows: Static simplification stage: Select multiple circuit faults from the list of faults to be tested that cannot be detected by any existing test vector in the current round, and generate test vectors for each circuit fault to fill the vector pool for the current round, and then perform static simplification. The method involves reducing the number of test vectors in the vector pool corresponding to the current round, repeatedly filling the vector pool and reducing the number of test vectors until the number of test vectors in the vector pool corresponding to the current round cannot be reduced and the number of test vectors equals a preset value. Each test vector includes multiple logic values, where each logic value is 0, 1, or an uncertain term. In the dynamic simplification stage, all test vectors obtained in the static simplification stage are processed using a dynamic simplification method to fill some uncertain terms in test vectors with 0 or 1, until the number of circuit faults detectable by all test vectors no longer increases. According to one embodiment of the present invention, the preset value is 64.

[0035] It should be noted that although the vector pool can expand its capacity during multiple rounds of simplification, the capacity of the vector pool cannot be expanded indefinitely. If the capacity pool reaches its maximum capacity after multiple rounds of simplification, it will not continue to expand. The maximum capacity of the capacity pool is determined according to actual needs. For example, the maximum capacity of the capacity pool can be set to 4096. This invention does not impose any special restrictions.

[0036] It should also be noted that the preset multiplier can be set based on actual needs, such as 2, 3, 4, etc., and this invention does not impose any special restrictions.

[0037] To better understand each round of streamlining operations, the static streamlining phase and the dynamic streamlining phase in each round will be introduced below.

[0038] 2.1 Static Simplification Stage

[0039] In the static simplification phase of each round of simplification: multiple circuit faults that cannot be detected by any existing test vectors in the current round are selected from the list of faults under test. A test vector is generated for each circuit fault to fill the vector pool corresponding to the current round. Static simplification is then used to reduce the number of test vectors in the filled vector pool. This process of filling and reducing the vector pool continues until the number of test vectors in the current round's vector pool cannot be reduced further and the number of test vectors equals a preset value. Each test vector includes multiple logic values, with each bit being 0, 1, or an indeterminate value. It should be noted that after multiple rounds of simplification, if there are few undetectable circuit faults remaining in the list of faults under test, the vector pool may not be full. In this case, test vectors are first generated for the remaining undetected circuit faults, and then the number of test vectors in the vector pool is reduced using static simplification before entering the dynamic simplification phase. This phase does not require repeated filling of the vector pool.

[0040] According to an embodiment of the present invention, the method further includes: in the static simplification phase of each round of simplification operation, the static simplification method is to reduce the number of test vectors in the vector pool corresponding to the current round that is filled by following the steps of: performing a compatibility check on any two test vectors in the vector pool corresponding to the current round that is filled to determine whether the two test vectors are compatible, and merging the two compatible test vectors into a new test vector and storing it in the vector pool, until there are no compatible test vectors in the vector pool.

[0041] According to an embodiment of the present invention, the method further includes: performing a compatibility check on any two test vectors in the following manner: analyzing whether the logical values ​​of each identical bit in the two test vectors are compatible; if the logical values ​​of each identical bit in the two test vectors are compatible, then the two test vectors are compatible; otherwise, the two test vectors are incompatible.

[0042] According to an embodiment of the present invention, the method further includes: analyzing whether the logical values ​​of each corresponding bit in two test vectors are compatible in the following manner: if the logical values ​​of the corresponding bits in the two test vectors are the same, or if the logical value of the corresponding bit in one of the test vectors is an uncertain term, then the logical values ​​of the corresponding bits in the two test vectors are compatible; otherwise, the logical values ​​of the corresponding bits in the two test vectors are incompatible.

[0043] To better understand the compatibility checks during the static simplification phase, the following will use... Figure 1 Taking the test vector shown as an example, and combining it with the aforementioned embodiments, we will explain how to determine whether test vectors are compatible. Figure 1This includes test vector P1 (0X11), test vector P2 (001X), and test vector P3 (0110).

[0044] For test vectors P1 (0X11) and P2 (001X), if the first logical value of both test vectors P1 and P2 is 0, then the logical values ​​of the first logical value of test vectors P1 and P2 are compatible. If the logical value of test vector P1 in the second bit is the uncertain term X, then the logical values ​​of test vectors P1 and P2 in the second bit are also compatible. If the third logical value of both test vectors P1 and P2 is 1, then the logical values ​​of test vectors P1 and P2 in the third bit are also compatible. If the logical value of test vector P2 in the fourth bit is the uncertain term X, then the logical values ​​of test vectors P1 and P2 in the fourth bit are also compatible. Since the logical values ​​of test vectors P1 (0X11) and P2 (001X) are compatible in every corresponding bit, therefore, test vectors P1 (0X11) and P2 (001X) are compatible.

[0045] For test vectors P1 (0X11) and P3 (0110), if the first logical value of both test vectors P1 and P3 is 0, then the logical values ​​of the first logical value of test vectors P1 and P3 are compatible. If the logical value of test vector P1 in the second bit is the uncertain term X, then the logical values ​​of test vectors P1 and P3 in the second bit are also compatible. If the third logical value of both test vectors P1 and P3 is 1, then the logical values ​​of test vectors P1 and P3 in the third bit are also compatible. However, if the logical value of test vector P1 in the fourth bit is 1, while the logical value of test vector P3 in the fourth bit is 0, then the logical values ​​of test vectors P1 and P3 in the fourth bit are incompatible. Since the logical values ​​of test vectors P1 (0X11) and P3 (0110) in the fourth bit are incompatible, therefore, test vectors P1 (0X11) and P3 (0110) are not compatible.

[0046] For test vectors P2 (001X) and P3 (0110), if the logical value of the first bit of both test vectors P2 and P3 is 0, then the logical values ​​of the first bit of test vectors P2 and P3 are compatible. If the logical value of the second bit of test vector P2 is 0, while the logical value of the third bit of test vector P3 is 1, then the logical values ​​of the second bit of test vectors P2 and P3 are incompatible. If the logical values ​​of the third bit of both test vectors P2 and P3 are 1, then the logical values ​​of the third bit of test vectors P2 and P3 are compatible. If the logical value of the fourth bit of test vector P2 is the uncertain term X, then the logical values ​​of the fourth bit of test vectors P2 and P3 are compatible. Since the logical values ​​of the second bit of test vectors P2 (001X) and P3 (0110) are incompatible, therefore, test vectors P2 (001X) and P3 (0110) are not compatible.

[0047] According to an embodiment of the present invention, the method further includes: merging two compatible test vectors into a new test vector in the following manner: determining the logical value of each common bit in the two test vectors; if the logical values ​​of the common bits of the two test vectors are the same, then keeping the logical value of the common bits unchanged; if the logical value of the common bit of one test vector is an indeterminate term, and the logical value of the common bit of the other test vector is 0 or 1, then setting the logical value of the common bit to 0 or 1.

[0048] To better understand the vector merging process in the static simplification phase, the following will still use... Figure 1 Taking the test vector shown as an example, and combining it with the aforementioned embodiments, we will explain how to merge two compatible test vectors into a new test vector.

[0049] Based on the foregoing, Figure 1 The test vectors P1 (0X11) and P2 (001X) are compatible. Specifically, test vectors P1 (0X11) and P2 (001X) are merged into a new test vector as follows: the first logical value of both test vectors P1 and P2 is 0, so the first logical value remains unchanged; the second logical value of test vector P1 is the uncertain term X, and the second logical value of test vector P2 is 0, so the second logical value is set to 0 (consistent with the second logical value of test vector P2); the third logical value of both test vectors P1 and P2 is 1, so the third logical value remains unchanged; the fourth logical value of test vector P1 is 1, and the fourth logical value of test vector P2 is X, so the fourth logical value is set to 1 (consistent with the fourth logical value of test vector P1). Based on this, the test vector obtained after merging test vectors P1 (0X11) and P2 (001X) is 0011.

[0050] As can be seen from the foregoing embodiments, the static simplification phase in each round of simplification can automatically increase the size of the vector pool to accommodate more test vectors, thereby improving the compatibility of test vectors.

[0051] 2.2 Dynamic Simplification Stage

[0052] In the dynamic simplification phase of each round of simplification: all test vectors obtained in the static simplification phase are processed using a dynamic simplification method to fill some uncertain terms in the test vectors with uncertain terms with 0 or 1, until the number of circuit faults that can be detected by all test vectors no longer increases.

[0053] According to an embodiment of the present invention, the method further includes: in each round of simplification, the dynamic simplification is performed by processing all test vectors obtained in the static simplification stage according to the following steps: determining all circuit faults in the circuit fault list that cannot be detected by any test vector obtained in the static simplification stage to obtain the current round fault detection set; analyzing all circuit faults in the current round fault detection set that are compatible with all test vectors obtained in the static simplification stage to obtain the current round dynamic simplification set; based on all circuit faults in the current round dynamic simplification set, filling some uncertain terms in the test vectors with uncertain terms with 0 or 1, until the number of circuit faults that can be detected by all test vectors in the vector pool corresponding to the current round no longer increases.

[0054] Based on the above embodiments, it is known that during dynamic simplification, it is necessary to analyze all circuit faults in the current round of fault detection set that are compatible with all test vectors obtained in the static simplification stage. This is done to improve the efficiency of dynamic simplification and avoid invalid searches. Specifically, although filling some uncertain terms in test vectors with 0 or 1 can enable the corresponding test vector to detect other circuit faults, test vectors with uncertain terms, constrained by their own logic values, can only be compatible with some undetected circuit faults (here, compatibility means that filling their own uncertain terms with 0 or 1 allows the test vector to detect the corresponding circuit fault). Therefore, to improve the efficiency of dynamic simplification and avoid invalid filling, it is necessary to analyze all circuit faults in the current round of fault detection set that are compatible with all test vectors obtained in the static simplification stage to obtain the current round of dynamic simplification set.

[0055] According to an embodiment of the present invention, the digital circuit under test includes multiple logic gates, each logic gate having an input pin and an output pin. Each circuit fault in the fault list indicates that the logic value of the corresponding logic gate's input pin or output pin is always 0 or always 1. The method further includes: analyzing all circuit faults in the current round of fault detection set that are compatible with all test vectors obtained in the static simplification stage in the following manner: injecting each circuit fault in the current round of fault detection set into the corresponding input or output pin of the digital circuit under test, filling all test vectors obtained in the static simplification stage into a fixed-bit machine word, and performing logic simulation using the machine word and the digital circuit under test after injecting different circuit faults. If the logic simulation result shows that the logic value of the input or output pin with the circuit fault is different from the logic value without the circuit fault, it indicates that one or more test vectors obtained in the static simplification stage are compatible with the corresponding circuit fault; otherwise, it indicates that one or more test vectors obtained in the static simplification stage are not compatible with the corresponding circuit fault.

[0056] To better understand the dynamic simplification phase, the following section combines the aforementioned embodiments with... Figure 3 This section details how to determine whether a test vector is compatible with a circuit fault. Figure 3 It includes a test vector 00X1 and a simple digital circuit.

[0057] Depend on Figure 3 It is known that there exists a simplified test vector 00X1. The digital circuit contains an SA0 fault at position 5 and an SA1 fault at position 7. After logic simulation, the logic value at position 5 is 0, which is the same as the fault value SA0. Therefore, the SA0 fault at position 5 is blocked and cannot be detected, indicating that test vector 00X1 is incompatible with the SA0 fault at position 5. After logic simulation, the simulation value at position 7 is an uncertain term X, indicating that test vector 00X1 is compatible with the SA1 fault at position 7. It should be noted that in the dynamic simplification process of this invention, each test vector obtained in the static simplification stage is not analyzed one by one to determine its compatibility with each circuit fault in the current round of fault detection. Instead, all test vectors (64 test vectors) obtained in the static simplification stage are filled into a fixed-bit machine word (64-bit machine word), and the compatibility between all test vectors obtained in the static simplification stage and one or more circuit faults in the current round of fault detection is determined through a single logic simulation.

[0058] Furthermore, to better understand the dynamic simplification stage, the following will combine the aforementioned embodiments with... Figure 4 This section details how to fill in some uncertainties in a test vector with 0 or 1 based on circuit faults. Figure 4 It includes a digital circuit and a filled test vector 0001 (obtained from test vector 00X1).

[0059] Depend on Figure 4 It is known that there is an SA1 fault at position 7 in the digital circuit. After performing logic simulation on the digital circuit using test vector 00X1, the simulation value at position 7 is an uncertain term X. In order to detect the SA1 fault at position 7, the uncertain term X in test vector 00X1 can be filled with 0 to obtain the filled test vector 0001. After filling, vector 0001 can activate the SA1 fault at position 7 and propagate the fault effect to the output port at position 10, indicating that the SA1 fault at position 7 has been detected.

[0060] To better understand the present invention, the following description is in conjunction with the foregoing embodiments. Figure 5 This section details how to construct the test vector set required for testing the digital circuit under test. Specifically, Figure 5 A schematic diagram of the execution flow for constructing test vectors.

[0061] Depend on Figure 5As can be seen, the Verilog gate-level design netlist of the digital circuit under test (represented by synthesized logic gates such as AND, OR, NOT, etc.) is read first and then parsed to connect all the logic gates in the digital circuit under test into a directed acyclic graph data structure. Faults (SA0 fault and SA1 fault) are then set on the input / output pins of each logic gate. The faults on the input / output pins of each logic gate are then summarized to obtain a list of faults under test. Subsequently, initialization settings are performed, namely, initializing the Test Generation Group (ATPG) configuration, initializing the vector pool for static simplification to an initial capacity of 64 test vectors, and initializing the maximum number of failures in the dynamic simplification stage to 100. The maximum number of failures in the dynamic simplification stage represents the cumulative number of compatibility failures from the remaining undetected circuit faults during the dynamic simplification stage. If it exceeds 100, the current round of dynamic simplification can be stopped early. It should be noted that the maximum number of failures in the dynamic simplification stage can be set based on actual needs, and this invention does not impose specific limitations.

[0062] Depend on Figure 5 It is known that after the initialization settings are completed, multiple rounds of simplification are performed until the number of circuit faults that can be detected by all the obtained test vectors is greater than or equal to the preset threshold, or the list of faults to be tested is empty (all circuit faults can be detected). Each round of simplification is performed as follows:

[0063] Static Simplification Phase: Select multiple circuit faults from the list of faults to be tested that cannot be detected by any existing test vectors in the current round, and generate test vectors for each circuit fault to fill the vector pool corresponding to the current round. Then, use static simplification to reduce the number of test vectors in the filled vector pool corresponding to the current round. Repeat the process of filling the vector pool and reducing the number of test vectors in the vector pool until the test vectors in the vector pool corresponding to the current round cannot be reduced and the number of test vectors is equal to a preset value. Each test vector includes multiple logic values, with each logic value being 0, 1, or an indeterminate value.

[0064] Dynamic simplification phase: All test vectors obtained in the static simplification phase are processed using a dynamic simplification method to fill some uncertain terms in the test vectors with uncertain terms with 0 or 1, until the number of circuit faults that can be detected by all test vectors no longer increases.

[0065] To better understand each round of simplification, the first and second rounds of simplification will be used as examples below, combined with... Figure 5 This section details the execution process of each round of streamlining operations.

[0066] In the static simplification phase of the first round of simplification, a circuit fault that has not yet been detected is selected from the list of faults to be tested. This fault is then injected into the corresponding pin of the digital circuit under test and activated. Test vectors are generated for this fault and filled into the vector pool (which has a capacity of 64). After filling the vector pool once, it is checked whether the pool is full. If not, test vectors are generated again. If the pool is full, static simplification is used to reduce the number of test vectors in the pool. The remaining test vectors in the pool after reduction are checked to see if they equal 64. If not, the pool is filled and the number of test vectors is reduced repeatedly until the number of test vectors in the pool cannot be reduced further and equals 64. If they do, the dynamic simplification phase begins.

[0067] In the dynamic simplification phase of the first round of simplification, a fault blocking analysis is first performed. That is, from all the remaining undetected circuit faults in the list of faults to be tested, all the circuit faults that the test vectors obtained in the static simplification phase can be compatible with are analyzed to obtain the current round of dynamic simplification set. Then, based on all the circuit faults in the current round of dynamic simplification set, a dynamic simplification method is used to fill some uncertain terms in the test vectors with uncertain terms with 0 or 1, until the number of circuit faults that can be detected by all test vectors no longer increases.

[0068] In the static simplification phase of the second round of simplification, the vector pool is first expanded based on a preset multiple, assuming the preset multiple is 2 times, resulting in a capacity of 128 vectors. Then, an undetected circuit fault is selected from the list of faults to be tested, and this fault is injected into the corresponding pin of the digital circuit under test and activated. Test vectors are generated for this fault and filled into the vector pool (capacity 128). After filling the vector pool once, it is checked whether the vector pool is full. If it is not full, test vectors are generated again. If it is full, the number of test vectors in the vector pool is reduced using static simplification. The remaining test vectors in the reduced vector pool are checked whether they equal 64. If they do not equal 64, the vector pool is repeatedly filled and the number of test vectors in the vector pool is reduced until the number of test vectors in the vector pool cannot be reduced and the number of test vectors equals 64. If they equal 64, the dynamic simplification phase begins.

[0069] In the dynamic simplification phase of the second round of simplification, a fault blocking analysis is first performed. This involves analyzing all the circuit faults that the test vectors obtained in the static simplification phase can be compatible with from all the remaining undetected circuit faults in the list of faults to be tested, to obtain the current round of dynamic simplification set. Then, based on all the circuit faults in the current round of dynamic simplification set, a dynamic simplification method is used to fill some uncertain terms in the test vectors with uncertain terms with 0 or 1, until the number of circuit faults that can be detected by all test vectors no longer increases.

[0070] It should be noted that existing generation techniques can be used to generate test vectors, and this invention does not impose any special restrictions.

[0071] The beneficial effects of the present invention are as follows: (1) Through multiple rounds of simplification operations in coordination of static simplification and dynamic simplification, the simplification efficiency of test vectors can be significantly improved while ensuring circuit fault coverage, thereby solving the problems of test vector expansion and high test costs; (2) The static simplification stage in each round of simplification operations can automatically increase the size of the vector pool to accommodate more test vectors, thereby improving the possibility of test vector compatibility; (3) The dynamic simplification stage in each round of simplification operations uses fault blocking analysis to eliminate circuit faults that cannot be compatible with the current round of simplification operations, and optimizes the performance of fault blocking analysis through machine word parallelism, thereby improving the efficiency of dynamic simplification.

[0072] It should be noted that although the steps are described in a specific order above, it does not mean that the steps must be executed in the above specific order. In fact, some of these steps can be executed concurrently, or even in a different order, as long as the required function can be achieved.

[0073] This invention can be a system, method, and / or computer program product. A computer program product may include a computer-readable storage medium having computer-readable program instructions loaded thereon for causing a processor to implement various aspects of the invention.

[0074] Computer-readable storage media can be tangible devices that hold and store instructions for use by an instruction execution device. Computer-readable storage media can include, for example, but not limited to, electrical storage devices, magnetic storage devices, optical storage devices, electromagnetic storage devices, semiconductor storage devices, or any suitable combination thereof. More specific examples (a non-exhaustive list) of computer-readable storage media include: portable computer disks, hard disks, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), static random access memory (SRAM), portable compact disc read-only memory (CD-ROM), digital multifunction disc (DVD), memory sticks, floppy disks, mechanical encoding devices, such as punch cards or recessed protrusions storing instructions thereon, and any suitable combination thereof.

[0075] The various embodiments of the present invention have been described above. These descriptions are exemplary and not exhaustive, nor are they limited to the disclosed embodiments. Many modifications and variations will be apparent to those skilled in the art without departing from the scope and spirit of the described embodiments. The terminology used herein is chosen to best explain the principles, practical application, or technical improvements to the embodiments in the market, or to enable others skilled in the art to understand the embodiments disclosed herein.

Claims

1. A test vector construction method for constructing a test vector set required for a digital circuit under test, wherein, The test vector set includes multiple test vectors, characterized in that the method includes: Step S1: Obtain the digital circuit under test and its corresponding list of faults under test, wherein the list of faults under test includes multiple circuit faults; Step S2: Perform multiple rounds of simplification until the number of circuit faults detected by all the obtained test vectors is greater than or equal to a preset threshold. All test vectors obtained in each round of simplification are stored in a vector pool with variable capacity. The capacity of the vector pool for each round is a preset multiple of the capacity of the vector pool for the previous round. Each round of simplification is performed as follows: Static simplification phase: Select multiple circuit faults from the list of faults to be tested that cannot be detected by any test vectors already in the current round, and generate test vectors for each circuit fault to fill the vector pool corresponding to the current round. Then, use static simplification to reduce the number of test vectors in the filled vector pool corresponding to the current round. Repeat filling the vector pool and reducing the number of test vectors in the vector pool until the test vectors in the vector pool corresponding to the current round cannot be reduced and the number of test vectors is equal to the preset value. Each test vector includes multiple logic values, each of which is 0, 1 or an uncertain term. Dynamic simplification phase: All test vectors obtained in the static simplification phase are processed using a dynamic simplification method to fill some uncertain terms in the test vectors with uncertain terms with 0 or 1, until the number of circuit faults that can be detected by all test vectors no longer increases.

2. The method according to claim 1, characterized in that, The method further includes: in the static simplification phase of each round of simplification, the static simplification is performed by reducing the number of test vectors in the vector pool corresponding to the current round that is filled, according to the following steps: For any two test vectors in the vector pool corresponding to the current round that are filled, perform a compatibility check to determine whether the two test vectors are compatible. Then, merge the two compatible test vectors into a new test vector and store it in the vector pool until there are no compatible test vectors in the vector pool.

3. The method according to claim 2, characterized in that, The method further includes performing a compatibility check on any two test vectors in the following manner: Analyze whether the logical values ​​of each identical bit in the two test vectors are compatible. If the logical values ​​of each identical bit in the two test vectors are compatible, then the two test vectors are compatible; otherwise, the two test vectors are incompatible.

4. The method according to claim 3, characterized in that, The method further includes: analyzing whether the logical values ​​of each identical bit in the two test vectors are compatible in the following manner: If two test vectors have the same logical value at the same bit, or if one of the test vectors has an indeterminate logical value at the same bit, then the logical values ​​at the same bit in the two test vectors are compatible. Otherwise, the logical values ​​at the same bit in the two test vectors are incompatible.

5. The method according to claim 4, characterized in that, The method further includes merging two compatible test vectors into a new test vector in the following manner: Determine the logical value of each common bit in two test vectors. If the logical values ​​of the common bits in the two test vectors are the same, then keep the logical value of the common bit unchanged. If the logical value of the common bit in one test vector is uncertain, and the logical value of the common bit in the other test vector is 0 or 1, then set the logical value of the common bit to 0 or 1.

6. The method according to claim 5, characterized in that, The method further includes: in each round of simplification, the dynamic simplification is performed by processing all test vectors obtained in the static simplification phase according to the following steps: The current round of fault detection set is obtained by identifying all circuit faults in the circuit fault list that cannot be detected by any test vector obtained in the static simplification phase. Analyze all circuit faults in the current round fault detection set that are compatible with all test vectors obtained in the static simplification phase to obtain the current round dynamic simplification set; Based on all circuit faults in the current round's dynamic simplified set, some uncertain terms in the test vectors containing uncertain terms are filled with 0 or 1 until the number of circuit faults that can be detected by all test vectors in the vector pool corresponding to the current round no longer increases.

7. The method according to claim 6, characterized in that, The digital circuit under test includes multiple logic gates, each with an input pin and an output pin. Each circuit fault in the fault list represents a logic value of either a constant 0 or a constant 1 for the corresponding logic gate's input or output pin. The method further includes analyzing all circuit faults in the current round of fault detection sets that are compatible with all test vectors obtained during the static simplification phase, as follows: Each circuit fault in the current fault detection set is injected into the corresponding input or output pin of the digital circuit under test. All test vectors obtained in the static simplification stage are filled into a fixed-bit machine word. Logic simulation is then performed using this machine word and the digital circuit under test after injecting different circuit faults. If the logic simulation results show that the logic value of the input or output pin with the circuit fault is different from the logic value without the circuit fault, it means that one or more test vectors obtained in the static simplification stage are compatible with the corresponding circuit fault. Otherwise, it means that one or more test vectors obtained in the static simplification stage are not compatible with the corresponding circuit fault.

8. The method according to claim 7, characterized in that, The preset value is 64.

9. A computer-readable storage medium, characterized in that, It contains a computer program that can be executed by a processor to implement the steps of the method according to any one of claims 1-8.

10. An electronic device, characterized in that, include: One or more processors, and memory, wherein the memory is used to store executable instructions; The one or more processors are configured to implement the steps of the method according to any one of claims 1-8 by executing the executable instructions.

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