Mantissa in-memory calculation unit based on five-bit approximate square, floating point in-memory calculation unit, circuit and chip

Abstract

The invention relates to the technical field of in-memory calculation circuit design, and discloses a mantissa in-memory calculation unit based on 5-bit approximate square, a floating point in-memory calculation unit, a circuit and a chip. The mantissa in-storage calculation unit based on the five-bit approximate square comprises a full-precision mantissa adder, three five-bit square circuits and a multi-operand adder. According to the mantissa in-memory calculation unit based on the five-bit approximate square, mantissa multiplication is converted into a combination of square operation and additive operation, a five-bit square circuit is designed to carry out square operation on the high five bits of the mantissa, and a traditional multiplication function is achieved in an approximate mode; and the logic complexity and the hardware overhead are obviously reduced under the condition that enough precision is met. The problem that the precision and the energy efficiency of an existing mantissa multiplication circuit are not balanced is solved.

Description

Technical Field

[0001] This invention relates to the field of in-memory computing circuit design technology, and more specifically, to: 1. an in-memory computing unit based on a 5-bit approximate square mantissa; 2. a floating-point in-memory computing unit; 3. a floating-point in-memory computing circuit; and 4. an in-memory computing chip. Background Technology

[0002] With the widespread application of deep neural networks in artificial intelligence fields such as image recognition and natural language processing, the demand for high-efficiency, low-power computing hardware is increasing daily. For in-memory computing architectures, the mantissa multiplication circuit in floating-point multiply-accumulate operations accounts for a significant proportion of power consumption and area. In other words, mantissa multiplication operations have extremely high energy efficiency optimization requirements.

[0003] Studies have shown that traditional mantissa multipliers incur significant circuit complexity and power consumption when implementing multi-bit wide operations. Existing common improvements involve using fixed-point or low-bit-width operations, which, while improving energy efficiency, struggle to meet the precision requirements of high-precision neural network algorithms for floating-point operations—especially in model training and complex inference tasks, where mantissa calculation precision directly reduces floating-point accuracy and leads to decreased model accuracy. Summary of the Invention

[0004] Therefore, it is necessary to provide a mantissa in-memory calculation circuit, a floating-point in-memory calculation circuit, and a chip based on 5-bit approximate square to address the problem that the accuracy and energy efficiency of existing mantissa multiplication circuits have not been balanced.

[0005] This invention is achieved using the following technical solution: In a first aspect, the present invention provides a mantissa in-memory calculation unit based on a 5-bit approximate square, which is used to obtain two 10-bit mantissas M. A [9:0]~M B The multiplication result M of [9:0] P [9:0].

[0006] The mantissa in-memory computation unit based on 5-bit approximate squares includes: a full-precision mantissa adder, three 5-bit square circuits, and a multi-operand adder.

[0007] A full-precision mantissa adder is used to: add M... A [9:0]、M B [9:0] is added together to obtain an 11-bit addition result Y[10:0]. The first 5-bit squaring circuit is used to: square Y[9:5] extracted from Y[10:0] to obtain a 10-bit squaring result P0[9:0]; the second 5-bit squaring circuit is used to: square Y[9:5] extracted from M[10:0] to obtain a 10-bit squaring result P0[9:0]; A [9:0] Extracted M A[9:5] Perform a square calculation to obtain a 10-bit square result P1[9:0]; the third 5-bit square circuit is used to: process the square from M B [9:0] Extracted M B [9:5] Perform a square calculation to obtain a 10-bit square result P2[9:0]. The multi-operand adder is used to combine Y[10:0], P0[9:0], P1[9:0], and P2[9:0] to obtain an 11-bit result M. c [10:0], then from M c [10:0] Extract M c [10:1] as M P [9:0]; where M c [10:0]=Y[10:0]+(P0[9:0]-P1[9:0]-P2[9:0]) / 2.

[0008] This implementation of a mantissa-based in-memory calculation circuit based on a 5-bit approximate square is a method or process according to embodiments of this disclosure.

[0009] Secondly, the present invention discloses a floating-point in-memory computing unit, which is used to obtain the multiplication result Final[16:0] of two 16-bit floating-point numbers FPA16~FPB16.

[0010] FPA16 includes: 1-bit sign S A

[15] , 5-digit exponent E A [14:10], 10-digit mantissa M A [9:0]; FPB16 includes: 1 bit sign S B

[15] , 5-digit exponent E B [14:10], 10-digit mantissa M B [9:0].

[0011] The floating-point in-memory calculation unit includes: a sign processing unit, an exponent processing unit, a mantissa processing unit, and a peripheral circuit unit.

[0012] The symbol processing unit is used for: processing S A

[15] , S B

[15] Obtain the symbolic computation result S by XOR operation. P

[15] . The index processing unit is used for: processing E A [14:10]、E B [14:10] Summation is performed to obtain the exponent calculation result E. P [14:10]. The mantissa processing unit is the mantissa in-memory calculation unit based on a 5-bit approximate square disclosed in the first aspect, used to obtain M. P [9:0]. The peripheral circuit section is used to: transfer S P

[15] , EP [14:10]、M p [9:0] is combined into Final[16:0].

[0013] The implementation of this floating-point in-memory computing unit is based on the method or process of an embodiment of this disclosure.

[0014] Thirdly, the present invention discloses a floating-point in-memory calculation circuit, which includes: a multiplication calculation unit and a floating-point adder.

[0015] The multiplication calculation unit includes M floating-point in-memory calculation units as disclosed in the second aspect; M ≥ 1. A floating-point adder is used to accumulate the output results of the multiplication calculation unit to obtain a floating-point multiplication accumulation result.

[0016] The implementation of this floating-point in-memory computing circuit is based on the method or process of an embodiment of this disclosure.

[0017] Fourthly, the present invention discloses an in-memory computing chip, which adopts the circuit layout of the in-memory computing unit based on the 5-bit approximate square of the mantissa as disclosed in the first aspect, or the circuit layout of the floating-point in-memory computing unit as disclosed in the second aspect, or the circuit layout of the floating-point in-memory computing circuit as disclosed in the third aspect.

[0018] The implementation of this in-memory computing chip is based on the methods or processes of embodiments of this disclosure.

[0019] Compared with the prior art, the present invention has the following beneficial effects: 1. The mantissa in-memory calculation unit based on 5-bit approximate square of the present invention transforms the mantissa multiplication operation into a combination of squaring and addition operations, and designs a 5-bit squaring circuit to perform squaring on the high five bits of the mantissa, thereby realizing the traditional multiplication function in an approximate manner, and significantly reducing the logic complexity and hardware overhead while meeting sufficient accuracy.

[0020] 2. The 5-bit square circuit of the present invention is based on mathematical identity transformation design. It is designed with three sub-stages: common factor generation unit, product term generation unit, and square output unit. By extracting and reusing common factors and product terms, logic redundancy and gate level are reduced, thereby reducing area overhead while ensuring timing performance.

[0021] 3. This invention constructs a floating-point in-memory computing unit and circuit based on a 5-bit approximate square mantissa in-memory computing unit, realizing parallel processing of the sign, exponent, and mantissa when performing FP16 floating-point multiplication and multiply-accumulate operations. This not only eliminates the need for a traditional floating-point mantissa multiplier, but also reduces circuit latency and improves system energy efficiency and error tolerance. It is particularly suitable for AI edge inference tasks that require both computational accuracy and energy efficiency. Attached Figure Description

[0022] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0023] Figure 1 This is an architecture diagram of the floating-point in-memory computing circuit provided in Embodiment 1 of the present invention; Figure 2 for Figure 1 Architecture diagram of the in-memory floating-point computing unit; Figure 3 for Figure 2 Architecture diagram of the middle tail number processing unit; Figure 4 for Figure 3 Input-output correspondence table for a 5-bit square circuit; Figure 5 The circuit structure diagram of the common factor generation section in a 5-bit square circuit; Figure 6 The circuit structure diagram of the product term generator in a 5-bit square circuit; Figure 7 The circuit structure diagram of the square output section in a 5-bit square circuit; Figure 8 The simulation result diagram is provided for Embodiment 1 of the present invention. Detailed Implementation

[0024] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0025] It should be noted that when a component is said to be "installed on" another component, it can be directly on the other component or it may be in a component that is centered on it. When a component is said to be "set on" another component, it can be directly set on the other component or it may also be in a component that is centered on it. When a component is said to be "fixed to" another component, it can be directly fixed to the other component or it may also be in a component that is centered on it.

[0026] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention pertains. The terminology used herein in the specification of this invention is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. The term "or / and" as used herein includes any and all combinations of one or more of the associated listed items.

[0027] First, it should be noted that this invention targets FP16 (half-precision floating-point) in-memory computation. FP16 is a 16-bit floating-point format widely used in deep learning and high-performance computing, aiming to balance computational efficiency and memory usage.

[0028] FP16 includes: ① Sign bit: 1 bit, which indicates whether the number is positive or negative - 0 indicates a positive number and 1 indicates a negative number.

[0029] ② Exponent: 5 bits, which represent the size of the number - its range is 00001 (1) to 11110 (30), and the actual exponent range is -14 to +15 (obtained by subtracting the bias value of 15).

[0030] ③ Mantissa (Fraction): 10 bits, which represent the precision of the number. It should be noted that the actual mantissa is 11 bits because it includes the first 1 (also known as the "hidden bit").

[0031] As mentioned in the background section, the precision of mantissa calculation directly affects the precision of floating-point operations. Therefore, this invention provides a floating-point in-memory calculation unit and circuit, with a focus on designing an in-memory calculation unit for mantissa based on a 5-bit approximate square.

[0032] Example 1 See Figure 1 This is an architecture diagram of the floating-point in-memory computing circuit provided in Embodiment 1, which includes: a multiplication calculation unit and a floating-point adder.

[0033] The multiplication calculation unit comprises: M floating-point in-memory calculation units; M ≥ 1. Each floating-point in-memory calculation unit is used to perform the multiplication of two 16-bit floating-point numbers.

[0034] It should be noted that if M > 1, the multiplication unit supports parallel computation by M floating-point in-memory computing units. Furthermore, due to computational requirements and circuit area limitations, M is typically set to 64.

[0035] The following is a detailed explanation of a single floating-point in-memory calculation unit: First, let the two 16-bit floating-point numbers be represented as FPA16~FPB16, and their multiplication result be represented as Final[15:0].

[0036] Then, refer to the above record: FPA16 includes: 1-bit sign S A

[15] , 5-digit exponent E A [14:10], 10-digit mantissa M A [9:0]; FPB16 includes: 1-bit sign S B

[15] , 5-digit exponent E B [14:10], 10-digit mantissa M B [9:0].

[0037] It should be noted that, since it is an in-memory computation, the FPA16 is pre-stored in the storage array, while the FPB16 interacts with the FPA16 for computation through external input.

[0038] See Figure 2 It shows the architecture of a single floating-point in-memory computing unit, which includes: a sign processing unit, an exponent processing unit, a mantissa processing unit, and a peripheral circuit unit.

[0039] 101. The symbol processing unit is used for: processing S A

[15] , S B

[15] Obtain the symbolic computation result S by XOR operation. P

[15]

[0040] In simple terms, the symbol processing unit includes: one XOR gate; the input of the XNOR gate is connected to S... A

[15] , Input terminal two is connected to S B

[15] , the output terminal is used to output S P

[15]

[0041] 102. The index processing unit is used for E A [14:10]、E B [14:10] Summation is performed to obtain the exponent calculation result E. P [14:10].

[0042] In simple terms, the exponent processing unit includes: a five-bit full adder; input terminals one through five of the five-bit full adder are respectively used to connect to E A

[14] ~E A

[10] , Input terminals six to seven are used to connect E. B

[14] ~E B

[10] , Output terminals one through five are respectively used to output E P

[14] ~E P

[10]

[0043] 103. The mantissa processing unit is used to obtain two 10-digit mantissas M. A [9:0]~M B The multiplication result M of [9:0] P [9:0].

[0044] See Figure 3 The mantissa processing unit adopts a mantissa in-memory calculation unit based on 5-bit approximate squares, which includes: a full-precision mantissa adder, three 5-bit square circuits, and a multi-operand adder.

[0045] It should be noted that the design of the mantissa processing unit is based on mathematical identity transformation: since the mantissa actually contains hidden bits of "1", then M A [9:0] and M B The multiplication of [9:0] can be written as: (1+M A [9:0])×(1+M B [9:0]) (1) Furthermore, the multiplication of two mantissas can be rewritten through equation transformation as follows: 1+M A [9:0]+M B [9:0]+[(M A [9:0]+M B [9:0]) 2 -(M A [9:0]) 2 -(M B [9:0]) 2 ] / twenty two) In equation (2) above, the first term "1" is actually the hidden bit—it can be hidden, thus obtaining: M A [9:0]+M B [9:0]+[(M A [9:0]+M B [9:0]) 2 -(M A [9:0]) 2 -(M B [9:0]) 2 ] / twenty three) So, M A [9:0] and M B The multiplication of [9:0] is thus transformed into a combination of squaring and addition. Therefore, the mantissa processing unit is to implement equation (3): ① The full-precision mantissa adder is used to: add M... A [9:0]、M B [9:0] Perform the addition to obtain the 11-bit addition result Y[10:0].

[0046] Y[10:0]=M A [9:0]+M B [9:0]——that is, the “M” in equation (3) is realized. A [9:0]+M B [9:0]” part.

[0047] ② The three 5-bit square circuits are the core of the mantissa processing unit, designed to calculate three square values: (M A [9:0]+M B [9:0]) 2 、(M A [9:0]) 2 、(M B [9:0]) 2 .

[0048] Specifically: The first 5-bit squaring circuit is used to: square Y[9:5] extracted from Y[10:0] to obtain a 10-bit squaring result P0[9:0]; The second 5-bit square circuit is used for: from M A [9:0] Extracted M A [9:5] Perform a square calculation to obtain a 10-digit square result P1[9:0]; The third 5-bit square circuit is used for: from M B [9:0] Extracted M B [9:5] Perform a square calculation to obtain a 10-digit square result P2[9:0].

[0049] P0[9:0] corresponds to (M in equation (3) A [9:0]+M B [9:0]) 2 ;P1[9:0] corresponds to (M) in equation (3) A [9:0]) 2 ;P2[9:0] corresponds to (M) in equation (3) B [9:0]) 2 .

[0050] In other words, the 5-bit squaring circuit performs squaring operations on the high five bits of the mantissa, thus approximating the traditional multiplication function and significantly reducing logic complexity and hardware overhead while maintaining sufficient precision.

[0051] Since the three 5-bit square circuits have the same structural design, let's take one of them as an example: For a certain 5-bit square circuit, its input is 5-bit data INPUT and its output is 10-bit data OUTPUT.

[0052] INPUT=[A,B,C,D,E]; A~E are the most significant bit, second most significant bit, middle bit, second least significant bit, and least significant bit of INPUT, respectively; OUTPUT=[P9,P8,P7,P6,P5,P4,P3,P2,P1,P0]; P9~P0 are the 10 data bits of OUTPUT respectively.

[0053] Therefore, we have: The INPUT of the first 5-bit square circuit is Y[9:5] and the OUTPUT is P0[9:0]. The INPUT for the second 5-bit square circuit is M. A [9:5], OUTPUT is P1[9:0]; The INPUT for the third 5-bit square circuit is M. B [9:5], OUTPUT is P2[9:0].

[0054] Furthermore, see Figure 4 The following relationship exists between OUTPUT and INPUT: P9=(A∩B)∪(A∩C∩D∩E); P8=(A∩ B )∪(A∩C); P7=( A ∩B∩C)∪(A∩ B ∩C∩ D )∪(A∩B∩D)∪(A∩C∩D∩ E ); P6=( A ∩B∩D)∪(A∩ B ∩D∩ E )∪(A∩B∩E)∪(A∩ C ∩D∩E)∪(B∩ C ∩ D ); P5=( A ∩B∩C∩E)∪(A∩ B ∩ C ∩E)∪(A∩ B ∩ D ∩E)∪(A∩ C ∩ D ∩E)∪( B ∩C∩D∩ E )∪(B∩ C ∩D∩ E ); P4=( B ∩C∩E)∪(B∩ C ∩E)∪(C∩ D ∩E ); P3=( C ∩D∩E)∪(C∩ D ∩E); P2=D∩ E ; P1=0; P0=E.

[0055] Based on the relationship between OUTPUT and INPUT, the 5-bit square circuit is designed to include: a common factor generation unit, a product term generation unit, and a square output unit.

[0056] I. The Public Factor Generation Department is used to generate public factor sets based on A~E. The public factor sets include: 18 public factors (specifically including: A , B , C , D , E D∩ E A∩B, D∩E, A∩ B A∩C A ∩B、C∩ D A∩ C C∩E C ∩E、 D ∩E、C∩ B B∩ C ).in, A , B , C , D , E These are the inverted signals A, B, C, D, and E, respectively.

[0057] See Figure 5 The common factor generation unit is designed to include: 5 inverters INV1~INV5 and 13 AND gates AND1~AND13.

[0058] The input terminal of INV1 is connected to A, and the output terminal is used for output. A ; The input of INV2 is connected to B, and the output is used for output. B ; The input of INV3 is connected to C, and the output is used for output. C ; The input of INV4 is connected to D, and the output is used for output. D ; The input terminal of INV5 is connected to E, and the output terminal is used for output. E ; The first input of AND1 is connected to A, the second input is connected to B, and the output is used to output A∩B. The first input of AND2 is connected to D, the second input is connected to E, and the output is used to output D∩E; The first input of AND3 is connected to A, the second input is connected to C, and the output is used to output A∩C. The first input of AND4 is connected to C, the second input is connected to E, and the output is used to output C∩E. Connect input 1 of AND5 to A, and input 2 to... B The output terminal is used to output A∩ B ; AND6 input terminal connected A The input terminal 2 is connected to B, and the output terminal is used for output. A ∩B; AND7's input terminal 1 is connected to C, and input terminal 2 is connected to... D The output terminal is used to output C∩ D ; Connect input 1 of the AND8 to A, and input 2 to... C The output terminal is used to output A∩ C ; AND9 input terminal one connected C The second input terminal is connected to E, and the output terminal is used for output. C ∩E; AND10 input terminal one connection D The second input terminal is connected to E, and the output terminal is used for output. D ∩E; Connect input 1 of AND11 to D, and input 2 to... E The output terminal is used to output D∩ E ; The first input of the AND12 is connected to C, and the second input is connected to... B The output terminal is used to output C∩ B ; Connect input 1 of AND13 to B, and input 2 to... C The output terminal is used to output B∩ C .

[0059] II. The product term generation section is used to generate product term groups based on A~E and common factor groups. The product term group includes 21 product terms (specifically: A∩C∩D∩E, ...). A ∩B∩C、A∩ B ∩C∩ D A∩B∩D, A∩C∩D∩ E , A ∩B∩D、A∩ B ∩D∩ E A∩B∩E, A∩ C ∩D∩E、B∩ C ∩D , A ∩B∩C∩E、A∩ B ∩ C ∩E、A∩ B ∩ D ∩E、A∩ C ∩ D ∩E、 B ∩C∩D∩ E B∩ C ∩D∩ E , B ∩C∩E、B∩ C ∩E、C∩ D ∩ E C∩ D ∩E、 C ∩D∩E).

[0060] See Figure 6 The product term generation unit is designed to include 21 AND gates AND14~AND34.

[0061] The first input terminal of the AND14 is connected to D∩E, the second input terminal is connected to A∩C, and the output terminal is used to output A∩C∩D∩E; AND15 input terminal one connection A ∩B, input terminal 2 is connected to C, output terminal is used for output. A ∩B∩C; The input terminal of AND16 is connected to A∩ B The second input terminal is connected to C∩ D The output terminal is used to output A∩ B ∩C∩ D ; The first input terminal of AND17 is connected to A∩B, the second input terminal is connected to D, and the output terminal is used to output A∩B∩D. The first input of AND18 is connected to A∩C, and the second input is connected to D∩C. E The output terminal is used to output A∩C∩D∩ E ; AND19 input terminal one connection A ∩B, input terminal 2 is connected to D, output terminal is used for output. A ∩B∩D; The input terminal of AND20 is connected to A∩ B The two input terminals are connected to D∩ E The output terminal is used to output A∩ B ∩D∩ E ; The AND21 input terminal 1 is connected to A∩B, the second input terminal is connected to E, and the output terminal is used to output A∩B∩E; The input of AND22 is connected to A∩ CThe two input terminals are connected to D∩E, and the output terminal is used to output A∩E. C ∩D∩E; The input of AND23 is connected to B∩ C Input terminal two connection D The output terminal is used to output B∩ C ∩ D ; AND24 input terminal one connected A ∩B, input terminals 2 are connected to C∩E, and the output terminal is used for output. A ∩B∩C∩E; The input terminal of AND25 is connected to A∩ B Input terminal two connection C ∩E, the output terminal is used to output A∩ B ∩ C ∩E; The input terminal of AND26 is connected to A∩ B Input terminal two connection D ∩E, the output terminal is used to output A∩ B ∩ D ∩E; The input terminal of AND27 is connected to A∩ C Input terminal two connection D ∩E, the output terminal is used to output A∩ C ∩ D ∩E; AND28 input terminal one connection B ∩C, input terminals two connected to D∩ E The output terminal is used for output. B ∩C∩D∩ E ; The input terminal of AND29 is connected to B∩ C The two input terminals are connected to D∩ E The output terminal is used to output B∩ C ∩D∩ E ; AND30 input terminal one connection B ∩C, input terminals are connected to E, and the output terminal is used for output. B ∩C∩E; The input of AND31 is connected to B∩ C The second input terminal is connected to E, and the output terminal is used to output B∩. C ∩E; The input terminal of the AND32 is connected to C∩ D Input terminal two connection E The output terminal is used to output C∩ D ∩ E ; The input of AND33 is connected to C∩D The input terminal is connected to E, and the output terminal is used to output C∩. D ∩E; AND34 input terminal one connected C ∩D, input terminal 2 is connected to E, output terminal is used for output. C ∩D∩E.

[0062] III. The squared output section is used to generate the OUTPUT by referring to A~E, the common factor group, and the product term group. The relationship between P9~P0 in the OUTPUT and A~E, the common factor group, and the product term group is described above and will not be repeated here.

[0063] See Figure 7 The square output section is designed to include: 13 OR gates OR1~OR13 and 3 buffers Buffer1~Buffer3.

[0064] OR1 has one input terminal connected to A∩B, another input terminal connected to A∩C∩D∩E, and its output terminal is used to output P9. The input of OR2 is connected to A∩ B The second input terminal is connected to A∩C, and the output terminal is used to output P8; OR3 input terminal one connection A ∩B∩C, input terminals two are connected to A∩ B ∩C∩ D The output terminal is connected to input terminal one of OR5; input terminal one of OR4 is connected to A∩B∩D, and input terminal two is connected to A∩C∩D∩ E The output terminal is connected to the second input terminal of OR5; the output terminal of OR5 is used to output P7; OR6 input terminal one connection A ∩B∩D, input terminals 2 are connected to A∩ B ∩D∩ E The three input terminals are connected to A∩B∩E, and the output terminal is connected to input terminal one of OR8; input terminal one of OR7 is connected to A∩ C ∩D∩E, input terminals two connected to B∩ C ∩ D The output terminal is connected to the second input terminal of OR8; the output terminal of OR8 is used to output P6; OR9 input terminal one connection A ∩B∩C∩E, input terminals two are connected to A∩ B ∩ C ∩E, input terminals are connected in three ways to A∩ B ∩ D ∩E, the output terminal is connected to input terminal one of OR11; input terminal one of OR10 is connected to A∩ C ∩ D ∩E, input terminals connected B ∩C∩D∩E The input terminals are connected in a three-way connection B∩ C ∩D∩ E The output terminal is connected to input terminal two of OR11; the output terminal of OR11 is used to output P5; OR12 input terminal one connection B ∩C∩E, input terminals two connected to B∩ C ∩E, input terminal three-connection C∩ D ∩ E The output terminal is used to output P4; The input of OR13 is connected to C∩ D ∩E, input terminals connected C ∩D∩E, the output terminal is used to output P3; The input of Buffer1 is connected to D∩ E The output terminal is used to output P2; The input of Buffer2 is connected to 0, and the output is used to output P1; The input of Buffer3 is connected to E, and the output is used to output P0.

[0065] The circuit design described above enables the reuse of common factors, effectively reducing logic redundancy and gate level, and reducing area overhead while ensuring timing performance.

[0066] ③ The multi-operand adder is used to combine Y[10:0], P0[9:0], P1[9:0], and P2[9:0] to obtain an 11-bit calculation result M. c [10:0], then from M c [10:0] Extract M c [10:1] as M P [9:0].

[0067] Among them, M c [10:0]=Y[10:0]+(P0[9:0]-P1[9:0]-P2[9:0]) / 2——that is, it corresponds to equation (3).

[0068] It is important to note that M c [10:1] with M P The bit correspondence of [9:0] is one bit different—that is, it is equivalent to M... c [10:1] Shifting each position to the right yields M P [9:0].

[0069] 104. The peripheral circuit section is used to: connect S P

[15] , E P [14:10]、M P [9:0] is combined into Final[15:0].

[0070] In summary, the calculation cycle of the above floating-point in-memory computing unit includes 11 clock cycles: Initially, the external input was processed in parallel through three paths: sign, exponent, and mantissa. After the start, the symbol processing unit completes the symbol calculation in the first clk clock cycle; The exponent processing unit completes the exponent calculation in the 1st to 11th clk clock cycles; The mantissa processing unit completes the mantissa calculation during the 6th to 11th clk clock cycles; Finally, the peripheral circuitry completes the integration and outputs the floating-point multiplication result.

[0071] 2. The floating-point adder is used to accumulate the output of the multiplication calculation unit to obtain the floating-point multiplication accumulation result.

[0072] This floating-point in-memory computing circuit also supports pipelined operation, which can maximize the completion of a mantissa multiplication and accumulation operation within 5 clock cycles.

[0073] In summary, the floating-point in-memory computing unit and circuit of the present invention realizes three-way parallel processing of the sign, exponent and mantissa. It not only eliminates the need for the traditional floating-point mantissa multiplier, but also reduces circuit latency and improves system energy efficiency and error tolerance. It is particularly suitable for AI edge inference tasks that require both computational accuracy and energy efficiency.

[0074] Furthermore, to illustrate the effectiveness and superiority of the present invention, this embodiment 1 also simulated the above-mentioned floating-point in-memory calculation circuit, examining the error between its circuit output value and the actual value. The results are shown in [reference needed]. Figure 8 The simulation conditions were: TSMC 28nm process, 0.9V operating voltage, and 200MHz clock frequency.

[0075] Figure 8 The area (a) in the diagram shows the absolute error—the darker the color, the greater the absolute error. It can be seen that the maximum absolute error of the above floating-point in-memory calculation circuit is only 0.03. Figure 8 The middle (b) area shows the relative error—the darker the color, the greater the relative error. It can be seen that the maximum relative error of the above floating-point in-memory calculation circuit is 3.07%. This indicates that the floating-point in-memory calculation circuit has high precision.

[0076] In addition, the peak energy efficiency of the floating-point in-memory computing circuit reaches 21.84 TFLOPS / W and the computing density is 0.75 TFLOPS / mm², both of which are excellent.

[0077] The simulations described above also verify that the present invention can significantly reduce logic complexity and hardware overhead while maintaining sufficient accuracy.

[0078] Example 2 This embodiment 2 also discloses an in-memory computing chip, which adopts the circuit layout of the in-memory computing circuit based on the 5-bit approximate square mantissa, or the circuit layout of the floating-point in-memory computing unit, or the circuit layout of the floating-point in-memory computing circuit disclosed in embodiment 1. The chip-packaged approach facilitates the promotion and application of the aforementioned circuit.

[0079] Of course, the mantissa storage calculation circuit based on the 5-bit approximate square can also be designed as a module—if designed as a module, the corresponding pins can be designed as terminals.

[0080] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0081] The embodiments described above are merely illustrative of several implementations of the present invention, and while the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the invention patent. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of the present invention, and these all fall within the protection scope of the present invention. Therefore, the protection scope of this invention patent should be determined by the appended claims.

Claims

1. A mantissa in-memory calculation unit based on 5-bit approximate square, characterized in that, It is used to obtain two 10-digit mantissas M A [9:0]~M B The multiplication result M of [9:0] P [9:0]; The mantissa in-memory calculation unit based on the 5-bit approximate square includes: A full-precision mantissa adder is used to: add M... A [9:0]、M B [9:0] Performing the addition yields an 11-bit addition result Y[10:0]; Three 5-bit squaring circuits; wherein, the first 5-bit squaring circuit is used to: square Y[9:5] extracted from Y[10:0] to obtain a 10-bit squaring result P0[9:0]; the second 5-bit squaring circuit is used to: square Y[9:5] extracted from M[10:0] to obtain a 10-bit squaring result P0[9:0]; A [9:0] Extracted M A [9:5] Perform a square calculation to obtain a 10-bit square result P1[9:0]; the third 5-bit square circuit is used to: process the square from M B [9:0] Extracted M B [9:5] Perform a square calculation to obtain a 10-digit square result P2[9:0]; and A multi-operand adder is used to combine Y[10:0], P0[9:0], P1[9:0], and P2[9:0] to obtain an 11-bit result M. c [10:0], then from M c [10:0] Extract M c [10:1] as M P [9:0]; where M c [10:0]=Y[10:0]+(P0[9:0]-P1[9:0]-P2[9:0]) / 2.

2. The mantissa in-memory calculation unit based on 5-bit approximate square as described in claim 1, characterized in that, For a given 5-bit square circuit, its input is 5-bit data INPUT and its output is 10-bit data OUTPUT; INPUT = [A, B, C, D, E]; A~E are the most significant bit, second most significant bit, middle bit, second least significant bit, and least significant bit of INPUT, respectively; OUTPUT = [P9, P8, P7, P6, P5, P4, P3, P2, P1, P0]; P9~P0 are the 10 data bits of OUTPUT, respectively. The INPUT of the first 5-bit square circuit is Y[9:5] and the OUTPUT is P0[9:0]. The INPUT for the second 5-bit square circuit is M. A [9:5], OUTPUT is P1[9:0]; The INPUT for the third 5-bit square circuit is M. B [9:5], OUTPUT is P2[9:0].

3. The mantissa in-memory calculation unit based on 5-bit approximate square as described in claim 2, characterized in that, A 5-bit square circuit includes: The public factor generation department is used to generate public factor sets based on A to E; the public factor sets include 18 public factors. A , B , C , D , E D∩ E A∩B, D∩E, A∩ B A∩C A ∩B、C∩ D A∩ C C∩E C ∩E、 D ∩E、C∩ B B∩ C ;in, A , B , C , D , E These are the inverted signals of A, B, C, D, and E, respectively. The product term generation unit is used to generate product term groups based on A~E and common factor groups; the product term groups include: 21 product terms A∩C∩D∩E, A ∩B∩C、A∩ B ∩C∩ D A∩B∩D, A∩C∩D∩ E , A ∩B∩D、A∩ B ∩D∩ E A∩B∩E, A∩ C ∩D∩E、B∩ C ∩ D , A ∩B∩C∩E、A∩ B ∩ C ∩E、A∩ B ∩ D ∩E、A∩ C ∩ D ∩E、 B ∩C∩D∩ E B∩ C ∩D∩ E , B ∩C∩E、B∩ C ∩E、C∩ D ∩ E C∩ D ∩E、 C ∩D∩E; as well as The squared output section is used to generate OUTPUT by referencing A~E, common factor groups, and product term groups; Where, P9=(A∩B)∪(A∩C∩D∩E); P8=(A∩B)∪(A∩C∩D∩E); B )∪(A∩C); P7=( A ∩B∩C)∪(A∩ B ∩C∩ D )∪(A∩B∩D)∪(A∩C∩D∩ E ); P6=( A ∩B∩D)∪(A∩ B ∩D∩ E )∪(A∩B∩E)∪(A∩ C ∩D∩E)∪(B∩ C ∩ D ); P5=( A ∩B∩C∩E)∪(A∩ B ∩ C ∩E)∪(A∩ B ∩ D ∩E)∪(A∩ C ∩ D ∩E)∪( B ∩C∩D∩ E )∪(B∩ C ∩D∩ E ); P4=( B ∩C∩E)∪(B∩ C ∩E)∪(C∩ D ∩ E ); P3=( C ∩D∩E)∪(C∩ D ∩E);P2=D∩ E ;P1=0;P0=E。 4. The mantissa in-memory calculation unit based on 5-bit approximate square as described in claim 3, characterized in that, The common factor generation section includes: 5 inverters INV1~INV5 and 13 AND gates AND1~AND13; The input terminal of INV1 is connected to A, and the output terminal is used for output. A ; The input of INV2 is connected to B, and the output is used for output. B ; The input of INV3 is connected to C, and the output is used for output. C ; The input of INV4 is connected to D, and the output is used for output. D ; The input terminal of INV5 is connected to E, and the output terminal is used for output. E ; The first input of AND1 is connected to A, the second input is connected to B, and the output is used to output A∩B. The first input of AND2 is connected to D, the second input is connected to E, and the output is used to output D∩E; The first input of AND3 is connected to A, the second input is connected to C, and the output is used to output A∩C. The first input of AND4 is connected to C, the second input is connected to E, and the output is used to output C∩E. Connect input 1 of AND5 to A, and input 2 to... B The output terminal is used to output A∩ B ; The input terminal of AND6 is connected to... A The input terminal 2 is connected to B, and the output terminal is used for output. A ∩B; AND7's input terminal 1 is connected to C, and input terminal 2 is connected to... D The output terminal is used to output C∩ D ; Connect input 1 of the AND8 to A, and input 2 to... C The output terminal is used to output A∩ C ; AND9 input terminal one connected C The second input terminal is connected to E, and the output terminal is used for output. C ∩E; AND10 input terminal one connection D The second input terminal is connected to E, and the output terminal is used for output. D ∩E; Connect input 1 of AND11 to D, and input 2 to... E The output terminal is used to output D∩ E ; The first input of the AND12 is connected to C, and the second input is connected to... B The output terminal is used to output C∩ B ; Connect input 1 of AND13 to B, and input 2 to... C The output terminal is used to output B∩ C .

5. The mantissa in-memory calculation unit based on 5-bit approximate square as described in claim 3, characterized in that, The product term generation unit includes 21 AND gates AND14~AND34; The first input terminal of the AND14 is connected to D∩E, the second input terminal is connected to A∩C, and the output terminal is used to output A∩C∩D∩E; AND15 input terminal one connection A ∩B, input terminals 2 are connected to C, and the output terminal is used for output. A ∩B∩C; The input terminal of AND16 is connected to A∩ B The second input terminal is connected to C∩ D The output terminal is used to output A∩ B ∩C∩ D ; The first input terminal of AND17 is connected to A∩B, the second input terminal is connected to D, and the output terminal is used to output A∩B∩D. The first input of AND18 is connected to A∩C, and the second input is connected to D∩C. E The output terminal is used to output A∩C∩D∩ E ; AND19 input terminal one connection A ∩B, input terminal 2 is connected to D, output terminal is used for output. A ∩B∩D; The input terminal of AND20 is connected to A∩ B The two input terminals are connected to D∩ E The output terminal is used to output A∩ B ∩D∩ E ; The AND21 input terminal 1 is connected to A∩B, the second input terminal is connected to E, and the output terminal is used to output A∩B∩E; The input of AND22 is connected to A∩ C The two input terminals are connected to D∩E, and the output terminal is used to output A∩E. C ∩D∩E; The input of AND23 is connected to B∩ C Input terminal two connection D The output terminal is used to output B∩ C ∩ D ; AND24 input terminal one connected A ∩B, input terminals 2 are connected to C∩E, and the output terminal is used for output. A ∩B∩C∩E; The input terminal of AND25 is connected to A∩ B Input terminal two connection C ∩E, the output terminal is used to output A∩ B ∩ C ∩E; The input terminal of AND26 is connected to A∩ B Input terminal two connection D ∩E, the output terminal is used to output A∩ B ∩ D ∩E; The input terminal of AND27 is connected to A∩ C Input terminal two connection D ∩E, the output terminal is used to output A∩ C ∩ D ∩E; AND28 input terminal one connected B ∩C, input terminals two connected to D∩ E The output terminal is used for output. B ∩C∩D∩ E ; The input terminal of AND29 is connected to B∩ C The two input terminals are connected to D∩ E The output terminal is used to output B∩ C ∩D∩ E ; AND30 input terminal one connection B ∩C, input terminals are connected to E, and the output terminal is used for output. B ∩C∩E; The input of AND31 is connected to B∩ C The second input terminal is connected to E, and the output terminal is used to output B∩. C ∩E; The input terminal of the AND32 is connected to C∩ D Input terminal two connection E The output terminal is used to output C∩ D ∩ E ; The input of AND33 is connected to C∩ D The input terminal is connected to E, and the output terminal is used to output C∩. D ∩E; AND34 input terminal one connected C ∩D, input terminal 2 is connected to E, output terminal is used for output. C ∩D∩E.

6. The mantissa in-memory calculation unit based on 5-bit approximate square as described in claim 3, characterized in that, The square output section includes: 13 OR gates OR1~OR13 and 3 buffers Buffer1~Buffer3; OR1 has one input terminal connected to A∩B, another input terminal connected to A∩C∩D∩E, and its output terminal is used to output P9. The input of OR2 is connected to A∩ B The second input terminal is connected to A∩C, and the output terminal is used to output P8; OR3 input terminal one connection A ∩B∩C, input terminals two are connected to A∩ B ∩C∩ D The output terminal is connected to input terminal one of OR5; input terminal one of OR4 is connected to A∩B∩D, and input terminal two is connected to A∩C∩D∩ E The output terminal is connected to the second input terminal of OR5; the output terminal of OR5 is used to output P7; OR6 input terminal one connection A ∩B∩D, input terminals 2 are connected to A∩ B ∩D∩ E The three input terminals are connected to A∩B∩E, and the output terminal is connected to input terminal one of OR8; input terminal one of OR7 is connected to A∩ C ∩D∩E, input terminals two connected to B∩ C ∩ D The output terminal is connected to the second input terminal of OR8; the output terminal of OR8 is used to output P6; OR9 input terminal one connection A ∩B∩C∩E, input terminals two are connected to A∩ B ∩ C ∩E, input terminals are connected in three ways to A∩ B ∩ D ∩E, the output terminal is connected to input terminal one of OR11; input terminal one of OR10 is connected to A∩ C ∩ D ∩E, input terminals connected B ∩C∩D∩ E The input terminals are connected in a three-way connection B∩ C ∩D∩ E The output terminal is connected to input terminal two of OR11; the output terminal of OR11 is used to output P5; OR12 input terminal one connection B ∩C∩E, input terminals two connected to B∩ C ∩E, input terminal three-connection C∩ D ∩ E The output terminal is used to output P4; The input of OR13 is connected to C∩ D ∩E, input terminals connected C ∩D∩E, the output terminal is used to output P3; The input of Buffer1 is connected to D∩ E The output terminal is used to output P2; The input of Buffer2 is connected to 0, and the output is used to output P1; The input of Buffer3 is connected to E, and the output is used to output P0.

7. A floating-point in-memory computing unit, characterized in that, It is used to obtain the multiplication result Final[15:0] of two 16-bit floating-point numbers FPA16~FPB16; where FPA16 includes: 1 bit sign S A [15], 5-digit exponent E A [14:10], 10-digit mantissa M A [9:0]; FPB16 includes: 1 bit sign S B [15], 5-digit exponent E B [14:10], 10-digit mantissa M B [9:0]; The floating-point in-memory computing unit includes: The symbol processing unit is used for: processing S A [15], S B [15] Obtain the symbolic computation result S by XOR operation. P [15]; The index processing unit is used for: processing E A [14:10]、E B [14:10] Summation is performed to obtain the exponent calculation result E. P [14:10]; The mantissa processing unit, as described in any one of claims 1-6, is a mantissa storage calculation unit based on a 5-digit approximate square, used to obtain M. P [9:0]; as well as The peripheral circuit section is used to: convert S P [15], E P [14:10]、M P [9:0] is combined into Final[15:0].

8. A floating-point in-memory computing circuit, characterized in that, It includes: The multiplication calculation unit includes: M floating-point in-memory calculation units as described in claim 7; M ≥ 1; as well as A floating-point adder is used to accumulate the output of the multiplication unit to obtain a floating-point multiplication accumulation result.

9. The floating-point in-memory calculation circuit according to claim 8, characterized in that, M=64。 10. An in-memory computing chip, characterized in that, The circuit layout of the mantissa-based in-memory calculation unit as described in any one of claims 1-6, or the circuit layout of the floating-point in-memory calculation unit as described in claim 7, or the circuit layout of the floating-point in-memory calculation circuit as described in any one of claims 8-9 is adopted.

Images