Method for reducing interference of clock signal on EMC (Electro Magnetic Compatibility) suitable for flow cytometer

Abstract

The invention relates to the technical field of electromagnetic compatibility (EMC) design of electronic circuits, in particular to a method suitable for a flow cytometer and capable of reducing interference of clock signals on EMC. The method comprises the steps that S100, clock circuit components are concentrated in a 5mm * 5mm area of the top layer of a PCB, routing is limited to a second layer through buried holes, and fundamental frequency is dynamically set; s200, laying copper in a key area for grounding, and adding a ground bounce suppression array to three layers; s300, arranging an upper ground copper layer and a lower ground copper layer by using a flexible circuit board; s400, covering the top circuit with a ferrite alloy cover, and welding and grounding; and S500, the flow velocity and the cell density are collected in real time, the clock frequency is dynamically adjusted, a frequency stabilization mechanism exists in an extreme scene, radiation is effectively reduced, and the detection precision and stability are improved. According to the method, the EMC interference of the clock signal of the flow cytometer is reduced from multiple dimensions of source inhibition, shielding protection, connection optimization and cooperative control.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of electromagnetic compatibility (EMC) design of electronic circuits, and particularly relates to a method for reducing interference of clock signals on EMC applicable to a flow cytometer. BACKGROUND

[0002] A flow cytometer is a precision instrument widely used in cell biology, immunology and clinical diagnosis. It detects individual cells in the detection area by laser irradiation and analyzes cell characteristics based on scattered light and fluorescent signals. During instrument operation, clock signal circuits are prone to generate high-frequency electromagnetic interference (EMI), which leads to a decline in EMC performance, and further causes signal distortion, data misjudgment or instrument failure. In the prior art, conventional EMC suppression methods mainly include: 1) PCB layout optimization: for example, placing sensitive circuits away from interference sources or adding ground planes. 2) Fixed frequency clock design: the clock frequency is preset to a fixed value, which is irrelevant to cell detection characteristics. 3) Shielding measures: shielding with metal covers or copper layers.

[0003] The above methods have significant defects, including: 1) unable to dynamically match the cell detection characteristic frequency, the clock signal base frequency is asynchronous with the cell event, and the EMI effect is amplified. 2) PCB interlayer shielding is insufficient, and ground bounce noise is easily propagated through vias during high-speed switching; 3) the EMC protection of external connection cables is weak, and interference is easily spread along the signal lines. SUMMARY

[0004] To solve the problems presented in the background art, the present application provides a method for reducing interference of clock signals on EMC applicable to a flow cytometer, which dynamically correlates the clock signal frequency with the cell detection characteristic frequency, optimizes the PCB multi-layer shielding structure, and introduces a flexible circuit board isolation, thereby significantly suppressing electromagnetic interference and improving the EMC performance and detection reliability of the instrument.

[0005] The technical solution of the present application is as follows: The technical solution of the present application provides a method for reducing interference of clock signals on EMC applicable to a flow cytometer, which includes: All electronic components of the clock signal generation circuit are arranged on the TOP layer of the PCB board, and the clock signal wiring is limited to the second layer through the buried hole; at the same time, the clock signal base frequency is dynamically set to satisfy: ; Wherein, is the clock signal base frequency, is the characteristic frequency of a single cell passing through the detection area in the flow cytometer, and the calculation formula is: , is the average residence time of the cell in the detection area, To detect the cell density per unit volume of the detection area, To preset the coefficient; The ground signal shielding is performed on the TOP layer and the third layer respectively, and specifically includes: (a) Full copper is laid on the TOP layer clock signal generation circuit area and the second layer clock signal trace area above and below, and the copper laying area is connected with the ground network; (b) A ground bounce suppression array is additionally arranged directly below the clock signal trace area of the third layer, that is, a setting unit, a plurality of vias are arranged in each unit, and the via and the ground network are formed by laser micro-melting to form a metallurgical bond; The connection between the PCB and the external circuit board is replaced by a flexible circuit board, and upper and lower ground copper layers are arranged in the trace layer of the flexible circuit board, and the upper and lower ground copper layers are connected to the ground network of the PCB through the through hole; A metal cover is covered on the clock signal generation circuit area of the TOP layer, and the metal cover is fixed to the ground network by continuous welding; In the cell flow rate-clock frequency cooperative control module of the flow cytometer, the corresponding system is established, and specifically includes: (a) Real-time acquisition of sample flow rate And cell density ; (b) Dynamic calculation , wherein ; (c) Adjust to , and the adjustment range is limited to .

[0006] As a further selection of the method of the application, all electronic components of the clock signal generation circuit are limited within a 5mm×5mm area of the TOP layer of the PCB, and the components include crystal oscillator, buffer and driving IC, so as to compress the signal path length to within 8mm.

[0007] As a further selection of the method of the application, the diameter of the buried hole is 0.15mm, the depth is 0.25mm, the clock signal trace width is 0.1mm to match the characteristic impedance of 50Ω, and the trace length is not more than 8mm; for the clock signal with a frequency higher than 50MHz, the diameter of the buried hole is reduced to 0.1mm, and the trace width is reduced to 0.08mm to optimize the high-frequency signal integrity.

[0008] As a further selection of the method of the application, the preset coefficient According to the detection area cell density per unit volume Dynamic adjustment: when <5×10 5 cells / mL, = 1.8; when 5 x 10 5 cells / mL≤ ≤2 x 10 6 cells / mL, = 2.0; when >2 x 10 6 cells / mL, = 2.3.

[0009] As a further selection of the method of the present application, the copper sheet is 1 oz thick and is designed in a grid pattern to reduce thermal stress deformation. The copper sheet is connected to the ground network through four vias with a diameter of 0.3 mm, which are arranged in a square pattern to ensure that the ground impedance is less than 5 mΩ.

[0010] As a further selection of the method of the present application, the copper sheet covers the entire second layer but avoids the power trace area, and the surface of the copper sheet is treated with an organic solderable preservative film. The distance between the copper sheet and the signal trace is at least 3 times the trace width, and the vias are connected through a fence structure and a teardrop transition.

[0011] As a further selection of the method of the present application, the via layout of the ground bounce suppression array is arranged in a quincunx pattern, including one central via and four peripheral vias, with a diameter of 0.2 mm and a pitch of 2 mm. The vias are non-punch structures that only connect the third and fourth ground planes, and the holes are filled with conductive epoxy.

[0012] As a further selection of the method of the present application, the substrate of the flexible circuit board is polyimide with a thickness of 0.1 mm. The minimum bending radius is 5 mm, the operating temperature range is -40°C to +125°C, and the bending life is greater than 10,000 times. The layered structure includes an upper ground copper layer, a signal trace layer, and a lower ground copper layer, which are insulated from each other by 25 μm PI glue to form a Faraday cage type electromagnetic isolation.

[0013] As a further selection of the method of the present application, the upper and lower ground copper layers are connected to the ground network of the PCB board through a via array with a diameter of 0.15 mm and a pitch of 1 mm, and the surface of the via is treated with gold plating to ensure that the contact resistance is less than 0.8 mΩ.

[0014] As a further selection of the method of the present application, when the sample flow rate changes by more than 30%, the cell counting is suspended and enters a frequency stabilization mode, with a stepwise adjustment of the clock frequency at a rate of 5% per 100 milliseconds. When the absolute deviation between the actual flow rate and the target flow rate is less than 5%, the detection is resumed. When the cell density exceeds 10 7 cells / mL, = 2.5 and enable dual clock window acquisition, with a main clock frequency of 2.5 x , the auxiliary clock frequency is 1.2x , to verify signal integrity.

[0015] The technical scheme provided by the embodiments of the present application has at least the following beneficial effects: 1) By arranging the clock circuit on the TOP layer and limiting the routing on the second layer, the signal path length and radiation source are reduced; the buried hole technology isolates the interference layer and reduces crosstalk. Experiments show that the radiation emission intensity is reduced by more than 20dB.

[0016] 2) The ground bounce suppression array provides a low-impedance grounding path, and the ground bounce noise peak is reduced by 60%, ensuring signal stability under high cell density.

[0017] 3) Based on the dynamic frequency adjustment of , the clock frequency is synchronized with the cell event rate; The limitation avoids frequency mutation, the system response time is shortened by 30%, and the false detection rate is reduced to below 0.5%.

[0018] 4) The upper and lower ground copper layers of the flexible circuit board and the metal cover are continuously welded to form 360° electromagnetic shielding, and the shielding effectiveness is improved by 25dB; the laser micro-melting technology ensures the metallurgical combination of the via and the ground network, and eliminates the contact impedance.

[0019] 5) The method is suitable for various flow cytometry analyzers, does not require complex hardware modification, and can be implemented only by PCB design and software control, which is low in cost and easy to integrate. BRIEF DESCRIPTION OF DRAWINGS

[0020] Figure 1 The whole process schematic diagram of the method for reducing the interference of the clock signal on EMC suitable for a flow cytometry analyzer; Figure 2 The step flow chart of the method for reducing the interference of the clock signal on EMC suitable for a flow cytometry analyzer S100; Figure 3 The step flow chart of the method for reducing the interference of the clock signal on EMC suitable for a flow cytometry analyzer S200; Figure 4 The detailed step flow chart of the method for reducing the interference of the clock signal on EMC suitable for a flow cytometry analyzer S300; Figure 5 The step flow chart of the method for reducing the interference of the clock signal on EMC suitable for a flow cytometry analyzer S400; Figure 6 The step flow chart of the method for reducing the interference of the clock signal on EMC suitable for a flow cytometry analyzer S500. DETAILED DESCRIPTION

[0021] Clearly and completely, the technical solutions in the embodiments of the present application will be described in combination with the drawings in the embodiments of the present application. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without creative labor fall within the scope of the present application.

[0022] Please refer to Figure 1 which shows a method for reducing the interference of a clock signal on EMC applicable to a flow cytometer, the method comprising: S100. All electronic components of the clock signal generation circuit are arranged on the TOP layer of the PCB board, and the clock signal wiring is limited to the second layer through the buried hole; at the same time, the clock signal base frequency is dynamically set to satisfy: ; wherein, is the clock signal base frequency, is the characteristic frequency of a single cell passing through the detection area in the flow cytometer, and the calculation formula is: , is the average residence time of the cell in the detection area, is the cell density per unit volume of the detection area, is a preset coefficient.

[0023] S200. Ground signal shielding is performed on the TOP layer and the third layer, specifically including: (a) Full copper is laid on the TOP layer clock signal generation circuit area and the second layer clock signal wiring area above and below, and the copper laying area is connected with the ground network; (b) A ground bounce suppression array is additionally arranged directly below the clock signal wiring area on the third layer, that is, 10mm×10mm is taken as a unit, 5 holes with a diameter of 0.2mm are arranged in each unit, the hole spacing is 2mm, and the holes and the ground network are connected through laser micro-melting to form metallurgical bonding.

[0024] S300. The connection between the PCB board and the external circuit board is replaced with a flexible circuit board, and upper and lower ground copper layers are arranged in the wiring layer of the flexible circuit board, and the upper and lower ground copper layers are connected to the ground network of the PCB board through the through hole.

[0025] S400. A metal cover is covered above the clock signal generation circuit area on the TOP layer, and the metal cover is fixed to the ground network through continuous welding.

[0026] S500. A corresponding system is established in the cell flow rate-clock frequency cooperative control module of the flow cytometer, specifically including: (a) Real-time acquisition of sample flow rate and cell density ; (b) dynamically calculating wherein, ; (c) adjusting to , and the adjustment range is limited to .

[0027] The specific solution is as follows: In the method for reducing the interference of a clock signal on EMC applicable to a flow cytometer, S100 realizes suppression of electromagnetic interference generated by the clock signal from the source by centrally arranging clock signal generation circuits on the TOP layer of a PCB board and limiting the wiring on the second layer, dynamically setting the base frequency of the clock signal, effectively reducing the radiation emission intensity, and improving the detection accuracy and stability of the flow cytometer.

[0028] Please refer to Figure 2 , which shows a flow chart of an example of the method S100 for reducing the interference of a clock signal on EMC applicable to a flow cytometer, the content of which includes: S110: All electronic components of the clock signal generation circuit are centrally arranged on the TOP layer of the PCB board.

[0029] In a flow cytometer, the clock signal is used for synchronous data acquisition, signal processing and system control, and its frequency range is 1-100MHz. When the components are dispersedly arranged, a larger loop area is formed, increasing electromagnetic radiation. By centrally arranging the components on the TOP layer, the signal path length and loop area are significantly reduced, thereby reducing electromagnetic radiation.

[0030] In a possible implementation, the clock signal generation circuit includes key components such as crystal oscillator, buffer and driving IC. The components are strictly limited within a 5mm×5mm area on the TOP layer of the PCB board.

[0031] S120: Limit the clock signal wiring to the second layer by using a buried hole.

[0032] By using a buried hole instead of a through hole to limit the clock signal wiring to the second layer, the clock signal wiring is prevented from penetrating through other functional layers, reducing cross-interference with other signals, and at the same time reducing radiation emission.

[0033] In a possible implementation, the specific parameter settings of the buried hole are as follows: Buried hole diameter: 0.15mm, less than 1 / 20 of the signal wavelength; Buried hole depth: 0.25mm, between the TOP layer and the second layer, avoiding penetration of the third layer; Trace width: 0.1mm, matching 50Ω characteristic impedance; Trace length: no more than 8mm, experiments show that when the trace length exceeds 10mm, the radiation at 250MHz frequency point is easy to exceed the standard.

[0034] In another possible implementation, for higher frequency clock signals, the buried hole diameter is reduced to 0.1mm, and the trace width is reduced to 0.08mm to further improve signal integrity.

[0035] S130: dynamically set the clock signal base frequency to satisfy: .

[0036] The traditional flow cytometer adopts a fixed frequency design, which cannot adapt to changes in sample conditions, resulting in increased interference when the cell density is high or the flow rate fluctuates. The present application establishes a dynamic relationship between the clock frequency and the cell event rate, synchronizing the clock frequency with the cell event rate, effectively avoiding interference spectrum overlap.

[0037] In one possible implementation, the characteristic frequency of a single cell passing through the detection area in the flow cytometer is calculated as: ; wherein, is the average residence time of the cell in the detection area, is the cell density per unit volume in the detection area.

[0038] In another possible implementation, the relationship between the sample flow rate is determined based on a fluid mechanics model. The calculation formula is: ; S140: determine the value range of the preset coefficient .

[0039] Specifically, the present application sets the value range of to 1.8-2.5, which is determined by a large amount of experimental data: When <1.8, the aliasing effect is significant in the flow rate mutation scenario, and the false detection rate exceeds 3%; When >2.5, the increase in high-frequency noise energy causes the PMT signal baseline to fluctuate more than 10mV.

[0040] In one possible implementation, the value can be dynamically selected according to the cell density: When ​<5x10^5cells / mL, i.e. low density scenario, = 1.8; When 5x10 5 ≤ 2x10 6 cells / mL, i.e. medium density scenario, = 2.0; When > 2x10 6 cells / mL, i.e. high density scenario, = 2.3.

[0041] In the method for reducing the interference of a clock signal on EMC applicable to a flow cytometer, S200 builds a comprehensive electromagnetic shielding system by shielding the ground signal on the TOP layer and the third layer respectively, effectively suppresses the ground bounce noise and radiation emission, and improves the signal integrity and system stability.

[0042] Please refer to Figure 3 which shows a flow chart of an exemplary method S200 for reducing the interference of a clock signal on EMC applicable to a flow cytometer, the contents of which include: S210: Pave copper on the TOP layer clock signal generation circuit area and the second layer clock signal trace area above and below, and connect the paved copper area to the ground network.

[0043] Paving copper is a basic means of electromagnetic shielding. By setting a continuous copper layer in the key area, an effective electromagnetic shield is formed to reduce electric field radiation and magnetic field interference.

[0044] In one possible implementation, the TOP layer copper paving requirements are as follows: Copper paving shape: closely adhere to the boundary of the clock signal generation circuit components, with a 0.2mm safety margin reserved at the edge.

[0045] Copper thickness: 1oz, grid design is adopted to reduce thermal stress deformation.

[0046] Grounding method: connected to the third layer ground plane through four vias with a diameter of 0.3mm, the vias are arranged in a square.

[0047] The copper paving requirements above and below the second layer clock signal trace area are as follows: Pave copper to cover the entire second layer, but avoid the power trace area; The copper surface is treated with an organic solderable protective film to ensure that the grounding impedance is <5mΩ.

[0048] ​In another possible implementation, the distance between the copper and the signal trace should be at least 3 times the trace width to avoid capacitive coupling. The via of the copper connection ground network adopts a via fence structure. To prevent the "island effect", a teardrop transition is added to the copper area to the via to avoid etching residues.

[0049] S220: Add a ground bounce suppression array directly below the clock signal trace area of the third layer.

[0050] The ground bounce suppression array is used to solve the problem of ground bounce noise in the high cell density scenario.

[0051] In one possible implementation, the design parameters of the ground bounce suppression array are as follows: Cell size: 10mm x 10mm, matching clock signal wavelength; Via layout: quincunx arrangement, i.e. 1 hole in the center + 4 holes on the periphery, via diameter 0.2mm, pitch 2mm; Via attribute: non-punch, only connecting the third layer and the fourth layer ground plane, hole filled with conductive epoxy.

[0052] By ANSYS Q3D Extractor simulation of different via density, 5 holes per unit is determined as the best balance point, as shown in Table 1: Table 1

[0053] The test results show that the ground bounce suppression array reduces the contact resistance from 10mΩ of traditional welding to 0.8mΩ, and the ground bounce noise peak is reduced by 62%.

[0054] In the method for reducing the interference of the clock signal on EMC suitable for a flow cytometer, S300 replaces the connection between the PCB board and the external circuit board with a flexible circuit board, and sets up upper and lower ground copper layers in the flexible circuit board, effectively solving the antenna effect problem of the traditional rigid connection cable, and further reducing the radiation emission.

[0055] Please refer to Figure 4 which shows a flow chart of one exemplary method S300 for reducing the interference of the clock signal on EMC suitable for a flow cytometer of the present application, the content of which includes: S310: Replace the connection between the PCB board and the external circuit board with a flexible circuit board.

[0056] The traditional flow cytometer uses a rigid PCB connection cable, and when the connection line length exceeds 10cm, a significant antenna effect will be produced, increasing the radiation emission intensity by about 18dB. The present application uses a flexible circuit board (FPC) to replace the rigid connection, effectively solving this problem.

[0057] In a possible implementation, the physical characteristic parameters of the flexible circuit board are as follows: Substrate: polyimide (PI), thickness 0.1 mm; Bending radius: minimum 5 mm, ensuring that the copper layer is not damaged during installation; Operating temperature range: -40 to +125 DEG C, meeting the environmental requirements of medical equipment; Bending life: > 10,000 times, meeting the equipment maintenance requirements.

[0058] S320: setting up the upper and lower copper layers in the trace layer of the flexible circuit board.

[0059] The upper and lower copper layers are set up in the flexible circuit board to form a Faraday cage structure, effectively suppressing the electromagnetic radiation generated by the signal trace.

[0060] In a possible implementation, the layer structure of the flexible circuit board is shown in Table 2: Table 2

[0061] In the method for reducing the interference of the clock signal on EMC suitable for a flow cytometer, S400 covers a metal cover above the clock signal generation circuit area of the TOP layer, and fixes the metal cover to the ground network through continuous welding, to build the last line of electromagnetic shielding defense, realize 360° omnidirectional shielding, and significantly improve the shielding effectiveness.

[0062] Please refer to Figure 5 which shows a flowchart of an example method S400 for reducing the interference of the clock signal on EMC suitable for a flow cytometer, and its content includes: S410: covering a metal cover above the clock signal generation circuit area of the TOP layer.

[0063] The metal cover is the last line of defense for electromagnetic shielding, and by setting a metal shielding cover above the clock signal generation circuit area, the radiation and invasion of electromagnetic waves are effectively blocked.

[0064] The metal cover of the application is preferably a ferrite alloy, which has better shielding effect on the main 10-100 MHz low frequency magnetic field interference in the flow cytometer due to its high magnetic permeability.

[0065] S420: fixing the metal cover to the ground network through continuous welding.

[0066] The connection quality of the metal cover and the ground network directly affects the shielding effectiveness. The traditional spot welding or screw fixing method has the problems of high contact impedance and poor shielding continuity. The application adopts continuous welding technology to ensure that the metal cover and the ground network form a low impedance and high reliability electrical connection.

[0067] In the method for reducing the interference of the clock signal on EMC applicable to the flow cytometer, S500 realizes the dynamic matching of the clock frequency and the cell event rate by establishing a cell flow rate-clock frequency cooperative control module, effectively avoids the signal distortion caused by the frequency mutation, and improves the adaptability and stability of the system when the sample condition changes.

[0068] Please refer to Figure 6 , which shows an exemplary flowchart of the method S500 for reducing the interference of the clock signal on EMC applicable to the flow cytometer, the content of which includes: S510: Real-time acquisition of sample flow rate And cell density .

[0069] Real-time acquisition of sample flow rate and cell density is the basis for dynamically adjusting the clock frequency, and accurate flow rate and cell density data are the prerequisite for calculating the characteristic frequency .

[0070] In one possible implementation, the sample flow rate Is collected by an ultrasonic Doppler sensor, and the cell density Is obtained by forward scattering light intensity calibration.

[0071] S520: Dynamically calculate the characteristic frequency of a single cell passing through the detection area in the flow cytometer .

[0072] Reflects the cell event rate passing through the detection area per unit time, and is the basis for determining the clock frequency.

[0073] In one possible implementation, The calculation formula is: ; ; Wherein, The sample flow rate is The cell density is

[0074] S530: Adjust To , and the adjustment range is limited to .

[0075] Adjusting the clock frequency to is the core control strategy of the present application, and limiting the adjustment range is the key to ensuring system stability.

[0076] In one possible implementation, the specific implementation of the clock frequency adjustment is as follows: When using AD9548 clock generator, receive the target frequency through SPI interface Target value Internal PLL locks the new frequency, key constraints: ; Example: current =600Hz, then the single adjustment amplitude ≤60Hz If the target frequency is 800Hz, it needs to be adjusted in 4 steps, each step 50Hz, interval 20ms.

[0077] In another possible implementation, the clock frequency adjustment adopts step change, each adjustment amount is not more than 2% of the target frequency, and the adjustment interval is 5-20ms.

[0078] S540: extreme scenario processing mechanism.

[0079] In the extreme scenario where the sample condition changes dramatically, special processing mechanism is needed to ensure system stability.

[0080] In one possible implementation, the processing flow when the flow rate mutation is >30% is: 1. Suspend cell counting and enter frequency stabilization mode; 2. Adjust the frequency at a rate of 5% / 100ms; 3. When - |<5%, resume detection.

[0081] In another possible implementation, the processing strategy when the cell density is >10 7 cells / mL is: 1. The value is forced to be 2.5; 2. Enable dual clock window acquisition: the main clock =2.5× ; the auxiliary clock =1.2× , used to verify signal integrity.

[0082] The basic principles of the present application are described above in combination with specific embodiments, but it is pointed out that the advantages, advantages, effects, etc. mentioned in the present application are only examples and not limitations, and these advantages, advantages, effects, etc. cannot be considered as the must-have of each embodiment of the present application. In addition, the above specific details disclosed are only for the purpose of example and understanding, and not for limitation, and the above details do not limit the present application to the must-use of the above specific details to realize.

[0083] The block diagrams of the devices, apparatuses, equipment, systems referred to in this application are only illustrative examples and are not intended to require or imply that the connection, arrangement, configuration must be as shown in the block diagrams. These devices, apparatuses, equipment, systems are connected, arranged, configured in any manner as will be appreciated by those skilled in the art. Words such as "include", "contain", "have", and the like are open-ended words, mean "including but not limited to", and can be used interchangeably with each other. The words "or" and "and" used herein mean the word "and / or", and can be used interchangeably with each other, unless the context clearly indicates otherwise. The word "such as" used herein means the phrase "such as but not limited to", and can be used interchangeably with each other.

[0084] It is also pointed out that, in the devices, equipment and methods of the present application, each of the components or steps are separable and / or recombined. These separations and / or recombination should be considered as equivalent solutions of the present application.

[0085] The above description of the disclosed aspects is provided to enable any person skilled in the art to make or use the application. Various modifications to these aspects will be readily apparent to those skilled in the art, and the principles defined herein can be applied to other aspects without departing from the scope of the application. Therefore, the present application is not intended to be limited to the aspects shown herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

[0086] The above description is merely illustrative of the preferred embodiments of the present application and is not intended to limit the application. Any modifications, equivalent replacements, and the like made within the spirit and principle of the present application should be included in the scope of the present application.

Claims

1. A method of reducing the interference of a clock signal on EMC for a flow cytometer, characterized in that, The application relates to a clock signal generation circuit and a flow cytometer. All electronic components of the clock signal generation circuit are arranged on the TOP layer of a PCB board, and the clock signal wire is limited on the second layer through a buried hole; meanwhile, the clock signal base frequency is dynamically set to satisfy: ； wherein, is a clock signal base frequency, is a characteristic frequency of a single cell passing through the detection region in a flow cytometer, and the calculation formula is: , is the average residence time of the cell in the detection region, is the cell density per unit volume of the detection region, is a preset coefficient; Ground signal shielding is performed on the TOP layer and the third layer, specifically including: (a) full copper is laid on the clock signal generation circuit region on the TOP layer and the clock signal wire region on the second layer, and the copper laying region is connected with a ground network; (b) a ground spring suppression array is additionally arranged below the clock signal wire region on the third layer, that is, a setting unit, a plurality of vias are arranged in each unit, and the vias are connected with the ground network through laser micro-melting to form metallurgical bonding; The connection between the PCB board and an external circuit board is replaced by a flexible circuit board, and upper and lower ground copper layers are arranged in the wire layer of the flexible circuit board, and the upper and lower ground copper layers are connected to the ground network of the PCB board through a through hole; A metal cover is arranged above the clock signal generation circuit region on the TOP layer, and the metal cover is fixed to the ground network through continuous welding; In the cell flow rate-clock frequency coordination control module of the flow cytometer, corresponding systems are established, specifically including: (a) real-time acquisition of sample flow rate and cell density ; (b) dynamically calculating wherein, ; (c) adjusting to , and the adjustment range is limited to .

2. The method of reducing clock signal interference with EMC suitable for use in a flow cytometer according to claim 1, wherein, All electronic components of the clock signal generation circuit are limited in a 5mm*5mm region on the TOP layer of the PCB board, and the components include a crystal oscillator, a buffer and a driving IC, so that the signal path length is compressed to within 8mm.

3. The method of reducing clock signal interference with EMC suitable for use in a flow cytometer according to claim 1, wherein, The diameter of the buried hole is 0.15mm, the depth is 0.25mm, the clock signal wire width is 0.1mm to match the characteristic impedance of 50Ω, and the wire length is not more than 8mm; for the clock signal with a frequency higher than 50MHz, the diameter of the buried hole is reduced to 0.1mm, and the wire width is reduced to 0.08mm to optimize the high-frequency signal integrity.

4. The method of reducing clock signal interference with EMC suitable for use in a flow cytometer according to claim 1, wherein, The preset coefficient According to the cell density per unit volume of the detection area Dynamic adjustment: when <5×10 5 cells / mL, =1.8; when 5×10 5 cells / mL≤ ≤2×10 6 cells / mL, =2.0; when >2×10 6 cells / mL, =2.

3.

5. The method of reducing clock signal interference with EMC suitable for use in a flow cytometer according to claim 1, wherein, The copper laying shape on the TOP layer is close to the boundary of the clock signal generation circuit component, and a 0.2mm safety interval is reserved on the edge; the copper thickness is 1oz and a grid design is adopted to reduce thermal stress deformation; the copper is connected to the ground network through four vias with a diameter of 0.3mm, the vias are arranged in a square shape, and the grounding impedance is ensured to be lower than 5mΩ.

6. The method of reducing clock signal interference with EMC suitable for use in a flow cytometer according to claim 5, wherein, The copper laying covers the entire second layer but avoids the power wire region, and the copper surface is treated with an organic solderable preservative film; the spacing between the copper laying and the signal wire is at least 3 times the wire width, and the via fence structure and the tear drop transition to the via are adopted.

7. The method of reducing clock signal interference with EMC suitable for use in a flow cytometer according to claim 1, wherein, The via layout of the ground spring suppression array is in a plum blossom shape, including one central via and four peripheral vias, the via diameter is 0.2mm, and the spacing is 2mm; The via is a non-punch structure, only connecting the third layer and the fourth layer ground plane, and the hole is filled with conductive epoxy resin.

8. The method of reducing clock signal interference with EMC suitable for use in a flow cytometer according to claim 1, wherein, The base material of the flexible circuit board is polyimide, the thickness is 0.1mm; the minimum bending radius is 5mm, the working temperature range is-40 DEG C to +125 DEG C, and the bending life is greater than 10,000 times; the laminated structure includes an upper ground copper layer, a signal wire layer and a lower ground copper layer, each layer is insulated by 25mu PI glue, and a Faraday cage type electromagnetic isolation is formed.

9. The method of reducing the interference of a clock signal with EMC suitable for use in a flow cytometer according to claim 8, characterized in that, The upper and lower copper layers are connected to the ground network of the PCB board through an array of through holes with a diameter of 0.15 mm, a pitch of 1 mm, and a gold-plated surface to ensure that the contact resistance is lower than 0.8 mΩ.

10. The method of reducing clock signal interference with EMC suitable for use in a flow cytometer according to claim 1, wherein, When the sample flow rate mutation amplitude is greater than 30%, the cell counting is paused and enters the frequency stabilization mode, and the clock frequency is adjusted in steps at a rate of 5% per 100 milliseconds; when the absolute deviation of the actual flow rate from the target flow rate is less than 5%, the detection is resumed; when the cell density exceeds 10 7 cells / mL, the detection is forcibly stopped, the clock frequency is set to 2.5, and the double clock window acquisition is enabled, the main clock frequency is 2.5× , and the auxiliary clock frequency is 1.2× , to verify the signal integrity.

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