Novel carrier wafer manufacturing method based on chip wafer bonding recombination

Abstract

The invention provides a novel carrier wafer manufacturing method based on chip wafer bonding recombination. The novel carrier wafer manufacturing method comprises the following steps: bonding a chip into a carrier wafer with a groove structure in a manner that the front surface of the chip faces downwards through a fusion bonding process; enabling the back surface of the chip to face outwards, and thinning from the back surface to realize fine planarization thinning of the whole thickness of the chip; taking the chip and the carrier wafer with the groove structure as a whole, and carrying out fusion bonding on the chip and the carrier wafer with another wafer; thinning and planarizing the carrier wafer with the groove structure from the back surface through grinding and chemical mechanical grinding so as to remove a non-groove part and expose the front surface of the chip; interconnected copper conductive holes / welding pads are formed on the front surface of a chip through a copper Damascus process, and secondary chemical mechanical grinding is carried out, so that the final mixed-bonded copper welding pads form a shallow dish shape. According to the invention, the technical optimization of chip-to-wafer stacking is realized, and the process maturity is improved.

Description

TECHNICAL FIELD

[0001] The present application belongs to the technical field of semiconductor manufacturing, and particularly relates to a novel carrier wafer manufacturing method based on chip wafer bonding recombination. BACKGROUND

[0002] With the continuous advancement of semiconductor process nodes, the critical dimensions of integrated circuits (ICs) continue to shrink, and the traditional "Moore's Law" that relies on transistor size reduction to improve performance and reduce costs is gradually facing bottlenecks. On the one hand, as lithography, etching, deposition and other front-end processes enter the nanometer or even sub-nanometer scale, the technical difficulty and manufacturing cost rise sharply; on the other hand, physical limitations such as power consumption, heat dissipation, and interconnection delay also make it difficult to increase the integration density of a single chip. In this context, the industry has begun to seek new technical paths to continue the development trend of performance growth and functional integration. Among them, advanced packaging technology has become an important means to break through the limitations of Moore's Law, as it can achieve multi-chip integration on the packaging level to effectively improve system performance and functional density.

[0003] Compared with 2.5D packaging, 3D packaging is a more advanced packaging solution. It achieves higher integration density and better performance by vertically stacking chips, representing the development direction of advanced packaging technology. The core idea is to improve the transistor density per unit volume by vertically stacking chips. However, if the chips are simply stacked vertically, although the area occupied in the two-dimensional plane is reduced, the overall volume is not reduced. Therefore, the chips need to be thinned to reduce the vertical height after stacking, so as to truly realize the improvement of transistor density per unit volume.

[0004] In the manufacturing process of chip stacking, wafer-to-wafer (wafer-to-wafer) and chip-to-wafer (chip-to-wafer) are two main stacking forms. Wafer-to-wafer stacking requires that the chip size of the participating stacking be consistent, the wafer size be uniform, and strict alignment and process compatibility requirements be met. However, when the chips to be stacked cannot meet the above conditions, chip-to-wafer stacking becomes a more suitable choice. Chip-to-wafer stacking has high flexibility and does not have strict restrictions on chip size, wafer size, and material. In addition, the chip-to-wafer process allows pre-screening of chips before bonding, and only chips that pass the yield test are used for stacking, thereby significantly improving the overall yield of the final stacked chips. However, in the field of hybrid bonding, the chip-to-wafer process is still not as mature as the wafer-to-wafer process, and there are many technical challenges and optimization spaces. In summary, wafer-to-wafer and chip-to-wafer stacking each has its own advantages and limitations, and the choice needs to be based on the specific application scenario and process requirements. The present application mainly targets the chip-to-wafer stacking process route and focuses on the thinning and planarization process of chips, aiming to optimize the technical implementation of chip-to-wafer stacking and improve the process maturity. SUMMARY

[0005] To this end, the present application is precisely to solve the above-mentioned problems in the prior art, and aims to provide a novel carrier wafer manufacturing method based on chip wafer bonding recombination, comprising: bonding a chip front face downward into a carrier wafer with a groove structure through a fusion bonding process; thinning the chip from the back face through grinding and chemical mechanical grinding with the chip back face facing outward, so as to achieve fine planarization thinning of the overall thickness of the chip to meet the requirements of the subsequent copper damascene process and hybrid bonding process for the overall flatness of the chip; fusing the chip and the carrier wafer with the groove structure as a whole with another wafer; thinning and planarizing the carrier wafer with the groove structure from the back face through grinding and chemical mechanical grinding, so as to remove the non-groove part and expose the front face of the chip; forming interconnected copper conductive holes / pads on the front face of the chip through the copper damascene process, and performing secondary chemical mechanical grinding, so as to form a shallow dish-shaped morphology of the final hybrid bonded copper pads.

[0006] In addition, preferably, the novel carrier wafer manufacturing method based on chip wafer bonding recombination of the present application further comprises: embedding the device chip in the carrier wafer through the pre-designed groove structure in the carrier wafer, the distance between the device chip and the groove structure being within 100 microns, and the size of the device chip being much smaller than the conventional isolated chip thinning structure.

[0007] In addition, preferably, the novel carrier wafer manufacturing method based on chip wafer bonding recombination of the present application further comprises: bonding a dummy chip around the device chip after the chip-to-wafer fusion bonding / hybrid bonding, and shortening the distance between the device chip and the dummy chip by attaching the dummy chip, so as to reduce the distance between the isolated chips.

[0008] In addition, preferably, the novel carrier wafer manufacturing method based on chip wafer bonding recombination of the present application further comprises: making a groove on the wafer through photolithography and plasma dry etching process, thereby forming a groove carrier wafer.

[0009] In addition, preferably, the novel carrier wafer manufacturing method based on chip wafer bonding recombination of the present application further comprises: optimizing the roughness of the groove bottom by bonding to form an etching stop layer.

[0010] In addition, preferably, in the novel carrier wafer manufacturing method based on chip wafer bonding recombination of the present application, the roughness of the groove bottom is optimized by forming an etching stop layer by bonding, comprising: depositing a dielectric film layer on the two wafers to be bonded respectively, and then performing face-to-face fusion bonding by chemical mechanical polishing process, thereby forming a silicon-dielectric film layer-silicon laminate structure; one of the wafers is thinned, and the silicon part is etched by photoetching and plasma dry etching process on the back surface of the wafer to stop on the dielectric film layer, thereby forming a groove structure.

[0011] In addition, preferably, the novel carrier wafer manufacturing method based on chip wafer bonding recombination of the present application comprises: after CVD dielectric film layer deposition, a step of CMP process is performed, thereby realizing the planarization treatment of the film layer to achieve the surface flatness after the conventional wafer CVD deposition film layer, and then subsequent CVD, photoetching and etching process is performed.

[0012] By using the present application, the technical optimization of chip-to-wafer stacking is realized, and the process maturity is improved. BRIEF DESCRIPTION OF DRAWINGS

[0013] Figure 1 FIG. 1 is a schematic diagram showing the process flow of chip bonding recombination to a 12-inch wafer according to an embodiment of the present application.

[0014] Figure 2 FIG. 3 is a schematic diagram showing the chip splitting mechanism and the supporting effect of the filling material in the CMP process according to an embodiment of the present application.

[0015] Figure 3 FIG. 5 is a schematic diagram showing the chip-wafer bonding recombination process flow using a groove carrier wafer according to an embodiment of the present application.

[0016] Figure 4 FIG. 7 is a schematic diagram showing the comparison of different polishing processes and chip shapes according to an embodiment of the present application.

[0017] Figure 5 FIG. 9 is a schematic diagram showing the process flow of the groove carrier wafer manufacturing process according to an embodiment of the present application.

[0018] Figure 6 FIG. 11 is a schematic diagram showing the process flow of the groove carrier wafer manufacturing process according to an embodiment of the present application.

[0019] Figure 7 FIG. 13 is a schematic diagram showing the process flow of the groove carrier wafer manufacturing process according to an embodiment of the present application.

[0020] Figure 8 FIG. 15 is a schematic diagram showing the chip and the groove carrier wafer size according to an embodiment of the present application.

[0021] Figure 9 This is a schematic diagram illustrating the distance and height dimensions of a pseudo-chip and a device chip according to one embodiment of the present invention.

[0022] Figure 10 This is a schematic diagram illustrating the structure of a groove carrier wafer according to one embodiment of the present invention. Detailed Implementation

[0023] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of the embodiments. Other embodiments or modifications obtained by those skilled in the art based on the embodiments of this application without creative effort are all within the scope of protection of this application.

[0024] In one embodiment of the present invention, to increase the integration density of transistors per unit volume and improve chip performance without reducing linewidth, stacked wafers or chips typically require a thinning process. In traditional wafer-to-wafer bonding processes, since both wafers are in wafer form, the entire process is relatively mature, and various conventional process steps (including CMP thinning) have good compatibility. However, in chip-to-wafer bonding, due to the significant differences in form between the chip and the wafer, the compatibility of subsequent processes such as CMP becomes a crucial consideration. This will be explained in detail below, and it is also the problem that this invention aims to solve.

[0025] In some applications, the chips used are not derived from 12-inch silicon wafers, but rather from 4-inch, 6-inch, or 8-inch wafers. Due to the limitations of CMP equipment capabilities for these wafer sizes, their surface flatness often fails to meet the stringent requirements of hybrid bonding (hybrid bonding) for nanometer-level interface gaps and uniformity. Furthermore, limited by existing process platforms, the lithography machines and plasma etching machines used for these chips cannot achieve the copper damask process for fabricating hybrid bonding conductive via / pad structures for high-density interconnects. Therefore, we need to reassemble the chip before further processing to meet the hybrid bonding process requirements, and then perform wafer-to-wafer hybrid bonding. This is the common process path of "chip reassembly to a 12-inch wafer, and then achieving high-density bonding through collective chip-to-wafer hybrid bonding," as illustrated in the schematic diagram of the chip bonding and reassembly to 12-inch wafer process. Figure 1 As shown. The key steps are as follows: 1. First, electrical tests are performed on 4-inch / 6-inch / 8-inch wafers, followed by chip screening and wafer dicing to obtain electrically qualified chips.

[0026] 2. Due to the poor initial planarity quality of non-12-inch wafer chips, which do not meet the interface roughness requirements for hybrid bonding and whose circuit structures do not meet the high-density interconnection requirements, subsequent high-precision planarization via CMP on the back side and fabrication of copper damask interconnect structures on the front side are necessary. Specifically, multiple discrete chips need to be reassembled into a composite wafer with a 12-inch form factor through chip-to-wafer fusion bonding before proceeding with the corresponding processes. The CMP process is involved in the aforementioned back-side CMP and front-side copper damask processes. Because gaps exist between chips, directly entering the CMP process can easily lead to isolated chips peeling off (chip stripping) or edge damage (chip edge fragmentation) during the grinding process. Therefore, after bonding, the gaps between the chips must be filled with a dielectric material (generally SiO2, commonly used in fabs and compatible with CMP processes) to transform isolated chips into a continuous, integral wafer form, thus achieving compatibility with subsequent CMP processes.

[0027] 3. In summary, after completing fusion bonding and gap filling, the back side of the chip is first thinned and polished (polishing + CMP) to significantly improve thickness uniformity. Then, the front surface undergoes CMP planarization to lay the foundation for the copper damascus process. Next, the copper conductive via / pad structure is formed using the damascus process (which also involves CMP), and a second CMP process creates a controllable shallow dish morphology on the copper pad surface, meeting the bonding interface requirements for hybrid bonding. At this point, the previously isolated die has been successfully reassembled into a 12-inch wafer, ready for direct entry into the subsequent wafer-to-wafer hybrid bonding process. This completes the chip-to-wafer hybrid bonding process.

[0028] This process enables the integration, recombination, and reprocessing of non-silicon-based, small-sized chips, which not only meets the requirements of hybrid bonding for interconnect structure and flatness, but also lays the technological foundation for the application of compound semiconductors in 3D heterogeneous integration.

[0029] However, in this process, after the chip-to-wafer fusion bonding / hybrid bonding and before the CMP process, the gaps between the chips need to be filled with a support material. The filling film must be compatible with subsequent standard fab processes. For example, while depositing the film to fill the gaps between the chips, some film inevitably deposits on top of the chips, which then needs to be removed by chemical mechanical polishing (CMP). Therefore, silicon oxide is commonly used as the deposition material. Since the chip thickness is tens of micrometers or more, and the distance between chips is over 500 μm, the amount of material to be filled is very large. Depositing such a large number of films presents a series of challenges, as described below: Warpage and Stress Issues: To ensure complete filling of the gaps between chips and coverage of the chip surface, the thickness of the deposited film must exceed the thickness of the chip. Typically, the minimum chip thickness is tens of micrometers (e.g., 10 μm). When a dielectric film tens of micrometers thick is deposited, the significant difference in the coefficient of thermal expansion (CTE) between the dielectric film (SiO2, etc.) and the silicon substrate leads to a sharp deterioration in wafer warpage. Abnormally warped wafers may cause processing anomalies in subsequent processes, affecting manufacturing stability. During chip operation, the temperature periodically rises and falls. This thermal cycling causes inconsistent expansion and contraction behavior between the silicon oxide and silicon materials deposited between the chips due to the difference in their coefficients of thermal expansion. Long-term, repeated stress will severely affect the structural stability and reliability of the chip.

[0030] Heat dissipation issues: Silicon (Si) has a high thermal conductivity, approximately 130-150 W / (m·K) (at room temperature), exhibiting excellent thermal conductivity and is therefore often used as a substrate material for electronic devices (such as chips) to effectively transfer heat. In contrast, silicon oxide (SiO2) has an extremely low thermal conductivity, only 1.3-1.5 W / (m·K) (at room temperature), making it a poor conductor of heat and commonly used for thermal insulation or insulating layers in chips. Stacked chips, due to their high performance, place stringent demands on heat dissipation. However, the large amount of silicon oxide material filling the gaps between chips severely hinders heat conduction, making it difficult to dissipate heat effectively, thus affecting the overall performance of the stacked chips.

[0031] In summary, there is currently a dilemma in the process of chip fabrication: if the gaps between chips are not filled and supported, isolated chips are prone to splitting under shear stress during the subsequent CMP process due to the lack of structural support; on the other hand, if support materials such as SiO2 are filled, problems such as warping, stress concentration and poor heat dissipation may occur.

[0032] To address these challenges, the current main solution is to optimize the filling material and deposition process for the chip gaps, while simultaneously reducing the chip thickness: on the one hand, low-stress dielectric film materials are used and the deposition volume is reduced to decrease warpage caused by the deposited film layer; on the other hand, silicon oxide with relatively high thermal conductivity is selected as the filling material, which helps to improve the heat dissipation performance of stacked chips.

[0033] However, the above methods are still not ideal in practical applications. This is because, to ensure compatibility with fab processes, only common silicon oxide materials are typically used (common silicon nitride is even less suitable due to its higher stress; thick silicon nitride can cause film peeling). While organic materials such as PI have relatively faster deposition rates, with WPH significantly improved compared to PECVD silicon oxide, using PI results in higher stress, leading to more severe warpage, and its thermal conductivity is much lower than that of inorganic silicon oxide films. More importantly, PI is not a commonly used fab material, and conventional CMP processes are incompatible with it. Therefore, silicon oxide remains the primary material choice. However, due to the inherent differences in thermal expansion coefficients and thermal conductivity between silicon oxide and silicon, problems such as warpage, stress, and heat dissipation remain difficult to fundamentally solve.

[0034] In summary, after chip-to-wafer bonding, there is an urgent need for an efficient and reliable solution that can perform CMP (Chip-to-Metal Hybridization) on the chip while mitigating potential risks caused by material stress mismatch and insufficient heat dissipation. Based on this, this invention innovatively develops a novel chip carrier wafer structure suitable for chip-to-wafer bonding processes and solves this key bottleneck problem through process integration.

[0035] Figure 1 This is a schematic diagram illustrating the process flow of chip bonding and reassembly to a 12-inch wafer according to one embodiment of the present invention.

[0036] As mentioned above, existing technologies commonly use silicon oxide as a filler material between chips. Attempts are made to alleviate problems such as warpage, stress, and heat dissipation by optimizing the PECVD process to improve silicon oxide performance or by further thinning the chip to reduce silicon oxide usage. However, due to the inherent differences in physical properties between silicon oxide and silicon, these methods only address the symptoms and cannot fundamentally solve the problem.

[0037] This invention innovatively proposes a novel chip carrier wafer structure. Through process integration, the SiO2 dielectric film material between chips is converted into silicon material, which is the same as the chip material, replacing the traditional silicon oxide filling. This fundamentally eliminates the warping, stress, and heat dissipation problems caused by material incompatibility, thereby completely solving the technical challenges faced by chip CMP chemical mechanical planarization after chip-to-wafer bonding.

[0038] As described above, during chip thinning, we don't directly thin the chip. Instead, we fill the bonding gaps with an ultra-thick silicon oxide film, then thin the surface silicon oxide layer, and finally thin the silicon chip before proceeding with subsequent processes. The purpose of filling the gaps is that CMP (Chip Motion Processing) is typically used during thinning. However, because the CMP bonding pads are soft, they deform during contact with the chip, generating strong shear forces on the chip's sidewalls. This can cause the chip to break off during CMP polishing, rendering it unusable. This is equivalent to chipping, requiring the replacement of many internal components of the CMP machine, such as bonding pads, pads, and head assemblies, with serious consequences.

[0039] Therefore, the current approach involves filling the gaps between chips with a certain thickness of material after the chip-to-wafer hybrid bonding. This fills the gaps during subsequent CMP milling and thinning, as the chips are supported by this material, no lateral shearing force is generated. This is equivalent to thinning an entire wafer, not individual isolated chips, thus preventing the chip splitting phenomenon mentioned above.

[0040] Figure 2 This is a schematic diagram illustrating the chip splitting mechanism and the supporting role of the filler material during the CMP process according to one embodiment of the present invention. The schematic diagram illustrates the principle of chip splitting caused by CMP polishing and the prevention of splitting by the filler material. Figure 2 As shown.

[0041] The chip-wafer bonding and recombination process using grooved carrier wafers in this invention is detailed below: Electrical tests are performed on the wafers, and then the chips are cut and screened to select those that pass the electrical tests for subsequent hybrid bonding.

[0042] We fabricate a carrier wafer with a grooved structure, and then use a fused deposition modeling (FDM) process to bond the chip face-down to the interior of the grooved carrier wafer. The grooved carrier wafer, as an innovation of this invention, will be described in detail later.

[0043] At this point, with the back of the chip facing outwards, we perform grinding and CMP back-side thinning to finely planarize and thin the overall thickness of the chip, in order to meet the requirements of subsequent copper damask and hybrid bonding processes for overall chip thickness planarization.

[0044] The chip and the carrier wafer with the groove structure are treated as a whole and fused together with another ordinary wafer.

[0045] A grinding and CMP process is used to thin and planarize the back side of the recessed carrier wafer, removing the non-recessed portion and exposing the front side of the chip.

[0046] The interconnecting copper vias / pads are fabricated using conventional copper damascus processes, including hybrid bonding vias / pads. A second CMP process is then performed to shape the final hybrid-bonded copper pads into a shallow dish-like morphology.

[0047] Figure 3 This is a schematic diagram illustrating a chip-wafer bonding and reassembly process using a grooved carrier wafer according to one embodiment of the present invention. The process flow diagram is as follows: Figure 3 As shown.

[0048] The novel grooved carrier wafer structure designed using this method solves the problems of peeling and edge fragmentation caused by isolated chips during CMP processing after chip-wafer reassembly. It also possesses the following significant advantages: (1) Warpage and stress control: The silicon material used in this solution is filled between the device chips. Since the silicon material is the same as the device chip itself, it effectively eliminates the macroscopic warpage and stress accumulation problems caused by the mismatch of the coefficient of thermal expansion (CTE). During the subsequent operation of the device, the thermal expansion / contraction difference caused by the alternating temperature rise and fall of different materials can also be avoided, ensuring the stability of the bonding structure and the stability of the device performance, and fundamentally improving the system reliability.

[0049] (2) Heat dissipation performance: Silicon is used as the filling material. Compared with the traditional dielectric film filling scheme, silicon has better thermal conductivity, which can efficiently conduct and dissipate heat during chip operation. The structure of this invention can significantly enhance the heat dissipation capacity of the chip, which helps to improve the operating performance of the device and extend its service life.

[0050] Through the above optimizations, this novel grooved carrier wafer structure provides an innovative and reliable solution for high-performance chip manufacturing, significantly improving the stability and durability of chips in complex process environments.

[0051] Additional notes: The reason why CMP using this process does not cause chip peeling and edge fragmentation is explained below: The chip thinning process typically consists of two stages: coarse grinding and fine grinding. The coarse grinding stage employs a grinding process that is essentially a purely mechanical process. The grinding wheel has high rigidity and undergoes almost no deformation. Material is removed gradually in a vertical direction, thus avoiding significant lateral shear forces on the chip sidewalls. Therefore, during the grinding process, no large shear forces are generated between the device chip and the carrier wafer, preventing failures such as peeling or edge splitting.

[0052] In contrast, the polishing pads used in CMP (Chemical Mechanical Polishing) processes are relatively soft. When used to polish isolated chips, the pads deform significantly at the chip edges and "embed" into the chip sidewalls, subjecting the sidewalls to large lateral shear forces. This often leads to chip edge splitting or even complete chip peeling. Therefore, the macroscopic deformation of CMP polishing pads is a key factor inducing splitting failure.

[0053] This invention guides the embedding of a device chip by pre-designing a recessed structure within a carrier wafer. Although a gap still exists between the device chip and the carrier wafer—at a distance of less than 100 micrometers—this size is much smaller than that of traditional isolated chip thinning structures. CMP bonding pads are unlikely to deform significantly within this gap, therefore the CMP bonding pads are processed on the chip surface. This significantly reduces the lateral shear force on the chip sidewalls, allowing the bonding strength between the device chip and the carrier wafer to withstand the CMP thinning and planarization process, thus avoiding device chip peeling and edge fragmentation.

[0054] Figure 4 This is a schematic diagram illustrating a comparison of different polishing processes and chip forms according to one embodiment of the present invention. The schematic diagram is as follows. Figure 4 As shown.

[0055] Based on the principle of this solution, after chip-to-wafer fusion bonding / hybrid bonding, we can bond dummy chips around the device chip. By mounting dummy chips, the distance between the device chip and the dummy chip is shortened, thereby reducing the distance between isolated chips. This method can effectively avoid peeling caused by edge grinding in CMP processes. However, the limitation of this method is that the bonding of dummy chips to the wafer must be performed one by one, resulting in low production efficiency (WPH). In contrast, the technical solution described in this solution, which uses a special groove carrier wafer to bond to the underlying wafer in a manner similar to wafer-to-wafer bonding, can significantly improve WPH. The design considerations for controlling the distance between the dummy chip and the device chip are also one of the inventions claimed in this application.

[0056] 2. Explanation of the fabrication of novel grooved carrier wafers: We can use the following process flow to fabricate the groove carrier wafer: Grooves are created on the wafer using photolithography and plasma dry etching processes, thus forming a groove carrier wafer.

[0057] This process is the simplest, but because the bottom of the groove is formed by etching, its flatness may be poor. Therefore, the final quality of the subsequent fusion bonding of the device chip will be poor, and subsequent CMP and copper damascus related processes may be affected.

[0058] Figure 5 This is a schematic diagram illustrating the fabrication process of a grooved carrier wafer according to one embodiment of the present invention. The process flow diagram is as follows: Figure 5 As shown.

[0059] An etch stop layer is formed by bonding, thereby optimizing the roughness at the bottom of the groove: (1) Deposit dielectric film layers (SiO2, SiN, etc.) on two wafers respectively, and then perform CMP process to perform face-to-face fusion bonding to form a silicon-dielectric film-silicon stack structure; (2) Thinning one of the wafers; (3) Photolithography and plasma dry etching are performed on the back of this wafer to complete the etching of the silicon part and stop on the dielectric film layer. The etching is completed, forming a groove structure.

[0060] The advantage of this process lies in the fact that, because the bottom layer being etched is a dielectric film material, it has a significantly different etch selectivity compared to silicon. Therefore, the dielectric film acts as a stop layer, with almost no etch rate and minimal loss on its surface, thus ensuring flatness. This significantly improves the quality of subsequent fusion bonding of the device chip and also significantly improves the overall quality of subsequent processes.

[0061] Near the end of the etching process, notching (later-like etching) may occur because the bottom dielectric layer cannot be further etched. This means that the etching process involves some degree of lateral erosion along the edges. However, this does not affect the overall process performance because the bottom dielectric layer remains intact, the overall flatness is not substantially affected, and it will not impact subsequent chip bonding. Therefore, this is acceptable.

[0062] Figure 6 This is a schematic diagram illustrating the fabrication process of a grooved carrier wafer according to one embodiment of the present invention. The process flow diagram is as follows: Figure 6 As shown.

[0063] A groove structure is first etched on one carrier wafer, then bonded face-to-face with another carrier wafer, and then thinned on the back side to form a groove carrier wafer.

[0064] (1) A groove structure is formed on a carrier wafer by photolithography and plasma dry etching processes; (2) Bond the carrier wafer with the groove to another carrier wafer face to face to form a stacked structure; (3) Thin the back side of the carrier wafer with the groove structure to expose the groove structure. Thus, the groove carrier wafer is fabricated.

[0065] The advantage of this process is that the bottom of the final recessed carrier wafer is the silicon surface of another carrier wafer, without any processes such as etching affecting its surface roughness. Therefore, the interface is very smooth. Furthermore, the bottom of the recess formed by etching is removed by the thinning process, so the roughness of the etched area will not adversely affect the bottom of the final recessed carrier wafer.

[0066] In this process, the depth of the preliminary etching (i.e., the groove structure etched in advance) needs to be ≥10um deeper than the remaining depth of the final wafer.

[0067] It is important to note that when thinning a carrier wafer with a grooved structure, the grooves are fully exposed at certain stages of the process, which is equivalent to thinning an isolated chip. If CMP (Continuous Molding Process) is still used at this stage, the flexibility of the CMP pads will cause deformation on the chip sidewalls and apply lateral shear forces, easily leading to failures such as peeling and edge fragmentation. Therefore, in the process flow of this grooved carrier wafer, the thinning stage must employ a grinding process, utilizing its rigidity and minimal deformation to avoid peeling and edge fragmentation. The specific mechanism is as follows: Figure 4 As shown, it has been explained in detail therein.

[0068] Figure 7 This is a schematic diagram illustrating the fabrication process of a grooved carrier wafer according to one embodiment of the present invention. The process flow diagram is as follows: Figure 7 As shown.

[0069] The final chip thickness can be controlled to be slightly below the groove depth (approximately 5–10 μm). During chemical mechanical polishing (CMP) in this state, some edge splitting (edge ​​fragmentation) may initially occur, but this defect will gradually be repaired as polishing continues. The reason peeling (detachment) does not occur is that this area only protrudes 5–10 μm above the die, with minimal morphological difference. The local deformation of the CMP polishing pad is not significant, resulting in low lateral shear force that does not exceed the bonding strength, thus avoiding peeling failure. In this case, only the aforementioned edge splitting will occur and will be gradually repaired during polishing. The reason for designing the groove depth to be higher than the die height (rather than the die height being higher than the groove depth) is that in this structure, the damage occurs to the carrier wafer, not the device die, thereby maximizing the protection of the device die from damage.

[0070] 3. After the chip is bonded to a specially designed recessed carrier wafer, when copper damask is used to perform electrical interconnection, some dielectric film will inevitably be deposited in the gap between the chip and the recessed carrier wafer. This may lead to uneven film deposition. Therefore, we can perform a CMP process after CVD dielectric film deposition to planarize the film and achieve the surface planarization level of conventional wafer CVD deposition before proceeding with subsequent CVD, photolithography, etching and other processes.

[0071] In this invention, a novel carrier wafer is designed to replace the conventional bare wafer as the carrier wafer. Using the newly designed grooved carrier wafer, chips are bonded to it to form a reconstituted wafer, which is then subjected to subsequent CMP and copper damask processes.

[0072] The dimensions of the groove structure of the present invention are as follows: the distance between the chip and the groove is ≤150um, and the height is 5um-10um lower than that of the groove.

[0073] Figure 8 This is a schematic diagram illustrating the carrier wafer dimensions of the chip and the recess according to one embodiment of the present invention. The schematic diagram of the carrier wafer dimensions of the chip and the recess of the present invention is shown below. Figure 8 As shown.

[0074] Similarly, by using a pseudo-chip bonding protection method, the distance between the pseudo-chip and the device chip is ≤150um, and the height of the device chip is 5um-10um lower than the height of the pseudo-chip, which can also achieve the same effect of avoiding chip splitting during CMP.

[0075] Figure 9 This is a schematic diagram illustrating the distance and height dimensions of a pseudo-chip and a device chip according to one embodiment of the present invention. The schematic diagram of the distance and height dimensions of the pseudo-chip and device chip of the present invention is as follows: Figure 9 As shown.

[0076] In the third type of groove carrier wafer fabrication process, the depth of the preliminary etching (i.e. the groove structure etched in advance) needs to be ≥10um deeper than the remaining depth of the final wafer.

[0077] Figure 10 This is a schematic diagram illustrating the structure of a grooved carrier wafer according to one embodiment of the present invention. The structural diagram is as follows. Figure 10 As shown.

[0078] Meanwhile, this process requires mechanical grinding to thin the carrier wafer with exposed groove structure, and cannot use CMP (chemical mechanical polishing) planarization process.

[0079] The above describes three manufacturing processes for carrier wafers with grooves. These three processes (especially the second and third) need to be protected. Please refer to Part III for details, and see the process flow diagrams below. Figure 5 , Figure 6 , Figure 7 .

[0080] After the chip is bonded to a specially designed recessed carrier wafer, as subsequent processes such as copper damask deposition advance, the films formed by CVD and other deposition processes will inevitably deposit in the gaps between the chip and the recessed carrier wafer, resulting in uneven film surfaces. To solve this problem, after completing the first CVD film deposition, we will use CMP (Chemical Vapor Processing) to planarize the surface, achieving the flatness requirements of conventional wafer surface films. Subsequent processes such as chemical vapor deposition (CVD), photolithography, and etching will then be carried out.

[0081] It should be noted that, in this document, relational terms such as "first" and "second" are used only to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.

[0082] The various embodiments in this specification are described in a related manner. The same or similar parts between the various embodiments can be referred to each other. Each embodiment focuses on describing the differences from other embodiments.

[0083] The above description is merely a specific embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the technical scope disclosed in the present invention should be included within the scope of protection of the present invention. Therefore, the scope of protection of the present invention should be determined by the scope of the claims.

[0084] The above embodiments of the present invention are merely examples for clearly illustrating the present invention and are not intended to limit the implementation of the present invention. Those skilled in the art will recognize that other variations or modifications can be made based on the above description. It is neither necessary nor possible to exhaustively describe all possible implementations here. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of the present invention should be included within the scope of protection of the claims of the present invention.

Claims

1. A novel carrier wafer manufacturing method based on chip wafer bonding and recombination, characterized in that, include: The chip is bonded face down to a carrier wafer with a groove structure using a fusion bonding process. With the back of the chip facing outward, the chip is thinned from the back through grinding and chemical mechanical polishing, thereby achieving fine planarization and thinning of the overall chip thickness to meet the requirements of subsequent copper damask and hybrid bonding processes for overall chip flatness. The chip and the carrier wafer with the groove structure are treated as a whole and fused together with another wafer; The carrier wafer with a grooved structure is thinned and planarized from the back side by grinding and chemical mechanical polishing, thereby removing the non-grooved portion and exposing the front side of the chip; Interconnected copper conductive holes / pads are formed on the front side of the chip using the copper damascus process, followed by secondary chemical mechanical polishing, which results in the final hybrid-bonded copper pads forming a shallow dish-like morphology.

2. The novel carrier wafer manufacturing method based on chip wafer bonding and recombination according to claim 1, characterized in that, Also includes: The device chip is guided to be embedded in a pre-designed groove structure in the carrier wafer. The distance between the device chip and the groove structure is within 100 micrometers, and the size of the device chip is much smaller than that of traditional isolated chip thinning structures.

3. The novel carrier wafer manufacturing method based on chip wafer bonding and recombination according to claim 1, characterized in that, Also includes: After the chip is melt-bonded / hybrid-bonded to the wafer, dummy chips are bonded around the device chip. By mounting dummy chips, the distance between the device chip and the dummy chips is shortened, thereby reducing the distance between isolated chips.

4. The novel carrier wafer manufacturing method based on chip wafer bonding and recombination according to claim 1, characterized in that, Also includes: Grooves are created on a wafer using photolithography and plasma dry etching processes, thereby forming a groove carrier wafer.

5. The novel carrier wafer manufacturing method based on chip wafer bonding and recombination according to claim 1 further includes: The roughness at the bottom of the groove is optimized by forming an etch stop layer through bonding.

6. The novel carrier wafer manufacturing method based on chip wafer bonding and recombination according to claim 5, characterized in that, Optimizing the roughness at the bottom of the groove by forming an etch stop layer through bonding includes: Dielectric film layers are deposited on the two wafers to be bonded, and then face-to-face fusion bonding is performed by chemical mechanical polishing process to form a silicon-dielectric film-silicon stack structure. One of the wafers is thinned, and the silicon portion is etched onto the dielectric film layer by photolithography and plasma dry etching on the back of the wafer, thereby forming a groove structure.

7. The novel carrier wafer manufacturing method based on chip wafer bonding and recombination according to claim 6, comprising: After CVD dielectric film deposition, a CMP process is performed to planarize the film, achieving the surface flatness of a conventional wafer after CVD deposition, before proceeding with subsequent CVD, photolithography, and etching processes.

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