Integrated circuit design method and system

Abstract

The invention discloses an integrated circuit design method and system, and belongs to the field of integrated circuit design, and the method comprises the following steps: obtaining function specifications and performance indexes of an integrated circuit, and determining physical parameters and manufacturing process parameters of a chip by combining the function specifications and the performance indexes with specific parameters of external equipment; historical design data are collected, a database is established, similarity matching is conducted on obtained parameters from history, a design framework is obtained, and an initial framework is generated; external data is collected in multiple channels, an early warning model is constructed, a constructed framework is evaluated, and the framework is optimized by grading; module design is further refined based on a framework and converted into a schematic diagram and a physical layout, and finally circuit functions are verified through a simulation tool and a result is output. According to the method, through historical data reuse, adaptive modification and external risk early warning, the design period is shortened, the adaptability of the design can be effectively improved, and technical lag is avoided.

Description

Technical Field

[0001] This invention relates to the field of integrated circuit design technology, and more specifically, to an integrated circuit design method and system. Background Technology

[0002] With the rapid iteration of integrated circuit technology, chip design faces challenges such as increased functional complexity, stringent performance indicators, and intensified market competition. Traditional design methods often rely on historical data accumulation or building frameworks from scratch, which has significant limitations: On the one hand, designs based solely on historical data are prone to becoming out of touch with current technological requirements due to incomplete data records and lagging process parameter updates, especially when competitors adopt new architectures, processes, or algorithms, making it difficult to guarantee product competitiveness. On the other hand, designing from scratch requires repeated verification of functional modules and performance indicators, which is time-consuming and labor-intensive, and cannot meet the needs of a rapidly iterating market. In addition, existing design flows lack sufficient compatibility between historical frameworks and actual functional specifications, and lack dynamic monitoring mechanisms for external technological changes, which can easily lead to design delays and extended verification cycles. Therefore, there is an urgent need for an integrated circuit design methodology that integrates historical design reuse, real-time risk warning, and dynamic adaptation optimization to shorten design cycles, improve solution reliability, and adapt to technological changes.

[0003] There are currently no effective solutions to the problems in the relevant technologies. Summary of the Invention

[0004] To address the problems in related technologies, this invention proposes an integrated circuit design method and system to overcome issues such as design lag due to reliance on historical data, insufficient functional specification adaptability, and lack of external technology risk monitoring in existing related technologies.

[0005] Therefore, the specific technical solution adopted by the present invention is as follows: An integrated circuit design method and system, the method comprising the following steps: S1. Obtain the functional specifications and performance indicators of the integrated circuit, and combine them with the specific parameters of the external equipment to determine the physical parameters and manufacturing process parameters of the chip. S2. Collect historical design data, establish a database, and perform similarity matching on the obtained parameters from the history to obtain the design framework and generate the initial framework; S3. Collect external data through multiple channels, build an early warning model, evaluate the built framework, and optimize the framework by classifying it into different levels. S4. Further refine the module design based on the framework, convert it into schematic diagram and physical layout, and finally verify the circuit function and output the results through simulation tools.

[0006] In a preferred embodiment, obtaining the functional specifications and performance indicators of the integrated circuit, and combining these with the specific parameters of the external device to determine the physical parameters and manufacturing process parameters of the chip, includes the following steps: S11. Clearly define the functional specifications and performance indicators of the integrated circuit. The functions specifically include image recognition, data encryption, audio processing, and microprocessing. The performance indicators include speed requirements, accuracy requirements, and power consumption limits. Speed ​​requirements refer to the circuit's clock frequency and data processing rate; accuracy requirements refer to the accuracy requirements specified for quantization operations in digital signal processing; power consumption limits refer to the upper limit of chip power consumption in different operating modes to meet the product's battery life or heat dissipation requirements. S12. Understand the interface standards that integrated circuits must follow to connect with external devices, and determine the chip size specifications and applicable package types; S13. Plan the functions and arrangement of chip pins, and determine the semiconductor manufacturing process nodes, process rules, and process limitations.

[0007] In a preferred embodiment, the steps of collecting historical design data, establishing a database, performing similarity matching on the obtained parameters from the history to obtain a design framework, and generating an initial framework include the following steps: S21. Establish a database, collect historical data and standardize the historical data. After processing, extract key features in a structured manner. Key features include functional modules, process nodes, performance indicators and interface types. S22. Store both the processed structured data and historical data in the database, and encode each historical design instance as a high-dimensional feature vector. It should be noted that these vectors can represent the core dimensions of their design goals and constraints; S23. Generate the corresponding feature vectors based on the known functional specifications, performance indicators, physical and process parameters, and perform an efficient similarity search in the vector database to obtain the few historical design instances with the highest similarity to the feature vectors, and sort and filter the results by key dimensions. S24. Extract the complete framework information corresponding to the scheme with the highest similarity from the database; S25. Based on existing data, modify the historical framework obtained through matching to generate an initial framework.

[0008] In a preferred embodiment, the step of adapting the matched historical framework based on existing data to generate the initial framework includes the following steps: S251. Based on the functional specifications, including image recognition, data encryption, audio processing, and microprocessing, accurately locate the corresponding functional unit in the module list of the historical framework, remove irrelevant modules, and update the core module parameters according to the accuracy requirements. S252. Based on performance indicators including speed requirements, accuracy requirements, and power consumption limits, firstly, increasing the CPU clock frequency requires replacing the high-performance process library unit; secondly, optimizing the data path bit width to meet the processing rate; and finally, inserting a low-power design structure to control the power consumption limit of each mode. S253. Replace the historical framework IO unit library model with the known interface standard and replan the pin layout; at the same time, adjust the layout according to the selected process node rules. S254. Output the adapted initial frame and mark the differences from the historical frame.

[0009] Marking the differences from the historical framework helps to build a clear design iteration trajectory, making it easier for the design team to quickly identify key modifications and efficiently assess the impact of design changes. As a preferred implementation, the process of collecting external data through multiple channels, constructing an early warning model, evaluating the constructed framework, and optimizing the framework by classifying it into levels includes the following steps: S31. Obtain data related to the design framework from multiple external channels; S32. Based on the collected external data, identify risk points, including process defects, performance lag weight settings, protocol obsolescence, and IP supply chain. Construct an early warning model based on the risk points and input the initial framework scheme into the early warning model to obtain the risk points. S33. Classify the risk points identified in the assessment into high-lag, medium-lag, and low-lag levels, and optimize the framework according to the level structure.

[0010] In a preferred implementation, the step of identifying risk points based on collected external data, including process defects, performance lag weight settings, protocol obsolescence, and IP supply chain, constructing an early warning model based on the risk points, and inputting the initial framework scheme into the early warning model to obtain the risk points includes the following steps: S321. Extract key parameters of the initial framework, define risk triggering rules, and generate binary labels, specifically: ; in, When, it indicates the first This type of risk has been triggered. When, it indicates the first The risk was not triggered. S322. Construct an early warning model, the specific formula is as follows: ; in, This is the calculated risk value, with a value range of [0-1]. For the first Risk weights are assigned as follows: process defect weight is set to 0.4, performance lag weight is set to 0.3, protocol obsolescence weight is set to 0.2, and IP supply chain risk weight is set to 0.1. For the first Risk-triggered state, Total number of risk types; S323. Input the initial framework scheme into the early warning model, obtain the risk points, and output the risk point values.

[0011] In a preferred embodiment, the step of classifying the risk points identified in the assessment into high-lag, medium-lag, and low-lag levels, and optimizing the framework according to the level structure, includes the following steps: S331. Set risk levels. It was judged to be of a high lag level. It is judged to be of medium lag level. It was determined to be of medium lag level. S332, when When this happens, directly replace the core risk module and reselect the processor architecture; when At that time, parameters are reconfigured for risk points. At the same time, add redundant design for modules with potential risks.

[0012] As a preferred implementation, the steps of further refining the module design based on the framework, converting it into schematic diagrams and physical layouts, and finally verifying the circuit function and outputting results through simulation tools include the following: S41. Based on the framework, determine the division of individual sub-modules and interface protocols, and finally output the module specification to generate design data. S42. First, convert the design data into a schematic diagram, and then convert the schematic diagram into a physical layout. S43. Use simulation tools to verify the entire process, and output the result solution after verification.

[0013] An integrated circuit design system, which employs any one of the above-described integrated circuit design methods, includes a data acquisition module, an initial framework generation module, an early warning module, and a simulation verification module. The data acquisition module is used to collect the functional specifications and performance indicators of the designed circuit, historical integrated circuit design data, and external integrated circuit design data from multiple channels. The initial framework generation module performs similarity matching in the database based on known functional specifications and performance indicators to obtain the design framework with the highest similarity, and then makes adaptation modifications. The early warning module uses collected external data to build an early warning model and calculate early warning values, classifies risk levels based on early warning values, and finally optimizes the framework based on risk levels. The simulation verification module clarifies the functions of each module in the framework, converts them into schematic diagrams and physical layouts, performs simulation verification, and outputs the design scheme.

[0014] The beneficial effects of this invention are as follows: 1. This invention enables the rapid construction of integrated circuit design frameworks by using historical data, thus shortening design time. By collecting historical design data and establishing a database, standardizing and extracting the historical data in a structured manner, generating feature vectors and performing similarity searches, similar historical design instances can be quickly matched. Based on this, adaptation modifications are made to generate an initial framework, avoiding the tedious process of designing from scratch, thereby significantly shortening the integrated circuit design cycle. 2. This invention adapts the design framework by combining it with known functional specifications and performance indicators, making the design framework more aligned with actual needs and improving the design's adaptability. It accurately locates corresponding functional units according to functional specifications, removes irrelevant modules and updates core module parameters, and replaces process library units, optimizes data paths, and inserts low-power design structures based on performance indicators. At the same time, it adapts to interface standards and process node rules, making the circuit design more compliant with requirements in terms of functionality, performance, compatibility, and manufacturability.

[0015] 3. This invention collects external data through multiple channels and establishes an early warning model to identify risk points, which can effectively avoid defects in solutions designed based on historical data. External data can capture situations such as incomplete records, missing data, or errors that may exist in historical data. In addition, the data updates quickly, and the use of historical data may result in technological lag. The early warning model sets weights for risk factors and calculates risk values ​​to classify and optimize risk points, which can ensure that the design solution can adapt to technological changes in a timely manner and keep the circuit design in line with the industry's cutting-edge technical standards. Attached Figure Description

[0016] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0017] Figure 1 This is a flowchart of an integrated circuit design method according to an embodiment of the present invention.

[0018] Figure 2 This is a block diagram of an integrated circuit design system according to an embodiment of the present invention. Detailed Implementation

[0019] To further illustrate the various embodiments, the present invention provides accompanying drawings, which are part of the disclosure of the present invention. These drawings are mainly used to illustrate the embodiments and can be used in conjunction with the relevant descriptions in the specification to explain the operating principles of the embodiments. With reference to these drawings, those skilled in the art should be able to understand other possible implementation methods and the advantages of the present invention. The components in the drawings are not drawn to scale, and similar component symbols are generally used to represent similar components.

[0020] According to embodiments of the present invention, an integrated circuit design method and system are provided.

[0021] The present invention will now be further described in conjunction with the accompanying drawings and specific embodiments, such as... Figures 1-2 As shown, according to an embodiment of the present invention, an integrated circuit design method includes the following steps: S1. Obtain the functional specifications and performance indicators of the integrated circuit, and combine them with the specific parameters of the external equipment to determine the physical parameters and manufacturing process parameters of the chip. Furthermore, obtaining the functional specifications and performance indicators of the integrated circuit, and combining these with the specific parameters of the external device to determine the physical parameters and manufacturing process parameters of the chip, includes the following steps: S11. Clearly define the functional specifications and performance indicators of the integrated circuit. The functions specifically include image recognition, data encryption, audio processing, and microprocessing. The performance indicators include speed requirements, accuracy requirements, and power consumption limits. S12. Understand the interface standards that integrated circuits must follow to connect with external devices, and determine the chip size specifications and applicable package types; S13. Plan the function and arrangement of chip pins, and determine the semiconductor manufacturing process node, process rules and process constraints; S2. Collect historical design data, establish a database, and perform similarity matching on the obtained parameters from the history to obtain the design framework and generate the initial framework; Furthermore, the process of collecting historical design data, establishing a database, performing similarity matching on the obtained parameters from the history to obtain a design framework, and generating an initial framework includes the following steps: S21. Establish a database, collect historical data and standardize the historical data. After processing, extract key features in a structured manner. Key features include functional modules, process nodes, performance indicators and interface types. S22. Store both the processed structured data and historical data in the database, and encode each historical design instance as a high-dimensional feature vector. S23. Generate the corresponding feature vectors based on the known functional specifications, performance indicators, physical and process parameters, and perform an efficient similarity search in the vector database to obtain the few historical design instances with the highest similarity to the feature vectors, and sort and filter the results by key dimensions. S24. Extract the complete framework information corresponding to the scheme with the highest similarity from the database; S25. Based on existing data, modify the historical framework obtained by matching to generate an initial framework; Furthermore, the process of adapting the matched historical framework based on existing data to generate the initial framework includes the following steps: S251. Based on the functional specifications, including image recognition, data encryption, audio processing, and microprocessing, accurately locate the corresponding functional unit in the module list of the historical framework, remove irrelevant modules, and update the core module parameters according to the accuracy requirements. S252. Based on performance indicators including speed requirements, accuracy requirements, and power consumption limits, firstly, increasing the CPU clock frequency requires replacing the high-performance process library unit; secondly, optimizing the data path bit width to meet the processing rate; and finally, inserting a low-power design structure to control the power consumption limit of each mode. S253. Replace the historical framework IO unit library model with the known interface standard and replan the pin layout; at the same time, adjust the layout according to the selected process node rules. S254. Output the adapted initial frame and mark the differences from the historical frame.

[0022] It should be noted that by adapting existing data to the historical framework and generating the initial framework, design reuse can be achieved by relying on historical design accumulation. Through precise positioning of functional modules and parameter updates, the design architecture can be ensured to closely fit specific functional requirements. Based on performance indicators and adaptation interface standards and process rules, compatibility risks can be eliminated and the feasibility of physical implementation can be guaranteed. S3. Collect external data through multiple channels, build an early warning model, evaluate the built framework, and optimize the framework by classifying it into different levels. Furthermore, the process of collecting external data through multiple channels, constructing an early warning model, evaluating the constructed framework, and optimizing the framework by classifying it into different levels includes the following steps: S31. Obtain data related to the design framework from multiple external channels; S32. Based on the collected external data, identify risk points, including process defects, performance lag weight settings, protocol obsolescence, and IP supply chain. Construct an early warning model based on the risk points and input the initial framework scheme into the early warning model to obtain the risk points. Furthermore, the process of identifying risk points based on collected external data, including process defects, performance lag weight settings, protocol obsolescence, and IP supply chain, and constructing an early warning model based on these risk points, involves the following steps: S321. Extract key parameters of the initial framework, define risk triggering rules, and generate binary labels, specifically: ; in, When, it indicates the first This type of risk has been triggered. When, it indicates the first The risk was not triggered. S322. Construct an early warning model, the specific formula is as follows: ; in, This is the calculated risk value, with a value range of [0-1]. For the first Risk weights are assigned as follows: process defect weight is set to 0.4, performance lag weight is set to 0.3, protocol obsolescence weight is set to 0.2, and IP supply chain risk weight is set to 0.1. For the first Risk-triggered state, Total number of risk types; S323. Input the initial framework scheme into the early warning model to obtain risk points, and output the risk point values. S33. Classify the risk points identified in the assessment into high-lag, medium-lag, and low-lag levels, and optimize the framework according to the level structure.

[0023] It should be noted that identifying risk points and building early warning models based on external data can systematically capture potential performance lags in dimensions such as process, performance, protocol, and supply chain. This allows the initial framework solution to undergo comprehensive risk screening, identify weaknesses in technology and supply chain links in advance, and avoid the problem of design solutions being outdated due to the use of historical data. Furthermore, the process of classifying the identified risk points into high-lag, medium-lag, and low-lag levels, and optimizing the framework based on this classification structure, includes the following steps: S331. Set risk levels. It was judged to be of a high lag level. It is judged to be of medium lag level. It was determined to be of medium lag level. S332, when When this happens, directly replace the core risk module and reselect the processor architecture; when At that time, parameters are reconfigured for risk points. At the same time, add redundant design for modules with potential risks; S4. Further refine the module design based on the framework, convert it into schematic diagram and physical layout, and finally verify the circuit function and output the results through simulation tools.

[0024] Furthermore, the module design based on the framework is further refined and converted into schematic diagrams and physical layouts. Finally, the circuit function is verified and the results are output using simulation tools, including the following steps: S41. Based on the framework, determine the division of individual sub-modules and interface protocols, and finally output the module specification to generate design data. S42. First, convert the design data into a schematic diagram, and then convert the schematic diagram into a physical layout. S43. Use simulation tools to verify the entire process, and output the result solution after verification.

[0025] An integrated circuit design system, which employs any one of the above-described integrated circuit design methods, includes a data acquisition module, an initial framework generation module, an early warning module, and a simulation verification module. The data acquisition module is used to collect the functional specifications and performance indicators of the designed circuit, historical integrated circuit design data, and external integrated circuit design data from multiple channels. The initial framework generation module performs similarity matching in the database based on known functional specifications and performance indicators to obtain the design framework with the highest similarity, and then makes adaptation modifications. The early warning module uses collected external data to build an early warning model and calculate early warning values, classifies risk levels based on early warning values, and finally optimizes the framework based on risk levels. The simulation verification module clarifies the functions of each module in the framework, converts them into schematic diagrams and physical layouts, performs simulation verification, and outputs the design scheme.

[0026] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the protection scope of the present invention.

Claims

1. An integrated circuit design method, characterized in that, The method includes the following steps: S1. Obtain the functional specifications and performance indicators of the integrated circuit, and combine them with the specific parameters of the external equipment to determine the physical parameters and manufacturing process parameters of the chip. S2. Collect historical design data, establish a database, and perform similarity matching on the obtained parameters from the history to obtain the design framework and generate the initial framework; S3. Collect external data through multiple channels, build an early warning model, evaluate the built framework, and optimize the framework by classifying it into different levels. S4. Further refine the module design based on the framework, convert it into schematic diagram and physical layout, and finally verify the circuit function and output the results through simulation tools.

2. The integrated circuit design method according to claim 1, characterized in that, The process of obtaining the functional specifications and performance indicators of the integrated circuit, and combining these with the specific parameters of external devices to determine the chip's physical parameters and manufacturing process parameters, includes the following steps: S11. Clearly define the functional specifications and performance indicators of the integrated circuit. The functions specifically include image recognition, data encryption, audio processing, and microprocessing. The performance indicators include speed requirements, accuracy requirements, and power consumption limits. S12. Understand the interface standards that integrated circuits must follow to connect with external devices, and determine the chip size specifications and applicable package types; S13. Plan the functions and arrangement of chip pins, and determine the semiconductor manufacturing process nodes, process rules, and process limitations.

3. The integrated circuit design method according to claim 2, characterized in that, The process of collecting historical design data, establishing a database, performing similarity matching on the obtained parameters from the history, obtaining a design framework, and generating an initial framework includes the following steps: S21. Establish a database, collect historical data and standardize the historical data. After processing, extract key features in a structured manner. Key features include functional modules, process nodes, performance indicators and interface types. S22. Store both the processed structured data and historical data in the database, and encode each historical design instance as a high-dimensional feature vector. S23. Generate the corresponding feature vectors based on the known functional specifications, performance indicators, physical and process parameters, and perform an efficient similarity search in the vector database to obtain the few historical design instances with the highest similarity to the feature vectors, and sort and filter the results by key dimensions. S24. Extract the complete framework information corresponding to the scheme with the highest similarity from the database; S25. Based on existing data, modify the historical framework obtained through matching to generate an initial framework.

4. The integrated circuit design method according to claim 3, characterized in that, The process of adapting the matched historical framework based on existing data to generate the initial framework includes the following steps: S251. Based on the functional specifications, including image recognition, data encryption, audio processing, and microprocessing, accurately locate the corresponding functional unit in the module list of the historical framework, remove irrelevant modules, and update the core module parameters according to the accuracy requirements. S252. Based on performance indicators including speed requirements, accuracy requirements, and power consumption limits, firstly, increasing the CPU clock frequency requires replacing the high-performance process library unit; secondly, optimizing the data path bit width to meet the processing rate; and finally, inserting a low-power design structure to control the power consumption limit of each mode. S253. Replace the historical framework IO unit library model with the known interface standard and replan the pin layout; at the same time, adjust the layout according to the selected process node rules. S254. Output the adapted initial frame and mark the differences from the historical frame.

5. The integrated circuit design method according to claim 1, characterized in that, The process of collecting external data through multiple channels, building an early warning model, evaluating the constructed framework, and optimizing the framework by classifying it into different levels includes the following steps: S31. Obtain data related to the design framework from multiple external channels; S32. Based on the collected external data, identify risk points, including process defects, performance lag weight settings, protocol obsolescence, and IP supply chain. Construct an early warning model based on the risk points and input the initial framework scheme into the early warning model to obtain the risk points. S33. Classify the risk points identified in the assessment into high-lag, medium-lag, and low-lag levels, and optimize the framework according to the level structure.

6. The integrated circuit design method according to claim 5, characterized in that, The process of identifying risk points based on collected external data, including process defects, performance lag weight settings, protocol obsolescence, and IP supply chain, involves constructing an early warning model based on these risk points and inputting the initial framework scheme into the early warning model. The process for obtaining risk points includes the following steps: S321. Extract key parameters of the initial framework, define risk triggering rules, and generate binary labels, specifically: ； in, When, it indicates the first This type of risk has been triggered. When, it indicates the first The risk was not triggered. S322. Construct an early warning model, the specific formula is as follows: ； in, This is the calculated risk value, with a value range of [0-1]. For the first Risk weights are assigned as follows: process defect weight is set to 0.4, performance lag weight is set to 0.3, protocol obsolescence weight is set to 0.2, and IP supply chain risk weight is set to 0.

1. For the first Risk-triggered state, Total number of risk types; S323. Input the initial framework scheme into the early warning model, obtain the risk points, and output the risk point values.

7. The integrated circuit design method according to claim 5, characterized in that, The process of classifying the identified risk points into high-lag, medium-lag, and low-lag levels, and then optimizing the framework based on this classification structure, includes the following steps: S331. Set risk levels. It was judged to be of a high lag level. It is judged to be of medium lag level. It was determined to be of medium lag level. S332, when When this happens, directly replace the core risk module and reselect the processor architecture; when At that time, parameters are reconfigured for risk points. At the same time, add redundant design for modules with potential risks.

8. The integrated circuit design method according to claim 1, characterized in that, The process of further refining the module design based on the framework, converting it into schematics and physical layouts, and finally verifying the circuit functionality and outputting results using simulation tools includes the following steps: S41. Based on the framework, determine the division of individual sub-modules and interface protocols, and finally output the module specification to generate design data. S42. First, convert the design data into a schematic diagram, and then convert the schematic diagram into a physical layout. S43. Use simulation tools to verify the entire process, and output the result solution after verification.

9. An integrated circuit design system, characterized in that, The system employs an integrated circuit design method as described in any one of claims 1-8, comprising a data acquisition module, an initial framework generation module, an early warning module, and a simulation verification module. The data acquisition module is used to collect the functional specifications and performance indicators of the designed circuit, historical integrated circuit design data, and external integrated circuit design data from multiple channels. The initial framework generation module performs similarity matching in the database based on known functional specifications and performance indicators to obtain the design framework with the highest similarity, and then makes adaptation modifications. The early warning module uses collected external data to build an early warning model and calculate early warning values, classifies risk levels based on early warning values, and finally optimizes the framework based on risk levels. The simulation verification module clarifies the functions of each module in the framework, converts them into schematic diagrams and physical layouts, performs simulation verification, and outputs the design scheme.

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