LED chip and manufacturing method thereof

Abstract

The invention provides an LED chip and a manufacturing method thereof, a stacking structure of the LED chip at least comprises a second type semiconductor layer, an active region and a first type semiconductor layer which are stacked in sequence, one side, deviating from the active region, of the first type semiconductor layer is a light emitting surface of the LED chip, and a first type current expansion layer is arranged in the first type semiconductor layer, a patterned lattice distortion structure is arranged in the first-type current expansion layer, the resistance value of the lattice distortion structure is larger than that of other areas of the first-type current expansion layer, the resistance values of the lattice distortion structure and the first-type current expansion layer are distributed in a periodic high-low mode, a current guiding path is formed through resistance difference, carriers are made to bypass transversely, and transverse expansion of current can be guided. Current crowding below the electrode is solved, the luminous efficiency of a non-electrode area can be improved under the condition that the area proportion of the electrode area is not increased, the luminous efficiency of the LED chip is improved, and the LED chip is simple and convenient in process manufacturing and convenient to produce.

Description

Technical Field

[0001] This invention relates to the field of light-emitting diode technology, and more specifically, to an LED chip and its manufacturing method. Background Technology

[0002] Light-emitting diodes (LEDs) are semiconductor devices used to convert electrical energy into light, and they have been widely used in public areas such as display indicators, traffic signs, and urban lighting.

[0003] Current LED chip designs require electrode structures (e.g., vertical, reverse polarity, etc.) on the light-emitting surface. To achieve higher light extraction efficiency, the electrode area on the light-emitting surface must be much smaller than the light-emitting area. In this case, the current is mainly confined to the area directly below the electrode, resulting in uneven current distribution and reduced luminous efficiency in non-electrode areas. The industry's common solution is to increase the proportion of the electrode area on the light-emitting surface, allowing the current to spread evenly throughout the device and improving the luminous efficiency in non-electrode areas. However, increasing the electrode area on the light-emitting surface reduces the light-emitting area due to electrode light absorption and shading, resulting in lower light extraction efficiency and thus limiting the luminous efficiency of the LED. Summary of the Invention

[0004] In view of this, the present invention provides an LED chip and its manufacturing method to overcome the problem that in existing LED chip designs, in order to obtain higher light extraction efficiency, the electrode area of ​​the light-emitting surface is much smaller than the light-emitting area. In this case, the current will be mainly confined to the area directly below the electrode, resulting in uneven current expansion and reduced luminous efficiency in the non-electrode area.

[0005] To achieve the above objectives, the technical solution adopted by the present invention is as follows:

[0006] An LED chip, characterized in that it comprises:

[0007] Conductive substrate;

[0008] A stacked structure disposed on one side of the conductive substrate, the stacked structure comprising at least a second type semiconductor layer, an active region, and a first type semiconductor layer stacked sequentially along a first direction; the first direction is perpendicular to the conductive substrate and extends from the conductive substrate toward the stacked structure;

[0009] A first type electrode is located on the side of the first type semiconductor layer away from the active region and is electrically connected to the first type semiconductor layer;

[0010] The second type electrode is located on the side of the conductive substrate away from the active region and is electrically connected to the second type semiconductor layer.

[0011] The side of the first type semiconductor layer away from the active region is the light-emitting surface of the LED chip. A first type current spreading layer is provided in the first type semiconductor layer. The first type current spreading layer has a patterned lattice distortion structure. The resistance value of the lattice distortion structure is greater than the resistance value of other regions of the first type current spreading layer, and the resistance values ​​of the two are periodically distributed at high and low levels to guide the lateral spread of current.

[0012] Preferably, the lattice distortion structure includes n lattice distortion sublayers, where n is an integer not less than 2, and each lattice distortion sublayer is composed of a number of lattice distortion units arranged to form a periodic structure.

[0013] The lattice distortion sublayers of each layer are arranged sequentially in a direction away from the active region, or the lattice distortion sublayers of each layer are arranged sequentially in a direction toward the active region.

[0014] Preferably, the lattice distortion units between adjacent lattice distortion sublayers are spaced apart and staggered in the vertical direction.

[0015] Preferably, the resistance value of each lattice-distorted sublayer first increases linearly or non-linearly along the direction toward the active region, and then decreases linearly or non-linearly.

[0016] Preferably, the horizontal spacing between adjacent lattice distortion units increases linearly or non-linearly from directly below the first type electrode outwards.

[0017] Preferably, the resistance value of the lattice distortion unit decreases linearly or non-linearly from directly below the first type electrode outwards.

[0018] Preferably, after the first type current spread layer is formed, a local area of ​​the first type current spread layer is treated with electron irradiation to form the lattice distortion structure.

[0019] Preferably, the first type semiconductor layer includes a first type confinement layer, a first type current spreading layer, and an ohmic contact layer sequentially stacked on the surface of the active region along the first direction; the second type semiconductor layer includes a second type confinement layer and a second type current spreading layer sequentially stacked on the surface of the active region along a direction opposite to the first direction.

[0020] It also includes a dielectric film layer and a reflector disposed between the second type semiconductor layer and the conductive substrate and stacked thereon. The reflector is connected to the conductive substrate, and the dielectric film layer is connected to the second type semiconductor layer. The dielectric film layer is provided with a conductive hole, and a conductive metal is provided in the conductive hole to conduct the reflector and the second type semiconductor layer.

[0021] The present invention also provides a method for manufacturing an LED chip, characterized by comprising the following steps:

[0022] Step 1: Provide a growth substrate and form a stacked structure on the growth substrate. The stacked structure includes a first type semiconductor layer, an active region, and a second type semiconductor layer stacked sequentially along the growth direction.

[0023] Step 2: Bond a conductive substrate to the side of the second type semiconductor layer away from the active region, and remove the growth substrate to expose the first type semiconductor layer;

[0024] Step 3: Forming the first type electrode, the second type electrode, and the lattice distortion structure;

[0025] A first type electrode is located on the side of the first type semiconductor layer away from the active region and is electrically connected to the first type semiconductor layer;

[0026] The second type electrode is located on the side of the conductive substrate away from the active region and is electrically connected to the second type semiconductor layer.

[0027] The side of the first type semiconductor layer away from the active region is the light-emitting surface of the LED chip. A first type current spreading layer is provided in the first type semiconductor layer. The first type current spreading layer has a patterned lattice distortion structure. The resistance value of the lattice distortion structure is greater than the resistance value of other regions of the first type current spreading layer, and the resistance values ​​of the two are periodically distributed at high and low levels to guide the lateral spread of current.

[0028] Preferably, after forming the first type current spread layer, the first type current spread layer is subjected to electron irradiation treatment to cause local distortion of the crystal structure of the first type current spread layer, forming the lattice distortion structure, specifically including the following steps:

[0029] Step S01: Form a lattice distortion photolithography pattern on the side of the first type semiconductor layer away from the active region;

[0030] Step S02: Using the lattice distortion lithography pattern as a mask, control the electron irradiation energy and electron irradiation dose to form a lattice distortion structure in the first type of current extension layer, and remove the lattice distortion lithography pattern.

[0031] The thickness of the lattice distortion unit in the vertical direction increases with the increase of the electron irradiation energy; the length and width of the lattice distortion unit in the horizontal direction increase with the increase of the electron irradiation dose; and the resistance value of the lattice distortion unit increases with the increase of the electron irradiation energy and the electron irradiation dose.

[0032] By means of the above technical solution, this application provides an LED chip and its manufacturing method. The LED chip is configured with a stacked structure including at least a second type semiconductor layer, an active region, and a first type semiconductor layer stacked sequentially. The side of the first type semiconductor layer away from the active region is the light-emitting surface of the LED chip. A first type current spreading layer is provided in the first type semiconductor layer. The first type current spreading layer has a patterned lattice distortion structure. The resistance value of the lattice distortion structure is greater than the resistance value of other regions of the first type current spreading layer, and the resistance values ​​of the two are periodically distributed. The resistance difference is used to form a current guiding path, so that the charge carriers (electrons or holes) can laterally bypass. This can be used to guide the lateral expansion of the current and more accurately control the distribution of charge carriers than traditional current spreading layers. Lattice distortion structures optimize light emission by regulating the movement path of charge carriers, enabling the current to spread evenly throughout the entire LED chip. This allows charge carriers to recombine fully even at the edge regions of the LED chip, solving the problem of current congestion below the electrodes and avoiding non-radiative losses caused by charge carrier accumulation in the area below the electrodes. It also improves the problem of poor current uniformity in the device. It can improve the luminous efficiency of non-electrode areas without increasing the area ratio of the electrode region, thereby improving the luminous efficiency of the LED chip. Its manufacturing process is simple and convenient, making it easy to mass-produce. Attached Figure Description

[0033] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on the provided drawings without creative effort.

[0034] Figure 1 This is a schematic diagram of the structure of an LED chip provided in an embodiment of the present invention;

[0035] Figure 2 This is a schematic diagram of another LED chip structure provided in an embodiment of the present invention;

[0036] Figure 3 This is a schematic diagram of a lattice distortion structure provided in an embodiment of the present invention;

[0037] Figure 4 This is a schematic diagram of the structure of another LED chip provided in an embodiment of the present invention;

[0038] Figure 5 This is a schematic diagram of another LED chip structure provided in an embodiment of the present invention;

[0039] Figure 6 A flowchart illustrating a method for manufacturing an LED chip according to an embodiment of the present invention;

[0040] Figures 7 to 12 This is a schematic diagram of the structure corresponding to each step of an LED chip manufacturing method provided in an embodiment of the present invention;

[0041] Figure 13 A flowchart illustrating a method for fabricating a lattice distortion structure according to an embodiment of the present invention;

[0042] Figure 14 A flowchart illustrating a method for fabricating another lattice distortion structure provided in an embodiment of the present invention;

[0043] Figures 15 to 18 The diagram shows the structural schematics corresponding to each step of a method for fabricating a lattice distortion structure provided in an embodiment of the present invention.

[0044] Explanation of symbols in the diagram:

[0045] 01. Growth substrate; 02. Buffer layer; 03. Etching stop layer; a. Thickness of lattice-distorted sublayer; b. Spacing between adjacent lattice-distorted sublayers; T1. First lattice-distorted lithographic pattern; T2. Second lattice-distorted lithographic pattern;

[0046] 1. Conductive substrate; 2. Type I semiconductor layer; 21. Ohmic contact layer; 22. Type I current spreading layer; 23. Type I confinement layer; 3. Active region; 4. Type II semiconductor layer; 41. Type II confinement layer; 42. Type II current spreading layer; 5. Type I electrode; 6. Type II electrode; 7. Dielectric film layer; 8. Conductive metal; 9. Mirror; 10. Lattice distortion structure; 11. Lattice distortion sublayer; 11.1. First lattice distortion sublayer; 11.2. Second lattice distortion sublayer; 12. Lattice distortion unit; 100. Stacked structure. Detailed Implementation

[0047] To make the content of this invention clearer, the technical solutions in the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments in this application, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the scope of protection of this application.

[0048] Many specific details are set forth in the following description in order to provide a full understanding of this application. However, this application may also be implemented in other ways different from those described herein. Those skilled in the art can make similar extensions without departing from the spirit of this application. Therefore, this application is not limited to the specific embodiments disclosed below.

[0049] Secondly, this application provides a detailed description in conjunction with schematic diagrams. When detailing the embodiments of this application, for ease of explanation, the cross-sectional views illustrating the device structure may be partially enlarged, not adhering to the usual scale. Furthermore, the schematic diagrams are merely examples and should not limit the scope of protection of this application. In addition, actual fabrication should include three-dimensional spatial dimensions of length, width, and depth.

[0050] An LED chip provided in this embodiment of the invention, such as... Figure 1 As shown, it includes:

[0051] Conductive substrate 1;

[0052] A stacked structure 100 disposed on one side of a conductive substrate 1 includes at least a second type semiconductor layer 4, an active region 3, and a first type semiconductor layer 2 stacked sequentially along a first direction; the first direction is perpendicular to the conductive substrate 1 and extends from the conductive substrate 1 toward the stacked structure 100.

[0053] The first type electrode 5 is located on the side of the first type semiconductor layer 2 away from the active region 3 and is electrically connected to the first type semiconductor layer 2.

[0054] The second type electrode 6 is located on the side of the conductive substrate 1 away from the active region 3 and is electrically connected to the second type semiconductor layer 4.

[0055] The side of the first type semiconductor layer 2 away from the active region 3 is the light-emitting surface of the LED chip. A first type current spreading layer 22 is provided in the first type semiconductor layer 2. The first type current spreading layer 22 has a patterned lattice distortion structure 10. The resistance value of the lattice distortion structure 10 is greater than the resistance value of other regions of the first type current spreading layer 22, and the resistance values ​​of the two are periodically distributed at high and low levels to guide the lateral spread of current.

[0056] It should be noted that in this embodiment, the side of the first type semiconductor layer 2 facing away from the active region 3 is set as the light-emitting surface of the LED chip, and a first type current spreading layer 22 is provided in the first type semiconductor layer 2. The first type current spreading layer 22 contains a patterned lattice distortion structure 10. The resistance value of the lattice distortion structure 10 is greater than the resistance value of other areas of the first type current spreading layer 22, and the resistance values ​​of the two are periodically distributed at high and low levels. This resistance difference forms a current guiding path, allowing charge carriers (electrons or holes) to laterally circumvent the current. This can be used to guide the lateral expansion of the current, providing more precise control over the charge carrier distribution than traditional current spreading layers. The lattice distortion structure 10 optimizes light emission by regulating the movement path of charge carriers, enabling the current to spread evenly throughout the entire LED chip. This allows charge carriers to fully recombine even in the edge region of the LED chip, solving the problem of current congestion below the electrodes and avoiding non-radiative losses caused by charge carrier accumulation in the area below the electrodes. This improves the problem of poor current uniformity in the device and can increase the luminous efficiency of the non-electrode region without increasing the area ratio of the electrode region, thereby improving the luminous efficiency of the LED chip.

[0057] It should also be noted that the specific doping types of the first type semiconductor layer 2 and the second type semiconductor layer 4 are not limited in the embodiments of this application. The doping types of the first type semiconductor layer 2 and the second type semiconductor layer 4 are opposite. The first type semiconductor layer 2 can be P-type doped or N-type doped.

[0058] In one optional embodiment of this application, the conductive substrate 1 includes, but is not limited to, a Si substrate.

[0059] In an optional embodiment of this application, the lattice distortion structure 10 includes a single-layer lattice distortion sublayer, which is composed of a number of lattice distortion units 12 arranged to form a periodic structure.

[0060] In another optional embodiment of this application, such as Figure 2 and Figure 3 As shown, the lattice distortion structure 10 includes n lattice distortion sub-layers 11, where n is an integer not less than 2. Each lattice distortion sub-layer 11 is composed of a number of lattice distortion units 12 arranged to form a periodic structure.

[0061] The lattice distortion sublayers of each layer are arranged sequentially in a direction away from the active region, or the lattice distortion sublayers of each layer are arranged sequentially in a direction toward the active region.

[0062] It should be noted that the above embodiments do not limit the specific structure of the arrangement of the lattice distortion units 12 of the lattice distortion sublayer 11. The lattice distortion sublayer 11 can be composed of a number of lattice distortion units 12 arranged to form a periodic lattice structure. The lattice structure can be any geometric shape, such as a circle, an ellipse, or a polygon.

[0063] Alternatively, the lattice distortion sublayer 11 can be composed of several lattice distortion units 12 arranged to form a periodic strip structure, such as stripes or straight lines.

[0064] Alternatively, the lattice distortion sublayer 11 can be composed of several lattice distortion units 12 arranged to form a periodic ring structure, such as a closed ring or a discontinuous ring.

[0065] Alternatively, the lattice distortion sublayer 11 can be composed of several lattice distortion units 12 arranged to form a periodic grid structure, such as a continuous grid or a discontinuous grid.

[0066] In an optional embodiment of this application, the lattice distortion units 12 between adjacent lattice distortion sublayers 11 are spaced apart and staggered in the vertical direction. This allows current to be guided layer by layer, increasing the scattering path, improving the lateral current expansion effect, and covering a wider area. The current can change direction multiple times, resulting in a more uniform distribution and improved current diffusion uniformity. Furthermore, the current is dispersed across different layers, and the multi-layer structure reduces local hot spots, thereby improving the electro-optical conversion efficiency and luminous uniformity of the LED chip.

[0067] It should be noted that in the embodiments of this application, "vertical direction" refers to the direction perpendicular to the conductive substrate.

[0068] It should be noted that the shape and distribution of each lattice distortion sublayer 11 can be the same or different.

[0069] In an optional embodiment of this application, the resistance value of each lattice-distorted sublayer 11 increases linearly or non-linearly along the direction towards the active region 3, and then decreases linearly or non-linearly. This allows for a low-resistance contact between the first-type current spreading layer 22 and the first-type electrode 5, ensuring efficient current injection. The initial linear or non-linear increase forms a potential gradient that drives the stratified diffusion of charge carriers, followed by a linear or non-linear decrease, reducing the contact resistance between the first-type current spreading layer 22 and the active region 3. This ensures efficient carrier injection into the active region 3 and increases the radiative recombination probability.

[0070] In an optional embodiment of this application, the spacing between adjacent lattice distortion sublayers 11 is uniformly set.

[0071] In another optional embodiment of this application, reference is made to Figure 3 As shown, the thickness of each lattice-distorted sublayer is 'a', and the spacing between adjacent lattice-distorted sublayers is 'b', with the value of 'b' ranging from 1 / 4a < b < 1 / 3a. This ensures that the lattice-distorted sublayers 11 are neither too dense nor too sparse, thus avoiding affecting the current spreading effect.

[0072] In one optional embodiment of this application, the spacing between adjacent lattice distortion units 12 in the horizontal direction is uniform.

[0073] It should be noted that in the embodiments of this application, "horizontal direction" refers to the direction parallel to the conductive substrate.

[0074] In another optional embodiment of this application, the horizontal spacing between adjacent lattice distortion units 12 increases linearly or non-linearly from directly below the first electrode 5 outwards. This gradually increases the channel area for conducting current outwards, thereby enhancing current compensation in the edge region far from the electrode, improving current spread, and making the current distribution more uniform.

[0075] In an optional embodiment of this application, the resistance value of the lattice distortion unit 12 is uniformly set from directly below the first type electrode 5 outwards in all directions.

[0076] In another optional embodiment of this application, the resistance value of the lattice distortion unit 12 decreases linearly or non-linearly from directly below the first electrode 5 outwards. This can enhance the lateral migration of charge carriers, improve the lateral current expansion effect and heat distribution uniformity, and avoid current congestion and heat accumulation below the electrode.

[0077] In an optional embodiment of this application, after the formation of the first type current spreading layer 22, a local area of ​​the first type current spreading layer 22 may be subjected to electron irradiation treatment to form a lattice distortion structure 10.

[0078] It should be noted that, in the embodiments of this application, after the formation of the first type current extension layer 22, the first type current extension layer 22 is subjected to electron irradiation treatment, so that when high-energy electrons pass through the semiconductor material of the first type current extension layer 22, they collide with lattice atoms, causing atoms to be ejected from their lattice positions, forming point defects or dislocations, so that the lattice structure of the first type current extension layer 22 is locally distorted to form a lattice distortion structure 10. The generated lattice defects and impurities become scattering centers, increasing the scattering probability of charge carriers (electrons or holes), reducing the mobility of charge carriers in the lattice distortion structure 10, increasing the resistance value, and making the resistance value of the lattice distortion structure 10 greater than the resistance value of other regions of the first type current extension layer 22, which is used to guide the lateral expansion of current.

[0079] In an optional embodiment of this application, the electron irradiation energy ranges from 50 to 1000 keV, including the endpoint value, and the electron irradiation dose ranges from 1E16 to 1E20e. - / cm, including endpoint values.

[0080] It should be noted that, in the embodiments of this application, electron irradiation energy refers to the kinetic energy carried by a single electron, which determines the penetrating power of the electron beam (the higher the energy, the deeper the penetration). Electron irradiation dose refers to the total energy absorbed per unit mass of material, which reflects the actual irradiation intensity received by the material.

[0081] In an optional embodiment of this application, the thickness of the lattice distortion unit 12 in the vertical direction increases with the increase of electron irradiation energy; the length and width of the lattice distortion unit 12 in the horizontal direction increase with the increase of electron irradiation dose; and the resistance value of the lattice distortion unit 12 increases with the increase of electron irradiation energy and electron irradiation dose.

[0082] It should be noted that, in the embodiments of this application, the thickness of the lattice distortion unit 12 in the vertical direction can be controlled by controlling the electron irradiation energy, and the length and width of the lattice distortion unit 12 in the horizontal direction can be controlled by controlling the electron irradiation dose. Subsequently, the resistance value of the lattice distortion unit 12 can be controlled by controlling the electron irradiation energy and the electron irradiation dose.

[0083] In an optional embodiment of this application, the direction of electron irradiation treatment of the first type current spreading layer 22 is from the light-emitting surface to the first type current spreading layer 22, and the distance between the lattice distortion sublayer 11 and the active region 3 decreases as the electron irradiation energy increases.

[0084] It should be noted that, in this embodiment of the application, by adjusting the magnitude of the electron irradiation energy, the position of the lattice distortion sublayer 11 in the first type current extension layer 22 and the spacing between the lattice distortion sublayers 11 can be located. The distribution of the lattice distortion sublayers 11 in the vertical direction can be controlled according to actual needs to guide the current path and enhance the lateral extension of the current.

[0085] In an optional embodiment of this application, the first type semiconductor layer 2 includes a first type confinement layer 23, a first type current spreading layer 22 and an ohmic contact layer 21 sequentially stacked on the surface of the active region 3 along a first direction; the second type semiconductor layer 4 includes a second type confinement layer 41 and a second type current spreading layer 42 sequentially stacked on the surface of the active region 3 along a direction away from the first direction.

[0086] In an optional embodiment of this application, the material of the first type confinement layer 23 includes, but is not limited to, AlInP; the material of the first type current spreading layer 22 includes, but is not limited to, AlGaInP; the material of the ohmic contact layer 21 includes, but is not limited to, GaAs; the material of the second type confinement layer 41 includes, but is not limited to, AlInP; and the material of the first type current spreading layer 22 includes, but is not limited to, GaP.

[0087] In one optional embodiment of this application, the thickness of the ohmic contact layer 21 ranges from 10nm to 30nm, including the endpoint values.

[0088] In an optional embodiment of this application, the thickness of the first type current spreading layer 22 ranges from 1 nm to 10 nm, including the endpoint values.

[0089] In an optional embodiment of this application, the material of the first type current spreading layer 22 includes, but is not limited to, Al, Ga, and InP.

[0090] In an optional embodiment of this application, the material of the first type current spreading layer 22 is (Al). X Ga 1-X ) 0.5 In 0.5 P.

[0091] In an optional embodiment of this application, a dielectric film layer 7 and a reflector 9 are disposed between the second type semiconductor layer 4 and the conductive substrate 1 and stacked sequentially. The reflector 9 is connected to the conductive substrate 1, and the dielectric film layer 7 is connected to the second type semiconductor layer 4. The dielectric film layer 7 is provided with a conductive hole, and the conductive hole is provided with conductive metal 8 of the second type semiconductor layer 4 for conducting the reflector 9 and the second type semiconductor layer 4.

[0092] In an optional embodiment of this application, the reflector 9 includes an ODR total reflection mirror.

[0093] In an optional embodiment of this application, such as Figure 4 As shown, the lattice distortion structure 10 includes a first lattice distortion sublayer 11.1 and a second lattice distortion sublayer 11.2 arranged sequentially along a first direction.

[0094] Based on the above embodiments, in one embodiment of this application, such as Figure 5 As shown, the second type current spreading layer 42 has a patterned lattice distortion structure 10. The resistance value of the lattice distortion structure 10 is greater than the resistance value of other areas of the second type current spreading layer 42, and the resistance values ​​of the two are periodically distributed at high and low levels to guide the lateral spread of current.

[0095] Based on the above embodiments, in one embodiment of this application, after forming the second type current spreading layer 42, the second type current spreading layer 42 includes, but is not limited to, forming a lattice distortion structure 10 by electron irradiation treatment.

[0096] It should be noted that, in the embodiments of this application, after the second type current extension layer 42 is formed, the second type current extension layer 42 is subjected to electron irradiation treatment, so that when high-energy electrons pass through the semiconductor material of the second type current extension layer 42, they collide with lattice atoms, causing atoms to be ejected from their lattice positions, forming point defects or dislocations, so that the lattice structure of the second type current extension layer 42 is locally distorted to form a lattice distortion structure 10. The generated lattice defects and impurities become scattering centers, increasing the scattering probability of charge carriers (electrons or holes), reducing the mobility of charge carriers in the lattice distortion structure 10, increasing the resistance value, and making the resistance value of the lattice distortion structure 10 greater than the resistance value of other regions of the second type current extension layer 42, which is used to guide the lateral expansion of current.

[0097] Based on the above embodiments, in one embodiment of this application, the direction of electron irradiation treatment of the second type current spreading layer 42 is from the second type electrode 6 to the second type current spreading layer 42, and the distance between the lattice distortion sublayer 11 and the active region 3 decreases as the electron irradiation energy increases.

[0098] It should be noted that, in this embodiment of the application, by adjusting the magnitude of the electron irradiation energy, the position of the lattice distortion sublayer 11 in the second type current extension layer 42 and the spacing between the lattice distortion sublayers 11 can be located. The distribution of the lattice distortion sublayers 11 in the vertical direction can be controlled according to actual needs to guide the current path and enhance the lateral extension of the current.

[0099] This invention also provides a method for manufacturing an LED chip, such as... Figure 6 As shown, it includes the following steps:

[0100] Step 1: Provide a growth substrate 01 and form a stacked structure 100 on the growth substrate 01. The stacked structure 100 includes a first type semiconductor layer 2, an active region 3 and a second type semiconductor layer 4 stacked sequentially along the growth direction.

[0101] Step 2: Bond the conductive substrate 1 to the side of the second type semiconductor layer 4 away from the active region 3, and remove the growth substrate 01 to expose the first type semiconductor layer 2.

[0102] Step 3: Form the first type electrode 5, the second type electrode 6, and the lattice distortion structure 10;

[0103] The first type electrode 5 is located on the side of the first type semiconductor layer 2 away from the active region 3 and is electrically connected to the first type semiconductor layer 2.

[0104] The second type electrode 6 is located on the side of the conductive substrate 1 away from the active region 3 and is electrically connected to the second type semiconductor layer 4.

[0105] The side of the first type semiconductor layer 2 away from the active region 3 is the light-emitting surface of the LED chip. A first type current spreading layer 22 is provided in the first type semiconductor layer 2. The first type current spreading layer 22 has a patterned lattice distortion structure 10. The resistance value of the lattice distortion structure 10 is greater than the resistance value of other regions of the first type current spreading layer 22, and the resistance values ​​of the two are periodically distributed at high and low levels to guide the lateral spread of current.

[0106] The method for manufacturing an LED chip according to an embodiment of the present invention will now be described in more detail with reference to the accompanying drawings.

[0107] Step A01, as follows Figure 7As shown, a growth substrate 01 is provided, and a stacked structure 100 is formed on the growth substrate 01. The stacked structure 100 includes a first type semiconductor layer 2, an active region 3 and a second type semiconductor layer 4 stacked sequentially along the growth direction.

[0108] In one optional embodiment of this application, the material of the growth substrate 01 includes, but is not limited to, GaAs.

[0109] In one optional embodiment of this application, the stacked structure 100 is grown using a method including but not limited to metal-organic chemical vapor deposition (MOCVD).

[0110] In an optional embodiment of this application, the first type semiconductor layer 2 includes an ohmic contact layer 21, a first type current spreading layer 22 and a first type confinement layer 23 formed sequentially along the growth direction; the second type semiconductor layer 4 includes a second type confinement layer 41 and a second type current spreading layer 42 formed sequentially along the growth direction.

[0111] In an optional embodiment of this application, a buffer layer 02 and an etching stop layer 03 are sequentially stacked on the growth substrate 01 along the growth direction before growing the stacked structure 100 to improve the crystal quality of the epitaxial stack.

[0112] In an optional embodiment of this application, the doping type of the buffer layer 02 and the corrosion stop layer 03 can be type I doping.

[0113] In an optional embodiment of this application, the material of the buffer layer 02 includes, but is not limited to, GaAs, and the material of the corrosion stop layer 03 includes, but is not limited to, GaInP.

[0114] Step A02, as follows Figure 10 As shown, a conductive substrate 1 is bonded to the side of the second type semiconductor layer 4 away from the active region 3, and the growth substrate 01 is removed to expose the first type semiconductor layer 2.

[0115] In an optional embodiment of this application, the buffer layer 02 and the etching stop layer 03 are removed simultaneously with the removal of the growth substrate 01.

[0116] In one optional embodiment of this application, wet etching is used to remove the growth substrate 01, buffer layer 02 and etching stop layer 03.

[0117] In an optional embodiment of this application, a dielectric film layer 7 and a reflector 9 are sequentially formed on the second type semiconductor layer 4 before bonding the conductive substrate 1, specifically including the following steps:

[0118] like Figure 8 As shown, a dielectric film layer 7 is deposited on the second type semiconductor layer 4, and a conductive hole is formed through the dielectric film layer 7. Then, a conductive metal 8 is fabricated in the conductive hole.

[0119] In an optional embodiment of this application, the reflector 9 includes an ODR total reflection mirror.

[0120] like Figure 9 As shown, after the reflector 9 is deposited on the dielectric film layer 7, the conductive substrate 1 is then bonded to the reflector 9.

[0121] In one optional embodiment of this application, the dielectric film 7 and the reflector 9 are grown using a method including but not limited to enhanced plasma chemical vapor deposition (PECVD).

[0122] Step A03, forming the first type electrode 5, the second type electrode 6, and the lattice distortion structure 10, specifically includes the following steps:

[0123] Step B01, as follows Figure 11 As shown, a second type electrode 6 is formed on the side of the conductive substrate 1 away from the active region 3.

[0124] In one optional embodiment of this application, a second type electrode 6 is formed on a conductive substrate 1 using a back-gold process, including but not limited to.

[0125] Step B02, as follows Figure 12 As shown, a lattice distortion structure 10 is formed within the first type current spreading layer 22.

[0126] Step B03, Reference Figure 1 As shown, a first-type electrode 5 is formed on the side of the first-type semiconductor layer 2 away from the active region 3, specifically including:

[0127] Part of the ohmic contact layer 21 is removed to expose part of the first type current spreading layer 22, and a first type electrode 5 is formed on the side of the ohmic contact layer 21 opposite to the first type current spreading layer 22.

[0128] In one optional embodiment of this application, the first type electrode 5 is formed by vapor deposition and alloying processes, including but not limited to.

[0129] In an optional embodiment of this application, reference is made to Figure 2 and Figure 3 As shown, the lattice distortion structure 10 includes n lattice distortion sub-layers 11, where n is an integer not less than 2. Each lattice distortion sub-layer 11 is composed of a number of lattice distortion units 12 arranged to form a periodic structure.

[0130] The lattice distortion sublayers 11 are arranged sequentially in the direction away from the active region 3, or the lattice distortion sublayers 11 are arranged sequentially in the direction towards the active region 3.

[0131] It should be noted that the formation order of each lattice distortion sublayer 11 is not limited in the embodiments of this application. Each lattice distortion sublayer 11 can be formed sequentially in the direction away from the active region 3, or each lattice distortion sublayer 11 can be formed sequentially in the direction towards the active region 3.

[0132] In an optional embodiment of this application, after forming the first type current spreading layer 22, the first type current spreading layer 22 is subjected to electron irradiation treatment, causing the lattice structure of the first type current spreading layer 22 to undergo local distortion, forming a lattice distortion structure 10, such as... Figure 13 As shown, the specific steps include:

[0133] Step S01: Form a lattice distortion photolithography pattern on the side of the first type semiconductor layer 2 away from the active region 3;

[0134] Step S02: Using the lattice distortion lithography pattern as a mask, control the electron irradiation energy and electron irradiation dose to form a lattice distortion structure 10 in the first type current extension layer 22, and remove the lattice distortion lithography pattern.

[0135] The thickness of the lattice distortion unit 12 in the vertical direction increases with the increase of electron irradiation energy; the length and width of the lattice distortion unit 12 in the horizontal direction increase with the increase of electron irradiation dose; the resistance value of the lattice distortion unit 12 increases with the increase of electron irradiation energy and electron irradiation dose.

[0136] In an optional embodiment of this application, reference is made to Figure 4 As shown, the lattice distortion structure 10 includes a first lattice distortion sublayer 11.1 and a second lattice distortion sublayer 11.2 sequentially arranged along a first direction, as follows: Figure 14 As shown, the specific steps include:

[0137] Step C01, as follows Figure 15 As shown, a first lattice distortion lithography pattern T1 is formed on the side of the first type semiconductor layer 2 away from the active region 3.

[0138] Optionally, in a specific embodiment of this application, a photoresist layer is first formed on the side of the first semiconductor layer 2 away from the active region 3 using PECVD, and then the photoresist is used to form a first lattice distortion photolithography pattern T1 by photolithography overlay process and ICP dry etching process. The material of the first lattice distortion photolithography pattern T1 includes, but is not limited to, SiO2.

[0139] Step C02, as follows Figure 16 As shown, using the first lattice distortion lithography pattern T1 as a mask, the first lattice distortion sublayer 11.1 is formed in the first type current extension layer 22 using the first electron irradiation energy and the first electron irradiation dose, and the first lattice distortion lithography pattern T1 is removed.

[0140] Step C03, as follows Figure 17 As shown, a second lattice distortion lithography pattern T2 is formed on the side of the first type semiconductor layer 2 away from the active region 3;

[0141] Optionally, in a specific embodiment of this application, a photoresist layer is first formed on the side of the first semiconductor layer 2 away from the active region 3 using PECVD, and then a second lattice distortion photolithography pattern T2 is formed by photolithography overlay process and ICP dry etching process. The material of the second lattice distortion photolithography pattern T2 includes, but is not limited to, SiO2.

[0142] Step C04, as follows Figure 18 As shown, using the second lattice distortion lithography pattern T2 as a mask, the second lattice distortion sublayer 11.2 is formed on the current spreading layer using the second electron irradiation energy and the second electron irradiation dose, and then the second lattice distortion lithography pattern T2 is removed.

[0143] It should be noted that in the embodiments of this application, the first lattice distortion lithography pattern T1 and the second lattice distortion lithography pattern T2 are staggered on the surface of the first semiconductor layer 2, and the shape and distribution of the first lattice distortion sublayer 11.1 and the second lattice distortion sublayer 11.2 are formed by controlling the first electron irradiation energy and the first electron irradiation dose, as well as the second electron irradiation energy and the second electron irradiation dose.

[0144] In summary, the above technical solution achieves the following results:

[0145] This embodiment provides an LED chip with a light-emitting surface on the side of a first-type semiconductor layer away from the active region. A first-type current spreading layer is provided within the first-type semiconductor layer. This first-type current spreading layer contains a patterned lattice distortion structure. The resistance of this lattice distortion structure is greater than the resistance of other areas within the first-type current spreading layer, and the resistance values ​​of the two are periodically distributed. This resistance difference forms a current guiding path, allowing charge carriers (electrons or holes) to traverse laterally. This can be used to guide the lateral expansion of the current, providing more precise control over charge carrier distribution than traditional current spreading layers. The lattice distortion structure optimizes light emission by regulating the movement path of charge carriers, enabling the current to spread uniformly throughout the entire LED chip. This allows for sufficient recombination of charge carriers even at the edge regions of the LED chip, solving the problem of current congestion below the electrodes and avoiding non-radiative losses caused by charge carrier accumulation in the area below the electrodes. This improves the problem of poor current uniformity in the device and can increase the luminous efficiency of non-electrode areas without increasing the area ratio of the electrode region, thus improving the overall luminous efficiency of the LED chip.

[0146] Furthermore, by setting the lattice distortion units between adjacent lattice distortion sublayers to be spaced apart and staggered in the vertical direction, current can be guided layer by layer, increasing the scattering path, improving the lateral current expansion effect, and allowing the current to cover a wider area. This enables the current to change direction multiple times, resulting in a more uniform distribution and improved current diffusion uniformity. In addition, the current is dispersed to different layers, and the multi-layer structure can reduce local hot spots, thereby improving the electro-optical conversion efficiency and luminous uniformity of the LED chip.

[0147] Furthermore, by setting the resistance values ​​of each lattice-distorted sublayer, which initially increase linearly or nonlinearly along the direction towards the active region, and then decrease linearly or nonlinearly, a low-resistance contact is achieved between the first-type current spread layer and the first-type electrode. This ensures efficient current injection. The initial linear or nonlinear increase creates a potential gradient that drives the stratified diffusion of charge carriers, while the subsequent linear or nonlinear decrease reduces the contact resistance between the first-type current spread layer and the active region, ensuring efficient carrier injection into the active region and increasing the radiative recombination probability.

[0148] Furthermore, by setting the thickness of each lattice distortion sublayer to 'a' and the spacing between adjacent lattice distortion sublayers to 'b', where the value of 'b' ranges from 1 / 4a < b < 1 / 3a, the lattice distortion sublayers can be prevented from being too densely or too sparsely spaced, thus avoiding any impact on the current spreading effect.

[0149] Furthermore, by setting the horizontal spacing between adjacent lattice distortion units, increasing linearly or non-linearly from directly below the first-type electrode outwards, the channel area for conducting current outwards is gradually increased. This enhances current compensation in the edge regions far from the electrode, improves current spreading, and makes the current distribution more uniform.

[0150] Furthermore, by setting the resistance value of the lattice distortion unit to decrease linearly or non-linearly from directly below the first-type electrode outwards, the lateral migration of charge carriers can be enhanced, improving the lateral current expansion effect and heat distribution uniformity, while avoiding current congestion and heat accumulation below the electrode.

[0151] Furthermore, by setting a localized area of ​​the first-type current spread layer after its formation, electron irradiation is applied to the semiconductor material of the first-type current spread layer. This causes high-energy electrons to collide with lattice atoms as they pass through the semiconductor material, resulting in atoms being ejected from their lattice positions and forming point defects or dislocations. This causes the lattice structure of the first-type current spread layer to exhibit local distortion, forming a lattice distortion structure. The resulting lattice defects and impurities become scattering centers, increasing the scattering probability of charge carriers (electrons or holes). This reduces the mobility of charge carriers in the lattice distortion structure and increases the resistance value. The resistance value of the lattice distortion structure is greater than that of other areas of the first-type current spread layer, which is used to guide the lateral expansion of the current.

[0152] Furthermore, the thickness of the lattice distortion unit in the vertical direction increases with increasing electron irradiation energy; the length and width of the lattice distortion unit in the horizontal direction increase with increasing electron irradiation dose; and the resistance value of the lattice distortion unit increases with increasing electron irradiation energy and electron irradiation dose. The thickness of the lattice distortion unit in the vertical direction can be controlled by controlling the electron irradiation energy, and the length and width of the lattice distortion unit in the horizontal direction can be controlled by controlling the electron irradiation dose. Consequently, the resistance value of the lattice distortion unit can be controlled by controlling both the electron irradiation energy and the electron irradiation dose.

[0153] This embodiment provides a method for manufacturing an LED chip that achieves the beneficial effects of the aforementioned LED chip while being simple, convenient, and easy to mass-produce.

[0154] Those skilled in the art should understand that, in the disclosure of this invention, the terms "lateral", "longitudinal", "upper", "lower", etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are only for the convenience of describing this invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, the above terms should not be construed as limiting this invention.

[0155] It should be noted that the various embodiments in this specification are described in a progressive manner, with each embodiment focusing on the differences from other embodiments. The same or similar parts between the various embodiments can be referred to each other.

[0156] The above description of the disclosed embodiments enables those skilled in the art to make or use the invention. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the invention. Therefore, the invention is not to be limited to the embodiments shown herein, but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. An LED chip, characterized by, The LED chip comprises: a conductive substrate; a stack structure arranged on one side of the conductive substrate, the stack structure comprising at least a second-type semiconductor layer, an active region and a first-type semiconductor layer stacked in sequence along a first direction; the first direction is perpendicular to the conductive substrate and points from the conductive substrate to the stack structure; a first-type electrode arranged on a side of the first-type semiconductor layer away from the active region and electrically connected to the first-type semiconductor layer; a second-type electrode arranged on a side of the conductive substrate away from the active region and electrically connected to the second-type semiconductor layer; a side of the first-type semiconductor layer away from the active region is a light-emitting surface of the LED chip, and a first-type current spreading layer is arranged in the first-type semiconductor layer, wherein a patterned lattice distortion structure is arranged in the first-type current spreading layer, the resistance value of the lattice distortion structure is greater than that of other regions of the first-type current spreading layer, and the resistance values of the two regions are periodically high and low, for guiding the lateral spreading of the current.

2. The LED chip of claim 1, wherein: The lattice distortion structure comprises n layers of lattice distortion sublayers, n is an integer not less than 2, and each layer of the lattice distortion sublayer is composed of a periodic structure arranged by a plurality of lattice distortion units; wherein each layer of the lattice distortion sublayer is arranged in sequence along the direction away from the active region, or each layer of the lattice distortion sublayer is arranged in sequence along the direction towards the active region.

3. The LED chip of claim 2, wherein: The lattice distortion units between adjacent lattice distortion sublayers are spaced apart and arranged in a vertical direction.

4. The LED chip of claim 2, wherein: The resistance value of each lattice distortion sublayer first increases linearly or non-linearly and then decreases linearly or non-linearly along the direction towards the active region.

5. The LED chip of claim 2, wherein: The spacing distance of adjacent lattice distortion units in the horizontal direction increases linearly or non-linearly from the position directly below the first-type electrode to the surrounding direction.

6. The LED chip of claim 2, wherein: The resistance value of the lattice distortion unit decreases linearly or non-linearly from the position directly below the first-type electrode to the surrounding direction.

7. The LED chip of claim 1, wherein: After the first-type current spreading layer is formed, the local region of the first-type current spreading layer is treated by electron irradiation to form the lattice distortion structure.

8. The LED chip of claim 1, wherein: The first-type semiconductor layer comprises a first-type confinement layer, the first-type current spreading layer and an ohmic contact layer stacked in sequence on the surface of the active region along the first direction; and the second-type semiconductor layer comprises a second-type confinement layer and a second-type current spreading layer stacked in sequence on the surface of the active region away from the first direction; Further comprising a dielectric film layer and a mirror arranged in sequence between the second-type semiconductor layer and the conductive substrate, the mirror being connected to the conductive substrate, and the dielectric film layer being connected to the second-type semiconductor layer, wherein a conductive hole is arranged on the dielectric film layer, and a conductive metal for conducting the mirror and the second-type semiconductor layer is arranged in the conductive hole.

9. A method for manufacturing an LED chip, characterized in that, The method comprises the following steps: Step 1: providing a growth substrate, and forming a stack structure on the growth substrate, the stack structure comprising a first-type semiconductor layer, an active region and a second-type semiconductor layer stacked in sequence along a growth direction; Step two, bonding a conductive substrate to the side of the second-type semiconductor layer away from the active region, and removing the growth substrate to expose the first-type semiconductor layer; Step three, forming a first-type electrode, a second-type electrode and a lattice distortion structure; The first-type electrode is located on the side of the first-type semiconductor layer away from the active region and forms an electrical connection with the first-type semiconductor layer; The second-type electrode is located on the side of the conductive substrate away from the active region and forms an electrical connection with the second-type semiconductor layer; The side of the first-type semiconductor layer away from the active region is the light-emitting surface of the LED chip, and a first-type current spreading layer is provided in the first-type semiconductor layer, wherein a patterned lattice distortion structure is provided in the first-type current spreading layer, the resistance value of the lattice distortion structure is greater than that of other regions of the first-type current spreading layer, and the resistance values of the two are periodically high and low, for guiding the lateral expansion of the current.

10. The method of claim 9, wherein: After the formation of the first-type current spreading layer, the first-type current spreading layer is subjected to electron irradiation treatment to make the lattice structure of the first-type current spreading layer locally distorted to form the lattice distortion structure, which specifically includes the following steps: Step S01, forming a lattice distortion photoetching pattern on the side of the first-type semiconductor layer away from the active region; Step S02, using the lattice distortion photoetching pattern as a mask, controlling the electron irradiation energy and the electron irradiation dose to form a lattice distortion structure in the first-type current spreading layer, and removing the lattice distortion photoetching pattern; The thickness of the lattice distortion unit in the vertical direction increases with the increase of the electron irradiation energy; the length and width of the lattice distortion unit in the horizontal direction increase with the increase of the electron irradiation dose; and the resistance value of the lattice distortion unit increases with the increase of the electron irradiation energy and the electron irradiation dose.

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