Data compression circuit and method for a single photon avalanche diode array

Abstract

The application relates to a data compression circuit and method suitable for a single photon avalanche diode array, wherein the circuit comprises: a pixel array, which has M rows and N columns of pixels in common; a multi-stage compression circuit, which comprises a plurality of compression buffer circuits connected in sequence, each stage of the compression buffer circuits comprises a plurality of first storage areas for storing TDC data, and address bits for storing positions of the TDC data corresponding to the pixels in the pixel array, the multi-stage compression circuit reads the TDC data of the pixel array row by row, and outputs the multi-stage compressed data to a subsequent circuit. Compared with the prior art, the application greatly compresses the pixel data in digital form, reduces the data transmission amount, solves the data transmission bottleneck problem of a large-scale array, and provides key technical support for a high-performance single photon detection system.

Description

Technical Field

[0001] This invention relates to the field of lidar, and in particular to a data compression circuit and method suitable for single-photon avalanche diode arrays. Background Technology

[0002] Single-photon detection technology, with its extremely high sensitivity and excellent time resolution, has demonstrated significant advantages in modern optics and electronics. Single-photon avalanche diode (SPAD) detectors can achieve single-photon level signal capture, meeting the detection requirements in extremely low-light environments. They possess picosecond to nanosecond time resolution, supporting high-speed photon counting and high-precision 3D imaging. Traditional analog methods suffer from excessive data volume. Although some existing technologies employ compression methods to reduce pulse width, the data volume remains substantial. To reduce information volume, digital output signals are generally used, simplifying subsequent processing and reducing the complexity of the detection system. Based on these advantages, single-photon detection has been widely applied in quantum communication and computing, LiDAR, low-light biomedical imaging, astronomical observation, spectral analysis, and environmental monitoring. While single-photon detection technology brings enhanced detection capabilities, it also presents a significant challenge—the generation of massive amounts of data. A typical SPAD array may contain hundreds or even thousands of pixels, each generating a digital signal upon detecting a photon to indicate the photon arrival time or photon count. Taking a 128x128 SPAD array as an example, if each pixel generates 1 million events per second, the entire array will generate approximately 16 billion events per second. Such a massive amount of raw data places extremely high demands on data transmission, storage, and subsequent processing.

[0003] As the scale of SPAD arrays continues to expand, the amount of data in the arrays has also exploded, leading to several problems: First, the data transmission bandwidth bottleneck: the data interface between the SPAD array chip and the subsequent processing unit often cannot withstand such high data rates, resulting in data congestion or limited system throughput; second, the increased cost of data storage: storing massive amounts of raw event data requires a large amount of storage space and high-speed storage devices, which is unacceptable in many portable or resource-constrained applications; finally, the complexity of subsequent data processing: whether data processing is based on FPGA, GPU, or application-specific integrated circuit (ASIC), high-dimensional and high-throughput data will put enormous pressure on algorithm implementation and the allocation of computing resources, prolonging processing time and even making real-time processing impossible.

[0004] Currently, two strategies are commonly used to process data generated by SPAD arrays: one is to directly transmit all raw event data to the backend for processing; the other is to perform some preprocessing and data filtering on-chip or near the chip. However, even with preprocessing, when the SPAD array operates in high background noise or high reflectivity scenarios, the photon event density is high, and both effective data and background noise events increase significantly, resulting in a still very large data volume. Existing data compression methods mainly focus on CMOS image sensors, such as JPEG and MPEG. These methods typically utilize spatial and temporal redundancy in images for compression. However, data generated by SPAD arrays differs significantly from traditional image data: SPAD arrays output discrete, sparse photon events, rather than continuous grayscale images. Therefore, traditional image compression methods are often difficult to apply directly to SPAD array data, or may cause unacceptable information loss when applied. Summary of the Invention

[0005] The purpose of this invention is to overcome the shortcomings of the prior art by providing a data compression circuit and method suitable for single-photon avalanche diode arrays.

[0006] The objective of this invention can be achieved through the following technical solutions:

[0007] A data compression circuit suitable for single-photon avalanche diode arrays includes:

[0008] A pixel array with M rows and N columns of pixels;

[0009] The multi-stage compression circuit includes multiple compression buffer circuits connected in sequence. Each compression buffer circuit includes multiple first storage areas for storing TDC data and address bits for storing the position of the pixel corresponding to the TDC data in the pixel array. The multi-stage compression circuit reads the TDC data of the pixel array line by line, performs multi-stage compression, and outputs it to the subsequent circuit.

[0010] In the multi-stage compression circuit, the number of first storage areas in each stage of the compression buffer circuit is half the number of first storage areas in the previous stage of the compression buffer circuit, wherein the number of first storage areas in the first stage of the compression buffer circuit is N / 2.

[0011] Each compression buffer circuit is configured as follows:

[0012] Reading steps: Read the TDC data of all pixels in the previous level compression buffer circuit;

[0013] The TDC data in the j-th first storage area of ​​the previous level compression cache circuit and the j+N-th... kThe TDC data in the two first storage areas are merged, and the merged TDC data is written into the j-th first storage area of ​​the current compression cache circuit, where N k The value of j represents the number of the first storage areas in the next-level compression cache circuit, and the value of j ranges from 1 to N. k A positive integer equal to 2.

[0014] When it is a first-level compression buffer circuit, the reading step reads the TDC data of all pixels in a row of the pixel array, k=0, and takes the total number of columns of the pixel array.

[0015] Add the elements of column j to column j+N k The methods for merging elements in column / 2 include:

[0016] If both TDC data points indicate invalidity, the merged TDC data will be all zeros. TDC data consists of multiple bits. When the first bit is 1, it indicates that an avalanche triggering event was detected in the entire detection time window, and it is recorded as valid data. When the first bit is 0, it indicates that no avalanche triggering event was detected in the entire detection time window, and it is recorded as invalid data.

[0017] If one TDC data point represents invalidity and the other represents validity, then the merged TDC data point represents the valid TDC data point.

[0018] If both TDC data points are valid, then the merged TDC data point is either one of the TDC data points.

[0019] A method for a circuit as described above includes:

[0020] Step S1: Obtain the TDC data of the pixel array and construct the original TDC data array;

[0021] Step S2: Determine the compression level K based on the size of the pixel array;

[0022] Step S3: Perform multi-level compression on each row of the original TDC data array to obtain the compressed row;

[0023] Step S4: Concatenate all the compressed rows to obtain the compressed TDC data array and output it.

[0024] Step S3 includes:

[0025] Step S3-1: Select the first row in the original TDC data array as the current target row, and initialize the compression level k=0;

[0026] Step S3-2: Combine the elements in the j-th column of the current target row with the (j+N)-th element. k The elements of column / 2 are merged and used as the element of the j-th column of the cache row, where Nk Let j be the column number of the cache row after the (k+1)th level of compression, where j ranges from 1 to N. k A positive integer equal to 2;

[0027] Step S3-3: Increment the compression level k by 1, and determine whether the compression level is equal to the total compression level K. If yes, proceed to step S3-5; otherwise, proceed to step S3-4.

[0028] Step S3-4: Update the cached line to the current target line and return to step S3-2;

[0029] Step S3-5: Use the cached line as the compressed line, determine whether there are any uncompressed lines in the original TDC data array. If yes, select the next line in the original TDC data array as the current target line, initialize the compression level k=0, and execute step S3-2. Otherwise, execute step S4.

[0030] Step S3-2 includes:

[0031] Step S3-2-1: Determine whether the first bit of the element in the j-th column of the current target row indicates validity. If yes, proceed to step S3-2-2; otherwise, proceed to step S3-2-3. The element in the j-th column of the current target row is multi-bit data. When the first bit is 1, it indicates that an avalanche triggering event was detected in the entire detection time window and is recorded as valid data. When the first bit is 0, it indicates that no avalanche triggering event was detected in the entire detection time window and is recorded as invalid data.

[0032] Step S3-2-2: Determine the (j+N)th row of the current target row. k If the element in column / 2 is valid, proceed to step S3-2-5; otherwise, proceed to step S3-2-4.

[0033] Step S3-2-3: Determine the (j+N)th row of the current target row. k If the element in column / 2 is valid, proceed to step S3-2-4; otherwise, proceed to step S3-2-6.

[0034] Step S3-2-4: Use the valid element as the element in the j-th column of the cache row, and write the address information of the valid element into the element address bit of the j-th column of the cache row;

[0035] Step S3-2-5: Find the element in the j-th column of the current target row and the (j+N)-th element. k Randomly select one element from the elements in column / 2 as the element in column j of the cache row, and write its address information into the address bit of the element in column j of the cache row;

[0036] Step S3-2-6: Output all zeros as the element in the j-th column of the cache row.

[0037] When in the first compression level, in step S3-2-4, after taking the valid element as the element of the j-th column of the cache row, address information is generated according to the position of the valid element in the original TDC data array and written into the element address bit of the j-th column of the cache row.

[0038] In step S3-2-5, the element in the j-th column of the current target row and the (j+N)-th element... k After randomly selecting one element from the elements in column / 2 as the element in column j of the cache row, the address information is generated based on the position of this element in the original TDC data array and written into the element address bit of column j of the cache row.

[0039] Compared with the prior art, the present invention has the following beneficial effects:

[0040] 1. By designing a multi-stage compression circuit, the TDC data in the original digital signal format output by the pixel array can be compressed. The line-by-line compression method is compatible with existing line-by-line scanning processing modes, requiring minimal modification to the radar main control. Furthermore, each compression buffer circuit, in addition to the first storage area, is equipped with address bits to store address information, indicating which pixel the compressed TDC data corresponds to, facilitating processing by subsequent circuits and the application layer. Due to the large-scale compression of digital signal format data through multi-stage compression circuits, the amount of data transmitted by the array can be significantly reduced in applications with sparse signals, solving the data transmission bottleneck problem of large-scale arrays.

[0041] 2. The distance between the merged pixels is as large as possible to reduce the amount of information lost during the compression process.

[0042] 3. Fusion methods were designed for the three scenarios. Data loss occurs when both TDCs are valid, while fusion methods using the j-th and j+N-th TDCs... k Merging two data points can reduce the probability of data loss. Attached Figure Description

[0043] Figure 1 This is a schematic diagram of the overall structure of the present invention;

[0044] Figure 2 This is a schematic diagram of the multi-stage compression process of the present invention;

[0045] Figure 3 This is a schematic diagram illustrating the specific compression process of the present invention;

[0046] Among them: 1. Pixel array, 2. Multi-level compression circuit. Detailed Implementation

[0047] The present invention will now be described in detail with reference to the accompanying drawings and specific embodiments. These embodiments are based on the technical solution of the present invention and provide detailed implementation methods and specific operating procedures. However, the scope of protection of the present invention is not limited to the following embodiments.

[0048] A data compression circuit suitable for single-photon avalanche diode arrays, such as Figure 1 As shown, it includes:

[0049] A pixel array with M rows and N columns of pixels;

[0050] Multi-stage compression circuits, such as Figure 2 As shown, it includes multiple compression buffer circuits connected in sequence. Each compression buffer circuit includes multiple first storage areas for storing TDC data and address bits for storing the position of the pixel corresponding to the TDC data in the pixel array. The multi-stage compression circuit reads the TDC data of the pixel array line by line, performs multi-stage compression, and outputs it to the subsequent stage circuit.

[0051] For an M×N pixel array, specifically a single-photon avalanche diode array, each pixel incorporates a multi-bit timing circuit to collect photon time-of-flight (TDC) data. When the single-photon avalanche diode array operates in 3D windowed detection mode, it effectively detects the TDC data of each pixel. The highest bit of the pixel data is set as the FLAG valid flag, with a value of 0 or 1. A FLAG valid flag of 0 indicates that the pixel did not trigger an event within the detection window, marking the data as an invalid signal. A FLAG valid flag of 1 indicates that the pixel triggered an event within the detection window, with the data being a photon arrival signal or an avalanche signal triggered by dark counting, indicating that the data is a valid signal.

[0052] In a multi-stage compression circuit, the number of first storage areas in each stage of the compression buffer circuit is half the number of first storage areas in the previous stage of the compression buffer circuit. Specifically, the number of first storage areas in the first stage of the compression buffer circuit is N / 2.

[0053] In this embodiment, each compression buffer circuit is configured as follows:

[0054] Reading steps: Read the TDC data of all pixels in the previous level compression buffer circuit;

[0055] The TDC data in the j-th first storage area of ​​the previous level compression cache circuit and the j+N-th... k The TDC data in the two first storage areas are merged, and the merged TDC data is written into the j-th first storage area of ​​the current compression cache circuit, where N kThe value of j represents the number of the first storage areas in the next-level compression cache circuit, and the value of j ranges from 1 to N. k A positive integer equal to 2.

[0056] When it is the first-level compression buffer circuit, the TDC data of all pixels in a row of the pixel array is read in the reading step, k=0, and the total number of columns of the pixel array is taken.

[0057] Here, the elements of column j and column (j+N) are combined. k The methods for merging elements in column / 2 include:

[0058] If both TDC data points indicate invalidity, the merged TDC data will be all zeros. TDC data consists of multiple bits. When the first bit is 1, it indicates that an avalanche triggering event was detected in the entire detection time window, and it is recorded as valid data. When the first bit is 0, it indicates that no avalanche triggering event was detected in the entire detection time window, and it is recorded as invalid data.

[0059] If one TDC data point represents invalidity and the other represents validity, then the merged TDC data point represents the valid TDC data point.

[0060] If both TDC data points are valid, the merged TDC data point is either one of them. In this embodiment, if both TDC data points are valid, one of them is selected randomly as the merged TDC data point.

[0061] Furthermore, a method based on the above-described circuit includes:

[0062] Step S1: Obtain the TDC data of the pixel array and construct the original TDC data array;

[0063] Step S2: Determine the compression level K based on the size of the pixel array;

[0064] Step S3: For each row of the original TDC data array, perform multi-level compression sequentially to obtain the compressed row, including:

[0065] Step S3-1: Select the first row in the original TDC data array as the current target row, and initialize the compression level k=0;

[0066] Step S3-2: Combine the elements in the j-th column of the current target row with the (j+N)-th element. k The elements of column / 2 are merged and used as the element of the j-th column of the cache row, where N k Let j be the column number of the cache row after the (k+1)th level of compression, where j ranges from 1 to N. k A positive integer equal to 2;

[0067] Step S3-2 includes:

[0068] Step S3-2-1: Determine whether the first bit of the element in the j-th column of the current target row indicates validity. If yes, proceed to step S3-2-2; otherwise, proceed to step S3-2-3. The element in the j-th column of the current target row is multi-bit data. When the first bit is 1, it indicates that an avalanche triggering event was detected in the entire detection time window and is recorded as valid data. When the first bit is 0, it indicates that no avalanche triggering event was detected in the entire detection time window and is recorded as invalid data.

[0069] Step S3-2-2: Determine the (j+N)th row of the current target row. k If the element in column / 2 is valid, proceed to step S3-2-5; otherwise, proceed to step S3-2-4.

[0070] Step S3-2-3: Determine the (j+N)th row of the current target row. k If the element in column / 2 is valid, proceed to step S3-2-4; otherwise, proceed to step S3-2-6.

[0071] Step S3-2-4: Use the valid element as the element in the j-th column of the cache row, and write the address information of the valid element into the element address bit of the j-th column of the cache row;

[0072] When in the first compression level, in step S3-2-4, after taking the valid element as the element of the j-th column of the cache row, address information is generated according to the position of the valid element in the original TDC data array and written into the element address bit of the j-th column of the cache row.

[0073] Step S3-2-5: Find the element in the j-th column of the current target row and the (j+N)-th element. k Randomly select one element from the elements in column / 2 as the element in column j of the cache row, and write its address information into the address bit of the element in column j of the cache row;

[0074] When in the first compression stage, in step S3-2-5, the element in the j-th column of the current target row and the (j+N)-th element... k After randomly selecting one element from the elements in column / 2 as the element in column j of the cache row, the address information is generated based on the position of this element in the original TDC data array and written into the element address bit of column j of the cache row.

[0075] Step S3-2-6: Output all zeros as the element in the j-th column of the cache row.

[0076] Step S3-3: Increment the compression level k by 1, and determine whether the compression level is equal to the total compression level K. If yes, proceed to step S3-5; otherwise, proceed to step S3-4.

[0077] Step S3-4: Update the cached line to the current target line and return to step S3-2;

[0078] Step S3-5: Use the cached line as the compressed line, determine whether there are any uncompressed lines in the original TDC data array. If yes, select the next line in the original TDC data array as the current target line, initialize the compression level k=0, and execute step S3-2. Otherwise, execute step S4.

[0079] Step S4: Concatenate all the compressed rows to obtain the compressed TDC data array and output it.

[0080] like Figure 2The three-level data compression process in this embodiment is illustrated below. In this embodiment, a row of TDC data for the pixel array contains 64 data points. Due to the sparsity of photon events, gray boxes represent valid data for the corresponding column positions of a row of pixels, while white boxes represent invalid data. The first-level compression compares and compresses the data in the first column and the 33rd column of the original TDC data for each row of pixels, outputting the resulting data to the first column of the first-level compression buffer. Similarly, the second and 34th columns of the original TDC data for each row of pixels are compared and compressed, outputting the resulting data to the second column of the first-level compression buffer. This process continues, with the 32nd and 64th columns of the original TDC data for each row of pixels being compared and compressed, outputting the resulting data to the 32nd column of the first-level compression buffer. The first-level compression requires 32 compression module units working in parallel. After the first-level compression, the amount of original TDC data for a row of pixels in this embodiment is reduced from 64 to 32. Next, the second level of compression is performed. The data in the first-level compression buffer is compared and compressed with the data in the first-level compression buffer, and the resulting data is output to the first column of the second-level compression buffer. The data in the second-level compression buffer is compared and compressed with the data in the first-level compression buffer, and the resulting data is output to the second column of the second-level compression buffer. And so on, the data in the 16th column of the first-level compression buffer is compared and compressed with the data in the 32nd column of the second-level compression buffer, and the resulting data is output to the 32nd column of the second-level compression buffer. The second-level compression requires 16 compression module units to work in parallel. After the second-level compression, the amount of original TDC data for one row of pixels in the embodiment is compressed from 64 to 16. Finally, a third level of compression is performed. The data in columns 1 and 9 of the second-level compression buffer are compared and compressed, and the resulting data is output to column 1 of the third-level compression buffer. Similarly, the data in columns 2 and 10 of the first-level compression buffer are compared and compressed, and the resulting data is output to column 2 of the third-level compression buffer. This process continues, with columns 8 and 16 of the second-level compression buffer being compared and compressed, and the resulting data is output to column 8 of the third-level compression buffer. This third-level compression requires eight compression module units working in parallel. After the third-level compression, the original TDC data volume of one row of pixels in this embodiment is compressed from 64 to 8. When the array size increases in this embodiment, the number of compression levels can be increased by multiple levels, achieving a significant improvement in data compression rate and effectively increasing the readout rate of single-photon avalanche diode array data.

[0081] like Figure 3As shown, the compression module in the embodiment will be described in detail. For two input data points to the compression module, if input IN1 is valid (data A) and input IN2 is invalid (data 0), then the output data OUT after compression and comparison is valid data, and its content is the data A from input IN1. If input IN1 is invalid (data 0) and input IN2 is valid (data B), then the output data OUT after compression and comparison is valid data, and its content is the data B from input IN2. Similarly, if both input IN1 and IN2 are valid (data A and B), then the output data OUT after compression and comparison is valid data, and its content is the data A from input IN1. Conversely, if both input IN1 and IN2 are invalid (data 0), then the output data OUT after compression and comparison is invalid data, and its content is 0.

[0082] If the aforementioned functions are implemented as software functional units and sold or used as independent products, they can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of this invention, or the part that contributes to the prior art, or a part of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute all or part of the steps of the methods described in the various embodiments of this invention. The aforementioned storage medium includes various media capable of storing program code, such as USB flash drives, portable hard drives, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical disks.

Claims

1. A data compression circuit suitable for single-photon avalanche diode arrays, comprising: A pixel array with M rows and N columns of pixels; Its characteristic is that it further includes: The multi-stage compression circuit includes multiple compression buffer circuits connected in sequence. Each compression buffer circuit includes multiple first storage areas for storing TDC data and address bits for storing the position of the pixel corresponding to the TDC data in the pixel array. The multi-stage compression circuit reads the TDC data of the pixel array line by line, performs multi-stage compression, and outputs it to the subsequent circuit. Each compression buffer circuit is configured as follows: Reading steps: When it is a first-level compression buffer circuit, read the TDC data of all pixels in one row of the pixel array; when it is not a first-level compression buffer circuit, read the TDC data of the first storage area in the previous level compression buffer circuit. The TDC data in the j-th first storage area of ​​the previous level compression cache circuit and the j+N-th... k The TDC data in the two first storage areas are merged, and the merged TDC data is written into the j-th first storage area of ​​this level of compression cache circuit. Simultaneously, the address information generated by the position of the pixel corresponding to the merged TDC data in the pixel array is written into the TDC data address bit of the j-th first storage area of ​​this level of compression cache circuit. Here, k is the compression level, an integer from 0 to K, and K is the total number of compression levels. When k=0, N... k Take the total number of columns in the pixel array. When k is an integer from 1 to K, N k The value of j represents the number of the first storage areas in the next-level compression cache circuit, and the value of j ranges from 1 to N. k A positive integer equal to 2; The TDC data in the j-th first storage area of ​​the previous level compression cache circuit and the (j+N)-th... k The methods for merging TDC data in the two first storage areas include: If both TDC data points indicate invalidity, the merged TDC data will be all zeros. TDC data consists of multiple bits, where the first bit is 1 to indicate valid data and the first bit is 0 to indicate invalid data. If one TDC data point represents invalidity and the other represents validity, then the merged TDC data point represents the valid TDC data point. If both TDC data points are valid, then one of the two TDC data points is randomly selected as the merged TDC data point.

2. The data compression circuit suitable for single-photon avalanche diode arrays according to claim 1, characterized in that, In the multi-stage compression circuit, the number of first storage areas in each stage of the compression buffer circuit is half the number of first storage areas in the previous stage of the compression buffer circuit, wherein the number of first storage areas in the first stage of the compression buffer circuit is N / 2.

3. A method based on the circuit according to any one of claims 1-2, characterized in that, include: Step S1: Obtain the TDC data of the pixel array and construct the original TDC data array; Step S2: Determine the total number of compression levels K based on the size of the pixel array; Step S3: Perform multi-level compression on each row of the original TDC data array to obtain the compressed row; Step S4: Concatenate all the compressed rows to obtain the compressed TDC data array and output it.

4. The method according to claim 3, characterized in that, Step S3 includes: Step S3-1: Select the first row in the original TDC data array as the current target row, and initialize the compression level k=0; Step S3-2: Combine the TDC data in the j-th column of the current target row with the (j+N)-th column... k The TDC data in column / 2 is merged and used as the TDC data in column j of the cache row; Step S3-3: Increment the compression level k by 1, and determine whether the compression level is equal to the total compression level K. If yes, proceed to step S3-5; otherwise, proceed to step S3-4. Step S3-4: Update the cached line to the current target line and return to step S3-2; Step S3-5: Use the cached line as the compressed line, determine whether there are any uncompressed lines in the original TDC data array. If yes, select the next line in the original TDC data array as the current target line, initialize the compression level k=0, and execute step S3-2. Otherwise, execute step S4.

5. The method according to claim 4, characterized in that, Step S3-2 includes: Step S3-2-1: Determine whether the first bit of the TDC data in the j-th column of the current target row indicates validity. If yes, proceed to step S3-2-2; otherwise, proceed to step S3-2-3. The TDC data in the j-th column of the current target row is multi-bit data. When the first bit is 1, it indicates valid data; when the first bit is 0, it indicates invalid data. Step S3-2-2: Determine the (j+N)th row of the current target row. k If the TDC data in column / 2 indicates that it is valid, then proceed to step S3-2-5; otherwise, proceed to step S3-2-4. Step S3-2-3: Determine the (j+N)th row of the current target row. k If the TDC data in column / 2 is valid, proceed to step S3-2-4; otherwise, proceed to step S3-2-6. Step S3-2-4: Use the valid TDC data as the TDC data in the j-th column of the cache row, and write the address information of the valid TDC data into the TDC data address bit in the j-th column of the cache row; Step S3-2-5: The TDC data in the j-th column of the current target row and the (j+N)-th column... k Randomly select one of the TDC data from column / 2 as the TDC data in the j-th column of the cache row, and write its address information into the address bit of the TDC data in the j-th column of the cache row; Step S3-2-6: Output all zero values ​​as the TDC data of the j-th column of the cache row.

6. The method according to claim 5, characterized in that, When in the first compression level, in step S3-2-4, after using the valid TDC data as the TDC data in the j-th column of the cache row, address information is generated according to the position of the valid TDC data in the original TDC data array and written into the TDC data address bit in the j-th column of the cache row. In step S3-2-5, the TDC data in the j-th column of the current target row and the (j+N)-th column... k After randomly selecting one TDC data from column / 2 as the TDC data in the j-th column of the cache row, the address information is generated based on the position of the TDC data in the original TDC data array and written into the TDC data address bit of the j-th column of the cache row.

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