Gallium oxide NMOS (N-channel metal oxide semiconductor) field effect transistor-based logic unit and implementation method thereof

Abstract

The invention discloses a logic unit based on a gallium oxide NMOS (N-channel Metal Oxide Semiconductor) field effect transistor. The logic unit comprises a pull-up structure and a pull-down network, the pull-up structure is composed of a gate-drain short circuit or gate-source short circuit gallium oxide NMOS transistor, and the pull-up structure is used for providing a potential pull-up function at an output end and pulling up an output signal to a high level; the pull-down network is formed by connecting at least one gallium oxide NMOS transistor according to a target logic function and a CMOS logic circuit design standard, and the pull-down network is used for providing a potential pull-down function at an output end and pulling down an output signal to a low level GND. The method does not need heterogeneous integration, and has the characteristics of low process difficulty, low cost, strong anti-interference capability and capability of supporting complete logic function realization.

Description

Technical Field

[0001] This invention belongs to the field of gallium oxide NMOS field-effect transistor technology, specifically relating to a logic unit based on gallium oxide NMOS field-effect transistor and its implementation method. Background Technology

[0002] Existing silicon-based CMOS complementary logic circuits are insufficient to meet the performance and reliability requirements under extreme environments.

[0003] Gallium oxide, with its wide bandgap, excellent radio frequency characteristics, high temperature stability, and radiation resistance, is an ideal material for producing high-reliability circuits. However, its P-type doped material is difficult to prepare. Currently realized P-type doped gallium oxides all suffer from problems such as low hole mobility, high manufacturing cost, and poor performance, which limits the development of gallium oxide-based logic circuits and chips.

[0004] Gallium oxide (GaO) semiconductors possess advantages such as high temperature stability, strong radiation resistance, excellent radio frequency performance, and low cost, making them ideal materials for realizing highly stable integrated circuits. However, compared to complementary digital logic circuits with conventional CMOS structures, GaO materials are limited by their own crystal structure. P-type doped materials are difficult to realize or have poor performance, resulting in poor performance of GaO PMOS transistors, thus limiting the application of GaO in CMOS complementary digital logic circuits.

[0005] CN115831968A discloses a hydrogen-terminated diamond / gallium oxide heterojunction complementary device and its fabrication method. This device combines hydrogen-terminated diamond PMOS and gallium oxide NMOS through heterojunction to fabricate an ultra-wide bandgap semiconductor CMOS device, bypassing the limitations of gallium oxide P-type materials. However, this approach has drawbacks: it introduces an additional material system, increasing process complexity, and heterojunction can easily lead to lattice constant mismatch, affecting device performance stability.

[0006] The β-Ga₂O₃ pseudo-CMOS monolithic inverter (document number 10.1109 / TED.2023.3305338) constructs both unipolar and bipolar pseudo-CMOS inverters using gallium oxide thin-film NMOS transistors. Its limitation is that it only provides simple inverter and simple logic gate verification, lacking a general logic circuit design method (ORN gates, NAND gates, multi-input XOR gates, complex combinational logic gates, etc.).

[0007] There are currently no patent reports on monolithically integrated gallium oxide CMOS circuits; existing research on monolithic gallium oxide logic circuits is limited to inverters, and there is still a lack in the implementation of digital logic functions. Summary of the Invention

[0008] In order to overcome the shortcomings of the existing technology, the present invention aims to provide a logic cell implementation method based on gallium oxide NMOS field-effect transistor. This method does not require heterogeneous integration and has the characteristics of low process difficulty, low cost, strong anti-interference ability, and support for the implementation of complete logic functions.

[0009] To achieve the above objectives, the technical solution adopted by the present invention is as follows: A logic cell based on gallium oxide NMOS field-effect transistors includes a pull-up structure and a pull-down network; The pull-up structure is composed of a gallium oxide NMOS transistor with its gate and drain shorted or its gate and source shorted. The pull-up structure is used to provide a potential pull-up function at the output terminal to pull the output signal up to a high level. The pull-down network is formed by connecting at least one gallium oxide NMOS transistor according to the target logic function and in accordance with the CMOS logic circuit design standard. The pull-down network is used to provide a potential pull-down function at the output terminal, pulling the output signal down to a low level (GND).

[0010] The pull-up structure acts as a load, connected between the power supply voltage and the output terminal, and is used to provide a path for the output signal to be pulled up to a logic high level.

[0011] The pull-down network is connected between the output terminal and ground, and is used to provide a path for the output signal to be pulled down to a logic low level when the input signal meets the conditions.

[0012] The target logic functions are NOT gate, NAND gate, NOR gate, and combinational logic.

[0013] When the target logic function is NOT gate, the pull-down network consists of a gallium oxide NMOS transistor with its gate connected to the input signal, its source grounded, and its drain connected to the output. The pull-up structure uses a gallium oxide NMOS transistor with its gate-drain or gate-source shorted, connected between the power supply voltage and the output. By designing the on-resistance of the pull-down transistor to be much smaller than that of the pull-up transistor, the logic inversion function of outputting a high level when the input is low and outputting a low level when the input is high is achieved.

[0014] When the target logic function is a NAND gate, the pull-down network consists of two or more gallium oxide NMOS transistors connected in series. The gate of each transistor is connected to the corresponding input signal, the source of the bottom transistor is grounded, and the drain of the top transistor is connected to the output terminal. The pull-up structure is connected between the power supply and the output terminal. When all inputs in the pull-down network are high, the series path is turned on, and the output is pulled low. When any input is low, the series path is turned off, and the output is pulled up to a high level, thus realizing the NAND logic function.

[0015] When the target logic function is a NOR gate, the pull-down network consists of two or more gallium oxide NMOS transistors connected in parallel. The gate of each transistor is connected to the corresponding input signal, all sources are grounded, and the drains are connected to the output terminal. The pull-up structure is connected between the power supply and the output terminal. When any input in the pull-down network is high, the corresponding transistor is turned on, and the output is pulled low. When all inputs are low, the pull-down network is turned off, and the output is pulled up to a high level, thus realizing the NOR logic function.

[0016] When the target logic function is to implement a general combinational logic function, the pull-down network combines gallium oxide NMOS transistors into a series, parallel, or series-parallel hybrid structure according to the target logic expression and the CMOS combinational logic circuit design method. Each input variable controls the gate of one or more transistors, and the entire network is connected between the output terminal and ground. The pull-up structure still uses gallium oxide NMOS transistors with gate-drain shorted or gate-source shorted as loads.

[0017] With the above structure, arbitrary combinational logic functions can be implemented in a monolithic gallium oxide process, and automated mapping and optimization can be achieved with the help of a CMOS-compatible design flow.

[0018] The implementation method based on the above-mentioned logical unit includes the following steps; Step 1: Based on the target logic function (such as NOT gate, NAND gate, NOR gate, combinational logic, etc.), construct a circuit structure with an enhancement-mode gallium oxide NMOS transistor as the only active device. The circuit structure includes a pull-up structure and a pull-down network: Step 2: Set an on-resistance ratio much greater than 1 for the load NMOS transistor of the pull-up structure and the driving NMOS transistor of the pull-down network; Step 3: Based on the on-resistance ratio determined in Step 2, differentiate the physical parameters of the driving NMOS transistor of the pull-down network and the load NMOS transistor of the pull-up structure. Step 4: Based on the physical parameters determined in Step 3, perform differentiated design, execute the standard gallium oxide NMOS integrated circuit manufacturing process, and integrate all logic units on the same chip.

[0019] The pull-down network in step 1 is determined by gallium oxide NMOS transistors according to the target digital logic function and the CMOS logic circuit design standard. The source of the gallium oxide NMOS transistor is connected to the drain of the corresponding other transistor or the low-level signal (ground signal, GND) according to the design standard; the drain is connected to the source of the corresponding other transistor or the output port according to the design standard; and the gate is connected to the corresponding input signal according to the design standard.

[0020] The pull-up structure in step 1 uses either a gallium oxide NMOS transistor with its gate and drain shorted or a gallium oxide NMOS transistor with its gate and source shorted. For the gallium oxide NMOS transistor with its gate and drain shorted, the gate is connected to a high-level signal source (power supply, VDD), the drain is connected to a high-level signal source (power supply, VDD), and the source is connected to the output interface. For the gallium oxide NMOS transistor with its gate and source shorted, the gate is connected to the output interface, the drain is connected to a high-level signal source (power supply, VDD), and the source is connected to the output interface.

[0021] In step 2, the on-resistance ratio, i.e., R on负载 / R on驱动 >>1, and the value is not less than 10; the purpose of this step is to ensure the correctness and stability of the output logic level by setting a large difference in the on-resistance ratio. When the input signal turns on the pull-down network, its overall on-resistance is much smaller than that of the pull-up load transistor, so that the output voltage can be strongly pulled down to the low level (GND); when the input signal turns off the pull-down network, the current path is cut off, and the output is pulled up to the high level (VDD) through the pull-up load transistor with a larger resistance.

[0022] In step 3, the precise control of the on-resistance in the differentiated design is achieved through one or more of the following methods in synergy: i) NMOS transistor width-to-length ratio design: The aspect ratio of the driving NMOS transistor in the pull-down network is designed to be much larger than that of the load NMOS transistor in the pull-up structure; Specifically, the width-to-length ratio of the driving NMOS transistor to the load NMOS transistor should be no less than 10, ranging from 10:1 to 100:1. This design utilizes the inverse relationship between on-resistance and width-to-length ratio to ensure that the on-resistance of the load transistor is much greater than the overall on-resistance of the pull-down network drive structure. ii) Channel doping engineering: Selective ion implantation is performed on the gallium oxide channel layer in the driving NMOS transistor region and the load NMOS transistor region to achieve differentiated doping. In the load NMOS transistor region, light doping or no additional doping is performed to control its channel carrier concentration at 10. 16 cm -3 Up to 10 17 cm -3 The lower doping concentration results in a lower concentration of free carriers (electrons) in the channel, which directly leads to a higher on-resistance. In the driving region of the NMOS transistor, a high concentration of n-type dopant (such as silicon (Si) or tin (Sn) is injected to increase the channel carrier concentration to 10. 17 cm -3 Up to 10 18cm -3 A higher range and higher doping concentration can provide sufficient free electrons, resulting in higher electron concentration and mobility, thereby achieving lower on-resistance and ensuring that the on-resistance of the load transistor is much greater than the overall on-resistance of the pull-down network drive structure.

[0023] The beneficial effects of this invention are: This invention requires only monolithic integration, eliminating the need for heterogeneous integration steps, which offers advantages in terms of process complexity and cost, and avoids the lattice matching problem of heterogeneous materials.

[0024] This invention uses only NMOS transistors to construct logic units, which increases power consumption compared to CMOS logic units, but results in shorter transmission delay and faster response speed.

[0025] This invention presents a logic cell design method based on gallium oxide NMOS field-effect transistors, constructs a complete basic logic gate library, and realizes an all-gallium oxide monolithic system. Because its pull-down network design is compatible with CMOS, existing electronic design automation (EDA) tools and design flows can be used directly after a small amount of adaptation, which greatly reduces the design threshold and cycle time. This enables gallium oxide chips to not only process "power flow" and "RF signals", but also "information flow", providing a solid technical foundation for the next generation of high-efficiency and highly integrated electronic systems. Attached Figure Description

[0026] Figure 1 The diagram shows the circuit structure of NOT gate (a), NOR gate (b), and NAND gate (c) based on gallium oxide NMOS field-effect transistors.

[0027] Figure 2 The diagram shows the circuit structure of NOT gate (a), NOR gate (b), and NAND gate (c) based on gallium oxide NMOS field-effect transistors.

[0028] Figure 3 This is a schematic diagram of a general combinational logic circuit structure based on gallium oxide NMOS field-effect transistors. Detailed Implementation

[0029] The present invention will now be described in further detail with reference to the accompanying drawings.

[0030] This invention discloses a logic unit based on gallium oxide NMOS field-effect transistors and its implementation method. According to the target digital logic function, a pull-down network composed of gallium oxide NMOS transistors is designed according to CMOS logic circuit to provide the output voltage pull-down function. The gallium oxide NMOS transistors are shorted through the port gate drain or gate source to form a resistor as a pull-up structure, which replaces the pull-up network in the CMOS design to realize the output signal pull-up function, thus realizing a gallium oxide monolithic integrated logic unit and chip.

[0031] As shown in the appendix Figure 1 respectively show the circuit structures of the NOT gate (a), NOR gate (b), and NAND gate (c); among which, the pull-up circuit is composed of gallium oxide NMOS transistors with shorted gate and drain, and the pull-down circuit is composed of gallium oxide NMOS transistors designed according to the CMOS logic circuit according to the target digital logic function. An example of the gallium oxide NMOS inverter logic circuit in the present invention is as Figure 1 (a) shown, including: input port V in , high-level signal VDD, low-level signal GND, pull-up structure T2, pull-down network T1, output port V out , where T1 and T2 are enhancement-mode gallium oxide NMOS transistors, and their on-resistance relationship is T1 << T2. The on-resistance R on of the transistor is related to the transconductance g m of the transistor, and the transconductance is regulated by the aspect ratio and channel doping concentration of the transistor. According to step 3 in the invention content, the on-resistance can be adjusted by changing the aspect ratio of the transistor and the gallium oxide channel doping concentration; The pull-down network T1 is determined to be a single gallium oxide NMOS transistor according to the inverter logic function requirements through the CMOS logic circuit design standard. In its structure, the source of the gallium oxide NMOS transistor is connected to the low-level signal (ground signal, GND); the drain is connected to the output port; the gate is connected to the corresponding input V in according to the design standard; The pull-up structure T2 selects a gallium oxide NMOS transistor with shorted gate and drain. Its gate is connected to the high-level signal VDD, its drain is connected to the high-level signal VDD, and its source is connected to the output terminal interface V out ;

[0032] When the input voltage V in is at a low level, T1 is turned off and T2 is turned on, and the output voltage V out is pulled up to a high level via T2; when the input voltage V in is at a high level, both T1 and T2 are turned on, and the output voltage V out is pulled down to a low level via T1.

[0033] Through this example, it can be seen that by only using enhancement-mode NMOS transistors and through reasonable circuit connection methods and precise physical designs, a correctly functioning inverter logic unit has been successfully constructed, directly addressing the core difficulties in the gallium oxide logic circuit mentioned in the background technology.

[0034] The following table shows the comparison between the present invention and the traditional CMOS circuit design: An example of the gallium oxide NMOS NOR gate logic circuit in the present invention is as Figure 1 As shown in (b), it includes: input ports A and B, high-level signal VDD, low-level signal GND, pull-up structure T3, and pull-down network T1. 、 T2, Output Port V out T1, T2, and T3 are enhancement-mode gallium oxide NMOS transistors, and their on-resistance relationship is T1 = T2 < <T3; The pull-down network, defined by the OR / NOT logic function requirements according to the CMOS logic circuit design standard, consists of two gallium oxide NMOS transistors, T1 and T2. In their structure, the source of the gallium oxide NMOS transistor is connected to the low-level signal (ground signal, GND); the drain is connected to the output port; and the gate is connected to the corresponding input ports A and B according to the design standard. The pull-up structure T3 uses a gallium oxide NMOS transistor with its gate and drain shorted. Its gate is connected to the high-level signal VDD, its drain is connected to the high-level signal VDD, and its source is connected to the output interface V. out Connected.

[0035] When input voltages A and B are both low, T1 and T2 are off, T3 is on, and the output voltage V... out The voltage is pulled high via T3; when either input voltage A or B is high, at least one of T1 or T2 is turned on, and the output voltage V... out Pull down to low level via T1 or T2 or T1 and T2.

[0036] This example demonstrates that by using only enhanced NMOS transistors, and through reasonable circuit connections and precise physical design, a functionally correct NOR gate logic unit can be successfully constructed, directly addressing the core challenge of implementing gallium oxide logic circuits mentioned in the background section.

[0037] An example of a gallium oxide NMOS NAND gate logic circuit in this invention is as follows: Figure 1 As shown in (c), it includes: input ports A and B, high-level signal VDD, low-level signal GND, pull-up structure T3, and pull-down network T1. 、 T2, Output Port V out T1, T2, and T3 are enhancement-mode gallium oxide NMOS transistors, and their on-resistance relationship is T1 = T2 < <T3。

[0038] The pull-down network, defined by the NAND logic function requirements and based on CMOS logic circuit design standards, consists of two gallium oxide NMOS transistors, T1 and T2. In this structure, the source of NMOS transistor T1 is connected to a low-level signal (ground, GND); its drain is connected to the source of T2; and its gate is connected to input port A. Similarly, the source of NMOS transistor T2 is connected to the drain of T1; its drain is connected to the output port; and its gate is connected to input port B. The pull-up structure T3 uses a gallium oxide NMOS transistor with its gate and drain shorted. Its gate is connected to the high-level signal VDD, its drain is connected to the high-level signal VDD, and its source is connected to the output interface V. out Connected.

[0039] When input voltages A and B are both high, T1, T2, and T3 are all turned on, and the output voltage V... out The input voltage is pulled low via T1 and T2; when either input voltage A or B is low, at least one of T1 and T2 is turned off, and the output voltage V... out It is pulled up to a high level via T3.

[0040] In the gallium oxide CMOS logic circuit design proposed in this invention, the pull-up circuit can be constructed from a gallium oxide NMOS transistor with its gate and drain shorted, such as... Figure 1 As shown; it can also be constructed using a gallium oxide NMOS transistor with its gate and source shorted, such as Figure 2 As shown. The pull-up circuit is composed of a gallium oxide NMOS transistor with its gate and source shorted, and the pull-down circuit is composed of gallium oxide NMOS transistors according to the CMOS logic circuit design based on the target digital logic function.

[0041] For different circuit structures, the on-resistance ratio of all transistors is determined according to CMOS design standards. Then, the physical parameters of each transistor are designed differently based on the on-resistance ratio. Specifically, this is achieved through one or more of the following methods: i) adjusting the width-to-length ratio of the NMOS transistor to control the on-resistance of the transistor; ii) channel doping engineering, which performs differentiated doping on different transistor channel regions to adjust the on-resistance of the transistor. The NMOS transistor materials involved in this invention are not limited to gallium oxide. Other wide-bandgap semiconductor materials that are difficult to dopant in or have poor performance in the P-type are also applicable, such as zinc oxide, zinc sulfide, aluminum nitride, and aluminum gallium nitride.

[0042] Based on the actual logic function requirements, the corresponding pull-down network is designed according to CMOS design principles to implement any general combinational logic function, such as... Figure 3 As shown ， The pull-up circuit is composed of a gallium oxide NMOS transistor with its gate and drain shorted, while the pull-down circuit is composed of gallium oxide NMOS transistors according to the CMOS logic circuit design based on the target digital logic function.

Claims

1. A logic cell based on gallium oxide NMOS field effect transistor, characterized in that, The pull-up structure and a pull-down network are included; The pull-up structure is composed of a gate-drain shorted or gate-source shorted gallium oxide NMOS transistor, and is used to provide a potential pull-up function at the output end to pull up the output signal to a high level. The pull-down network is connected between the output end and the ground, and is used to provide a path for the output signal to be pulled down to a low logic level when the input signal meets the condition.

2. The gallium oxide NMOS field effect transistor-based logic cell of claim 1, wherein, The pull-up structure is connected between the power supply voltage and the output end as a load, and is used to provide a path for the output signal to be pulled up to a logic high level.

3. The gallium oxide NMOS field effect transistor-based logic cell of claim 1, wherein, The pull-down network is connected between the output end and the ground, and is used to provide a path for the output signal to be pulled down to a low logic level when the input signal meets the condition. The target logic function is a NOT gate, a NAND gate, a NOR gate, or a combination logic.

4. The gallium oxide NMOS field effect transistor-based logic cell of claim 3, wherein, When the target logic function is a NOT gate, the pull-down network is composed of one gallium oxide NMOS transistor, the gate of which is connected to the input signal, the source is connected to the ground, and the drain is connected to the output end; the pull-up structure is a gate-drain shorted or gate-source shorted gallium oxide NMOS transistor connected between the power supply voltage and the output end; by designing the on-resistance of the pull-down transistor to be much smaller than the on-resistance of the pull-up transistor, the logic inversion function of output high level when input is low level and output low level when input is high level is realized. When the target logic function is a NAND gate, the pull-down network is composed of two or more gallium oxide NMOS transistors in series, the gates of each transistor are connected to the corresponding input signal, the source of the lowermost transistor is connected to the ground, and the drain of the uppermost transistor is connected to the output end; the pull-up structure is connected between the power supply and the output end; when all inputs in the pull-down network are high level, the series path is turned on and the output is pulled low; when any input is low level, the series path is turned off and the output is pulled up to high level, realizing the NAND logic function. When the target logic function is a NOR gate, the pull-down network is composed of two or more gallium oxide NMOS transistors in parallel, the gates of each transistor are connected to the corresponding input signal, all sources are connected to the ground, and the drains are connected to the output end; the pull-up structure is connected between the power supply and the output end; when any input in the pull-down network is high level, the corresponding transistor is turned on and the output is pulled low; when all inputs are low level, the pull-down network is turned off and the output is pulled up to high level, realizing the NOR logic function. When the target logic function is to realize general combination logic function, the pull-down network is composed of gallium oxide NMOS transistors in series, parallel or series-parallel hybrid structure according to the target logic expression and CMOS combination logic circuit design method, wherein each input variable corresponds to the gate of one or more transistors, and the network is connected between the output end and the ground; the pull-up structure still uses a gate-drain shorted or gate-source shorted gallium oxide NMOS transistor as a load.

5. A method of implementing a logic unit as claimed in any of claims 1-4, characterized in that, The method comprises the following steps: Step 1: according to the target logic function, build a circuit structure with gallium oxide NMOS transistor as the only active device, the circuit structure includes a pull-up structure and a pull-down network: Step 2: set a much larger on-resistance ratio than 1 for the load NMOS tube of the pull-up structure and the drive NMOS tube of the pull-down network; Step 3: according to the on-resistance ratio determined in step 2, the physical parameters of the drive NMOS tube of the pull-down network and the load NMOS tube of the pull-up structure are designed differently; Step 4: according to the physical parameters determined in step 3, perform the standard gallium oxide NMOS integrated circuit manufacturing process to integrate all logic units on the same chip.

6. The method of claim 5, wherein the logic unit is implemented by a field programmable gate array (FPGA). The pull-down network in step 1 is determined by the CMOS logic circuit design standard according to the target digital logic function, and the source of the gallium oxide NMOS tube is connected to the drain of the corresponding transistor or low-level signal according to the design standard; the drain is connected to the source of the corresponding transistor or output port according to the design standard; the gate is connected to the corresponding input signal according to the design standard.

7. The method of claim 5, wherein the logic unit is implemented by a field programmable gate array (FPGA). The pull-up structure in step 1 uses one of the gate-drain shorted gallium oxide NMOS tube and the gate-source shorted gallium oxide NMOS tube, the gate-drain shorted gallium oxide NMOS tube, the gate of which is connected to the high-level signal source, the drain of which is connected to the high-level signal source, and the source of which is connected to the output interface; the gate of the gate-source shorted gallium oxide NMOS tube is connected to the output interface, the drain is connected to the high-level signal source, and the source is connected to the output interface.

8. The method of claim 5, wherein the logic unit is implemented by a field programmable gate array (FPGA). The step 2, the on resistance ratio is R on负载 / on驱动 > 1, and the value is not less than 10.

9. The method of claim 5, wherein the logic unit is implemented by a field programmable gate array (FPGA). In step 3, the differential design accurately controls the on-resistance, which is achieved by one or more of the following means: i) The width-length ratio of the drive NMOS tube in the pull-down network is designed to be much larger than the width-length ratio of the load NMOS tube in the pull-up structure; The width-length ratio of the drive NMOS tube to the load NMOS tube is not less than 10, ranging from 10:1 to 100:1; ii) Selective ion implantation is performed on the gallium oxide channel layer in the drive NMOS tube region and the load NMOS tube region to achieve differential doping, and in the load NMOS tube region, light doping or no additional doping is performed to control the channel carrier concentration in the low range; In the drive NMOS tube region, high-concentration n-type dopants are implanted.

10. The implementation method of the logic unit according to claim 9, characterized in that, Low range is channel carrier concentration in 10 16 cm -3 to 10 17 cm -3 ; High concentration of n-type dopant is channel carrier concentration 10 17 cm -3 to 10 18 cm -3 .

Images