Ternary univariate up- and down-spin logic circuits based on memristors

Abstract

The application discloses a three-value single-variable up-spin logic and down-spin logic circuit based on a memristor. M 1, a second memristor M 2, a first NMOS tube T 1 and a second NMOS tube T 2 are composed of; the three-value single-variable down-spin logic circuit based on the memristor is composed of a third memristor M 3, a fourth memristor M 4, a fifth memristor M 5, a third NMOS tube T 3, a fourth NMOS tube T 4 and a fifth NMOS tube T 5 are composed of. The three-value single-variable up-spin and down-spin logic circuit based on the memristor in the application has clear and simple circuit model structure and is easy to realize, and has important significance for application research in many fields such as multi-value digital logic circuit design.

Description

Technical Field

[0001] This invention belongs to the field of circuit design technology and relates to a ternary digital logic circuit structure, specifically to the design and implementation of a physically realizable memristor-based ternary single-variable spin-up and spin-down logic circuit. Background Technology

[0002] Integrated circuit technology is the foundation of today's digital information society. However, as the size of traditional complementary metal-oxide-semiconductor (CMOS) devices gradually shrinks to their limits, the continuation of Moore's Law is facing difficulties. The emergence of memristors promises to bring new opportunities for the development of the information technology industry. In 1971, Chua first theoretically predicted the existence of a fourth basic circuit element after resistors, capacitors, and inductors, naming it the memristor. In 2008, HP Labs successfully fabricated a practical memristor device. Since then, memristors have attracted widespread attention from researchers due to their unique characteristics. After years of research, it has been found that they play an important role in many fields such as digital logic circuits, chaotic circuits, non-volatile memory, and artificial neural networks.

[0003] In the research of memristor digital logic circuits, researchers have proposed various implementation methods based on different design concepts, such as material implication (IML) for binary logic, memristor-ratioed logic (MRL), and memristor-aided logic (MAGIC). Ternary logic, as a type of multi-valued logic, possesses more complex logical functions compared to binary logic, providing more efficient transmission capabilities and reducing system complexity. Furthermore, it can easily solve some problems that are difficult to address with binary logic. Therefore, ternary logic circuits, with their highest information cost-performance ratio, hold the promise of replacing binary logic circuits, thereby realizing high-density logic information systems.

[0004] In ternary logic circuits, single-variable logic functions, as a means of implementing certain digital functions, have attracted the attention and widespread use of researchers. Zhu Yucheng's "Theory of Multi-Valued Digital Logic" provides a corresponding description of these ternary single-variable logic functions, among which spin-up logic and spin-down logic have attracted researchers' attention due to their unique numerical and physical characteristics. Spin-up logic is a logic function that increments the input logic value by one; similarly, spin-down logic decrements the input logic value by one. These two logic transformations have been widely applied in the design of more complex ternary digital logic circuits. Because memristors are compatible with CMOS technology and have a small size, they are more conducive to further improving circuit integration. Therefore, designing ternary logic circuits based on memristors is expected to improve information storage density and information transmission efficiency, and will have a certain promoting effect on improving the architecture of existing computers. Summary of the Invention

[0005] To address the shortcomings of existing technologies, this invention proposes a design scheme for a three-valued single-variable spin-up logic and spin-down logic circuit based on memristors.

[0006] The technical solution adopted by this invention to solve the technical problem is as follows:

[0007] The memristor-based three-valued single-variable spin-up logic circuit is composed of a first memristor M1, a second memristor M2, a first NMOS transistor T1, and a second NMOS transistor T2.

[0008] The memristor-based three-valued single-variable downspin logic circuit is composed of a third memristor M3, a fourth memristor M4, a fifth memristor M5, a third NMOS transistor T3, a fourth NMOS transistor T4, and a fifth NMOS transistor T5.

[0009] The source of the first NMOS transistor T1 is connected to the gate of the second NMOS transistor T2, and serves as the input terminal of the three-valued single-variable spin-up logic circuit; the drain of the first NMOS transistor T1 is connected to the positive terminal of the second memristor M2; the gate of the first NMOS transistor T1 is connected to the power supply V. DD Connected.

[0010] The positive terminal of the first memristor M1 and the negative terminal of the second memristor M2 are connected to the drain of the second NMOS transistor T2, and serve as the output terminal of the three-valued single-variable spin-up logic circuit. The negative terminal of the first memristor M1 is connected to the power supply V. DD Connected. The source of the second NMOS transistor T2 is grounded.

[0011] The gates of the third NMOS transistor T3 and the fourth NMOS transistor T4 are connected to the negative terminal of the fifth memristor M5 and serve as the input terminals of the three-valued single-variable downspin logic circuit; the drain of the third NMOS transistor T3 is connected to the positive terminal of the fourth memristor M4; and the source of the third NMOS transistor T3 is grounded.

[0012] The positive terminal of the third memristor M3 and the negative terminal of the fourth memristor M4 are connected to the drain of the fifth NMOS transistor T5, serving as the output of a three-valued single-variable downspin logic circuit. The gate of the fifth NMOS transistor T5 and the drain of the fourth NMOS transistor T4 are connected to the positive terminal of the fifth memristor M5. The negative terminal of the third memristor M3 is connected to the power supply V. DD Connected. The source of the fourth NMOS transistor T4 is grounded. The source of the fifth NMOS transistor T5 is grounded.

[0013] The inputs and outputs of the memristor-based three-valued single-variable spin-up and spin-down logic circuits follow the following relationships:

[0014] For a ternary single-variable spin-up logic circuit, when the input is logic 0, the output Y of the ternary single-variable spin-up logic circuit... UP The output is logic 1; when the input is logic 1, Y UP The output is logic 2; when the input is logic 2, Y UP The output is logic 0.

[0015] For a ternary single-variable spin-down logic circuit, when the input is logic 0, the output Y of the ternary single-variable spin-up logic circuit... DOWN The output is logic 2; when the input is logic 1, Y... DOWN The output is logic 0; when the input is logic 2, Y DOWN The output is logic 1.

[0016] Furthermore, the threshold voltages of both the first NMOS transistor T1 and the second NMOS transistor T2 are 1.5V.

[0017] Furthermore, the threshold voltages of the third NMOS transistor T3 and the fourth NMOS transistor T4 are both 1.5V. The threshold voltage of the fifth NMOS transistor T5 is 0.8V.

[0018] The beneficial effects of this invention are: the three-valued single-variable top-spin and bottom-spin logic circuits based on memristors have a clear and simple circuit model structure that is easy to implement, and are of great significance for application research in many fields such as multi-valued digital logic circuit design. Attached Figure Description

[0019] Figure 1 This is a structural diagram of a three-valued single-variable spin-up logic circuit based on memristors, according to the present invention.

[0020] Figure 2 This is a structural diagram of a three-valued single-variable downspin logic circuit based on memristors, according to the present invention. Detailed Implementation

[0021] The preferred embodiments of the present invention will now be described in detail with reference to the accompanying drawings.

[0022] The three-valued single-variable top-down and bottom-up logic circuit structures based on memristors of this invention are as follows: Figure 1 and Figure 2 As shown in the figure. The upward logic circuit consists of two memristors and two NMOS transistors; the downward logic circuit consists of three memristors and three NMOS transistors, and is implemented by utilizing the resistance switching and memory characteristics of the memristors.

[0023] The memristor-based three-valued single-variable spin-up logic circuit is composed of a first memristor M1, a second memristor M2, a first NMOS transistor T1, and a second NMOS transistor T2; the memristor-based three-valued single-variable spin-down logic circuit is composed of a third memristor M3, a fourth memristor M4, a fifth memristor M5, a third NMOS transistor T3, a fourth NMOS transistor T4, and a fifth NMOS transistor T5.

[0024] For a ternary single-variable spin-up logic circuit, the source of the first NMOS transistor T1 is connected to the gate of the second NMOS transistor T2, and serves as the input terminal X of the ternary single-variable spin-up logic circuit; the drain of the first NMOS transistor T1 is connected to the positive terminal of the second memristor M2; the gate of the first NMOS transistor T1 is connected to the power supply V. DD The positive terminal of the first memristor M1 and the negative terminal of the second memristor M2 are connected to the drain of the second NMOS transistor T2, and serve as the output terminal Y of the three-valued single-variable spin-up logic circuit. UP The negative terminal of the first memristor M1 is connected to the power supply V. DD Connected, the source of the second NMOS transistor T2 is grounded.

[0025] For the ternary single-variable downspin logic circuit, the gates of the third NMOS transistor T3 and the fourth NMOS transistor T4 are connected to the negative terminal of the fifth memristor M5, serving as the input terminal X of the ternary single-variable downspin logic circuit; the drain of the third NMOS transistor T3 is connected to the positive terminal of the fourth memristor M4; and the source of the third NMOS transistor T3 is grounded. The positive terminal of the third memristor M3 and the negative terminal of the fourth memristor M4 are connected to the drain of the fifth NMOS transistor T5, serving as the output terminal Y of the ternary single-variable downspin logic circuit. DOWN The gate of the fifth NMOS transistor T5 and the drain of the fourth NMOS transistor T4 are connected to the positive terminal of the fifth memristor M5. The negative terminal of the third memristor M3 is connected to the power supply V. DDConnected. The source of the fourth NMOS transistor T4 is grounded. The source of the fifth NMOS transistor T5 is grounded.

[0026] In memristor-based ternary single-variable spin-up and spin-down logic circuits, the logic state is a voltage value, where voltage V is defined. DD 2V corresponds to logic "2"; V DD / 2 is 1V, corresponding to logic "1"; GND is 0V, corresponding to logic "0". The truth table of the three-valued single-variable spin-up and spin-down logic designed in this invention is shown in the table below:

[0027]

[0028] For a three-valued single-variable upspin logic circuit, the threshold voltages of the first NMOS transistor T1 and the second NMOS transistor T2 are both 1.5V. When the input terminal X is connected to GND, i.e., the input is logic "0", the first NMOS transistor T1 is turned on and the second NMOS transistor T2 is turned off. According to the resistance change law of memristors, current flows in from the negative terminal of the first memristor M1 and the positive terminal of the second memristor M2, and the resistance will increase to R. OFF Output Y UP Voltage is divided by the first memristor M1 and the second memristor M2, i.e., V DD / 2, output is logic "1"; when input X is connected to V DD When / 2, i.e., the input is logic "1", both the first NMOS transistor T1 and the second NMOS transistor T2 are cut off, and the output terminal Y... UP The pull-up resistor, formed by the first memristor M1, is connected to V. DD The output is logic "2"; when input X is connected to V DD When the input is logic "2", the first NMOS transistor T1 is off, the second NMOS transistor T2 is on, and the output Y... UP The second NMOS transistor T2 is connected to GND, and the output is logic "0".

[0029] For a three-valued single-variable spin-up logic circuit, the threshold voltages of the third NMOS transistor T3 and the fourth NMOS transistor T4 are both 1.5V, and the threshold voltage of the fifth NMOS transistor T5 is 0.8V. When the input terminal X is connected to GND, i.e., the input is logic "0", the third NMOS transistor T3, the fourth NMOS transistor T4, and the fifth NMOS transistor T5 are all cut off, and the output terminal Y... DOWN Connected to V via a pull-up resistor formed by the third memristor M3. DD The output is logic "2"; when input X is connected to V DD When / 2, i.e., the input is logic "1", the third NMOS transistor T3 and the fourth NMOS transistor T4 are cut off, the fifth NMOS transistor T5 is turned on, and the output terminal Y... DOWNThe fifth NMOS transistor T5 is connected to GND, and the output is logic "0"; when the input terminal X is connected to V... DD When the input is logic "2", the third NMOS transistor T3 and the fourth NMOS transistor T4 are turned on, and the fifth NMOS transistor T5 is turned off. According to the resistance change law of memristors, current flows in from the negative terminal of the third memristor M3 and the fourth memristor M4 and flows out from the positive terminal, and the resistance will increase to R. OFF Output Y UP Voltage is divided by the third memristor M3 and the fourth memristor M4, i.e., V DD / 2, the output is logic "1".

[0030] Those skilled in the art should recognize that the above embodiments are only used to verify the present invention and are not intended to limit the present invention. Any changes or modifications to the above embodiments that are within the scope of the present invention will fall within the protection scope of the present invention.

Claims

1. A ternary univariate up-spin logic circuit based on memristor characterized by: The first and second memristors M1 and M2, the first and second NMOS transistors T1 and T2; The source of the first NMOS transistor T1 is connected with the gate of the second NMOS transistor T2, and serves as an input terminal X of the ternary single-variable up-spin logic circuit; the drain of the first NMOS transistor T1 is connected with the anode of the second memristor M2; the gate of the first NMOS transistor T1 is connected with the power supply V DD ; The positive pole of the first memistor M1, the negative pole of the second memistor M2 and the drain of the second NMOS transistor T2 are connected, and serve as the output end Y of the ternary single-variable up-spin logic circuit UP ; the negative pole of the first memistor M1 is connected with the power supply V DD ; and the source of the second NMOS transistor T2 is grounded. For a ternary single-variable spin-up logic circuit, when the input is logic 0, the output Y of the ternary single-variable spin-up logic circuit... UP The output is logic 1; when the input is logic 1, the output Y is... UP The output is logic 2; when the input is logic 2, the output is Y. UP The output is logic 0; The threshold voltage of the first NMOS transistor T1 and the second NMOS transistor T2 is 1.5V, the voltage V DD is 2V, corresponding to logic 2; V DD / 2 is 1V, corresponding to logic 1; GND is 0V, corresponding to logic 0; When the input X is GND, i.e. the input is logic 0, the first NMOS transistor T1 is turned on, the second NMOS transistor T2 is turned off, the current flows from the negative pole to the positive pole of the first and second memristors M1 and M2, and the resistance of both will increase to R OFF , the output Y UP is divided by the first and second memristors M1 and M2, i.e. V DD / 2, and the output is logic 1; When input X is connected to V DD / 2, that is, the input is logic 1, the first NMOS transistor T1 and the second NMOS transistor T2 are both turned off, the output end Y UP is connected to V DD , and the output is logic 2; When input X is connected to V DD logic 2, the first NMOS transistor T1 is turned off, the second NMOS transistor T2 is turned on, and the output Y UP connected to GND through the second NMOS transistor T2, and the output is logic 0.

2. A ternary univariate down-spiral logic circuit based on memristors, characterized by: The third, fourth and fifth memristors M3, M4 and M5, the third, fourth and fifth NMOS transistors T3, T4 and T5; The gate of the third NMOS transistor T3, the gate of the fourth NMOS transistor T4 and the negative electrode of the fifth memristor M5 are connected, and serve as an input end X of the ternary single-variable down shift logic circuit; the drain of the third NMOS transistor T3 is connected with the positive electrode of the fourth memristor M4; and the source of the third NMOS transistor T3 is grounded. The positive pole of the third memristor M3, the negative pole of the fourth memristor M4 and the drain of the fifth NMOS transistor T5 are connected, and serve as the output end Y of the ternary single-variable down-spin logic circuit DOWN ; the gate of the fifth NMOS transistor T5 and the drain of the fourth NMOS transistor T4 are connected with the positive pole of the fifth memristor M5; the negative pole of the third memristor M3 is connected with the power supply V DD ; the source of the fourth NMOS transistor T4 is grounded; and the source of the fifth NMOS transistor T5 is grounded; For the ternary univariate down-rotation logic circuit, when the input end is logic 0, the output end Y of the ternary univariate up-rotation logic circuit DOWN is logic 2; when the input end is logic 1, Y DOWN is logic 0; when the input end is logic 2, Y DOWN is logic 1; The threshold voltage of the third NMOS transistor T3 and the fourth NMOS transistor T4 is 1.5V; the threshold voltage of the fifth NMOS transistor T5 is 0.8V, and the voltage V DD is 2V, corresponding to logic 2; V DD / 2 is 1V, corresponding to logic 1; GND is 0V, corresponding to logic 0; When the input end X is connected to GND, that is, the input is logic 0, the third NMOS transistor T3, the fourth NMOS transistor T4 and the fifth NMOS transistor T5 are all turned off, the output end Y is connected to VDD through the first NMOS transistor T1, and the output is logic 1. DOWN The pull-up resistor formed by the third memristor M3 is connected to V DD , and the output is logic 2. When input X is connected to V DD / 2, i.e. input is logic 1, the third NMOS transistor T3 and the fourth NMOS transistor T4 are turned off, the fifth NMOS transistor T5 is turned on, the output Y DOWN is connected to GND through the fifth NMOS transistor T5, and the output is logic 0. When input X is V DD , i.e. input is logic 2, the third NMOS transistor T3 and the fourth NMOS transistor T4 are turned on, and the fifth NMOS transistor T5 is turned off. The current flows from the negative pole to the positive pole of the third memristor M3 and the fourth memristor M4, and the resistance of both will increase to R OFF . The output Y UP is V DD / 2 through the voltage division of the third memristor M3 and the fourth memristor M4, and the output is logic 1.

Images