A data verification method and apparatus for a chip programming system

Abstract

This application relates to the field of data verification technology, specifically to a data verification method and apparatus for a chip programming system. The method includes: for a multi-channel parallel chip programming system, statistically analyzing the clock cycles of each channel within each time window; determining the clock phase offset of each channel; evaluating the deviation between each channel and a second reference channel in the current clock cycle and the deviation of the clock phase offset, obtaining the timing deviation of each channel; and dynamically determining the verification delay time of each channel using the timing deviation and clock cycle, generating the verification trigger time for each channel for data verification. This balances verification accuracy and overall efficiency.

Description

Technical Field

[0001] This application relates to the field of data verification technology, specifically to a data verification method and apparatus for a chip programming system. Background Technology

[0002] Chip programming refers to writing specific software programs, configuration data, or system firmware into the non-volatile memory of a chip using a dedicated programmer. During the writing process, the programmer transfers data bit by bit or block by block to the chip's memory cells according to the chip's timing requirements, and then uses voltage pulses or other methods to solidify the data in the memory. Programmers are typically multi-channel parallel architectures, programming multiple chips simultaneously. The programming timing of each channel may differ, including clock phase offset, write operation delay, and data transmission jitter. These timing differences can affect the accuracy of data verification.

[0003] Existing data verification methods typically employ a fixed-time-window approach, where a preset time window is waited after programming before data from each channel is read and verified. However, this method treats timing differences between channels as identical, causing some channels to begin verification before the data is fully stable, while others experience excessively long waiting times, impacting the accuracy and efficiency of data verification. Summary of the Invention

[0004] To address the aforementioned technical problems, the purpose of this application is to provide a data verification method and apparatus for a chip programming system, the specific technical solution of which is as follows:

[0005] In a first aspect, embodiments of this application provide a data verification method for a chip programming system, the method comprising the following steps:

[0006] For a multi-channel parallel chip programming system, after chip programming starts, the clock cycles of each channel are counted within each time window;

[0007] Based on the stability of the clock cycle of each channel, the first reference channel is selected from all channels; the clock synchronization error between each channel and the first reference channel is quantified, and the clock phase offset of each channel in each time window is determined.

[0008] By analyzing the fluctuations in the clock cycle and clock phase offset of each channel, a second reference channel is selected from all channels. The deviation of each channel from the second reference channel in clock cycle and clock phase offset at the end of programming is evaluated to obtain the timing deviation of each channel.

[0009] By utilizing the timing deviation and clock cycle of each channel, the verification delay time of each channel is dynamically determined, and the verification trigger time of each channel is generated for data verification.

[0010] In one embodiment, the clock cycle of each channel is counted as the time interval from the rising edge of the channel clock to the next rising edge.

[0011] In one embodiment, selecting the first reference channel from all channels includes:

[0012] Within the time window, calculate the dispersion of all clock cycles for each channel and select the channel with the smallest dispersion as the first reference channel.

[0013] In one embodiment, determining the clock phase offset of each channel in each time window includes:

[0014] Calculate the time difference between each channel and the first reference channel at the corresponding time of the rising edge of the clock in the same bit sequence, and the average value of the clock cycles of each channel and the first reference channel in the same bit sequence;

[0015] Determine the ratio of the absolute value of the time difference to its corresponding average value, multiply the ratio by 2π to convert it into a phase angle, and determine the average value of all phase angles obtained within the time window as the clock phase offset.

[0016] In one embodiment, selecting the second reference channel from all channels includes:

[0017] Calculate the average value of all clock cycles counted within the time window for each channel, and denot it as the average clock cycle. When any channel is burned in, calculate the fusion result of the dispersion of the average clock cycle and the dispersion of the clock phase offset for each channel in all historical time windows. The channel corresponding to the minimum value of the fusion result is taken as the second reference channel.

[0018] In one embodiment, obtaining the timing deviation of each channel includes:

[0019] Calculate the difference between the average clock cycle of each channel at the time window when the burning is completed and the current time window of the second reference channel, as well as the difference between the clock phase offsets. Sum these two differences with weights to determine the timing deviation of each channel.

[0020] In one embodiment, the dispersion of the average clock cycle of the current time window of all channels and the dispersion of the clock phase offset of the current time window of all channels are calculated, and the weights of the two differences are determined by the relative magnitudes of the two dispersions.

[0021] In one embodiment, the expression for determining the verification delay time of each channel is:

[0022] In the formula, Let be the verification delay time for the i-th channel. The preset base delay time, Let be the timing deviation of the i-th channel within the time window at which the burning is completed. Let N be the average clock cycle of the i-th channel within the time window at which the programming is completed, and N be the number of channels in the chip programming system.

[0023] In one embodiment, the verification trigger time is the corresponding time after adding the programming completion time of each channel to the verification delay time.

[0024] Secondly, embodiments of this application also provide a data verification device for a chip programming system, including a memory, a processor, and a computer program stored in the memory and running on the processor, wherein the processor executes the computer program to implement the steps of any of the methods described above.

[0025] This application has at least the following beneficial effects:

[0026] This application assesses the degree of timing deviation of each channel relative to the system baseline by calculating the timing deviation of each channel. Traditional methods treat all channels as identical, employing a uniform verification timing. In contrast, this application effectively distinguishes the timing differences between different channels. By dynamically adjusting the verification timing of each channel based on the timing deviation, it achieves differentiated scheduling of verification timing for each channel. Channels with large timing deviations require longer stabilization times, while channels with small timing deviations can begin verification earlier. This effectively avoids efficiency losses caused by fixed waiting times, balancing verification accuracy and overall efficiency. Attached Figure Description

[0027] To more clearly illustrate the technical solutions and advantages in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0028] Figure 1 This is a flowchart illustrating the steps of a data verification method for a chip programming system, provided as an embodiment of this application. Detailed Implementation

[0029] To further illustrate the technical means and effects adopted by this application to achieve the intended purpose of the invention, the following, in conjunction with the accompanying drawings and preferred embodiments, details the specific implementation, structure, features, and effects of a data verification method and apparatus for a chip programming system proposed in this application. In the following description, different "one embodiment" or "another embodiment" do not necessarily refer to the same embodiment. Furthermore, specific features, structures, or characteristics in one or more embodiments can be combined in any suitable form.

[0030] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application pertains.

[0031] The following description, in conjunction with the accompanying drawings, details a specific scheme for a data verification method and apparatus for a chip programming system provided in this application.

[0032] Please see Figure 1 The diagram illustrates a flowchart of a data verification method for a chip programming system according to an embodiment of this application. The method includes the following steps:

[0033] S1 is for multi-channel parallel chip programming systems. After chip programming starts, it counts the clock cycles of each channel within each time window.

[0034] In a multi-channel parallel chip programming system, the timing characteristics (such as clock stability and synchronization) of each channel differ due to factors such as hardware variations and varying loads. Therefore, during the programming process, it is necessary to first collect the timing characteristic data of each channel. Specifically:

[0035] Once chip programming begins, sampling starts according to a time window, shifting by one time window length each time. The sampling time window width is set to the theoretical duration of 100 clock cycles to ensure sufficient sample size for analysis and statistics. In this embodiment, when the main clock frequency is 50MHz, the time window width is set to 2 microseconds.

[0036] For each channel, the clock signal of each channel is synchronously sampled within each time window, and the clock cycle within the sampling time window is counted. A high-speed counter records the time interval from the rising edge to the next rising edge of the clock for each channel as a complete clock cycle. The duration of each complete clock cycle within a single time window is recorded and sequentially formed into a periodic sequence.

[0037] S2, based on the stability of the clock cycle of each channel, select the first reference channel among all channels; quantify the clock synchronization error between each channel and the first reference channel, and determine the clock phase offset of each channel in each time window.

[0038] The arithmetic mean of the periodic sequences for each channel within the time window is calculated to obtain the average clock cycle for each channel. This average value eliminates the influence of instantaneous fluctuations and reflects the actual center operating frequency of the channel clock. Further calculation of the dispersion of the periodic sequences reflects the degree of clock cycle fluctuation. A higher dispersion indicates a more unstable clock, and thus a higher risk of timing errors during data transmission. It should be noted that the dispersion can be calculated using variance, standard deviation, coefficient of variation, etc.; in this embodiment, standard deviation is used for all dispersion calculations.

[0039] To quantify the clock synchronization error between channels, a channel needs to be selected as a reference channel. Usually, the most stable channel is selected as the reference channel, and then the difference in the clock rising edge time between other channels and the reference channel is compared. In this embodiment, the channel with the smallest dispersion of the periodic sequence is selected as the first reference channel.

[0040] For the i-th channel, starting from the beginning of the sampling time window, a global timestamp counter is used to record the first rising edge of the clock for the first reference channel and the first rising edge of the clock for the i-th channel, obtaining the absolute time difference between the two moments. To obtain the fundamental phase difference within one cycle, firstly, the average value of the first clock cycle between the i-th channel and the first reference channel is calculated; then, the absolute value of the time difference between the two moments is divided by the average value of the clock cycles between the i-th channel and the first reference channel, and then multiplied by... Convert to phase angle. Continuously sample within the sampling time window, and calculate the absolute value of the time difference between the rising edges of the clocks of the same bit sequence in turn to obtain the phase angle after each calculation. Calculate the average value of all phase angles obtained within the time window using the vector averaging method, and use this average value as the clock phase offset for each time window.

[0041] It should be understood that a clock signal can be viewed as a periodic oscillation, with one complete cycle corresponding to... Phase angle, the absolute value of the time difference divided by the average clock cycle to obtain the proportion of the time difference to one cycle, multiplied by This is converted into a phase angle. The phase angle reflects the amount of phase lead or lag of the i-th channel relative to the first reference channel, indicating the degree of synchronization of the clocks of each channel. The phase offset of the first reference channel is 0. The larger the clock phase offset, the more out of sync the clocks of that channel and the first reference channel are, and the higher the risk of timing errors in data transmission.

[0042] S3. Select a second reference channel from all channels based on the fluctuation of the clock cycle and clock phase offset of each channel; evaluate the deviation of the clock cycle and clock phase offset of each channel from the second reference channel when the burning is completed, and obtain the timing deviation of each channel.

[0043] First, the average clock period and clock phase offset of all channels within the same time window are normalized using the maximum-minimum normalization method. The normalized average clock period and clock phase offset of each channel within the same time window are then used to form a timing feature vector. This timing feature vector contains an average clock period component and a clock phase offset component, which are used to characterize the timing state of the channel.

[0044] The timing feature vectors of each channel can be used to represent its timing state, but they cannot be directly used to determine how long each channel needs to wait before verification begins. Therefore, it is necessary to obtain the timing deviation from the baseline state based on the timing feature vectors of each channel. The larger the timing deviation, the further the timing features of that channel deviate from the baseline state, and the longer it will take to reach a stable state before verification can begin.

[0045] Therefore, the channel with the most stable timing characteristics is first selected as the baseline state of the programming system. For each channel, calculations are performed separately. Taking the i-th channel as an example, when the i-th channel is programmed, the dispersion of the two components of the timing feature vector of each channel across all historical time windows is fused. The channel with the smallest fusion result is selected as the second reference channel, and the timing feature vector of the second reference channel in the current time window is used as the baseline state vector. A smaller dispersion indicates the smallest overall fluctuation, meaning the most stable timing characteristics, and minimal impact from the environment and load, representing the best timing performance achievable by the programming system. Comparing other channels with the second reference channel reveals their own timing deviation. If the timing feature vector of a channel is closer to the baseline state vector, the timing deviation of that channel is smaller; otherwise, it indicates a larger difference in timing state between that channel and the second reference channel, requiring a longer time to reach stability. It should be noted that fusion combines multiple variables, which can be calculated using methods such as addition, multiplication, or averaging. In this embodiment, addition is used for fusion. In addition, the clock cycle sampling process for each channel starts from the start of the programming process and ends when the programming is completed. If the second reference channel is completed earlier than the programming of the i-th channel, the timing feature vector of the second reference channel in the time window where the programming is completed will be used as the reference state vector.

[0046] Since the effects of clock jitter and phase shift vary at different times, this embodiment considers the impact of different timing characteristics on timing differences. By dynamically calculating weighting coefficients, different components of the timing feature vector are weighted, allowing the timing deviation to more accurately reflect the degree of timing deviation of each channel relative to the baseline state. The timing deviation of each channel is calculated as follows:

[0047]

[0048] in, This represents the timing deviation of the i-th channel within the time window when the burning process is complete. , Let represent the average clock cycle component and the clock phase offset component in the timing feature vector of the i-th channel within the time window when the programming is completed, respectively. , These represent the average clock cycle component and the clock phase offset component in the reference state vector, respectively. , These represent the weighting coefficients for each component. This represents the difference between the average clock cycles of the i-th channel and the second reference channel within the current time window. This represents the difference between the clock phase offset of the i-th channel and the second reference channel within the current time window, where the difference indicates the degree of difference between the two variables. In another embodiment, this can be achieved using... and The absolute value of the difference between them and Calculate the absolute value of the difference between them.

[0049] The weighting coefficient of each component is determined by its dispersion across all channels. Specifically, it uses the dispersion of the average clock cycle and the dispersion of the clock phase offset across all channels within the current time window as its weights. Greater dispersion indicates a more significant difference between the component and different channels, making it more effective in distinguishing timing differences between channels; smaller dispersion indicates that the component tends to be consistent across channels. The weighting coefficients are then normalized. The dispersion of the average clock cycle across all channels within the current time window is divided by the sum of the dispersion of the average clock cycle and the dispersion of the clock phase offset. The dispersion of the clock phase offset for all channels in the current time window is divided by the sum of the dispersion of the average clock cycle and the dispersion of the clock phase offset.

[0050] S4 uses the timing deviation and clock cycle of each channel to dynamically determine the verification delay time of each channel and generate the verification trigger time of each channel for data verification.

[0051] After programming is completed, the verification delay time of each channel is dynamically determined based on the timing deviation of each channel. Channels with large timing deviations require a longer stabilization time before verification can begin, while channels with small timing deviations can shorten the waiting time and begin verification earlier, thereby achieving differentiated scheduling of verification timing for each channel.

[0052] Timing deviation reflects the degree of deviation of the timing characteristics of each channel. Therefore, this embodiment first establishes a mapping relationship between timing deviation and actual delay time. Channels with a timing deviation of 0 use the base delay time, while channels with larger timing deviations require additional delay time. The expression for the verification delay time of each channel is as follows:

[0053] In the formula, Let be the verification delay time for the i-th channel. The preset base delay time is the minimum stabilization time that all channels must wait for, because the reference channel is only the channel with the least fluctuation and may not be completely free of deviation. In this embodiment, the base delay time is set to 10 clock cycles. Let be the timing deviation of the i-th channel within the time window when the burning is completed. The amplification factor is represented by N, which is the number of channels in the chip programming system. Since the number of channels affects timing, the more channels there are, the more difficult it is to coordinate the timing between channels, and the longer the stabilization time is required. The square root is used to avoid the linear increase in delay time when the number of channels increases, which would lead to low efficiency.

[0054] This represents the delay factor. Since the delay time should be proportional to the timing deviation, the square root is used to avoid excessive delay time due to excessive timing deviation. When the timing deviation is smaller, the delay factor increases faster, which can quickly respond to changes in timing deviation. Conversely, when the timing deviation is larger, the delay factor increases slower, which avoids the delay time from increasing too quickly. The average clock cycle of the i-th channel during the time window when the burning is completed (obtained from step S2) is used to correlate the delay time with the channel's own operating frequency. A high-speed channel with a smaller average clock cycle has a faster stable speed and requires a smaller delay, while a high-speed channel requires a larger delay.

[0055] After programming is complete, different channels wait for different delay times before verification. The verification trigger time for the i-th channel is the programming completion time plus the verification delay time. The verification trigger times for each channel are arranged in ascending order to generate a verification timing schedule table. The schedule table contains the verification trigger time and the channel's identifier for each channel. The programming system controller triggers the data verification operation for each channel at the corresponding time according to the schedule table.

[0056] When the verification trigger time for each channel arrives, the controller of the programming system sends a verification command to the corresponding channel to initiate the data verification operation. This operation first reads the raw byte data that has already been programmed from the chip's designated storage address, and simultaneously retrieves theoretical data from the programming file cache. Then, the programming system performs a bit-by-bit comparison byte by byte, and calculates the cyclic redundancy check (CRC) code of the read data and the theoretical value for secondary verification. If the comparison and verification are completely consistent, the channel is deemed to have passed verification, and the success result is recorded. If any inconsistency is found, the channel is deemed to have failed verification, and the channel is marked as abnormal.

[0057] Based on the same inventive concept as the above method, this application embodiment also provides a data verification device for a chip programming system, including a memory, a processor, and a computer program stored in the memory and running on the processor. When the processor executes the computer program, it implements the steps of any one of the above-described data verification methods for a chip programming system.

[0058] It should be noted that the order of the embodiments described above is merely for descriptive purposes and does not represent the superiority or inferiority of the embodiments. Furthermore, specific embodiments of this specification have been described above. Additionally, the processes depicted in the accompanying drawings do not necessarily require a specific or sequential order to achieve the desired results. In some implementations, multitasking and parallel processing are possible or may be advantageous.

[0059] The various embodiments in this specification are described in a progressive manner. The same or similar parts between the various embodiments can be referred to each other. Each embodiment focuses on describing the differences from other embodiments.

[0060] The above description is only a preferred embodiment of this application and is not intended to limit this application. Any modifications, equivalent substitutions, improvements, etc., made within the principles of this application should be included within the protection scope of this application.

Claims

1. A data verification method for a chip programming system, characterized in that, The method includes the following steps: For a multi-channel parallel chip programming system, after chip programming starts, the clock cycles of each channel are counted within each time window; Based on the stability of the clock cycle of each channel, the first reference channel is selected from all channels; the clock synchronization error between each channel and the first reference channel is quantified, and the clock phase offset of each channel in each time window is determined. By analyzing the fluctuations in the clock cycle and clock phase offset of each channel, a second reference channel is selected from all channels. The deviation of each channel from the second reference channel in clock cycle and clock phase offset at the end of programming is evaluated to obtain the timing deviation of each channel. By utilizing the timing deviation and clock cycle of each channel, the verification delay time of each channel is dynamically determined, and the verification trigger time of each channel is generated for data verification. Determining the clock phase offset of each channel in each time window includes: Calculate the time difference between each channel and the first reference channel at the corresponding time of the rising edge of the clock in the same bit sequence, and the average value of the clock cycles of each channel and the first reference channel in the same bit sequence; Determine the ratio of the absolute value of the time difference to its corresponding average value, multiply the ratio by 2π to convert it into a phase angle, and determine the average value of all phase angles obtained within the time window as the clock phase offset; The process of obtaining the timing deviation of each channel includes: Calculate the difference between the average clock cycle of each channel at the time window when the programming is completed and the current time window of the second reference channel, as well as the difference between the clock phase offsets. Sum these two differences with weights to determine the timing deviation of each channel. The verification trigger time is the corresponding time obtained by adding the completion time of each channel's programming to the verification delay time.

2. The data verification method for a chip programming system as described in claim 1, characterized in that, The statistics for each channel's clock cycle are the time interval between the rising edge of each channel's clock and the next rising edge.

3. The data verification method for a chip programming system as described in claim 1, characterized in that, The selection of the first reference channel from all channels includes: Within the time window, calculate the dispersion of all clock cycles for each channel and select the channel with the smallest dispersion as the first reference channel.

4. The data verification method for a chip programming system as described in claim 1, characterized in that, The selection of the second reference channel from all channels includes: Calculate the average value of all clock cycles counted within the time window for each channel, and denot it as the average clock cycle. When any channel is burned in, calculate the fusion result of the dispersion of the average clock cycle and the dispersion of the clock phase offset for each channel in all historical time windows. The channel corresponding to the minimum value of the fusion result is taken as the second reference channel.

5. A data verification method for a chip programming system as described in claim 4, characterized in that, Calculate the dispersion of the average clock cycle of all channels in the current time window, and the dispersion of the clock phase offset of all channels in the current time window. Determine the weight of the two differences by the relative magnitude of these two dispersions.

6. The data verification method for a chip programming system as described in claim 4, characterized in that, The expression for determining the verification delay time of each channel is: In the formula, Let be the verification delay time for the i-th channel. The preset base delay time, Let be the timing deviation of the i-th channel within the time window at which the burning is completed. Let N be the average clock cycle of the i-th channel within the time window at which the programming is completed, and N be the number of channels in the chip programming system.

7. A data verification device for a chip programming system, comprising a memory, a processor, and a computer program stored in the memory and running on the processor, characterized in that, When the processor executes the computer program, it implements the steps of the method as described in any one of claims 1-6.

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