Avalanche transistor and multi-chip series integrated packaging structure and working method thereof

Abstract

The invention belongs to the technical field of power semiconductor device packaging, and particularly discloses an avalanche transistor, a multi-chip series integrated packaging structure thereof and a working method. The integrated packaging structure comprises a chip module formed by n stacked avalanche transistors, an epitaxial layer is arranged above a substrate of a single avalanche transistor, and a base electrode and an emitter electrode are arranged above the epitaxial layer; the collector electrode is located below the substrate, and surface heat dissipation isolation layers are arranged in other areas above the epitaxial layer except a base electrode area and an emitting electrode area; the resistor connecting piece and the voltage-sharing resistor are located on the side faces of the epitaxial layer and the substrate, and one side of the resistor connecting piece is connected with the collector. According to the invention, parasitic inductance and parasitic capacitance can be effectively reduced, and the switching performance of the avalanche transistor is improved.

Description

Technical Field

[0001] This application belongs to the field of power semiconductor device packaging technology, and relates to an avalanche transistor and its multi-chip tandem integrated packaging structure and working method. Background Technology

[0002] High-amplitude, fast-lead-edge pulsed power technology is widely used in plasma generation, ultra-wideband applications, and other fields. Power semiconductor devices, as the core switching elements in pulsed power systems, determine the output performance of the system through their static and dynamic characteristics. The static withstand voltage, on-resistance, and voltage drop rate of power semiconductor devices are key parameters for pulse switching elements.

[0003] With the continuous improvement of the performance of modern electronic devices, power semiconductor devices, especially avalanche bipolar junction transistors (ABJTs), are being used more and more widely. An avalanche transistor is a power semiconductor device that operates in the avalanche breakdown region and can maintain high performance under high-speed switching and high-current operating environments. Due to its excellent current carrying capacity and switching speed, avalanche transistors have significant application prospects in high-power power supplies, radio frequency switches, and ultra-wideband (UWB) pulse power supplies.

[0004] However, with increasing integration and the growing demand for miniaturization and high performance in systems, traditional avalanche transistor packaging technology has gradually revealed the following problems: 1. Parasitic Inductance and Capacitance Issues: Traditional avalanche transistor packages, especially the commonly used SOT-23 package, connect the chip to external circuitry via wire bonding. While wire bonding offers advantages in cost and manufacturing processes, it also results in higher parasitic inductance and capacitance. These parasitic effects significantly impact the switching performance of devices, particularly in high-speed switching applications. The impact of parasitic inductance is especially pronounced in ultra-high-speed pulse power systems, potentially limiting the device's maximum operating frequency and pulse response speed.

[0005] 2. Insufficient Heat Dissipation: Avalanche transistors typically withstand high power loads, so heat dissipation performance directly affects the long-term reliability and operational stability of the device. Traditional SOT-23 packages, due to their small size and limited packaging materials, have poor heat dissipation performance. Especially under high-power and high-speed switching operations, heat accumulation causes the device temperature to rise rapidly, thus affecting the transistor's efficiency and lifespan. The lack of an effective heat dissipation path makes junction temperature management in SOT-23 packages difficult, leading to a high susceptibility to overheating.

[0006] 3. Packaging size and integration limitations. As electronic devices become increasingly space-constrained, traditional single-chip packaging technologies cannot meet the demands of multi-chip integration. To improve power density and reduce overall size, many applications require the integration of multiple power devices into a single package. However, traditional packaging technologies often employ single-chip packaging, which cannot effectively support parallel or series operation of multiple chips. This limits the application of power semiconductor devices in highly integrated systems.

[0007] To address these issues, in recent years, most existing packaging technologies have focused on single-chip packaging or the integration of a small number of chips. For high-power semiconductor systems with multiple chips connected in series or parallel, especially in ultra-wideband pulse systems with strict requirements for size, heat dissipation, and electrical performance, there is still considerable room for improvement. Summary of the Invention

[0008] In view of the shortcomings of the prior art, the purpose of this application is to provide an avalanche transistor and its multi-chip series integrated packaging structure and operating method, which aims to solve the problem that the traditional multi-avalanche transistor packaging connects the chip to the external circuit through wire bonding, resulting in high parasitic inductance and parasitic capacitance, which in turn affects the switching performance of the device and limits the maximum operating frequency and pulse response speed of the device.

[0009] The first aspect of this application relates to an avalanche transistor for generating pulse waveforms through multi-stage series conduction, comprising: a substrate, a collector, an epitaxial layer, a base, an emitter, a voltage equalizing resistor, a resistor connector, and a surface heat dissipation isolation layer; An epitaxial layer is disposed above the substrate, and a base and an emitter are disposed above the epitaxial layer; the collector is located below the substrate, and a surface heat dissipation isolation layer is disposed in all areas above the epitaxial layer except for the base and emitter regions; a resistor connector and a voltage equalizing resistor are located on the side of the epitaxial layer and the substrate, and one side of the resistor connector is connected to the collector.

[0010] In some embodiments, the base and emitter are fabricated as follows: An epitaxial layer is formed on a substrate by an epitaxial growth process. Then, boron and phosphorus doping processes are performed on the epitaxial layer to form the base region and emitter region; Finally, passivation and metal layers are deposited on the surfaces of the base and emitter regions to form the base and emitter.

[0011] In some embodiments, the base and emitter are metal electrode layers disposed on the surface of the epitaxial layer, and the metal electrode layers are single-layer metal or multi-layer metal stacks.

[0012] In some embodiments, the single-layer metal includes aluminum, copper, or an aluminum-silicon-copper alloy; the multi-layer metal stack includes titanium / nickel / silver, titanium / nickel / gold, or titanium / tungsten / copper; the metal electrode layer is formed by sputtering, evaporation plating, or electroplating processes and is patterned by photolithography and etching and / or stripping processes.

[0013] In some embodiments, the collector is a metallized electrode on the back surface of the substrate. After the back surface of the substrate is thinned, an adhesion layer, a barrier layer, and a weldable layer are formed; among them, the adhesion layer includes titanium or titanium-tungsten, the barrier layer includes nickel, and the weldable layer includes silver, gold, or a tin-based metal layer.

[0014] In some embodiments, the resistance connection member is a metal clip or a metal interconnect piece with a wide-face interconnection; the material of the resistance connection member includes copper, copper alloy, molybdenum, or a copper-molybdenum composite material, and its surface is provided with a nickel / gold, nickel / silver, or nickel / tin plating layer; The resistance connection member is obtained by stamping, etching, and / or electroplating forming, and is electrically connected to the collector and the end electrode of the voltage-sharing resistor respectively through reflow welding, brazing, silver sintering, and / or conductive adhesive processes.

[0015] In a second aspect, the present application provides a multi-chip series integrated packaging structure based on an avalanche transistor, including a chip module composed of n stacked avalanche transistors as described above, a collector terminal, an emitter terminal, a base terminal, emitter bonding wires, and base bonding wires; The base and emitter of the kth avalanche transistor are connected to the collector of the (k + 1)th avalanche transistor; except for the first avalanche transistor, the resistance connection member of the remaining kth avalanche transistor is connected to the voltage-sharing resistor of the (k - 1)th avalanche transistor; the other end of the voltage-sharing resistor of the nth avalanche transistor is provided with an (n + 1)th resistance connection member, and the other end of the (n + 1)th resistance connection member is connected to the emitter of the nth avalanche transistor; the collector of the first avalanche transistor serves as the collector of the chip module and is welded to the collector terminal at the bottom; the emitter of the nth avalanche transistor serves as the emitter of the chip module and is connected to the emitter terminal through an emitter bonding wire; the base of the nth avalanche transistor serves as the base of the chip module and is connected to the base terminal through a base bonding wire; the surface heat dissipation isolation layer is used to avoid contact between the collector of the (k + 1)th avalanche transistor and other regions of the kth avalanche transistor except the base and emitter regions when the kth avalanche transistor and the (k + 1)th avalanche transistor are connected in series, and at the same time provide a heat dissipation path; where 1 < k < n and k is an integer; A bias voltage V is applied between the collector and the emitter of the chip module; the voltage-sharing resistor is used for voltage division control so that each avalanche transistor bears a voltage of V / n; a trigger pulse is applied between the base and the emitter of the chip module to make the chip module conduct in series to generate a pulse waveform.

[0016] In some implementations, the multi-chip tandem integrated packaging structure also includes an epoxy molding compound to encapsulate the chip module, some collector terminals, some emitter terminals, some base terminals, emitter bonding wires, and base bonding wires, preventing moisture and impurities from entering its interior.

[0017] Thirdly, this application provides a working method for a multi-chip tandem integrated packaging structure based on avalanche transistors, specifically as follows: A bias voltage V is set between the collector and emitter terminals of the chip module, which is controlled by the voltage division of the voltage equalization resistor. Each avalanche transistor bears a bias voltage of V / n between its collector and emitter. A trigger pulse is then applied between the base terminal and the emitter terminal to trigger the nth avalanche transistor to turn on. The voltage between the collector and emitter of the avalanche transistor decreases, which in turn causes the first to the (n-1)th avalanche transistors to turn on due to overvoltage. The pulse current flows through the emitter and collector of all avalanche transistors, generating a pulse waveform.

[0018] Overall, the technical solutions conceived in this application have the following beneficial effects compared with the prior art: This application provides a multi-chip cascaded integrated package structure based on avalanche transistors. By integrating multiple avalanche transistor chips in series within the same package, the resistor connectors adopt an improved low-inductance path design such as wide-area interconnect metal clips. Compared with the traditional series structure of multiple SOT-23 wire-bonded packages, this significantly shortens the current loop between chips and expands the conductive cross-sectional area, thereby effectively reducing parasitic inductance and parasitic capacitance and improving the switching performance of avalanche transistors.

[0019] This application provides a multi-chip tandem integrated packaging structure based on avalanche transistors. It adopts a multi-chip common base plate and multi-layer heat conduction path design, such as a multi-chip common heat dissipation substrate and lateral heat dissipation path, to build a more efficient three-dimensional heat dissipation channel than the traditional SOT-23 package. This can significantly reduce junction temperature, reduce temperature gradient and improve the long-term reliability of the device.

[0020] This application provides a multi-chip cascaded integrated package structure based on avalanche transistors. By integrating multiple avalanche transistors in a chip-level series manner into a single package structure, the additional PCB traces and independent package devices required by traditional external series connection are eliminated, thereby achieving high integration, reducing system size, and improving the system's anti-parasitic effect capability. The overall package structure is more compact than the traditional multiple independent SOT-23 package solution, and is more suitable for high-speed pulse system applications such as ultra-wideband technology that are sensitive to device size.

[0021] The biggest difference between the multi-chip cascaded integrated package structure provided in this application and a single avalanche transistor is that a single avalanche transistor has a limited withstand voltage, such as 300V, and generates pulses below 300V. The multi-chip cascaded integrated package structure can increase the withstand voltage; for example, stacking 5 chips can reach 1500V, and the generated pulses can exceed 1000V. The difference lies in the fact that traditional 5-chip individual packaging results in higher parasitic inductance / capacitance, leading to poorer pulse waveform quality. The improved 5-chip cascaded integrated module generates pulse waveform quality with better peak voltage (higher peak voltage, faster rise time, and narrower pulse width). Attached Figure Description

[0022] Figure 1 This application provides a three-dimensional structure of a single avalanche transistor chip in a multi-chip tandem integrated packaging structure based on avalanche transistors.

[0023] Figure 2 This is a three-dimensional structure of n avalanche transistor chips stacked in series in the multi-chip series integrated packaging structure based on avalanche transistors provided in this application embodiment. In this embodiment, n is 5.

[0024] Figure 3 This application provides a multi-chip cascaded integrated packaging structure based on avalanche transistors. In this embodiment, a three-dimensional structure of five chips stacked in series and packaged is shown.

[0025] Figure 4 The comparison results are as follows: the pulse waveform generated by connecting five independently packaged avalanche transistors in series according to the embodiments of this application, and the pulse waveform generated by the multi-chip series integrated package structure based on avalanche transistors in this application.

[0026] In all the accompanying drawings, the same reference numerals are used to denote the same elements or structures, wherein: Figure 1 In the diagram: 1 is the chip base; 2 is the chip emitter; 3 is the chip collector; 4 is the chip substrate; 5 is the chip epitaxial layer; 6 is the first resistor connector D1; 7 is the voltage equalizing resistor R; 8 is the second resistor connector D2 for the second chip; 9 is the surface heat dissipation isolation layer B. Figure 2 In the diagram: 10 is the first avalanche transistor chip; 11 is the nth avalanche transistor chip; 12 is the surface resistive connector Dn2 of the nth chip, where n is 5 in this embodiment; Figure 3 In the diagram: 13 is the base bonding line; 14 is the emitter bonding line; 15 is the collector terminal; 16 is the base terminal; 17 is the emitter terminal; 18 is the epoxy encapsulation material. Detailed Implementation

[0027] To make the objectives, technical solutions, and advantages of this application clearer, the following detailed description is provided in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the scope of this application.

[0028] In this application, the term "and / or" describes the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent three cases: A existing alone, A and B existing simultaneously, and B existing alone. In this application, the symbol " / " indicates that the related objects are in an "or" relationship, for example, A / B means A or B.

[0029] In this application, the terms “first” and “second” are used to distinguish different objects, rather than to describe a specific order of objects.

[0030] In this application, the term "electrical connection" can refer to a direct circuit connection or a signal transmission via a communication protocol.

[0031] In the embodiments of this application, the terms "exemplary" or "for example" are used to indicate that something is an example, illustration, or description. Any embodiment or design that is described as "exemplary" or "for example" in the embodiments of this application should not be construed as being more preferred or advantageous than other embodiments or design. Specifically, the use of the terms "exemplary" or "for example" is intended to present the relevant concepts in a specific manner.

[0032] In the description of the embodiments of this application, unless otherwise stated, "multiple" means two or more. The embodiments of this application are described below with reference to the accompanying drawings.

[0033] This application provides a multi-chip cascaded integrated package structure based on avalanche transistors, consisting of multiple avalanche transistor chips 1 to n stacked together, and multiple voltage-equalizing resistors. ~ The chips are integrated in series to form a chip module. The base and emitter of a single chip are located on the chip surface, and the collector is located on the bottom of the chip. The base and emitter of the first chip are connected to the collector of the second chip, and so on. The collector of the first chip serves as the collector of the chip module, and its bottom is directly soldered to the collector terminal. The emitter of the nth chip serves as the emitter of the chip module and is connected to the emitter terminal via a bonding wire. The base of the nth chip serves as the base of the chip module and is connected to the base terminal via a bonding wire. The entire chip module and the three electrode terminals are encapsulated with encapsulation material to protect the chip module and prevent external moisture and impurities from entering the encapsulation. Only the soldered parts of the three electrode terminals are exposed by the epoxy encapsulation material. A surface heat dissipation isolation layer is laid between two chips, except at the electrode connection points. ~ Single chip iWith a single voltage equalizing resistor Parallel connection; except for the first chip, the second chip to the nth chip, resistor connections are set. Responsible for the first i Collector and equalizing resistor of the chip The connection, and the equalizing resistor The connection; the first resistor connector of the first chip. Connect the collector of the first chip and the first equalizing resistor The nth resistor connector of the nth chip The voltage equalization resistor connected to the nth chip and emitter; When this integrated package structure is in operation, a bias voltage V is first set between the collector and emitter of the chip module, controlled by the voltage division of the voltage equalizing resistors, and the voltage across each chip is V / n; a trigger pulse is provided between the base and emitter of the chip module, with a pulse amplitude of When the nth chip is turned on by the base, the voltage drops, causing the first to (n-1)th chips to be turned on by overvoltage. Current flows through the emitter and collector, and also through the emitter and collector of the first to nth chips.

[0034] In some embodiments, the base and emitter are metal electrode layers disposed on the surface of the epitaxial layer, and the metal electrode layers are single-layer metal or multi-layer metal stacks.

[0035] In some embodiments, the single-layer metal includes aluminum, copper, or an aluminum-silicon-copper alloy; the multilayer metal stack includes titanium / nickel / silver, titanium / nickel / gold, or titanium / tungsten / copper; the metal electrode layer is formed by sputtering, vapor deposition, or electroplating processes and patterned by photolithography and etching and / or stripping processes.

[0036] In some embodiments, the collector is a metallized electrode on the back side of the substrate, and the back side of the substrate is thinned to form an adhesion layer, a barrier layer and a solderable layer; wherein the adhesion layer includes titanium or titanium-tungsten, the barrier layer includes nickel, and the solderable layer includes a silver, gold or tin-based metal layer.

[0037] In some embodiments, the resistor connector is a wide-area interconnected metal clip or metal interconnect sheet; the material of the resistor connector includes copper, copper alloy, molybdenum or copper-molybdenum composite material, and its surface is provided with a nickel / gold, nickel / silver or nickel / tin plating. The resistor connector is obtained by stamping, etching and / or electroplating, and is electrically connected to the collector and the terminal electrodes of the equalizing resistor by reflow soldering, brazing, silver sintering and / or conductive adhesive processes, respectively.

[0038] Example like Figure 1As shown, a single avalanche transistor chip is prepared by performing an epitaxial growth process to form a chip epitaxial layer 5 on a chip substrate 4. Then, a boron and phosphorus doping process is performed to form a base region and an emitter region. After that, a passivation layer and a metal layer are deposited on the chip surface, thereby forming the base 1 and emitter 2 of the chip on the chip surface. The base 1 and emitter 2 of a single chip are located on the chip surface, and the collector 3 is located at the bottom of the chip. like Figure 1 As shown, depositing a surface heat dissipation isolation layer 9 on the chip surface is to ensure that the collector of the second chip is connected to the base and emitter of the first chip during series connection, while avoiding accidental contact between the collector of the second chip and the rest of the first chip, and can also provide a good heat dissipation path when the series is turned on. like Figure 1 As shown, a first resistor connector 6 is led out from the collector of the chip, and the first resistor connector 6 is soldered to one side of the first voltage equalizing resistor 7. The other side of the voltage equalizing resistor 7 is connected to the second resistor connector 8 of the second chip; as shown... Figure 1 As shown, the chip is located near the voltage equalization resistor; It consists of multiple avalanche transistor chips stacked together (1 to n), and multiple voltage-equalizing resistors. ~ Serial integration, single chip i With a single voltage equalizing resistor in parallel; Multi-chip cascaded integrated structure such as Figure 2 As shown; the base and emitter of the first chip are connected to the collector of the second chip, and so on. The first avalanche transistor chip 10 is located at the bottom of the chip module, and the nth avalanche transistor chip 11 is located at the top. In this embodiment, n is 5; a surface heat dissipation isolation layer 9 is laid between the two avalanche transistor chips except at the electrode connection point; resistor connectors In addition to the first chip, the second to n chips are equipped with resistor connectors. Responsible for the first i Chip and equalizing resistor The connection, and the equalizing resistor The connection, the resistor connector of the first chip. Connect the collector of the first chip to the first equalizing resistor; Surface resistance connector of the nth chip 12, located at the nth chip, the resistor connector of the nth chip. The voltage equalization resistor connected to the nth chip And the emitter, in this embodiment n is 5; In this embodiment, five chips are stacked in series, and the packaged three-dimensional structure is as follows: Figure 3As shown; this application provides a multi-chip cascaded integrated packaging structure based on avalanche transistors. The collector of the first chip serves as the collector of the chip module, and its bottom is directly soldered to the collector terminal 15 of the chip module; the emitter of the nth chip serves as the emitter of the chip module, and is connected to the emitter terminal 8 of the chip module through emitter bonding wire 14; the base of the nth chip serves as the base of the chip module, and is connected to the base terminal 16 of the chip module through base bonding wire 13.

[0039] like Figure 3 As shown, this application provides a multi-chip tandem integrated packaging structure based on avalanche transistors. The entire chip module and three electrode terminals are wrapped with epoxy molding compound 18 to protect the chip module and prevent external moisture and impurities from entering the package. Only three electrode terminals are exposed by the epoxy molding compound, which are the welded parts of collector terminal 15, base terminal 16 and emitter terminal 17. like Figure 3 As shown, when a multi-chip cascaded integrated package structure based on avalanche transistors is working, a bias voltage V is first set between the collector terminal 15 and the emitter terminal 17 of the chip module, and then subjected to an equalizing resistor. ~ The voltage is divided and controlled, with each chip bearing a voltage of V / n; then a trigger pulse is provided between the base terminal 16 and the emitter terminal 17 of the chip module, with a pulse amplitude of... The nth chip is turned on by base trigger, and the voltage between the collector and emitter of the nth chip decreases, causing the first chip to (n-1)th chip to be turned on by overvoltage. The chip module current flows through the emitter terminal 17 and the collector terminal 15, and also through the emitter and collector of the first chip to the nth chip; in this embodiment, n is 5. like Figure 4 As shown, this application provides a pulse waveform generated by the series conduction of 5 chips in a multi-chip integrated package structure based on avalanche transistors when it is working, and compares it with the pulse waveform generated by the series conduction of 5 individually packaged avalanche transistor devices in a traditional manner. The pulse waveform generated by the improved multi-chip integrated package structure based on avalanche transistors has a faster pulse rise edge, a narrower pulse width, and a higher pulse peak value. This is because the improved integrated package structure has lower parasitic inductance and parasitic capacitance, which has less impact on nanosecond or even sub-nanosecond pulse waveforms, thus obtaining pulses with better output characteristics.

[0040] This application provides a multi-chip tandem integrated package structure based on avalanche transistors. By innovatively designing the traditional SOT-23 package based on avalanche transistors, a novel multi-chip tandem integrated package structure is proposed, which adopts optimized electrical interconnection and efficient thermal management design. This design can not only effectively reduce parasitic inductance and parasitic capacitance, but also improve heat dissipation performance. Furthermore, the compact structure further reduces the package size, meeting the requirements of modern high-power, ultra-high-speed pulse systems for integration and heat dissipation performance.

[0041] It should be understood that expressions such as “comprising” and “may include” used in this application indicate the existence of the disclosed functions, operations, or constituent elements, and do not limit one or more additional functions, operations, and constituent elements. In this application, terms such as “comprising” and / or “having” are to be interpreted as indicating a particular characteristic, number, operation, constituent element, component, or combination thereof, but not to exclude the existence or possibility of adding one or more other characteristics, numbers, operations, constituent elements, components, or combinations thereof.

[0042] Furthermore, in this application, the expression "and / or" includes any and all combinations of the associated listed words. For example, the expression "A and / or B" may include A, may include B, or may include both A and B.

[0043] In the description of the embodiments of this application, it should be noted that, unless otherwise explicitly specified and limited, the term "connection" should be interpreted broadly. For example, "connection" can be a detachable connection or a non-detachable connection; it can be a direct connection or an indirect connection through an intermediate medium.

[0044] Furthermore, the mathematical concepts mentioned in the embodiments of this application, such as symmetry, equality, parallelism, and perpendicularity, are limitations specific to the current technological level, rather than absolute and strict mathematical definitions. Slight deviations are permissible; approximations of symmetry, equality, parallelism, and perpendicularity are all acceptable. For example, "A and B are parallel" means that A and B are parallel or approximately parallel, and the angle between A and B can be between 0 and 10 degrees. "A and B are perpendicular" means that A and B are perpendicular or approximately perpendicular, and the angle between A and B can be between 80 and 100 degrees.

[0045] The above description is merely a specific embodiment of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

Claims

1. An avalanche transistor, characterized in that, For generating a pulse waveform through multi-stage series conduction, it includes: a substrate, a collector, an epitaxial layer, a base, an emitter, a voltage-sharing resistor, a resistor connecting piece, and a surface heat dissipation isolation layer; An epitaxial layer is provided above the substrate, a base and an emitter are provided above the epitaxial layer, and a surface heat dissipation isolation layer is provided in other areas above the epitaxial layer except for the base and emitter regions; the collector is located below the substrate; the resistor connecting piece and the voltage-sharing resistor are located on the side of the epitaxial layer and the substrate, one side of the resistor connecting piece is connected to the collector, and the other side is connected to the voltage-sharing resistor.

2. The avalanche transistor according to claim 1, characterized in that, The preparation methods for the base and the emitter are as follows: An epitaxial growth process is carried out on the substrate to form an epitaxial layer; Then, a doping process of boron and phosphorus is carried out on the epitaxial layer to form a base region and an emitter region; Finally, a passivation layer and a metal layer are deposited on the surfaces of the base region and the emitter region to form the base and the emitter.

3. The avalanche transistor according to claim 1, characterized in that, The base and the emitter are metal electrode layers provided on the surface of the epitaxial layer, and the metal electrode layer is a single-layer metal or a multi-layer metal stack.

4. The avalanche transistor according to claim 3, characterized in that, The single-layer metal includes aluminum, copper or aluminum-silicon-copper alloy; the multi-layer metal stack includes titanium / nickel / silver, titanium / nickel / gold or titanium / tungsten / copper; the metal electrode layer is formed by sputtering, evaporation plating or electroplating process, and is patterned by photolithography, etching and / or stripping process.

5. The avalanche transistor according to claim 1, characterized in that, The collector is a metallized electrode on the back of the substrate, and an adhesion layer, a barrier layer and a weldable layer are formed after the back of the substrate is thinned; among them, the adhesion layer includes titanium or titanium-tungsten, the barrier layer includes nickel, and the weldable layer includes silver, gold or a tin-based metal layer.

6. The avalanche transistor according to claim 1, characterized in that, The resistor connecting piece is a wide-surface interconnected metal clip or metal interconnection piece; the material of the resistor connecting piece includes copper, copper alloy, molybdenum or copper-molybdenum composite material, and its surface is provided with a nickel / gold, nickel / silver or nickel / tin plating; The resistor connecting piece is obtained by stamping, etching and / or electroplating forming, and is electrically connected to the end electrodes of the collector and the voltage-sharing resistor respectively through reflow welding, brazing, silver sintering and / or conductive adhesive process.

7. A multi-chip tandem integrated packaging structure based on the avalanche transistor of claim 1, characterized in that, It includes a chip module composed of n stacked avalanche transistors as described in claim 1, a collector terminal, an emitter terminal, a base terminal, an emitter bonding wire and a base bonding wire; The base and the emitter of the kth avalanche transistor are connected to the collector of the (k + 1)th avalanche transistor; except for the first avalanche transistor, the resistor connecting piece of the remaining kth avalanche transistor is connected to the voltage-sharing resistor of the (k - 1)th avalanche transistor; the other end of the voltage-sharing resistor of the nth avalanche transistor is provided with an (n + 1)th resistor connecting piece, and the other end of the (n + 1)th resistor connecting piece is connected to the emitter of the nth avalanche transistor; the collector of the first avalanche transistor serves as the collector of the chip module and is welded to the collector terminal at the bottom; the emitter of the nth avalanche transistor serves as the emitter of the chip module and is connected to the emitter terminal through an emitter bonding wire; the base of the nth avalanche transistor serves as the base of the chip module and is connected to the base terminal through a base bonding wire; the surface heat dissipation isolation layer is used to avoid the contact between the collector of the (k + 1)th avalanche transistor and other regions of the kth avalanche transistor except the base and emitter regions when the kth avalanche transistor and the (k + 1)th avalanche transistor are connected in series, and at the same time provide a heat dissipation path; where 1 < k < n and k is an integer; A bias voltage V is applied between the collector and emitter of the chip module; the voltage equalizing resistor is used for voltage division control, so that each avalanche transistor withstands a voltage of V / n; a trigger pulse is applied between the base and emitter of the chip module to make the chip module conduct in series and generate a pulse waveform.

8. The multi-chip tandem integrated packaging structure according to claim 7, characterized in that, It also includes epoxy molding compound, which is used to wrap the chip module, some collector terminals, some emitter terminals, some base terminals, emitter bonding wires and base bonding wires to prevent moisture and impurities from entering its interior.

9. A method for operating a multi-chip tandem integrated packaging structure based on claim 7, characterized in that, Specifically: A bias voltage V is set between the collector and emitter terminals of the chip module, which is controlled by the voltage division of the voltage equalization resistor. Each avalanche transistor bears a bias voltage of V / n between its collector and emitter. Then, a trigger pulse current is applied between the base terminal and the emitter terminal to trigger the nth avalanche transistor to turn on. The voltage between the collector and emitter of the avalanche transistor decreases, which in turn causes the first to the (n-1)th avalanche transistors to turn on due to overvoltage. The pulse current flows through the emitter and collector of all avalanche transistors, generating a pulse waveform.

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