Shield gate transistor and preparation method thereof, chip and electronic equipment

Abstract

The invention provides a shield gate transistor and a preparation method thereof, a chip and electronic equipment, and relates to the technical field of semiconductors, and the shield gate transistor comprises a substrate and an epitaxial layer located at the first side of the substrate; a first conductive type body region; the first conductive type body region is formed in the epitaxial layer from one side, deviating from the substrate, of the epitaxial layer; a second conductive type heavily doped region and a trench gate structure; the second conductive type heavily doped region is formed in the first conductive type body region from one side, deviating from the substrate, of the first conductive type body region; the trench gate structure is at least formed in the first conductive type body region from one side, deviating from the substrate, of the first conductive type body region; wherein the doping concentration in the second conductive type heavily doped region and / or the junction depth of the PN junction in the second conductive type heavily doped region are / is changed in a gradient manner along the extension direction of the trench gate structure. According to the technical scheme, the starting risk of the parasitic triode is low, and the saturation current density of the device is reduced.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, and in particular to a shielded gate transistor and its fabrication method, chip, and electronic device. Background Technology

[0002] A shielded gate MOSFET (SGT MOSFET) adds an additional shielding gate within the trench of a traditional trench MOSFET. This shielding gate is typically connected to the source and serves to shield charges and modulate the electric field.

[0003] In existing conventional shielded gate transistors, the doping concentration and spatial distribution of ions in the active region are uniformly distributed throughout the entire region. This makes it easy to form a uniform PN junction at the interface between the active region and the bulk region. Consequently, the turn-on threshold of the parasitic bipolar transistor in the device is low, and the risk of parasitic conduction is significantly increased. At the same time, the uniformly doped active region will cause the device to have an excessively high saturation current density. Under extreme operating conditions, local current concentration is likely to occur, which will compress the safe operating area (SOA) of the device. Ultimately, this will easily lead to heat accumulation effect, causing thermal failure of the device, thereby affecting the chip's operational reliability and long-term stability. Summary of the Invention

[0004] This application provides a shielded gate transistor and its fabrication method, chip and electronic device, which provides a technical solution with low risk of parasitic transistor turn-on and reduced device saturation current density.

[0005] In a first aspect, embodiments of this application provide a shielded gate transistor, the shielded gate transistor comprising: Substrate, epitaxial layer located on the first side of the substrate; A first conductivity type body region; the first conductivity type body region is formed in the epitaxial layer from the side of the epitaxial layer away from the substrate; A second conductivity type heavily doped region and a trench gate structure; the second conductivity type heavily doped region and the trench gate structure are formed in the first conductivity type body region from the side of the first conductivity type body region away from the substrate; Wherein, along the extension direction perpendicular to the trench gate structure, the second conductivity type heavily doped region is located on one side of the trench gate structure; along the extension direction of the trench gate structure, the doping concentration in the second conductivity type heavily doped region varies with a gradient, and / or, along the extension direction of the trench gate structure, the PN junction depth in the second conductivity type heavily doped region varies with a gradient.

[0006] In one alternative embodiment, the doping concentration in the heavily doped region of the second conductivity type gradually increases along the extension direction of the trench gate structure, and / or the junction depth of the PN junction in the heavily doped region of the second conductivity type gradually increases along the extension direction of the trench gate structure. Alternatively, along the extension direction of the trench gate structure, the doping concentration in the heavily doped region of the second conductivity type gradually decreases, and / or, along the extension direction of the trench gate structure, the junction depth of the PN junction in the heavily doped region of the second conductivity type gradually decreases; Alternatively, along the extension direction of the trench gate structure, the doping concentration in the heavily doped region of the second conductivity type first gradually decreases and then gradually increases, and / or, along the extension direction of the trench gate structure, the junction depth of the PN junction in the heavily doped region of the second conductivity type first gradually decreases and then gradually increases; Alternatively, along the extension direction of the trench gate structure, the doping concentration in the heavily doped region of the second conductivity type first gradually increases and then gradually decreases, and / or, along the extension direction of the trench gate structure, the junction depth of the PN junction in the heavily doped region of the second conductivity type first gradually increases and then gradually decreases.

[0007] In one alternative embodiment, the shielded gate transistor further includes: a contact structure, a source, an insulating layer, and a heavily doped region of a first conductivity type; The insulating layer is formed on the epitaxial layer along the side of the epitaxial layer opposite to the substrate; Along the extension direction perpendicular to the trench gate structure, the contact structure is located on one side of the trench gate structure, and along the thickness direction of the epitaxial layer, the contact structure penetrates the insulating layer and the second conductivity type heavily doped region, up to the first conductivity type body region; The source electrode is formed on the contact structure and is electrically connected to the contact structure; The first conductivity type heavily doped region is formed in the first conductivity type body region and covers the bottom of the contact structure.

[0008] In one optional embodiment, the shielded gate transistor further includes a drain located on a second side of the substrate and forming an ohmic contact with the substrate; wherein the first side and the second side of the substrate are two sides disposed opposite to each other along the thickness direction of the substrate.

[0009] Secondly, embodiments of this application provide a method for fabricating a shielded gate transistor, the method comprising: Provide substrate; An epitaxial layer is formed on the first side of the substrate; A first conductivity type body region is formed in the epitaxial layer from the side of the epitaxial layer opposite to the substrate; A second conductivity type heavily doped region is formed in the first conductivity type body region from the side opposite to the substrate, and a trench gate structure is formed in at least the first conductivity type body region. Wherein, along the extension direction perpendicular to the trench gate structure, the second conductivity type heavily doped region is located on one side of the trench gate structure, the doping concentration in the second conductivity type heavily doped region varies with a gradient along the extension direction of the trench gate structure, and / or, along the extension direction of the trench gate structure, the junction depth of the PN junction in the second conductivity type heavily doped region varies with a gradient.

[0010] In one alternative embodiment, forming a first conductivity type body region in the epitaxial layer from the side of the epitaxial layer opposite to the substrate includes: From the side of the epitaxial layer away from the substrate, the epitaxial layer is doped with ions of a first conductivity type to form a first conductivity type body region in the epitaxial layer, and the region in the epitaxial layer that is not doped with the first conductivity type ions forms a drift region.

[0011] In one alternative embodiment, forming a second conductivity type heavily doped region in the first conductivity type body region from the side opposite to the substrate, and forming a trench gate structure in at least the first conductivity type body region includes: From the side of the first conductivity type body region away from the substrate, the first target region of the first conductivity type body region is heavily doped with second conductivity type ions to form the second conductivity type heavily doped region; Along the side of the second conductivity type heavily doped region away from the first conductivity type body region, the second conductivity type heavily doped region is etched in the second target region until the first conductivity type body region is reached to form a gate trench. A gate is formed by filling the gate trench with conductive material, thus obtaining the trench gate structure.

[0012] In one optional embodiment, forming a second conductivity type heavily doped region by second conductivity type ions from the side of the first conductivity type body region facing away from the substrate includes: A target mask is formed on a third target region on the surface of the epitaxial layer from the side of the first conductivity type body region away from the substrate; wherein the target mask includes a plurality of target sub-masks, and the spacing between the plurality of target sub-masks varies in a gradient along the extension direction of the trench gate structure; Based on the target mask, the first conductivity type body region is heavily doped with second conductivity type ions on the side opposite to the substrate from the first conductivity type body region to form the second conductivity type heavily doped region.

[0013] In one optional implementation, the gradient variation in the spacing between the plurality of target sub-masks includes: the spacing between the plurality of target sub-masks gradually increasing, or the spacing between the plurality of target sub-masks gradually decreasing, or the spacing between the plurality of target sub-masks first gradually decreasing and then gradually increasing, or the spacing between the plurality of target sub-masks first gradually increasing and then gradually decreasing.

[0014] In one alternative embodiment, after forming a second conductivity type heavy doping in the first conductivity type body region and forming a trench gate structure at least in the first conductivity type body region, the method further includes: An insulating layer is formed on the surface of the first conductive type body region along the side of the first conductive type body region away from the substrate; Along the side of the insulating layer away from the first conductivity type body region, the fourth target region is etched to form a contact hole that penetrates the insulating layer and the second conductivity type heavily doped region and extends into the first conductivity type body region; wherein, along the extension direction perpendicular to the trench gate structure, the second target region is spaced apart on one side of the trench gate structure. Along the bottom of the contact hole, the first conductivity type body region is heavily doped with first conductivity type ions to form a first conductivity type heavily doped region covering the bottom of the contact hole in the first conductivity type body region; The contact hole is filled with conductive material to form a contact structure; A source electrode is formed on the side of the contact structure opposite to the insulating layer.

[0015] In one alternative embodiment, after forming a second conductivity type heavy doping in the first conductivity type body region and forming a trench gate structure at least in the first conductivity type body region, the method further includes: A drain is formed from the second side of the substrate in a fifth target region on the surface of the substrate, and the drain forms an ohmic contact with the substrate; wherein the first side and the second side of the substrate are two sides disposed opposite to each other along the thickness direction of the substrate.

[0016] Thirdly, embodiments of this application also provide a chip, including a shielded gate transistor as described in any of the first aspects, or a shielded gate transistor prepared by the method for preparing a shielded gate transistor as described in any of the second aspects.

[0017] Fourthly, the application provides an electronic device including the chip described in the fourth aspect.

[0018] With the above technical solution adopted, embodiments of this application provide a shielded gate transistor and its fabrication method, chip, and electronic device. The shielded gate transistor includes: a substrate, an epitaxial layer located on a first side of the substrate; a first conductivity type body region; the first conductivity type body region being formed in the epitaxial layer away from the substrate; a second conductivity type heavily doped region and a trench gate structure; the second conductivity type heavily doped region being formed in the first conductivity type body region away from the substrate; the trench gate structure being formed at least in the first conductivity type body region away from the substrate; wherein, along an extension direction perpendicular to the trench gate structure, the second conductivity type heavily doped region is located on one side of the trench gate structure; along the extension direction of the trench gate structure, the doping concentration in the second conductivity type heavily doped region and / or the junction depth of the PN junction in the second conductivity type heavily doped region exhibits a gradient change.

[0019] Based on the above description, in the embodiments of this application, the doping concentration in the heavily doped region of the second conductivity type and / or the junction depth of the PN junction in the heavily doped region of the second conductivity type exhibit a gradient change along the extension direction of the trench gate structure. In conventional power semiconductor devices, a uniform PN junction is formed between the active region and the body region. Under specific operating conditions, such as when the device is in a high current and high voltage state, this uniform PN junction structure easily satisfies the conditions for the parasitic bipolar transistor to turn on. Once the parasitic bipolar transistor turns on, it will generate an uncontrollable large current, which will seriously affect the normal operation of the device and even lead to device damage.

[0020] In this embodiment, by varying the doping concentration and / or PN junction depth in the heavily doped region of the second conductivity type along the trench gate structure extension direction in a gradient manner, this non-uniform doping distribution completely alters the electric field and charge distribution at the interface between the active and bulk regions. Specifically, the differences in doping concentration and PN junction depth at different locations cause the electric field intensity at the interface to no longer be uniformly distributed, but rather exhibit a non-uniform pattern. Simultaneously, the charge distribution also changes due to the variation in doping concentration, with the originally uniformly distributed charge becoming dispersed and uneven. This change disrupts the conditions for forming a uniform PN junction. Because the uniformity of the PN junction is broken, the electric field and charge conditions required for the parasitic bipolar transistor to turn on become difficult to achieve simultaneously, thus significantly increasing the turn-on threshold of the parasitic bipolar transistor. This means that under the same operating conditions, the transistor requires a higher voltage or current to trigger the parasitic bipolar transistor to turn on, effectively reducing the risk of parasitic conduction and thus greatly enhancing the stability of the device.

[0021] Furthermore, in traditional device structures, due to the uniformity of materials and structure, current tends to become excessively concentrated in localized areas within the transistor. This excessive local current concentration leads to a much higher current density in these areas compared to other areas, generating a large amount of heat and creating a thermal accumulation effect. This thermal accumulation effect not only causes a sharp increase in the local temperature of the transistor, affecting its electrical performance, but may also lead to thermal damage, severely shortening the transistor's lifespan.

[0022] This application's embodiments optimize the internal current distribution of the device by varying the doping concentration and / or PN junction depth in the heavily doped region of the second conductivity type along the extension direction of the trench gate structure. The differences in doping concentration and PN junction depth at different locations cause variations in the current conduction capability of different regions of the device. Specifically, regions with higher doping concentration and deeper PN junction depth have stronger current conduction capability and can carry larger currents; while regions with lower doping concentration and shallower PN junction depth have relatively weaker current conduction capability and can carry smaller currents.

[0023] This non-uniform doping and junction depth distribution automatically adjusts current flow in different regions based on their characteristics. This adjustment avoids excessive local current concentration, allowing for a more uniform current distribution within the device. The uniform current distribution reduces the transistor's saturation current density because the current is no longer concentrated in a few areas but is dispersed throughout the entire transistor. Simultaneously, the uniform current distribution effectively reduces heat accumulation effects, resulting in a more stable overall transistor temperature. This not only expands the transistor's safe operating area, enabling it to operate safely and reliably over a wider voltage and current range, but also significantly improves the chip's operational reliability and long-term stability, extending the transistor's lifespan. Attached Figure Description

[0024] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with the invention and, together with the description, serve to explain the principles of the invention.

[0025] Figure 1(a) is a schematic diagram of a shielded gate transistor provided in an embodiment of the present invention; Figure 1(b) is a schematic diagram of the structure of a shielded gate transistor provided in an embodiment of the present invention. Figure 2 ; Figure 2 A schematic diagram of the steps in a method for fabricating a shielded gate transistor according to an embodiment of the present invention is shown below; Figure 3 A schematic diagram of the steps in a method for fabricating a shielded gate transistor according to an embodiment of the present invention. Figure 2 ; Figure 4A schematic diagram of the steps in a method for fabricating a shielded gate transistor according to an embodiment of the present invention, in a first direction. Figure 3 ; Figure 5(a) is a schematic diagram of the mask structure in a method for fabricating a shielded gate transistor according to an embodiment of the present invention; Figure 5(b) is a schematic diagram of the steps of a method for fabricating a shielded gate transistor according to an embodiment of the present invention in the second direction. Figure 6(a) is a schematic diagram of the mask structure in a method for fabricating a shielded gate transistor according to an embodiment of the present invention. Figure 2 ; Figure 6(b) is a schematic diagram of the steps of a shielded gate transistor fabrication method provided in an embodiment of the present invention in the second direction. Figure 2 ; Figure 7(a) is a schematic diagram of the mask structure in a method for fabricating a shielded gate transistor according to an embodiment of the present invention. Figure 3 ; Figure 7(b) is a schematic diagram of the steps of a shielded gate transistor fabrication method provided in an embodiment of the present invention in the second direction. Figure 3 ; Figure 8(a) is a schematic diagram of the mask structure in a method for fabricating a shielded gate transistor according to an embodiment of the present invention. Figure 4 ; Figure 8(b) is a schematic diagram of the steps of a shielded gate transistor fabrication method provided in an embodiment of the present invention in the second direction. Figure 4 .

[0026] 101-Substrate; 102-Epipolar layer; 201-First conductivity type bulk region; 202-Drift region; 30-Second conductivity type heavily doped region; 40-Trench gate structure; 501-Target submask; 502-Trench gate mask; 503-Contact structure mask; 60-Contact structure; 70-Insulating layer; 80-Source; 90-Drain. Detailed Implementation

[0027] Exemplary embodiments will now be described in detail, examples of which are illustrated in the accompanying drawings. When the following description relates to the drawings, unless otherwise indicated, the same numbers in different drawings denote the same or similar elements. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with the present invention.

[0028] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the scope of this application. It is understood that the terms “first,” “second,” etc., as used herein may be used to describe various information or data, but these elements are not limited by these terms. These terms are only used to distinguish first information from another type of information. For example, without departing from the scope of this application, first action information may be referred to as second action information, and similarly, second action information may be referred to as first action information. Both first action information and second action information are action information, but they are not the same action information.

[0029] In this document, it should be understood that the terminology used is for convenience of understanding only and does not imply any limitation on its meaning. Furthermore, any number of elements in the accompanying drawings is for illustrative purposes only and not for limitation, and any naming is for distinction only and has no limiting meaning.

[0030] A shielded gate MOSFET (SGT MOSFET) adds an additional shielding gate within the trench of a traditional trench MOSFET. This shielding gate is typically connected to the source and serves to shield charges and modulate the electric field.

[0031] In existing conventional shielded gate transistors, the doping concentration and spatial distribution of ions in the active region are uniformly distributed throughout the entire region. This makes it easy to form a uniform PN junction at the interface between the active region and the bulk region. Consequently, the turn-on threshold of the parasitic bipolar transistor in the device is low, and the risk of parasitic conduction is significantly increased. At the same time, the uniformly doped active region will cause the device to have an excessively high saturation current density. Under extreme operating conditions, local current concentration is likely to occur, which will compress the safe operating area (SOA) of the device. Ultimately, this will easily lead to heat accumulation effect, causing thermal failure of the device, thereby affecting the chip's operational reliability and long-term stability.

[0032] Based on this, the inventive concept of this application is to change the electric field and charge distribution at the interface between the active region and the bulk region to disrupt the conditions for the formation of a uniform PN junction, increase the turn-on threshold of the parasitic bipolar transistor, and utilize the non-uniform doping of ions and the variation in junction depth within the active region to regulate the current flow in different regions. Regions with high doping concentration and deep junctions have strong conductivity and carry large current; conversely, regions with low doping concentration and deep junctions have weak conductivity and carry small current. By optimizing the current distribution, the safe operating area of ​​the transistor is expanded, enabling the transistor to operate stably over a wider voltage and current range.

[0033] The technical solutions shown in this application will now be described in detail through specific embodiments. It should be noted that the following embodiments may exist independently or in combination with each other; for identical or similar content, the description will not be repeated in different embodiments.

[0034] Referring to Figures 1(a) and 1(b), a shielded gate transistor according to an embodiment of this application is shown, the shielded gate transistor comprising: Substrate 101, epitaxial layer located on the first side of substrate 101.

[0035] In this embodiment, substrate 101 serves as the support structure for the entire shielded gate transistor, providing a stable physical platform for the growth of subsequent layers. The material of substrate 101 is typically selected based on the performance requirements and application scenarios of the shielded gate transistor. For example, silicon substrate 101 is widely used in common power semiconductor devices and has good semiconductor properties and process compatibility.

[0036] The epitaxial layer is located on the first side of the substrate 101 and is formed on the substrate 101 using epitaxial growth technology. The function of the epitaxial layer is to provide a suitable material layer for the formation of subsequent structures such as the first conductivity type body region 201. Its thickness, doping concentration, and other parameters directly affect the device performance. For example, an appropriate epitaxial layer thickness can optimize the device's breakdown voltage and on-resistance.

[0037] First conductivity type body region 201; the first conductivity type body region 201 is formed in the epitaxial layer from the side of the epitaxial layer away from the substrate 101.

[0038] In this embodiment, a first conductivity type body region 201 is formed in the epitaxial layer from the side of the epitaxial layer away from the substrate 101. The first conductivity type body region 201 is the region in the shielded gate transistor where a PN junction is formed and the device functions. Its conductivity type is opposite to that of the subsequently formed second conductivity type heavily doped region 30. Through interaction with the second conductivity type heavily doped region 30, a PN junction is formed, thereby controlling the current conduction and cutoff of the device. For example, the first conductivity type body region 201 may be a P-type body region, and the second conductivity type heavily doped region 30 may be an N-type second conductivity type heavily doped region 30; a PN junction is formed with the N-type second conductivity type heavily doped region 30.

[0039] The second conductivity type heavily doped region 30 and the trench gate structure 40 are formed in the first conductivity type body region 201 from the side of the first conductivity type body region 201 away from the substrate 101; the trench gate structure 40 is formed in the first conductivity type body region 201 from the side of the first conductivity type body region 201 away from the substrate 101, at least in the first conductivity type body region 201.

[0040] Wherein, along the extension direction perpendicular to the trench gate structure 40, the second conductivity type heavily doped region 30 is located on one side of the trench gate structure 40; along the extension direction of the trench gate structure 40, the doping concentration in the second conductivity type heavily doped region 30 and / or the PN junction depth in the second conductivity type heavily doped region 30 exhibit a gradient change.

[0041] In this embodiment, the heavily doped region 30 of the second conductivity type is used to provide a large number of charge carriers, enhancing the conductivity of the shielded gate transistor. Its doping concentration is higher than that of the body region 201 of the first conductivity type, to ensure that charge carriers can be injected quickly and in large quantities when the device is turned on.

[0042] Along a direction perpendicular to the trench gate structure 40, a heavily doped region 30 of the second conductivity type is located on one side of the trench gate structure 40. This arrangement allows the trench gate structure 40 to effectively control the electric field distribution and current flow between the heavily doped region 30 of the second conductivity type and the body region 201 of the first conductivity type. When a voltage is applied to the trench gate structure 40, a conductive channel can be formed around it, thereby controlling the on and off states of the shielded gate transistor.

[0043] Along the extension direction of the trench gate structure 40, the doping concentration in the heavily doped region 30 of the second conductivity type and / or the PN junction depth in the heavily doped region 30 of the second conductivity type exhibit a gradient change. This gradient change can be achieved by controlling the ion implantation process, while the gradient change in the PN junction depth can be achieved by adjusting parameters such as implantation energy and annealing process.

[0044] In this embodiment, the trench gate structure 40 is formed at least in the first conductivity type body region 201, away from the substrate 101. The trench gate structure 40 is the control portion of the shielded gate transistor; it controls the device's conduction and cutoff using an electric field effect by forming a gate electrode within the trench. Compared to conventional planar gate structures, the trench gate structure 40 can more effectively utilize chip area, improve device integration, and better control the electric field distribution, thereby increasing the device's breakdown voltage and reducing on-resistance.

[0045] Based on the above description, in this embodiment, along the extension direction of the trench gate structure 40, the doping concentration in the heavily doped region 30 of the second conductivity type and / or the junction depth of the PN junction in the heavily doped region 30 of the second conductivity type exhibit a gradient change. In conventional power semiconductor devices, a uniform PN junction is formed between the active region and the body region. Under specific operating conditions, such as when the power semiconductor device is in a high current and high voltage state, this uniform PN junction structure easily satisfies the conditions for the parasitic bipolar transistor to turn on. Once the parasitic bipolar transistor turns on, it will generate an uncontrollable large current, which will seriously affect the normal operation of the device and may even lead to damage to the power semiconductor device.

[0046] In this embodiment, by varying the doping concentration and / or PN junction depth in the heavily doped region 30 of the second conductivity type along the extension direction of the trench gate structure 40 in a gradient manner, this non-uniform doping distribution completely alters the electric field and charge distribution at the interface between the active and bulk regions. Specifically, the differences in doping concentration and PN junction depth at different locations cause the electric field intensity at the interface to no longer be uniformly distributed, but rather exhibit a non-uniform pattern. Simultaneously, the charge distribution also changes due to the variation in doping concentration, with the originally uniformly distributed charge becoming dispersed and uneven. This change disrupts the conditions for forming a uniform PN junction. Because the uniformity of the PN junction is broken, the electric field and charge conditions required for the parasitic bipolar transistor to turn on become difficult to achieve simultaneously, thus significantly increasing the turn-on threshold of the parasitic bipolar transistor. This means that under the same operating conditions, the transistor requires a higher voltage or current to trigger the parasitic bipolar transistor to turn on, effectively reducing the risk of parasitic conduction and thus greatly enhancing the stability of the device.

[0047] Furthermore, in traditional device structures, due to the uniformity of materials and structures, current tends to excessively concentrate in localized areas within the transistor. This excessive local current concentration leads to a much higher current density in these areas compared to other areas, generating a significant amount of heat. This not only raises the local temperature of the transistor, affecting its electrical performance, but can also cause thermal damage, severely shortening its lifespan. However, the embodiments of this application optimize the current distribution within the device by varying the doping concentration and / or PN junction depth in the heavily doped region 30 of the second conductivity type along the extension direction of the trench gate structure 40. The differences in doping concentration and PN junction depth at different locations cause variations in the current conduction capability of different regions of the device. Specifically, regions with higher doping concentration and deeper PN junction depth have stronger current conduction capability and can carry larger currents; while regions with lower doping concentration and shallower PN junction depth have relatively weaker current conduction capability and can carry smaller currents.

[0048] This non-uniform doping and junction depth distribution automatically adjusts current flow in different regions based on their characteristics. This adjustment avoids excessive local current concentration, allowing for a more uniform current distribution within the device. The uniform current distribution reduces the transistor's saturation current density because the current is no longer concentrated in a few areas but is dispersed throughout the entire transistor. Simultaneously, the uniform current distribution effectively reduces heat accumulation effects, resulting in a more stable overall transistor temperature. This not only expands the transistor's safe operating area, enabling it to operate safely and reliably over a wider voltage and current range, but also significantly improves the chip's operational reliability and long-term stability, extending the transistor's lifespan.

[0049] The following describes in detail the gradual increase in doping concentration in the heavily doped region 30 of the second conductivity type, and / or the junction depth of the PN junction in the heavily doped region 30 of the second conductivity type: In one example, along the extension direction of the trench gate structure 40, the doping concentration in the second conductivity type heavily doped region 30 gradually increases, and / or the junction depth of the PN junction in the second conductivity type heavily doped region 30 gradually increases.

[0050] In this embodiment, the gradual increase in doping concentration in the second conductivity type heavily doped region 30 along the extension direction of the trench gate structure 40 means that the number of impurity atoms incorporated into the second conductivity type heavily doped region 30 gradually increases from one end to the other in the extension direction of the trench gate structure 40. For example, in an ion implantation process, by controlling the implantation dose, the number of impurity atoms implanted at different positions can show an increasing trend.

[0051] The gradual increase in the PN junction depth in the heavily doped region 30 of the second conductivity type along the extension direction of the trench gate structure 40 means that as the trench gate structure 40 extends further, the depth to which the PN junction formed by the heavily doped region 30 of the second conductivity type and the body region 201 of the first conductivity type extends into the body region 201 of the first conductivity type gradually increases. This can be achieved by adjusting the ion implantation energy; the higher the energy, the deeper the impurity atoms can be implanted, thereby increasing the PN junction depth.

[0052] In this embodiment, the conditions required for the parasitic bipolar transistor to turn on are relatively stringent at the end near the extension direction of the trench gate structure 40, where the doping concentration and junction depth are smaller. This is because the lower doping concentration and shallower junction depth make the electric field and charge distribution in this region unfavorable for the turn-on of the parasitic bipolar transistor. As the doping concentration and junction depth gradually increase, although the turn-on conditions gradually become relatively easier, the overall high turn-on threshold at the starting end increases the turn-on threshold of the parasitic bipolar transistor in the entire shielded gate transistor, reducing the risk of parasitic conduction.

[0053] Furthermore, the doping concentration and junction depth gradually increase in the heavily doped region 30 of the second conductivity type, resulting in a more rational current distribution within the device. In regions with lower doping concentration and junction depth, conductivity is relatively weaker, and current is smaller; while in regions with higher doping concentration and junction depth, conductivity is enhanced, enabling the device to carry larger currents. This differentiated conductivity causes the current to gradually change along the extension direction of the trench gate structure 40, avoiding excessive local current concentration and optimizing the current distribution. This optimized current distribution reduces Joule heating caused by localized high current densities. Especially in regions with lower doping concentration and junction depth, the smaller current generates relatively less heat, which is beneficial for the overall heat dissipation of the device and improves the thermal stability of the shielded gate transistor.

[0054] In another example, along the extension direction of the trench gate structure 40, the doping concentration in the second conductivity type heavily doped region 30 gradually decreases, and / or, the junction depth of the PN junction in the second conductivity type heavily doped region 30 gradually decreases.

[0055] In this embodiment, the doping concentration in the second conductivity type heavily doped region 30 can be gradually reduced along the extension direction of the trench gate structure 40 by gradually reducing the implantation dose in the ion implantation process.

[0056] In this embodiment, as the trench gate structure 40 extends, the depth of the PN junction formed by the second conductivity type heavily doped region 30 and the first conductivity type body region 201 extending into the first conductivity type body region 201 gradually decreases. This can be achieved by reducing the ion implantation energy; lower energy reduces the implantation depth of impurity atoms, thus making the PN junction shallower.

[0057] It should be understood that the conditions required for the parasitic bipolar transistor to turn on are relatively stringent at the end near the extension direction of the trench gate structure 40, where the doping concentration and junction depth are smaller. This is because the lower doping concentration and shallower junction depth make the electric field and charge distribution in this region unfavorable for the turn-on of the parasitic bipolar transistor. As the doping concentration and junction depth gradually increase, although the turn-on conditions gradually become relatively easier, the overall high turn-on threshold at the beginning of the process increases the turn-on threshold of the parasitic bipolar transistor in the entire shielded gate transistor, reducing the risk of parasitic conduction.

[0058] Gradually decreasing doping concentration and junction depth help optimize the electric field distribution inside the shielded gate transistor: the electric field strength is relatively high in regions with higher doping concentration and junction depth, and relatively low in regions with lower doping concentration and junction depth. This avoids excessive local concentration of the electric field, reduces electric field spikes, and improves the breakdown voltage and reliability of the shielded gate transistor.

[0059] In another example, along the extension direction of the trench gate structure 40, the doping concentration in the second conductivity type heavily doped region 30 first gradually decreases and then gradually increases, and / or the junction depth of the PN junction in the second conductivity type heavily doped region 30 first gradually decreases and then gradually increases.

[0060] In this embodiment, the doping concentration in the second conductivity type heavily doped region 30 can be gradually decreased and then gradually increased along the extension direction of the trench gate structure 40 by segmenting the ion implantation dose. Specifically, the implantation dose can be reduced first and then gradually increased.

[0061] Optionally, the PN junction depth in the heavily doped region 30 of the second conductivity type can be gradually reduced and then gradually increased along the extension direction of the trench gate structure 40 by first reducing and then increasing the ion implantation energy.

[0062] In the embodiments of this application, in the portion where the doping concentration and junction depth are reduced, the turn-on threshold of the parasitic bipolar transistor of the shielded gate transistor can be increased, reducing the risk of parasitic conduction, while improving the electric field distribution of the shielded gate transistor and reducing leakage current; in the portion where the doping concentration and junction depth are increased, the current distribution of the shielded gate transistor can be optimized, enhancing heat dissipation performance.

[0063] In another example, along the extension direction of the trench gate structure 40, the doping concentration in the second conductivity type heavily doped region 30 first gradually increases and then gradually decreases, and / or the junction depth of the PN junction in the second conductivity type heavily doped region 30 first gradually increases and then gradually decreases.

[0064] The doping concentration in the second conductivity type heavily doped region 30 can be gradually decreased and then gradually increased along the extension direction of the trench gate structure 40 by segmenting the ion implantation dose. Specifically, the implantation dose can be increased first and then gradually decreased.

[0065] Optionally, the PN junction depth in the heavily doped region 30 of the second conductivity type can be gradually reduced and then gradually increased along the extension direction of the trench gate structure 40 by first increasing and then decreasing the ion implantation energy.

[0066] In the embodiments of this application, the conductivity of the shielded gate transistor is enhanced when the doping concentration and junction depth increase, enabling it to conduct current quickly; while when the doping concentration and junction depth decrease, the conductivity of the shielded gate transistor is relatively weakened, which limits the current to a certain extent.

[0067] It should be understood that in regions where the doping concentration and junction depth increase, the electric field strength of the shielded gate transistor is higher, and the heat generated is also relatively more; while in regions where the doping concentration and junction depth decrease, the electric field strength and heat generated by the shielded gate transistor are relatively less. Based on this, excessive concentration of local electric field and heat can be avoided, thereby improving the reliability and stability of the device.

[0068] In one alternative embodiment, the shielded gate transistor further includes: a contact structure 60, a source 80, an insulating layer 70, and a heavily doped region of a first conductivity type.

[0069] An insulating layer 70 is formed on the epitaxial layer along the side of the epitaxial layer opposite to the substrate 101; a contact structure 60 is located on at least one side of the trench gate structure 40 along the extension direction perpendicular to the trench gate structure 40; the contact structure 60 penetrates the insulating layer 70 and the second conductivity type heavily doped region 30 along the thickness direction of the epitaxial layer, extending to the first conductivity type body region 201; a source electrode 80 is formed on the contact structure 60 and electrically connected to the contact structure 60; the first conductivity type heavily doped region is formed in the first conductivity type body region 201 and covers the bottom of the contact structure 60.

[0070] In this embodiment, an insulating layer 70 is formed on the surface of the epitaxial layer along the side of the epitaxial layer opposite to the substrate 101. This insulating layer 70 isolates the epitaxial layer from other structures that may cause electrical interference, providing a stable electrical environment for the shielded gate transistor. The insulating layer 70 can be made of a material with good insulating properties, such as silicon dioxide. The thickness of the insulating layer 70 is precisely controlled according to the design requirements of the shielded gate transistor to ensure effective isolation without adversely affecting other performance characteristics of the shielded gate transistor.

[0071] Optionally, the contact structure 60 is located on both sides of the trench gate structure 40 and is made of a metallic material, such as aluminum. Its shape and size are optimized according to the design and process requirements of the shielded gate transistor. It is used to establish an electrical connection channel between the source 80 and the first conductivity type body region 201, allowing current to flow smoothly between the source 80 and the first conductivity type body region 201.

[0072] The source 80 is formed on the contact structure 60 and achieves a good electrical connection with the contact structure 60. The source 80 is the port for the transistor current input, and its material can be a metal with good conductivity, such as copper. The shape and size design of the source 80 need to consider the matching with the contact structure 60 and the ease of connection with other circuit components to ensure that the current can be efficiently input into the shielded gate transistor.

[0073] In this embodiment, a heavily doped region of the first conductivity type is formed within the first conductivity type body region 201 and covers the bottom of the contact structure 60. The doping concentration of the heavily doped region of the first conductivity type is higher than that of other parts of the first conductivity type body region 201, which is used to reduce the contact resistance and improve the current transmission efficiency between the contact structure 60 and the first conductivity type body region 201.

[0074] It should be understood that the heavily doped region of the first conductivity type covers the bottom of the contact structure 60. Due to the high concentration of impurity doping in this region, its resistivity is significantly reduced. When current flows from the contact structure 60 into the first conductivity type body region 201, the reduced contact resistance allows the current to flow more smoothly, reducing energy loss in the contact area. Therefore, the current transfer efficiency of the transistor can be improved, allowing a larger current to flow through the transistor at the same input voltage, thereby improving the transistor's power handling capability. Simultaneously, the reduced heat generated by contact resistance contributes to improving the reliability and stability of the transistor.

[0075] Furthermore, in this embodiment, the contact structure 60 penetrates the insulating layer 70, the second conductivity type heavily doped region 30, and reaches the first conductivity type body region 201. This structure works in conjunction with the first conductivity type heavily doped region to adjust the electric field distribution inside the transistor and avoid excessive concentration of the electric field in a localized area.

[0076] The contact structure 60 is located on one side of the trench gate structure 40 and forms a good electrical connection with the heavily doped region of the first conductivity type and the body region 201 of the first conductivity type. This structure allows the current to be distributed more evenly when entering the body region 201 of the first conductivity type. At the same time, the presence of the heavily doped region of the first conductivity type further optimizes the current distribution near the contact area, thereby improving the uniformity of the current distribution inside the transistor and enabling the transistor to exhibit more consistent electrical performance under different operating conditions.

[0077] Optionally, the shielded gate transistor further includes a drain 90, which is located on the second side of the substrate 101 and forms an ohmic contact with the substrate 101; wherein the first side and the second side of the substrate 101 are two sides disposed opposite to each other along the thickness direction of the substrate 101.

[0078] In this embodiment, the drain 90 forms an ohmic contact with the substrate 101. An ohmic contact is an ideal form of electrical contact, characterized by extremely low resistance at the contact point, allowing current to flow freely, and a linear relationship between the voltage drop and current in the contact area. To achieve a good ohmic contact, the drain 90 can be made of a metal material that matches the material of the substrate 101 and has good conductivity. For example, for a silicon substrate 101, commonly used metals include aluminum and gold. The shape and size of the drain 90 are determined according to the overall transistor design and packaging requirements. Generally, a uniform metal thin film is formed on the second side surface of the substrate 101 to cover as large an area as possible, thereby reducing contact resistance.

[0079] When the shielded transistor is operating, current flows in from the source 80, passes through the conductive channel in the epitaxial layer, and finally flows out from the drain 90. The ohmic contact between the drain 90 and the substrate 101 ensures that the current can be efficiently conducted out of the substrate 101, providing the necessary termination connection for the current path of the entire transistor.

[0080] In this embodiment, the drain 90 forms an ohmic contact with the substrate 101. This contact allows electrons to flow freely at the interface between the drain 90 and the substrate 101 without any additional potential barrier. Compared to non-ohmic contacts such as ordinary Schottky contacts, the resistance of an ohmic contact is extremely small, almost negligible. Therefore, when current flows from the substrate 101 to the drain 90, the energy loss in the contact area is greatly reduced due to the lower contact resistance. This improves the current transfer efficiency of the transistor, allowing a larger current to flow through it under the same driving conditions. This can be applied to high-current applications such as power amplification and power conversion. Simultaneously, it reduces the heat generated by contact resistance, contributing to improved transistor reliability and stability, and extending its lifespan.

[0081] Secondly, embodiments of this application provide a method for fabricating a shielded gate transistor, the method comprising the following steps: First step, refer to Figure 2 Substrate 101 is provided.

[0082] In this embodiment, a suitable semiconductor material is selected as the substrate 101, such as a silicon substrate 101. After providing the substrate 101, pretreatment steps such as cleaning are usually performed to remove surface impurities, oxides, and other contaminants.

[0083] The second step, refer to Figure 2 An epitaxial layer is formed on the first side of the substrate 101.

[0084] In this embodiment, an epitaxial layer can be grown on the first side of the substrate 101 using epitaxial growth techniques such as chemical vapor deposition (CVD). The material of the epitaxial layer can be the same as or different from the material of the substrate 101, depending on the design requirements of the shielded gate transistor. For example, for a silicon-based shielded gate transistor, a silicon epitaxial layer is typically grown on a silicon substrate 101.

[0085] It should be understood that an epitaxial layer that is too thin may not provide sufficient conductive channels and device structural support, while one that is too thick will increase fabrication costs and process complexity. Both excessively high and low doping concentrations will affect the electrical characteristics of the transistor, such as threshold voltage and breakdown voltage. Therefore, parameters such as the thickness and doping concentration of the epitaxial layer can be controlled according to actual needs to meet the performance requirements of the transistor.

[0086] Third step, refer to Figure 3 A first conductivity type body region 201 is formed in the epitaxial layer from the side opposite to the substrate 101.

[0087] In this embodiment, impurity ions of a first conductivity type (such as boron ions for P-type, phosphorus ions or arsenic ions for N-type) can be implanted into the epitaxial layer via ion implantation to form a first conductivity type body region 201. The energy and dose of ion implantation can be controlled according to actual needs to determine the depth and doping concentration distribution of the first conductivity type body region 201.

[0088] It should be understood that after ion implantation, annealing is usually required to activate the implanted impurity ions and repair the damage to the crystal structure caused during ion implantation, so that the first conductivity type body region 201 has good electrical properties and crystal structure. The first conductivity type body region 201 provides the foundation for the subsequent formation of the second conductivity type heavily doped region 30 and the trench gate structure.

[0089] Fourth step, refer to Figure 4 A second conductivity type heavily doped region 30 is formed in the first conductivity type body region 201 from the side opposite to the substrate 101, and a trench gate structure is formed in at least the first conductivity type body region 201. Wherein, along the extension direction perpendicular to the trench gate structure, the second conductivity type heavily doped region 30 is located on one side of the trench gate structure, and along the extension direction of the trench gate structure, the doping concentration in the second conductivity type heavily doped region 30 and / or the junction depth of the PN junction in the second conductivity type heavily doped region 30 varies in a gradient.

[0090] Similarly, in this embodiment, an ion implantation process is also used to implant impurity ions of a second conductivity type (opposite to the first conductivity type, such as phosphorus or arsenic ions for heavily doped P-type regions in an N-type body region, and boron ions for heavily doped N-type regions in a P-type body region) into the first conductivity type body region 201, forming a second conductivity type heavily doped region 30. Along the extension direction perpendicular to the trench gate structure, the second conductivity type heavily doped region 30 is located on one side of the trench gate structure. By controlling the energy and dosage of ion implantation, the second conductivity type heavily doped region 30 can be made to form a specific distribution in the first conductivity type body region 201.

[0091] Along the extension direction of the trench gate structure, the doping concentration and / or PN junction depth in the heavily doped region 30 of the second conductivity type exhibit a gradient change. This gradient change can be achieved through multiple ion implantations, each with different energies and doses, or by employing variable-energy ion implantation techniques. For example, gradually increasing the implantation energy and dose from one end to the other will gradually increase the doping concentration of the heavily doped region 30 of the second conductivity type; or by controlling the annealing process conditions, the PN junction depth can be varied at different locations, thus creating a gradient change.

[0092] Forming a trench gate structure may include: firstly, using photolithography to form a patterned mask of trenches on the surface of the first conductivity type body region 201. The photolithography process, through steps such as exposure and development, transfers the pre-defined trench pattern onto photoresist to form a mask pattern.

[0093] Then, dry etching techniques, such as reactive ion etching (RIE), are used to etch trenches in the first conductivity type body region 201, using a photoresist mask as a template. During the etching process, etching parameters, such as gas flow rate, power, and pressure, need to be controlled to ensure the depth, width, and sidewall perpendicularity of the trenches.

[0094] After etching, the photoresist mask is removed, and then the trench is filled with a gate dielectric material (such as silicon dioxide) and a gate material (such as polysilicon). The gate dielectric material can be filled using methods such as chemical vapor deposition to form a uniform and dense insulating layer to isolate the gate from the first conductivity type body region 201. After filling the gate material, the trench surface is smoothed using processes such as chemical mechanical polishing (CMP) to remove excess gate material and form a complete trench gate structure.

[0095] Based on the above description, the doping concentration and / or PN junction depth of the heavily doped region 30 of the second conductivity type exhibit a gradient change along the extension direction of the trench gate structure. This allows for adjustment of the electric field distribution within the transistor. Under reverse bias, the electric field distribution within the transistor is no longer uniform but is redistributed according to the gradient change of the heavily doped region 30 of the second conductivity type. The gradient change in doping concentration and PN junction depth prevents excessive local concentration of the electric field, resulting in a more uniform distribution of electric field lines throughout the transistor structure. This improves the transistor's breakdown voltage, enabling it to operate normally at higher voltages without being damaged by breakdown. This can be applied to applications requiring high voltage withstand capabilities, such as power management and power amplification, expanding the transistor's application range and improving its reliability and stability.

[0096] Furthermore, the gradient structure of the heavily doped region 30 of the second conductivity type can improve the current distribution inside the transistor. During forward conduction, current flows from the source, passes through the body region 201 of the first conductivity type and the heavily doped region 30 of the second conductivity type, and finally reaches the drain. The gradient doping concentration and PN junction depth can adjust the flow resistance of current at different locations, making the current more uniformly distributed throughout the conductive region. This improves the uniformity of the transistor's current distribution, making the current density at different locations closer. It also improves the performance consistency of the transistor; in large-scale integrated circuits, multiple transistors can work together more stably, reducing performance differences caused by uneven current distribution and improving the reliability and stability of the entire circuit system.

[0097] In one alternative implementation, refer to Figure 3 The formation of a first conductivity type body region 201 in the epitaxial layer from the side of the epitaxial layer opposite to the substrate 101 includes: From the side of the epitaxial layer away from the substrate 101, the epitaxial layer is doped with ions of a first conductivity type to form a first conductivity type body region 201 in the epitaxial layer, and a drift region 202 is formed in the region of the epitaxial layer that is not doped with the first conductivity type ions.

[0098] In this embodiment, after the epitaxial layer growth is completed and the surface undergoes pretreatment such as cleaning and drying to ensure that the surface is clean and free of impurities, first conductivity type ion doping is performed. At this time, it is necessary to select a suitable first conductivity type impurity ion source. For common silicon-based shielded gate transistors, if a P-type body region is to be formed, the impurity ion source is usually boron (B); if an N-type body region is to be formed, the impurity ion source is phosphorus (P) or arsenic (As).

[0099] Next, prepare the ion implantation equipment, which can precisely control key parameters such as ion implantation energy, dose, and angle. Ion implantation energy determines the implantation depth of impurity ions in the epitaxial layer; the higher the energy, the deeper the ions can penetrate. The dose determines the number of impurity ions implanted per unit area, directly affecting the doping concentration of the first conductivity type body region 201. The implantation angle affects the uniformity of impurity ion distribution in the epitaxial layer.

[0100] Then, the energy and dose parameters of ion implantation are set according to the design requirements of the shielded gate transistor. For example, if a shallower body region 201 with a higher doping concentration is required, a lower implantation energy and a higher dose can be selected; if a deeper body region with a relatively lower doping concentration is required, a higher implantation energy and a lower dose can be selected.

[0101] When the ion implantation equipment is activated, impurity ions are accelerated under the influence of an electric field, bombarding the surface of the epitaxial layer at high speed and penetrating to a certain depth into the interior of the epitaxial layer. During the implantation process, impurity ions collide with atoms in the epitaxial layer, gradually lose energy, and eventually remain in the epitaxial layer, forming a first conductivity type impurity distribution region, namely the first conductivity type volume region 201.

[0102] It should be understood that during the first conductivity type ion doping process, not the entire epitaxial layer is implanted with impurity ions. Those regions not doped with the first conductivity type ions retain the original conductivity type and doping concentration of the epitaxial layer; these regions form the drift region 202. The drift region 202 provides a channel for the flow of charge carriers (electrons or holes) between the source and drain in a shielded gate transistor. Its length and doping concentration, among other parameters, have a crucial impact on the transistor's breakdown voltage, on-resistance, and other performance indicators.

[0103] Based on the above description, the embodiments of this application can control parameters such as doping concentration, depth, and shape of the body region 201 of the first conductivity type through ion doping technology. Meanwhile, since the drift region 202 is an undoped region in the epitaxial layer, its characteristics are also related to the initial parameters of the epitaxial layer and the body region doping process. By rationally designing the energy and dosage of ion doping, the boundaries between the body region and the drift region 202 can be defined, and their electrical characteristics can be controlled. This allows the shielded gate transistor to be customized according to different application requirements. For example, in applications requiring high breakdown voltage, the length of the drift region 202 can be appropriately increased and its doping concentration reduced; while in applications requiring low on-resistance, the doping concentration and shape of the body region can be optimized to improve carrier mobility. This precise control helps optimize the overall performance of the transistor and improves its applicability in large-scale integrated circuits.

[0104] In one optional embodiment, forming a second conductivity type heavily doped region 30 in the first conductivity type body region 201 from the side of the first conductivity type body region 201 opposite to the substrate 101, and forming a trench gate structure at least in the first conductivity type body region 201 includes: First, refer to Figure 4 From the side of the first conductivity type body region 201 away from the substrate 101, the first target region of the first conductivity type body region 201 is heavily doped with second conductivity type ions to form the second conductivity type heavily doped region 30.

[0105] In this embodiment, starting from the side of the first conductivity type body region 201 facing away from the substrate 101, ions of the second conductivity type are implanted into the first conductivity type body region 201 at a high dose and high energy using an ion implantation device. For example, if the first conductivity type is N-type, the second conductivity type may be P-type, and the ions of the second conductivity type may be boron ions, etc.; if the first conductivity type is P-type, the second conductivity type may be N-type, and the ions of the second conductivity type may be phosphorus ions, etc.

[0106] By controlling the energy and dosage of ion implantation, ions can form a high-concentration second-conductivity heavily doped region 30, i.e., the second-conductivity heavily doped region 30, within a specific depth range of the first conductivity type body region 201.

[0107] It should be understood that the ion implantation energy determines the implantation depth of ions in the first conductivity type body region 201. The energy value needs to be set according to the actual requirements of the shielded gate transistor to ensure that the second conductivity type heavily doped region 30 is located at a suitable depth. The dose determines the doping concentration; high-dose implantation can form a heavily doped region, meeting the shielded gate transistor's requirement for high doping concentration in a specific area. Simultaneously, during ion implantation, a mask is typically used to define the implantation area, ensuring that the second conductivity type heavily doped region 30 is formed only in a specific area of ​​the first conductivity type body region 201.

[0108] Then, along the side of the second conductivity type heavily doped region 30 away from the first conductivity type body region 201, the second conductivity type heavily doped region 30 is etched in the second target region until the first conductivity type body region 201 is reached to form a gate trench. In this embodiment, along the side of the first conductivity type body region 201 opposite to the substrate 101, in the second target region, the first conductivity type body region 201 can be etched using a dry etching apparatus (such as a reactive ion etching apparatus, RIE). During the etching process, the etching rate and etching profile are controlled by controlling parameters such as the flow rate and power of the etching gas. Based on the etching profile and etching rate, a gate trench is formed until it penetrates at least through the second conductivity type heavily doped region 30, reaching a certain depth inside the first conductivity type body region 201.

[0109] It is worth noting that by adjusting the etching rate and etching energy, gate trenches with suitable depth, width, and sidewall perpendicularity can be obtained to meet the design requirements of the trench gate structure. Simultaneously, during the etching process, a mask is used to define a second target region, ensuring that the gate trench is formed at a specific location.

[0110] Finally, conductive material is filled into the gate trench to form a gate, thus obtaining the trench gate structure.

[0111] In this embodiment, after forming the gate trench, a conductive material is filled into the gate trench using chemical vapor deposition (CVD) or other suitable methods. Commonly used conductive materials include polycrystalline silicon, metals (such as aluminum and copper), or metal compounds (such as titanium silicides). During the filling process, it is necessary to control the deposition process parameters to ensure that the conductive material can uniformly and densely fill the entire gate trench, avoiding defects such as voids. After filling, some post-processing may be required, such as planarization of the filled conductive material (e.g., chemical mechanical polishing, CMP) to remove excess conductive material outside the trench, making the surface smooth and obtaining the final trench gate structure.

[0112] Optionally, from the side of the first conductivity type body region 201 opposite to the substrate 101, the first conductivity type body region 201 is heavily doped with second conductivity type ions to form the second conductivity type heavily doped region 30, including: First, a target mask is formed on a third target region on the surface of the epitaxial layer from the side of the first conductivity type body region 201 away from the substrate 101; wherein the target mask includes a plurality of target sub-masks, and the spacing between the plurality of target sub-masks varies in a gradient along the extension direction of the trench gate structure.

[0113] In this embodiment, a mask material is deposited on the surface of the epitaxial layer. Commonly used mask materials include silicon dioxide and silicon nitride. A layer of photoresist is coated on the surface of the mask material. Then, using a photolithography machine, a preset target sub-mask pattern is transferred onto the photoresist through exposure and development processes. During exposure, parameters such as exposure dose and focal length are controlled according to the design requirements of the target sub-mask to ensure accurate pattern transfer. After development, a pattern corresponding to the target sub-mask is formed on the photoresist.

[0114] Next, using the photoresist pattern as a mask, the deposited mask material is etched using dry etching (such as reactive ion etching, RIE) or wet etching methods to form multiple target submasks. In dry etching, a suitable etching gas is selected; for example, fluorine-based gases can be used for silicon dioxide masks. By controlling parameters such as the flow rate and power of the etching gas, the etching rate and etching profile are controlled to obtain target submasks with the desired shape and size. After etching, the remaining photoresist is removed.

[0115] It is worth noting that, depending on specific needs, multiple photolithography and etching processes can be used to create a gradient variation in the spacing between multiple target submasks along the extension direction of the trench gate structure. For example, a series of initial submasks with uniform spacing can be fabricated first, and then a layer of material can be deposited on the sidewalls of the submasks and etched again to change the effective size and spacing of the submasks, thus achieving a gradient variation in spacing.

[0116] Second, based on the target mask, the first conductivity type body region 201 is heavily doped with second conductivity type ions on the side opposite to the substrate 101 from the first conductivity type body region 201 to form the second conductivity type heavily doped region 30.

[0117] In this embodiment, appropriate ions of the second conductivity type are selected according to the specific requirements of the first and second conductivity types. For example, if the first conductivity type is N-type, the second conductivity type is P-type; if the first conductivity type is P-type, the second conductivity type is N-type. Simultaneously, based on the depth requirement of the target second conductivity type heavily doped region 30 within the first conductivity type body region 201, the ion implantation energy is precisely selected; the higher the energy, the deeper the ion implantation.

[0118] Subsequently, using the target mask as a barrier layer, the first conductivity type body region 201 is heavily doped with second conductivity type ions from the side opposite to the substrate 101. During ion implantation, the ion beam is incident on the epitaxial layer surface perpendicularly or at a certain angle. The area covered by the target mask will prevent ion implantation, while the area not covered by the mask will receive ion implantation, forming the second conductivity type heavily doped region 30. Since the spacing between the multiple target sub-masks varies with a gradient, the doping distribution at different positions of the formed second conductivity type heavily doped region 30 will also exhibit certain gradient characteristics.

[0119] After ion implantation, in order to eliminate lattice damage generated during the ion implantation process and activate the implanted ions to become effective dopant atoms, the sample needs to be annealed. Annealing can be performed using methods such as rapid thermal annealing (RTA) or furnace tube annealing; this application does not impose any specific limitations on these methods. For example, in rapid thermal annealing, the sample is heated to a high temperature (e.g., 800-1200°C) in a short time (e.g., a few seconds to tens of seconds) and then rapidly cooled; in furnace tube annealing, the sample is placed in a furnace tube and held at a certain temperature (e.g., 600-1000°C) for a period of time (e.g., tens of minutes to several hours), and then slowly cooled. Through annealing, the crystal structure of the heavily doped region 30 of the second conductivity type is repaired, improving the uniformity and stability of the doping concentration distribution.

[0120] Based on the above description, in this embodiment, the spacing between multiple target sub-masks varies with a gradient, resulting in a gradient characteristic in the doping concentration and PN junction depth of the heavily doped region 30 of the second conductivity type at different locations. This gradient distribution can adjust the distribution of the electric field and current inside the device, making the current flow more uniformly in the device, reducing hotspot problems caused by excessive local current density, and improving the reliability and stability of the device. For example, in power semiconductor devices, a uniform current distribution can reduce the conduction loss of the device and improve the efficiency of the device.

[0121] Furthermore, the embodiments of this application, through the fabrication of the target mask and the control of the ion implantation process, can achieve control over the doping concentration and PN junction depth of the heavily doped region 30 of the second conductivity type. The pattern definition and spacing gradient variation of the target sub-mask enable the ion implantation process to perform doping in specific regions according to actual needs, reducing the randomness and uncertainty of doping and improving the stability of the process.

[0122] In one example, the gradient variation in the spacing between the plurality of target sub-masks includes: the spacing between the plurality of target sub-masks gradually increasing, or the spacing between the plurality of target sub-masks gradually decreasing, or the spacing between the plurality of target sub-masks first gradually decreasing and then gradually increasing, or the spacing between the plurality of target sub-masks first gradually increasing and then gradually decreasing.

[0123] It should be understood that, referring to Figures 5(a) and 5(b), Figure 5(b) is a cross-sectional view cut along line AA in Figure 5(a). Along the extension direction B of the trench gate mask 502 and the extension direction of the contact structure mask 503, as the spacing between the plurality of target sub-masks 501 gradually decreases and the width of the sub-masks correspondingly increases, the area of ​​the region not covered by the target sub-masks 501 and receiving ion implantation gradually decreases during ion implantation. Under the condition that the implantation parameters remain consistent, the total amount of ions implanted per unit area is relatively fixed. Therefore, as the implantable area decreases, the ion implantation dose per unit volume will show a decreasing trend. This change directly leads to a gradual decrease in the doping concentration of the heavily doped region 30 of the second conductivity type along the extension direction of the trench gate structure. Simultaneously, the reduction in the ion implantation dose will correspondingly weaken the diffusion amplitude of ions in the subsequent annealing process, ultimately manifesting as a gradual shallowing of the PN junction depth formed by the heavily doped region 30 of the second conductivity type along the extension direction of the trench gate structure.

[0124] Referring to Figures 6(a) and 6(b), Figure 6(b) is a cross-sectional view cut along AA in 6(a).

[0125] Along the extension direction B of the trench gate mask 502 and the extension direction of the contact structure mask 503, as the spacing between the plurality of target sub-masks 501 gradually increases and their width correspondingly decreases, the area of ​​the implantation region exposed to the ion beam without being shielded by the target sub-masks 501 will continuously expand during the ion implantation process. Under the condition that the implantation parameters remain consistent, the total amount of ion implantation per unit area is basically constant. Therefore, as the effective implantation area increases, the ion implantation dose per unit volume will show an upward trend. This change results in: along the extension direction of the trench gate structure, the doping concentration of the heavily doped region 30 of the second conductivity type gradually increases. Simultaneously, the increase in the ion implantation dose will correspondingly enhance the diffusion amplitude of ions in the subsequent annealing process, ultimately manifesting as: along the extension direction of the trench gate structure, the junction depth of the PN junction formed by the heavily doped region 30 of the second conductivity type gradually increases.

[0126] Referring to Figures 7(a) and 7(b), Figure 7(b) is a cross-sectional view taken along line AA in Figure 7(a). Along the extension direction B of the trench gate mask 502 and the extension direction of the contact structure mask 503, the target sub-mask spacing first gradually decreases and then gradually increases; during the stage where the target sub-mask spacing first decreases, the width of the target sub-mask will correspondingly gradually increase. In this ion implantation process, the area of ​​the effective implantation region exposed to the ion beam without being masked will continuously shrink. Under the premise of keeping the implantation parameters consistent, the total amount of ion implantation per unit area is basically constant. Therefore, as the area of ​​the effective implantation region gradually decreases, the ion implantation dose per unit volume will show a decreasing trend. This change results in: along the extension direction of the trench gate structure, the doping concentration of the second conductivity type heavily doped region 30 gradually decreases. At the same time, the reduction in ion implantation dose will weaken the diffusion motion amplitude of ions in the subsequent annealing process, ultimately manifested as: along the extension direction of the trench gate structure, the junction depth of the PN junction formed by the second conductivity type heavily doped region 30 gradually becomes shallower.

[0127] As the target submask spacing increases, the width of the target submask gradually decreases. During this ion implantation process, the area of ​​the effective implantation region exposed to the ion beam, not covered by the mask, continuously expands. With consistent implantation parameters, the total ion implantation volume per unit area remains essentially constant; therefore, as the effective implantation area gradually increases, the ion implantation dose per unit volume increases. This change results in a gradual increase in the doping concentration of the heavily doped region 30 of the second conductivity type along the extension direction of the trench gate structure. Simultaneously, the increased ion implantation dose enhances the diffusion amplitude of ions in the subsequent annealing process, manifested as a gradual increase in the junction depth of the PN junction formed by the heavily doped region 30 of the second conductivity type along the extension direction of the trench gate structure.

[0128] Referring to Figures 8(a) and 8(b), Figure 7(b) is a cross-sectional view cut along line AA in Figure 7(a). Along the extension direction B of the trench gate mask 502 and the extension direction of the contact structure mask 503, as the spacing between the target sub-masks 501 gradually increases and then gradually decreases, the width of the target sub-masks 501 gradually decreases during the initial stage of increasing spacing. In this ion implantation process, the area of ​​the effective implantation region exposed to the ion beam without being masked continuously expands. Under the premise of consistent implantation parameters, the total ion implantation amount per unit area remains essentially constant; therefore, as the effective implantation region area gradually increases, the ion implantation dose per unit volume increases. This change results in a gradual increase in the doping concentration of the heavily doped region 30 of the second conductivity type along the extension direction of the trench gate structure. Simultaneously, the increase in ion implantation dose enhances the diffusion amplitude of ions in the subsequent annealing process, manifested as a gradual increase in the junction depth of the PN junction formed by the heavily doped region 30 of the second conductivity type along the extension direction of the trench gate structure.

[0129] As the target submask spacing decreases, the width of the target submask gradually increases. During this ion implantation process, the area of ​​the effective implantation region exposed to the ion beam, not covered by the mask, continuously shrinks. With consistent implantation parameters, the total ion implantation amount per unit area remains essentially constant. Therefore, as the effective implantation area gradually decreases, the ion implantation dose per unit volume decreases. This change results in a gradual decrease in the doping concentration of the heavily doped region 30 of the second conductivity type along the extension direction of the trench gate structure. Simultaneously, the reduction in ion implantation dose weakens the diffusion amplitude of ions in the subsequent annealing process, ultimately manifesting as a gradual shallowing of the PN junction depth formed by the heavily doped region 30 of the second conductivity type along the extension direction of the trench gate structure.

[0130] In one alternative embodiment, after forming a second conductivity type heavy doping in the first conductivity type body region 201 and forming a trench gate structure in at least the first conductivity type body region 201, the method further includes: First, an insulating layer is formed on the surface of the first conductive type body region 201 along the side of the first conductive type body region 201 away from the substrate 101.

[0131] In this embodiment, after forming a second conductivity type heavily doped layer in the first conductivity type body region 201 and forming a trench gate structure in at least the first conductivity type body region 201, an insulating layer is formed on the surface of the first conductivity type body region 201 along the side of the first conductivity type body region 201 away from the substrate 101 using thin film deposition techniques such as chemical vapor deposition and physical vapor deposition. The insulating layer material can be silicon dioxide, silicon nitride, etc., and this insulating layer is used to isolate the first conductivity type body region 201 from the subsequently formed structure to prevent leakage current, while also providing a basis for subsequent etching and contact hole formation.

[0132] Second, along the side of the insulating layer away from the first conductive type body region 201, the fourth target region is etched to form a contact hole that penetrates the insulating layer and the second conductive type heavily doped region 30 and extends into the first conductive type body region 201; wherein, along the extension direction perpendicular to the trench gate structure, the fourth target region is spaced apart on one side of the trench gate structure.

[0133] In this embodiment, the fourth target region is etched along the side of the insulating layer opposite to the first conductivity type body region 201. Dry etching or wet etching processes can be used to etch contact holes that penetrate the insulating layer and the second conductivity type heavily doped region 30, extending into the first conductivity type body region 201. During the etching process, etching parameters, such as etching gas composition, flow rate, and power, need to be strictly controlled to ensure that the dimensional accuracy and shape of the contact holes meet the actual requirements.

[0134] Third, along the bottom of the contact hole, the first conductivity type body region 201 is heavily doped with first conductivity type ions to form a first conductivity type heavily doped region covering the bottom of the contact hole in the first conductivity type body region 201.

[0135] In this embodiment, the first conductivity type body region 201 is heavily doped with ions of the first conductivity type along the bottom of the contact hole. For example, if the first conductivity type is N-type, N-type impurity ions such as phosphorus (P) and arsenic (As) are implanted; if the first conductivity type is P-type, P-type impurity ions such as boron (B) are implanted. By controlling the implantation energy and dosage using an ion implantation device, a first conductivity type heavily doped region covering the bottom of the contact hole is formed in the first conductivity type body region 201. The function of this first conductivity type heavily doped region is to reduce the contact resistance.

[0136] Fourth, the contact hole is filled with conductive material to form a contact structure.

[0137] In this embodiment, the contact holes are filled with conductive material, commonly including metals (such as aluminum and copper) or polycrystalline silicon. The conductive material can be filled into the contact holes using processes such as physical vapor deposition (PVD), chemical vapor deposition (CVD), or electroplating to form a contact structure. The contact structure needs to form a good ohmic contact with the first conductivity type heavily doped region and the second conductivity type heavily doped region 30 to ensure smooth current flow.

[0138] Fifth, a source electrode is formed on the side of the contact structure opposite to the insulating layer.

[0139] In this embodiment, a source electrode is formed on the side of the contact structure away from the insulating layer using processes such as photolithography, evaporation, and sputtering. The source electrode material is typically a metal, such as aluminum or an aluminum alloy. The function of the source electrode is to connect the device to an external circuit, enabling current input and output.

[0140] In this embodiment, the formation of the insulating layer effectively isolates the first conductive type body region 201 from other structures, preventing leakage.

[0141] A heavily doped region of the first conductivity type is formed at the bottom of the contact hole, increasing the carrier concentration in that region. When current flows through the contact structure, the increased carrier concentration facilitates the migration of electrons or holes at the contact interface, significantly reducing contact resistance. Lower contact resistance reduces power loss during device operation and improves the device's energy conversion efficiency.

[0142] Furthermore, the formation of the heavily doped region of the first conductivity type can adjust the electric field distribution between the first conductivity type body region 201 and the contact structure. When the shielded gate transistor is operating, the electric field will form a gradient distribution between regions with different doping concentrations. By reasonably controlling the doping concentration and size of the heavily doped region of the first conductivity type, the electric field distribution can be made more uniform, avoiding the occurrence of electric field spikes. A uniform electric field distribution helps to improve the breakdown voltage of the shielded gate transistor, enhance its withstand voltage capability, and enable it to operate safely at higher voltages.

[0143] In one alternative embodiment, after forming a second conductivity type heavy doping in the first conductivity type body region 201 and forming a trench gate structure in at least the first conductivity type body region 201, the method further includes: A drain is formed on a fifth target region on the surface of the substrate 101 from the second side of the substrate 101, and the drain forms an ohmic contact with the substrate 101; wherein the first side and the second side of the substrate 101 are two sides disposed opposite each other along the thickness direction of the substrate 101.

[0144] In this embodiment, a suitable first conductivity type substrate 101 is selected, such as an N-type or P-type single-crystal silicon substrate 101. The substrate 101 undergoes a rigorous cleaning process using chemical cleaning methods to remove impurities, oxides, and organic contaminants from its surface, ensuring a clean and flat surface for subsequent processes.

[0145] The fifth target region is defined on the second side surface of substrate 101 using photolithography. The photolithography process includes steps such as photoresist coating, exposure, and development. First, a layer of photoresist is uniformly coated on the second side surface of substrate 101. Then, using a specific photomask, the pattern on the photomask is transferred onto the photoresist using exposure equipment (such as an ultraviolet light exposure machine). Finally, the photoresist in the exposed or unexposed areas is removed using a developer, thereby forming the pattern of the fifth target region on the surface of substrate 101.

[0146] It is worth noting that, in order to achieve an ohmic contact between the drain and the substrate 101, ion implantation of the same conductivity type as the substrate 101 can be performed in the fifth target region. For example, if the substrate 101 is N-type, N-type impurity ions such as phosphorus (P) and arsenic (As) are implanted; if the substrate 101 is P-type, P-type impurity ions such as boron (B) are implanted. By controlling the energy and dosage of ion implantation, a high-concentration doped region is formed in the fifth target region, reducing the contact resistance.

[0147] Subsequently, a thin metal film is deposited on the second side surface of substrate 101 as a drain material using processes such as physical vapor deposition and chemical vapor deposition. Commonly used metal materials include aluminum, copper, titanium, and nickel. Multilayer metal structures can also be used to improve the conductivity, adhesion, and oxidation resistance of the drain.

[0148] A second photolithography process is performed to define the drain pattern on the deposited metal film. Then, an etching process is used to remove excess metal, forming the drain structure corresponding to the fifth target region.

[0149] Finally, the formed drain is annealed, with the annealing temperature and time precisely controlled according to the selected metal material and process requirements. The purpose of annealing is to form a good ohmic contact between the metal and the substrate 101, eliminate defects and stress at the interface between the metal and the substrate 101, reduce contact resistance, and improve the performance and reliability of the shielded gate transistor.

[0150] Thirdly, embodiments of this application provide a chip including a shielded gate transistor as described in any of the first aspects, or a shielded gate transistor prepared by the method described in any of the second aspects.

[0151] In the embodiments of this application, the chip can be applied to the fields of industrial electronics, consumer electronics, and new energy vehicles.

[0152] The beneficial effects of this chip can be found in the descriptions in the first and second aspects, and will not be repeated here.

[0153] Fourthly, embodiments of this application provide an electronic device including the chip described in the third aspect.

[0154] In the embodiments of this application, the electronic device can be applied to scenarios such as daily communication and fast charging.

[0155] For example, when an electronic device is connected to a charger, the shielded gate transistor in the chip participates in charging management. It can precisely control the charging current and voltage according to the battery status and charging needs, achieving a fast and safe charging process. For example, electronic devices that support fast charging technology can replenish a large amount of power to the battery in a short time.

[0156] It should also be noted that the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.

[0157] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of this application, and are not intended to limit them. Although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features therein. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of this application.

Claims

1. A shielded gate transistor, characterized in that, The shielded gate transistor includes: Substrate, epitaxial layer located on the first side of the substrate; A first conductivity type body region; the first conductivity type body region is formed in the epitaxial layer from the side of the epitaxial layer away from the substrate; A second conductivity type heavily doped region and a trench gate structure; the second conductivity type heavily doped region and the trench gate structure are formed in the first conductivity type body region from the side of the first conductivity type body region away from the substrate; Wherein, along the extension direction perpendicular to the trench gate structure, the second conductivity type heavily doped region is located on one side of the trench gate structure; along the extension direction of the trench gate structure, the doping concentration in the second conductivity type heavily doped region varies with a gradient, and / or, along the extension direction of the trench gate structure, the PN junction depth in the second conductivity type heavily doped region varies with a gradient.

2. The shielded gate transistor according to claim 1, characterized in that, Along the extension direction of the trench gate structure, the doping concentration in the heavily doped region of the second conductivity type gradually increases, and / or, along the extension direction of the trench gate structure, the junction depth of the PN junction in the heavily doped region of the second conductivity type gradually increases; Alternatively, along the extension direction of the trench gate structure, the doping concentration in the heavily doped region of the second conductivity type gradually decreases, and / or, along the extension direction of the trench gate structure, the junction depth of the PN junction in the heavily doped region of the second conductivity type gradually decreases; Alternatively, along the extension direction of the trench gate structure, the doping concentration in the heavily doped region of the second conductivity type first gradually decreases and then gradually increases, and / or, along the extension direction of the trench gate structure, the junction depth of the PN junction in the heavily doped region of the second conductivity type first gradually decreases and then gradually increases; Alternatively, along the extension direction of the trench gate structure, the doping concentration in the heavily doped region of the second conductivity type first gradually increases and then gradually decreases, and / or, along the extension direction of the trench gate structure, the junction depth of the PN junction in the heavily doped region of the second conductivity type first gradually increases and then gradually decreases.

3. The shielded gate transistor according to claim 1, characterized in that, The shielded gate transistor further includes: a contact structure, a source, an insulating layer, and a heavily doped region of a first conductivity type; The insulating layer is formed on the epitaxial layer along the side of the epitaxial layer opposite to the substrate; Along the extension direction perpendicular to the trench gate structure, the contact structure is located on at least one side of the trench gate structure, and along the thickness direction of the epitaxial layer, the contact structure penetrates the insulating layer and the second conductivity type heavily doped region, up to the first conductivity type body region; The source electrode is formed on the contact structure and is electrically connected to the contact structure; The first conductivity type heavily doped region is formed in the first conductivity type body region and covers the bottom of the contact structure.

4. The shielded gate transistor according to claim 1, characterized in that, The shielded gate transistor further includes a drain, which is located on the second side of the substrate and forms an ohmic contact with the substrate; wherein the first side and the second side of the substrate are two sides disposed opposite to each other along the thickness direction of the substrate.

5. A method for fabricating a shielded gate transistor, characterized in that, The method includes: Provide substrate; An epitaxial layer is formed on the first side of the substrate; A first conductivity type body region is formed in the epitaxial layer from the side of the epitaxial layer opposite to the substrate; A second conductivity type heavily doped region is formed in the first conductivity type body region from the side opposite to the substrate, and a trench gate structure is formed in at least the first conductivity type body region. Wherein, along the extension direction perpendicular to the trench gate structure, the second conductivity type heavily doped region is located on one side of the trench gate structure, the doping concentration in the second conductivity type heavily doped region varies with a gradient along the extension direction of the trench gate structure, and / or, along the extension direction of the trench gate structure, the junction depth of the PN junction in the second conductivity type heavily doped region varies with a gradient.

6. The preparation method according to claim 5, characterized in that, The formation of a first conductivity type body region in the epitaxial layer on the side opposite to the substrate includes: From the side of the epitaxial layer away from the substrate, the epitaxial layer is doped with ions of a first conductivity type to form a first conductivity type body region in the epitaxial layer, and the region in the epitaxial layer that is not doped with the first conductivity type ions forms a drift region.

7. The preparation method according to claim 5, characterized in that, Forming a second conductivity type heavily doped region in the first conductivity type body region from the side opposite to the substrate, and forming a trench gate structure in at least the first conductivity type body region, includes: From the side of the first conductivity type body region away from the substrate, the first target region of the first conductivity type body region is heavily doped with second conductivity type ions to form the second conductivity type heavily doped region; Along the side of the second conductivity type heavily doped region away from the first conductivity type body region, the second conductivity type heavily doped region is etched in the second target region until the first conductivity type body region is reached to form a gate trench. A gate is formed by filling the gate trench with conductive material, thus obtaining the trench gate structure.

8. The preparation method according to claim 7, characterized in that, The process of forming a second-conductivity-type heavily doped region by performing second-conductivity-type ion heavy doping on the side of the first conductivity-type body region away from the substrate includes: A target mask is formed on a third target region on the surface of the epitaxial layer from the side of the first conductivity type body region away from the substrate; wherein the target mask includes a plurality of target sub-masks, and the spacing between the plurality of target sub-masks varies in a gradient along the extension direction of the trench gate structure; Based on the target mask, the first conductivity type body region is heavily doped with second conductivity type ions on the side opposite to the substrate from the first conductivity type body region to form the second conductivity type heavily doped region.

9. The preparation method according to claim 8, characterized in that, The gradient variation in the spacing between the multiple target sub-masks includes: the spacing between the multiple target sub-masks gradually increasing, or the spacing between the multiple target sub-masks gradually decreasing, or the spacing between the multiple target sub-masks first gradually decreasing and then gradually increasing, or the spacing between the multiple target sub-masks first gradually increasing and then gradually decreasing.

10. The preparation method according to any one of claims 5-9, characterized in that, After forming a second conductivity type heavy doping in the first conductivity type body region and forming a trench gate structure at least in the first conductivity type body region, the method further includes: An insulating layer is formed on the surface of the first conductive type body region along the side of the first conductive type body region away from the substrate; Along the side of the insulating layer away from the first conductivity type body region, the fourth target region is etched to form a contact hole that penetrates the insulating layer and the second conductivity type heavily doped region and extends into the first conductivity type body region; wherein, along the extension direction perpendicular to the trench gate structure, the fourth target region is spaced apart on one side of the trench gate structure. Along the bottom of the contact hole, the first conductivity type body region is heavily doped with first conductivity type ions to form a first conductivity type heavily doped region covering the bottom of the contact hole in the first conductivity type body region; The contact hole is filled with conductive material to form a contact structure; A source electrode is formed on the side of the contact structure opposite to the insulating layer.

11. The preparation method according to any one of claims 5-9, characterized in that, After forming a second conductivity type heavy doping in the first conductivity type body region and forming a trench gate structure at least in the first conductivity type body region, the method further includes: A drain is formed from the second side of the substrate in a fifth target region on the surface of the substrate, and the drain forms an ohmic contact with the substrate; wherein the first side and the second side of the substrate are two sides disposed opposite to each other along the thickness direction of the substrate.

12. A chip, characterized in that, Includes the shielded gate transistor according to any one of claims 1-4, or the shielded gate transistor prepared by the method of preparing the shielded gate transistor according to any one of claims 5-11.

13. An electronic device, characterized in that, Includes the chip described in claim 12.

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