LVDS (Low Voltage Differential Signaling) receiving circuit with wide common-mode input range

Abstract

The invention discloses an LVDS (Low Voltage Differential Signaling) receiving circuit with a wide common-mode input range. The LVDS receiving circuit comprises a common-mode conversion circuit, a main comparator circuit, a secondary comparison circuit and a logical judgment circuit, the common-mode conversion circuit is used for converting an external wide common-mode input differential signal into a signal with constant common-mode voltage and no attenuation of the differential signal; the main comparator circuit identifies the converted differential signal to complete differential-to-single-ended data conversion; the secondary comparator circuit is composed of two low-speed comparators; and the logic judgment circuit judges the output of the main comparator and the window comparator to ensure that the output of the input end of the circuit group is a constant level under the short circuit and disconnection conditions, so that the function of dynamic failure protection of the circuit is realized. The wide common-mode input circuit can realize discrimination of wide common-mode input signals ranging from-4V to 5V, and has a dynamic failure protection function.

Description

Technical Field

[0001] This invention relates to an LVDS receiver circuit with a wide common-mode input range, belonging to the field of high-speed interface circuit technology. Background Technology

[0002] According to the TIA-EIA-644-A protocol standard, LVDS receiver circuits must guarantee a common-mode voltage range of 0 to 2.4V. However, in environments with high noise or unstable ground potential, the common-mode voltage of the signal may be lower than 0V or higher than the power supply voltage, leading to bit errors in system data transmission and, in severe cases, even damage to components. A wide common-mode input range of -4V to 5V expands the receiver circuit's tolerance to voltage deviations and provides a higher noise margin, which helps simplify system design, improves electromagnetic compatibility, and ensures long-term stable operation of the system.

[0003] For LVDS receiver circuits with a wide common-mode input of -4V to 5V, since the port needs to work normally under a common-mode level of less than 0V, the traditional pull-up / pull-down and double pull-up failure protection circuits are not applicable. Therefore, the circuit failure protection function needs to be redesigned. Summary of the Invention

[0004] The technical problem solved by this invention is to overcome the shortcomings of the prior art and propose an LVDS receiving circuit with a wide common-mode input range, which extends the traditional LVDS common-mode input range to -4V to 5V and can realize circuit failure protection in the entire common-mode range.

[0005] The technical solution of this invention is:

[0006] A wide common-mode input range LVDS receiver circuit includes a common-mode conversion circuit, a main comparator circuit, a secondary comparator circuit, and a logic judgment circuit.

[0007] The common-mode converter circuit converts the differential signal from the external wide common-mode input into a signal with constant common-mode voltage and no attenuation of differential level;

[0008] The main comparator circuit compares the signal output by the common-mode converter circuit, completes the data conversion from differential to single-ended, and outputs it to the logic judgment circuit.

[0009] The secondary comparison circuit detects whether there is differential level attenuation in the signal output by the common-mode converter circuit, and outputs the detection signal to the logic judgment circuit.

[0010] The logic judgment circuit judges the signals output by the main comparator and the secondary comparator to realize the normal function output or failure protection of the LVDS receiving circuit.

[0011] Furthermore, the common-mode converter circuit includes resistors R1, R2, R3, R4 and R5, capacitors C1, C2, C3 and C4, voltage operational amplifier OP1 and current operational amplifier OP2.

[0012] One end of resistor R1 and one end of capacitor C1 are connected together to serve as the input terminal V of the common converter circuit. IA The other end of resistor R1 and the other end of capacitor C1, one end of resistor R2 and one end of capacitor C2 are connected together to form the output terminal V of the common-mode converter circuit. OA The other end of capacitor C2 is grounded;

[0013] One end of resistor R3 and one end of capacitor C3 are connected together to serve as the input terminal V of the common converter circuit. IB The other end of resistor R3 and the other end of capacitor C3, one end of resistor R4 and one end of capacitor C4 are connected together to form the output terminal V of the common converter circuit. OB The other end of capacitor C4 is grounded; the other end of resistor R4 is connected to the other end of resistor R2 and the non-inverting input of voltage operational amplifier OP1 respectively.

[0014] The inverting input of the voltage operational amplifier OP1 is connected to a fixed reference level V. REF1 The output terminal is connected to the inverting input terminal of the current operational amplifier OP2 via resistor R5;

[0015] The non-inverting input of the current operational amplifier OP2 is connected to a fixed reference level V. REF2 The output terminals are respectively connected to the output terminal V of the common-mode converter circuit. OA and V OB This creates negative feedback, causing the output V to... OA and V OB The common-mode level is adjusted to the reference level V. REF1 .

[0016] Furthermore, resistors R1 and R3 have the same resistance value, resistors R2 and R4 have the same resistance value, and the resistance values ​​of resistors R2 and R4 are greater than the resistance values ​​of resistors R1 and R3, with a ratio of more than 10; capacitors C1 and C3 have the same capacitance value, capacitors C2 and C4 have the same capacitance value, and the resistance ratio of resistors R1 and R2 is equal to the capacitance ratio of capacitors C2 and C1.

[0017] Furthermore, the current operational amplifier OP2 includes NMOS transistors MN1-MN5, PMOS transistors MP1-MP5, and current source I. A and I B ;

[0018] The source of PMOS transistor MP1 is simultaneously connected to the source of PMOS transistor MP2, the source of PMOS transistor MP3, and current source I. AOne end of the PMOS transistor is connected to the power supply VDD. The gate of PMOS transistor MP1 is connected to the drain of PMOS transistor MP1, the gate of PMOS transistor MP2, the gate of PMOS transistor MP3, and the drain of NMOS transistor MN4. The drain of PMOS transistor MP2 is connected to the drain of NMOS transistor MN2 and then serves as the output terminal V of the common-mode converter circuit. OA The drain of PMOS transistor MP3 is connected to the drain of NMOS transistor MN3, and then serves as the output terminal V of the common-mode converter circuit. OB The gate of NMOS transistor MN4, the gate of NMOS transistor MN5, the drain of NMOS transistor MN5, and current source I. A One end is connected;

[0019] The source of NMOS transistor MN4 is connected to the source of PMOS transistor MP4 as the input terminal V of the current operational amplifier. IN The source of MN5 is connected to the source of PMOS transistor MP5 and then connected to the reference voltage V. REF2 The source of NMOS transistor MN1 is simultaneously connected to the source of NMOS transistor MN2, the source of NMOS transistor MN3, and current source I. B One end of the transistor is connected to ground (GND). The gate of NMOS transistor MN1 is simultaneously connected to the drain of NMOS transistor MN1, the gate of NMOS transistor MN2, the gate of NMOS transistor MN3, and the drain of PMOS transistor MP4. The gate of PMOS transistor MP4 is connected to the gate of PMOS transistor MP5, the drain of PMOS transistor MP5, and current source I. B One end is connected.

[0020] Furthermore, PMOS transistors MP1, MP2, and MP3 have the same width-to-length ratio, and NMOS transistors MN1, MN2, and MN3 have the same width-to-length ratio. Therefore, the current flowing through PMOS transistors MP2 and MP3 is equal to the current flowing through PMOS transistor MP1, and the current flowing through NMOS transistors MN2 and MN3 is equal to the current flowing through NMOS transistor MN1.

[0021] Furthermore, the secondary comparator circuit includes comparator CMP1 and comparator CMP2, and the comparator circuits CMP1 and CMP2 are completely identical.

[0022] One output of the common-mode converter circuit is connected to the non-inverting input of comparator CMP1 and the inverting input of comparator CMP2, while the other output is connected to the inverting input of comparator CMP1 and the non-inverting input of comparator CMP2. An offset voltage V is introduced into the inverting inputs of comparators CMP1 and CMP2. th For comparator CMP1, only when V OB >V OA +V thWhen V changes from high to low, the output changes from high to low; for comparator CMP2, this only happens when V... OA >V OB +V th When this happens, the output changes from high level to low level.

[0023] Furthermore, the bandwidth of the master comparator circuit is much greater than that of the slave comparator circuits CMP1 and CMP2, with a ratio of more than 100 times.

[0024] Furthermore, the logic judgment circuit includes resistor inverter INV1, resistor inverter INV2, buffer BUFF1, capacitor C1, capacitor C2, NOR gate NOR1, NOR gate NOR2, NOR gate NOR3, and NAND gate NAND1.

[0025] The output of the main comparator circuit is V. CMP Connect the input terminals of resistor inverter INV1 and NOR gate NOR3 respectively. Connect the output terminal of resistor inverter INV1 to the input terminal of resistor inverter INV2 and the input terminal of buffer BUFF1 respectively. Connect the output terminal of resistor inverter INV2 to capacitor C5 and one input terminal of NOR gate NOR1 respectively. Connect the output terminal of buffer BUFF1 to capacitor C6 and the other input terminal of NOR gate NOR1 respectively. Connect the output terminal of NOR gate NOR1 to one input terminal of NOR gate NOR2.

[0026] From the comparator output V CMP1 and V CMP2 Connect the two inputs of NAND gate NAND1 to the other input of NOR gate NOR2. Connect the output of NAND gate NAND1 to the other input of NOR gate NOR3. Connect the output of NOR gate NOR3 to V. OUT .

[0027] Furthermore, in the logic judgment circuit, capacitors C5 and C6 have the same capacitance value.

[0028] Furthermore, the output V of the main comparator circuit CMP When a level flip occurs, the logic judgment circuit restarts the timing from 0, with the timing window being the set duration. If the main comparator output level remains unchanged for more than the timing window, the secondary comparator output state is checked. If the secondary comparator output V... CMP1 and V CMP2 When it is high, the output V OUT A constant low level is used to implement LVDS receiver circuit failure protection; if the secondary comparator output V CMP1 and V CMP2 It consists of one high level and one low level, outputting V. OUT Follow V CMP The changes enable the LVDS receiver circuit to function normally and output correctly.

[0029] The advantages of this invention compared to the prior art are:

[0030] (1) The present invention extends the common mode reception range of the LVDS receiver from 0 to 2.4V to -4V to 5V through a common mode conversion circuit, providing higher noise margin and electromagnetic compatibility, and can be used in harsher environments;

[0031] (2) While ensuring the common-mode reception range of -4V to 5V, the present invention implements circuit failure protection function by using a slow comparator and logic judgment, ensuring that the circuit output is stable when there is no differential input signal.

[0032] (3) The LVDS receiving circuit with a common mode receiving range of -4V to 5V proposed in this invention can be implemented using standard CMOS technology, which reduces the requirements of the circuit for manufacturing process. Attached Figure Description

[0033] Various other advantages and benefits will become apparent to those skilled in the art upon reading the following detailed description of preferred embodiments. The accompanying drawings are for illustrative purposes only and are not intended to limit the invention. Furthermore, the same reference numerals denote the same parts throughout the drawings. In the drawings:

[0034] Figure 1 This is a block diagram of the overall structure of the wide common-mode input range LVDS receiver circuit according to an embodiment of the present invention;

[0035] Figure 2 This is a block diagram of the common-mode converter circuit according to an embodiment of the present invention;

[0036] Figure 3 This is a circuit diagram of a current operational amplifier according to an embodiment of the present invention;

[0037] Figure 4 This is a block diagram of the main comparator circuit according to an embodiment of the present invention;

[0038] Figure 5 This is a block diagram of the comparator circuit according to an embodiment of the present invention;

[0039] Figure 6 This is a block diagram of the logic judgment circuit in an embodiment of the present invention. Detailed Implementation

[0040] Exemplary embodiments of the present disclosure will now be described in more detail with reference to the accompanying drawings. While exemplary embodiments of the present disclosure are shown in the drawings, it should be understood that the present disclosure may be implemented in various forms and should not be limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the disclosure to those skilled in the art.

[0041] This invention proposes an LVDS receiver circuit with a wide common-mode input range, such as... Figure 1 As shown, it includes a common-mode converter circuit, a main comparator circuit, a secondary comparator circuit, and a logic judgment circuit. The P and N input terminals are first connected to the common-mode converter circuit. The output of the common-mode converter circuit is connected to both the input of the main comparator circuit and the input of the secondary comparator circuit. The output of the main comparator is connected to the input of the logic judgment circuit, and the output of the secondary comparator is connected to the input of the combinational logic circuit. The combinational logic output is the final output of the LVDS receiving circuit.

[0042] (1) Common-mode converter circuit

[0043] The common-mode converter circuit converts a differential signal with a wide common-mode input into a signal with a constant common-mode voltage and no attenuation of the differential signal.

[0044] The common-mode converter circuit includes a common-mode converter, a voltage operational amplifier, and a current-input operational amplifier; the output of the common-mode converter is connected to the non-inverting input of the voltage amplifier, and the inverting input of the voltage amplifier is connected to the reference voltage V. REF1 The output of the voltage amplifier is connected to the inverting input of the current amplifier through resistor R5, and the non-inverting input of the current amplifier is connected to voltage V. REF2 The current amplifier outputs are connected to V respectively. OA and V OB This creates negative feedback.

[0045] Common-mode converter circuits such as Figure 2 As shown, the circuit includes resistors R1, R2, R3, and R4; capacitors C1, C2, C3, and C4; voltage operational amplifier OP1; and current operational amplifier OP2. One end of resistor R1 and one end of capacitor C1 are connected together to serve as the input terminal V of the common converter circuit. IA The other end of resistor R1 and the other end of capacitor C1, one end of resistor R2 and one end of capacitor C2 are connected together to form the output terminal V of the common-mode converter circuit. OA The other end of capacitor C2 is grounded, and one end of resistor R3 is connected to one end of capacitor C3 to serve as the input terminal V of the common converter circuit. IB The other end of resistor R3 and the other end of capacitor C3, one end of resistor R4 and one end of capacitor C4 are connected together to form the output terminal V of the common converter circuit. OB The other end of capacitor C4 is grounded. Resistor R1 and capacitor C1 are connected in parallel, and resistor R3 and capacitor C3 are connected in parallel. The non-inverting input of voltage operational amplifier OP1 is connected to the other ends of resistors R2 and R4, and the inverting input is connected to a fixed reference level V. REF1 The output terminal is connected to the inverting input of the current operational amplifier OP2 via resistor R5. The non-inverting input of the current operational amplifier OP2 is connected to a fixed reference level V. REF2The inverting input terminal is connected to the output terminal of OP1 through resistor R5. Specifically, resistors R1 = R3, R2 = R4, and the resistance values ​​of R2 and R4 are much larger than those of R1 and R3. Capacitors C1 = C3, C2 = C4, and R1 / R2 = C2 / C1.

[0046] Current operational amplifier OP2, such as Figure 3 As shown, it includes NMOS transistors MN1-MN5, PMOS transistors MP1-MP5, and current source I. A and I B The source of MP1 is simultaneously connected to the source of MP2, the source of MP3, and the current source I. A One end of the circuit is connected to the power supply VDD. The gate of MP1 is connected to the drain of MP1, the gate of MP2, the gate of MP3, and the drain of MN4. The drain of MP2 is connected to the drain of MN2 and serves as the output terminal V of the common-mode converter circuit. OA The drain of MP3 is connected to the drain of MN3 and then serves as the output terminal V of the common-mode converter circuit. OB The gates of MN4 and MN5, the drain of MN5, and the current source I. A One end is connected; the source of MN4 is connected to the source of MP4 as the input terminal V of the current operational amplifier. IN After the source of MN5 is connected to the source of MP5, a reference voltage V is connected. REF2 The source of MN1 is simultaneously connected to the source of MN2, the source of MN3, and the current source I. B One end of MN1 is connected to ground (GND). The gate of MN1 is also connected to the drain of MN1, the gate of MN2, the gate of MN3, and the drain of MP4. The gate of MP4 is connected to the gate of MP5, the drain of MP5, and the current source I. B One end is connected. MP1, MP2, and MP3 have the same width-to-length ratio, and MN1, MN2, and MN3 have the same width-to-length ratio. Therefore, the current flowing through MP2 and MP3 is equal to the current I1 of MP1, and the current flowing through MN2 and MN3 is equal to the current I2 of MN1.

[0047] Because resistors R2 and R4 have very large resistances, the positive input terminal of voltage operational amplifier OP1 is equal to 1 / 2 (V). OA +V OB ), that is, V OA and V OB The common-mode level. Considering only the common-mode condition, V... OA =V OB ,at this time:

[0048]

[0049] When the common-mode voltage of the external input signal changes, due to the negative feedback regulation of the voltage operational amplifier OP1 and the current operational amplifier OP2, I1 and I2 also change accordingly, ensuring that V... OA =V OB =V IA The value of -(I1-I2)R1 remains unchanged, meaning that for an external common-mode input of -4V to 5V, the internal common-mode level remains at V after adjustment. REF1 .

[0050] The above equation can be transformed to obtain:

[0051] V IA -V OA =V IB -V OB

[0052] V IA -V IB =V OA -V OB

[0053] That is, the common-mode converter circuit keeps the input differential level unchanged while completing the common-mode level conversion.

[0054] (2) Main comparator circuit

[0055] The main comparator circuit identifies the differential signal after common-mode conversion and completes the data conversion from differential to single-ended through positive feedback failure hysteresis. For example... Figure 4 As shown, the positive input terminal of the main comparator is connected to the output terminal V of the common-mode converter circuit. OA The negative input of the main comparator is connected to the output V of the common-mode converter circuit. OB The main comparator uses a symmetrical operational amplifier, and the circuit can achieve V... OA and V OB The signal comparison function utilizes the positive feedback structure of the circuit to achieve the hysteresis function of the main comparator.

[0056] (3) Secondary Comparison Circuit

[0057] The secondary comparator circuit is used to detect differential signals with an input differential amplitude of less than 80mV and consists of two slow comparators.

[0058] The secondary comparator circuit is as follows: Figure 5 As shown, it includes two comparators, CMP1 and CMP2, and the output terminal V of the common-mode converter circuit. OA Connect the non-inverting input of comparator CMP1 and the inverting input of CMP2, and the output V of the common-mode converter circuit. OBConnect the inverting input of comparator CMP1 and the non-inverting input of comparator CMP2. The comparator circuits CMP1 and CMP2 are identical, but their bandwidths are much smaller than the main comparator's bandwidth. An 80mV offset voltage is introduced into the inverting inputs of comparators CMP1 and CMP2. For CMP1, this offset voltage only applies when V... OB >V OA +V th When the output changes from high to low; for CMP2, when V OA >V OB +V th The output changes from high to low. The LVDS standard TIA / EIA644 specifies a recognition threshold of 100mV; therefore, the threshold V of the secondary comparator is designed accordingly. th It must be less than 100mV. Considering external noise, the value cannot be too small. With a margin, it can be set to 40mV to 80mV. In this embodiment, it is set to 80mV.

[0059] (4) Logic judgment circuit

[0060] Logic judgment circuit: It judges the outputs of the main comparator and the secondary comparator to realize the normal function output or failure protection function of the circuit.

[0061] Logic judgment circuits such as Figure 6 As shown, it includes resistor inverters INV1 and INV2, buffer BUFF1, capacitors C5 and C6, NOR gates NOR1, NOR2, NOR2, and NAND gate NAND1. V CMP Connect INV1 to the inputs of INV1 and NOR3. Connect the output of INV1 to the inputs of INV2 and BUFF1. Connect the output of INV2 to the input of NOR1 via capacitor C5. Connect the output of BUFF1 to the other input of NOR1 via capacitor C6. Connect the output of NOR1 to the input of NOR2. V CMP1 and V CMP2 Connect the inputs of NAND1 to NOR2, the output of NAND1 to another input of NOR2, the output of NOR2 to another input of NOR3, and the output of NOR3 to V. OUT Specifically, capacitors C5 and C6 are equal. INV2 charges and discharges capacitor C5, and BUFF1 charges and discharges capacitor C6. By adjusting the pull-up and pull-down capabilities of the pre-amplifier INV2 and the buffer BUFF1, the charging time of capacitors C5 and C6 is slow, and the power-off time is fast. Therefore, V CMP After each level transition, points A and B remain low for 600ns simultaneously, causing the NOR1 output to remain high for less than 600ns, ultimately resulting in the output V. OUT To follow V CMP The change occurs when point C goes low after 600ns, ultimately outputting V.OUT By V CMP1 and V CMP2 The decision has been made. The 600ns setting is adjustable and controlled by the pull-up / pull-down capability of the preamplifier.

[0062] The logic circuit restarts its count from 0 whenever the main comparator output flips, with a maximum counting window of 600ns. If the main comparator output remains unchanged for more than 600ns, it checks the secondary comparator output state. If the secondary comparator output V... CMP1 and V CMP2 When the external differential input is high (i.e., the external differential input is less than 80mV), the output V OUT To maintain a constant low level, thus providing circuit failure protection; if the secondary comparator outputs V CMP1 and V CMP2 With one high and one low, the output V OUT Follow V CMP The circuit operates normally with the changes. The 600ns time window is achieved through the charging and discharging of capacitors C5 and C6. By adjusting the pull-up and pull-down capabilities of the pre-amplifier, the charging time of capacitors C5 and C6 is slowed down while the power-down time is fast.

[0063] The embodiments described above are merely preferred embodiments of the present invention. Ordinary variations and substitutions made by those skilled in the art within the scope of the technical solution of the present invention should be included within the protection scope of the present invention.

Claims

1. An LVDS receiver circuit with a wide common-mode input range, characterized in that, It includes a common-mode converter circuit, a main comparator circuit, a secondary comparator circuit, and a logic judgment circuit; The common-mode converter circuit converts the differential signal from the external wide common-mode input into a signal with constant common-mode voltage and no attenuation of differential level; The main comparator circuit compares the signal output by the common-mode converter circuit, completes the data conversion from differential to single-ended, and outputs it to the logic judgment circuit. The secondary comparison circuit detects whether there is differential level attenuation in the signal output by the common-mode converter circuit, and outputs the detection signal to the logic judgment circuit. The logic judgment circuit judges the signals output by the main comparator and the secondary comparator to realize the normal function output or failure protection of the LVDS receiving circuit.

2. The LVDS receiving circuit with a wide common-mode input range according to claim 1, characterized in that, The common-mode converter circuit includes resistors R1, R2, R3, R4 and R5, capacitors C1, C2, C3 and C4, voltage operational amplifier OP1 and current operational amplifier OP2. One end of resistor R1 and one end of capacitor C1 are connected together to serve as the input terminal V of the common converter circuit. IA The other end of resistor R1 and the other end of capacitor C1, one end of resistor R2 and one end of capacitor C2 are connected together to form the output terminal V of the common-mode converter circuit. OA The other end of capacitor C2 is grounded; One end of resistor R3 and one end of capacitor C3 are connected together to serve as the input terminal V of the common converter circuit. IB The other end of resistor R3 and the other end of capacitor C3, one end of resistor R4 and one end of capacitor C4 are connected together to form the output terminal V of the common converter circuit. OB The other end of capacitor C4 is grounded; the other end of resistor R4 is connected to the other end of resistor R2 and the non-inverting input of voltage operational amplifier OP1 respectively. The inverting input of voltage operational amplifier OP1 is connected to a fixed reference level V. REF1 The output terminal is connected to the inverting input terminal of the current operational amplifier OP2 via resistor R5; The non-inverting input of the current operational amplifier OP2 is connected to a fixed reference level V. REF2 The output terminals are respectively connected to the output terminal V of the common-mode converter circuit. OA and V OB This creates negative feedback, causing the output V to... OA and V OB The common-mode level is adjusted to the reference level V. REF1 .

3. The LVDS receiving circuit with a wide common-mode input range according to claim 2, characterized in that, Resistors R1 and R3 have the same resistance value, and resistors R2 and R4 have the same resistance value. The resistance values ​​of resistors R2 and R4 are greater than the resistance values ​​of resistors R1 and R3, and their ratio is more than 10 times. Capacitors C1 and C3 have the same capacitance value, and capacitors C2 and C4 have the same capacitance value. Furthermore, the resistance ratio of resistor R1 to resistor R2 is equal to the capacitance ratio of capacitor C2 to capacitor C1.

4. The LVDS receiving circuit with a wide common-mode input range according to claim 2, characterized in that, The current operational amplifier OP2 includes NMOS transistors MN1-MN5, PMOS transistors MP1-MP5, and current source I. A and I B ; The source of PMOS transistor MP1 is simultaneously connected to the source of PMOS transistor MP2, the source of PMOS transistor MP3, and current source I. A One end of the PMOS transistor is connected to the power supply VDD. The gate of PMOS transistor MP1 is connected to the drain of PMOS transistor MP1, the gate of PMOS transistor MP2, the gate of PMOS transistor MP3, and the drain of NMOS transistor MN4. The drain of PMOS transistor MP2 is connected to the drain of NMOS transistor MN2 and then serves as the output terminal V of the common-mode converter circuit. OA The drain of PMOS transistor MP3 is connected to the drain of NMOS transistor MN3, and then serves as the output terminal V of the common-mode converter circuit. OB The gate of NMOS transistor MN4, the gate of NMOS transistor MN5, the drain of NMOS transistor MN5, and current source I. A One end is connected; The source of NMOS transistor MN4 is connected to the source of PMOS transistor MP4 as the input terminal V of the current operational amplifier. IN The source of MN5 is connected to the source of PMOS transistor MP5 and then connected to the reference voltage V. REF2 The source of NMOS transistor MN1 is simultaneously connected to the source of NMOS transistor MN2, the source of NMOS transistor MN3, and current source I. B One end of the transistor is connected to ground (GND). The gate of NMOS transistor MN1 is simultaneously connected to the drain of NMOS transistor MN1, the gate of NMOS transistor MN2, the gate of NMOS transistor MN3, and the drain of PMOS transistor MP4. The gate of PMOS transistor MP4 is connected to the gate of PMOS transistor MP5, the drain of PMOS transistor MP5, and current source I. B One end is connected.

5. The LVDS receiving circuit with a wide common-mode input range according to claim 4, characterized in that, PMOS transistors MP1, MP2, and MP3 have the same width-to-length ratio, and NMOS transistors MN1, MN2, and MN3 have the same width-to-length ratio. Therefore, the current flowing through PMOS transistors MP2 and MP3 is equal to the current flowing through PMOS transistor MP1, and the current flowing through NMOS transistors MN2 and MN3 is equal to the current flowing through NMOS transistor MN1.

6. The LVDS receiving circuit with a wide common-mode input range according to claim 1, characterized in that, The secondary comparator circuit includes comparator CMP1 and comparator CMP2, and the comparator circuits CMP1 and CMP2 are completely identical. One output of the common-mode converter circuit is connected to the non-inverting input of comparator CMP1 and the inverting input of comparator CMP2, while the other output is connected to the inverting input of comparator CMP1 and the non-inverting input of comparator CMP2. An offset voltage V is introduced into the inverting inputs of comparators CMP1 and CMP2. th For comparator CMP1, only when V OB >V OA +V th When V changes from high to low, the output changes from high to low; for comparator CMP2, this only happens when V... OA >V OB +V th When this happens, the output changes from high level to low level.

7. The LVDS receiving circuit with a wide common-mode input range according to claim 6, characterized in that, The bandwidth of the master comparator circuit is much greater than that of the slave comparator circuits CMP1 and CMP2, with a ratio of more than 100 times.

8. The LVDS receiving circuit with a wide common-mode input range according to claim 1, characterized in that, The logic judgment circuit includes resistor inverter INV1, resistor inverter INV2, buffer BUFF1, capacitor C1, capacitor C2, NOR gate NOR1, NOR gate NOR2, NOR gate NOR3, and NAND gate NAND1. The output of the main comparator circuit, V CMP Connect the input terminals of resistor inverter INV1 and NOR gate NOR3 respectively. Connect the output terminal of resistor inverter INV1 to the input terminal of resistor inverter INV2 and the input terminal of buffer BUFF1 respectively. Connect the output terminal of resistor inverter INV2 to capacitor C5 and one input terminal of NOR gate NOR1 respectively. Connect the output terminal of buffer BUFF1 to capacitor C6 and the other input terminal of NOR gate NOR1 respectively. Connect the output terminal of NOR gate NOR1 to one input terminal of NOR gate NOR2. From the comparator output V CMP1 and V CMP2 Connect the two inputs of NAND gate NAND1 to the other input of NOR gate NOR2. Connect the output of NAND gate NAND1 to the other input of NOR gate NOR3. Connect the output of NOR gate NOR3 to V. OUT .

9. The LVDS receiving circuit with a wide common-mode input range according to claim 8, characterized in that, In the logic judgment circuit, capacitors C5 and C6 have the same capacitance value.

10. The LVDS receiving circuit with a wide common-mode input range according to claim 8, characterized in that, The output of the main comparator circuit, V CMP When a level flip occurs, the logic judgment circuit restarts the timing from 0, with the timing window being the set duration. If the main comparator output level remains unchanged for more than the timing window, the secondary comparator output state is checked. If the secondary comparator output V... CMP1 and V CMP2 When it is high, the output V OUT A constant low level is used to implement LVDS receiver circuit failure protection; if the secondary comparator output V CMP1 and V CMP2 It consists of one high level and one low level, outputting V. OUT Follow V CMP The changes enable the LVDS receiver circuit to function normally and output correctly.

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