Phase inverter, phase inverter module and control method of phase inverter

Abstract

The invention discloses an inverter, an inverter module and a control method of the inverter, the inverter comprises a first transistor and a second transistor, the grid electrode of the first transistor is connected to a first input end, and the grid electrode of the second transistor is connected to a second input end; a first node is arranged between the first input end and the grid electrode of the first transistor, and a second node is arranged between the second input end and the grid electrode of the second transistor; the bias temperature instability recovery unit is respectively connected to a first node and a second node and is used for enabling the first node and the second node to be connected when the first transistor and the second transistor are in a working state; and when the first transistor and the second transistor are in a recovery state, the first node and the second node are disconnected, a first recovery voltage signal is provided for the first node, and a second recovery voltage signal is provided for the second node. The inverter is capable of recovering bias temperature instability of the inverter.

Description

Technical Field

[0001] This disclosure relates to the field of integrated circuits, and more particularly to an inverter, an inverter module, and a control method for an inverter. Background Technology

[0002] Bias temperature instability (BTI) refers to the degradation effects on the electrical characteristics of a transistor under certain temperature conditions when a bias voltage is applied to the transistor gate, such as threshold voltage drift and a decrease in saturation current. Bias temperature instability includes negative bias temperature instability (NBTI) in PMOS transistors and positive bias temperature instability (PBTI) in NMOS transistors.

[0003] Bias temperature instability recovery involves applying a preset bias voltage to a transistor to restore its performance to a certain extent. However, the bias temperature instability recovery of inverters, which are devices that share gates between PMOS and NMOS transistors, requires further improvement. Summary of the Invention

[0004] This disclosure provides an inverter, an inverter module, and an inverter control method, which can improve the recovery of the inverter's bias temperature instability and enhance the inverter's electrical performance.

[0005] To address the above problems, this disclosure provides an inverter, which includes:

[0006] A first transistor and a second transistor with different conductivity types are provided, wherein the gate of the first transistor is connected to a first input terminal, and the gate of the second transistor is connected to a second input terminal; wherein a first node is provided between the first input terminal and the gate of the first transistor, and a second node is provided between the second input terminal and the gate of the second transistor.

[0007] A bias temperature instability recovery unit is connected to the first node and the second node respectively. It is used to make the first node and the second node a circuit when the first transistor and the second transistor are in the working state; and to make the first node and the second node an open circuit when the first transistor and the second transistor are in the recovery state. It also provides a first recovery voltage signal to the first node and a second recovery voltage signal to the second node.

[0008] Optionally, the bias temperature instability recovery unit includes a third transistor connected between the first node and the second node, as well as a first switch connected to the first node and a second switch connected to the second node.

[0009] The third transistor is used to control the switching between the first node and the second node based on the states of the first transistor and the second transistor; the first switch is used to provide a first recovery voltage signal to the first node when the first transistor and the second transistor are in a recovery state; the second switch is used to provide a second recovery voltage signal to the second node when the first transistor and the second transistor are in a recovery state.

[0010] Optionally, the source of the third transistor is connected to the first node, the drain is connected to the second node, and the gate is connected to the first control terminal;

[0011] The first control terminal is used to provide a first control signal, wherein the first control signal is used to control the third transistor to be in a conducting state when the first transistor and the second transistor are in an operating state, and to control the third transistor to be in a cut-off state when the first transistor and the second transistor are in a recovery state.

[0012] Optionally, one end of the first switching transistor is connected to the first node, and the other end is connected to the first recovery voltage terminal, which is used to provide a first recovery voltage signal; one end of the second switching transistor is connected to the second node, and the other end is connected to the second recovery voltage terminal, which is used to provide a second recovery voltage signal.

[0013] When the first transistor and the second transistor are in the working state, the first switch is turned off; when the first transistor and the second transistor are in the recovery state, the first switch is turned on to provide a first recovery voltage signal to the first transistor.

[0014] When the first transistor and the second transistor are in the operating state, the second switch is turned off; when the first transistor and the second transistor are in the recovery state, the second switch is turned on to provide a second recovery voltage signal to the second transistor.

[0015] Optionally, the first switching transistor is a first diode, and the second switching transistor is a second diode;

[0016] The first transistor is a PMOS transistor, the anode of the first diode is connected to the first recovery voltage terminal, and the cathode is connected to the first node; the first recovery voltage terminal provides a first recovery voltage signal when the first transistor and the second transistor are in the recovery state, and provides a first shutdown signal when the first transistor and the second transistor are in the working state, the first recovery voltage terminal is used to turn off the first diode;

[0017] The first transistor is an NMOS transistor, the positive terminal of the second diode is connected to the second node, and the negative terminal is connected to the second recovery voltage terminal; the second recovery voltage terminal provides a second recovery voltage signal when the first transistor and the second transistor are in the recovery state, and provides a second shutdown signal when the first transistor and the second transistor are in the working state, the second recovery voltage terminal is used to turn off the second diode.

[0018] Optionally, the bias temperature instability recovery unit further includes a fourth transistor connected to the third node and the fourth node; the third node is the node between the first input terminal and the gate of the first transistor, and the fourth node is the node between the second input terminal and the gate of the second transistor; the fourth transistor is used to control the on / off state between the third node and the fourth node based on the states of the first transistor and the second transistor.

[0019] Optionally, the source of the fourth transistor is connected to the third node, the drain is connected to the fourth node, and the gate is connected to the second control terminal;

[0020] The second control terminal is used to provide a second control signal, wherein the second control signal is used to control the fourth transistor to be in the on state when the first transistor and the second transistor are in the working state, and to control the fourth transistor to be in the off state when the first transistor and the second transistor are in the recovery state.

[0021] Optionally, the well region where the third transistor is located is isolated from the well regions where the first transistor and the second transistor are located; the well region where the fourth transistor is located is isolated from the well regions where the first transistor and the second transistor are located.

[0022] Optionally, the first transistor is a PMOS transistor, and the first recovery voltage signal is used to enable the first transistor to perform negative bias temperature instability recovery.

[0023] The second transistor is an NMOS transistor, and the second recovery voltage signal is used to enable the second transistor to perform positive bias temperature instability recovery;

[0024] The source of the first transistor is connected to a first voltage source, and the drain is connected to a first output terminal; the source of the second transistor is connected to a second voltage source, and the drain is connected to a second output terminal.

[0025] This disclosure also provides a method for controlling an inverter, the inverter including a first transistor and a second transistor with different conductivity types, the gate of the first transistor being connected to a first input terminal, and the gate of the second transistor being connected to a second input terminal, wherein a first node is formed between the first input terminal and the gate of the first transistor, and a second node is formed between the second input terminal and the gate of the second transistor, the method including:

[0026] When the first transistor and the second transistor are in the working state, a path is established between the first node and the second node;

[0027] When the first transistor and the second transistor are in the recovery state, the circuit between the first node and the second node is controlled to be open, and a first recovery voltage signal is provided to the first node and a second recovery voltage signal is provided to the second node.

[0028] This disclosure also provides an inverter module, including: a plurality of inverters connected in sequence as described above;

[0029] In the direction of signal transmission path, the first output terminal of the previous inverter is connected to the second input terminal of the next inverter, and the second output terminal of the previous inverter is connected to the first input terminal of the next inverter.

[0030] Compared with the prior art, the technical solution of the present disclosure has the following advantages:

[0031] The inverter in this embodiment employs a bias temperature instability recovery unit between a first node connected between the first input terminal and the gate of the first transistor and a second node connected between the second input terminal and the gate of the second transistor. When the first transistor and the second transistor are in the operating state, the first node and the second node are connected as a circuit, so that the gates of the first transistor and the second transistor share the gate signals of the first input terminal and the second input terminal. When the first transistor and the second transistor are in the recovery state, the first node and the second node are disconnected, thereby isolating the gates of the first transistor and the second transistor. A first recovery voltage signal is provided to the first node so that the gate of the first transistor performs bias temperature instability recovery based on the first recovery voltage signal, and a second recovery voltage signal is provided to the second node so that the gate of the second transistor performs bias temperature instability recovery based on the second recovery voltage signal.

[0032] Compared to the method of simultaneously applying the recovery voltage signal to the gate of the first transistor and the gate of the second transistor for bias instability recovery, the embodiments of this disclosure can avoid the problem of exacerbating the bias temperature instability of the other transistor when performing bias temperature instability recovery on either the first transistor or the second transistor with shared gates in the inverter.

[0033] Furthermore, when the first transistor and the second transistor are in the working state, a path is established between the first node and the second node so that the gates of the first transistor and the second transistor share the gate signals of the first input terminal and the second input terminal. When the first transistor and the second transistor are in the recovery state, a circuit is established between the first node and the second node in the inverter, thereby isolating the gates of the first transistor and the second transistor. A first recovery voltage signal and a second recovery voltage signal are applied to the gates of the first transistor and the second transistor, respectively, thereby simultaneously realizing the recovery of the bias temperature instability of the first transistor and the second transistor, thus improving the recovery of the bias temperature instability of the inverter, enhancing the electrical performance of the inverter, and slowing down the aging rate of the inverter. Attached Figure Description

[0034] Figure 1 This is a schematic diagram of the frame structure of an embodiment of the inverter provided in this disclosure.

[0035] Figure 2 This is a schematic diagram of the circuit structure of an embodiment of the inverter provided in this disclosure.

[0036] Figure 3 This is an optional flowchart of a control method for an inverter provided by the technical solution disclosed herein;

[0037] Figure 4 This is a circuit control diagram of the inverter provided in this disclosure during its working state;

[0038] Figure 5 This is a circuit control diagram of the inverter in the recovery state provided by the technical solution disclosed herein. Detailed Implementation

[0039] The technical solutions of the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this disclosure, and not all of them. Based on the embodiments of this disclosure, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the scope of protection of this disclosure.

[0040] Currently, bias temperature instability (NBTI) recovery circuits cannot simultaneously recover the bias temperature instability of the two transistors sharing a gate in an inverter. The inventors, after research, believe this is because the two transistors sharing a gate in an inverter are transistors of different conductivity types, and their corresponding recovery voltage signals are different. Therefore, applying recovery voltage signals to the gates of both transistors simultaneously for bias instability recovery cannot achieve simultaneous recovery of the bias instability of both transistors. For example, applying a recovery voltage signal to the gate to recover the NBTI (negative bias temperature instability) of a PMOS transistor will lead to a more severe PBTI (positive bias temperature instability) problem in an NMOS transistor, and vice versa. This severely affects the performance and lifespan of the device.

[0041] To address the aforementioned problems, this disclosure provides an inverter, comprising: a first transistor and a second transistor with different conductivity types, wherein the gate of the first transistor is connected to a first input terminal, and the gate of the second transistor is connected to a second input terminal; wherein a first node is formed between the first input terminal and the gate of the first transistor, and a second node is formed between the second input terminal and the gate of the second transistor; a bias temperature instability recovery unit is connected to the first node and the second node respectively, for establishing a circuit between the first node and the second node when the first transistor and the second transistor are in an operating state; and establishing an open circuit between the first node and the second node when the first transistor and the second transistor are in a recovery state, while simultaneously providing a first recovery voltage signal to the first node and a second recovery voltage signal to the second node.

[0042] The inverter in this embodiment employs a bias temperature instability recovery unit connected to a first node between the first input terminal and the gate of the first transistor, and a second node between the second input terminal and the gate of the second transistor. When the first transistor and the second transistor are in the operating state, the first node and the second node are connected as a circuit, allowing the gates of the first transistor and the second transistor to share the gate signals of the first input terminal and the second input terminal. When the first transistor and the second transistor are in the recovery state, the first node and the second node are disconnected, thereby isolating the gates of the first transistor and the second transistor. A first recovery voltage signal is provided to the first node, enabling the gate of the first transistor to perform bias temperature instability recovery based on the first recovery voltage signal. A second recovery voltage signal is provided to the second node, enabling the gate of the second transistor to perform bias temperature instability recovery based on the second recovery voltage signal.

[0043] Compared to the method of simultaneously applying the recovery voltage signal to the gate of the first transistor and the gate of the second transistor for bias instability recovery, the embodiments of this disclosure can avoid the problem of exacerbating the bias temperature instability of the other transistor when performing bias temperature instability recovery on either the first transistor or the second transistor with shared gates in the inverter.

[0044] Furthermore, when the first transistor and the second transistor are in the working state, a path is made between the first node and the second node so that the gates of the first transistor and the second transistor share the gate signals of the first input terminal and the second input terminal. When the first transistor and the second transistor are in the recovery state, a circuit is made between the first node and the second node in the inverter, thereby isolating the gates of the first transistor and the second transistor. A first recovery voltage signal and a second recovery voltage signal are applied to the gates of the first transistor and the second transistor, respectively, thereby simultaneously realizing the recovery of the bias temperature instability of the first transistor and the second transistor, improving the electrical performance of the inverter, and slowing down the aging speed of the inverter.

[0045] To make the above-mentioned objects, features and advantages of this disclosure more apparent and understandable, specific embodiments of this disclosure will be described in detail below with reference to the accompanying drawings.

[0046] First, it should be noted that in the embodiments of this disclosure, the recovery state refers to the state of the transistor when performing bias instability recovery; the working state refers to the state of the transistor when different voltage signals are applied to the gate and source of the transistor, so that the transistor is turned on when the voltage difference between its gate and source meets the threshold voltage, and turned off when the voltage difference between its gate and source does not meet the threshold voltage.

[0047] Figure 1 This is a schematic diagram of the frame structure of an embodiment of the inverter provided in this disclosure. Figure 2 This is a schematic diagram of the circuit structure of an embodiment of the inverter provided in this disclosure.

[0048] Reference Figure 1 and Figure 2 An inverter includes a first transistor P1 and a second transistor N1 with different conductivity types. The gate of the first transistor P1 is connected to a first input terminal, and the gate of the second transistor N1 is connected to a second input terminal. A first node A1 is located between the first input terminal and the gate of the first transistor, and a second node B1 is located between the second input terminal and the gate of the second transistor.

[0049] A bias temperature instability recovery unit is connected to the first node A1 and the second node B1 respectively. When the first transistor P1 and the second transistor N1 are in the working state, it makes the first node A1 and the second node B1 a closed circuit; when the first transistor P1 and the second transistor N1 are in the recovery state, it makes the first node A1 and the second node B1 an open circuit. It also provides a first recovery voltage signal to the first node A1 and a second recovery voltage signal to the second node B1.

[0050] It is understood that a first transistor and a second transistor with different conductivity types are used to operate as an inverter. The gate of the first transistor is connected to the first input terminal, the source is connected to the first voltage source, and the drain is connected to the first output terminal; the gate of the second transistor is connected to the second input terminal, the source is connected to the second voltage source, and the drain is connected to the second output terminal.

[0051] In an optional example, the first transistor can be a PMOS transistor, and correspondingly, the first recovery voltage signal is used to enable the first transistor to perform negative bias temperature instability recovery; the second transistor can be an NMOS transistor, and the second recovery voltage signal is used to enable the second transistor to perform positive bias temperature instability recovery. Accordingly, the first voltage source connected to the source of the first transistor can be a power supply voltage signal Vdd, the input signal of the first input terminal connected to the gate can be Input_N, and the first output terminal connected to the drain can be Outut_P; the second voltage source connected to the source of the second transistor can be a ground voltage signal Vss, the input signal of the second input terminal connected to the gate can be Input_P, and the second output terminal connected to the drain can be Outut_N. The power supply voltage signal Vdd can provide a stable voltage supply to the device, for example, a 1V power supply; the ground voltage signal Vss is used to provide a ground voltage to the device, i.e., always maintaining 0V.

[0052] The bias temperature instability recovery unit is used to create a path between the first node and the second node when the first transistor and the second transistor are in the working state, so that the gates of the first transistor and the second transistor share the gate signals of the first input terminal and the second input terminal.

[0053] When the first transistor and the second transistor are in the recovery state, the bias temperature instability recovery unit makes the first node and the second node open circuit, thereby isolating the gates of the first transistor and the second transistor. Furthermore, it provides a first recovery voltage signal and a second recovery voltage signal through the first node and the second node, respectively, so that both the first transistor and the second transistor can perform bias temperature instability recovery, thereby improving the electrical performance of the inverter and slowing down the aging rate of the inverter.

[0054] In a specific example, the bias temperature instability recovery unit may include a third transistor connected between the first node and the second node, as well as a first switch connected to the first node and a second switch connected to the second node.

[0055] The third transistor is used to control the connection / disconnection between the first node and the second node based on the states of the first transistor and the second transistor. When the first transistor and the second transistor are in the operating state, the third transistor can be in the conducting state, thereby creating a circuit between the first node and the second node; when the first transistor and the second transistor are in the restoring state, the third transistor can be in the cut-off state, thereby creating an open circuit between the first node and the second node.

[0056] In a specific example, the source of the third transistor can be connected to the first node, the drain can be connected to the second node, and the gate can be connected to the first control terminal; the first control terminal is used to provide a first control signal, wherein the first control signal is used to control the third transistor to be in the on state when the first transistor and the second transistor are in the working state, and to control the third transistor to be in the off state when the first transistor and the second transistor are in the recovery state.

[0057] In specific examples, refer to Figure 2 As shown, the third transistor can be a PMOS transistor P2, and the first control signal can be labeled Vpg. Correspondingly, Vpg can provide a turn-on voltage (e.g., 0V) when the first and second transistors are in the operating state to control the third transistor to conduct, and a turn-off voltage (e.g., 2V) when the first and second transistors are in the recovery state to control the third transistor to turn off. The body region of the third transistor can continuously receive a third body region voltage signal Vpb (e.g., 1V) to ensure the normal operation of the third transistor.

[0058] In an optional example, the cutoff voltage (e.g., 2V) provided by the first control signal can control the third transistor to turn off while simultaneously enabling the third transistor to recover from bias temperature instability.

[0059] In a further alternative example, the well region where the third transistor is located is isolated from the well region where the first transistor is located. For example, when the first transistor and the second transistor are in the same well region, the well region where the third transistor is located is isolated from the well regions where the first transistor and the second transistor are located; when the first transistor and the second transistor are in different well regions, the well region where the third transistor is located is isolated from the well regions where the first transistor and the second transistor are located, respectively.

[0060] This is because when the third transistor and the first or second transistor are transistors of the same conductivity type, the conductivity type of their corresponding well regions is the same (for example, the third transistor P2 and the first transistor P1 are PMOS, and their corresponding well regions are both N-type semiconductors). If two well regions of the same type are connected and different well region voltages are applied, a large static leakage current will occur, and the actual voltage of the well region will not be in place. When the third transistor and the first or second transistor are transistors of different conductivity types, the conductivity types of their corresponding well regions are different. Accordingly, if two different types of well regions are connected, and a high voltage is applied to one well region and a low voltage is applied to the other (for example, a higher voltage is applied to the P region and a lower voltage is applied to the N region), a large static leakage current will also occur, and the actual voltage of the well region will not be in place.

[0061] In view of this, the embodiments of this disclosure isolate the well region where the third transistor is located from the well regions where the first transistor and the second transistor are located, thereby avoiding the above-mentioned phenomenon.

[0062] The first switch is used to provide a first recovery voltage signal to the first node when the first transistor and the second transistor are in the recovery state; the second switch is used to provide a second recovery voltage signal to the second node when the first transistor and the second transistor are in the recovery state.

[0063] One end of the first switch is connected to the first node, and the other end is connected to the first recovery voltage terminal, which provides the first recovery voltage signal. Accordingly, when the first transistor and the second transistor are in the operating state, the first switch is turned off; when the first transistor and the second transistor are in the recovery state, the first switch is turned on to provide the first recovery voltage signal to the first transistor.

[0064] The first switching transistor can be either a MOS transistor or a diode. Using a diode as the first switching transistor simplifies the circuit structure. In this example, a diode is used as the first switching transistor for illustration. (Refer to...) Figure 2 The first switching transistor can be the first diode D1.

[0065] In this configuration, when the first transistor is a PMOS transistor, the anode of the first diode D1 is connected to the first recovery voltage terminal Vpr, and the cathode is connected to the first node. Accordingly, the first recovery voltage terminal Vpr can provide a first recovery voltage signal (e.g., 1V) when the first transistor and the second transistor are in a recovery state. At this time, the first switch is turned on, allowing the first recovery voltage signal to be transmitted through the first node to the gate of the first transistor, enabling the first transistor to perform negative bias temperature instability recovery.

[0066] It should be noted that when the first transistor and the second transistor are in the working state, the first recovery voltage terminal Vpr can provide a first shutdown signal, for example, it can be 0V. This first shutdown signal is used to turn off the first diode D1, thereby preventing the branch line from affecting the normal operation of the inverter.

[0067] When the first switching transistor is a MOSFET, its source can be connected to the first recovery voltage terminal, its drain can be connected to the first node, and its gate can be connected to the corresponding first switching transistor control terminal. Based on this control terminal, the first switching transistor is controlled to turn off when the first and second transistors are in the operating state and to turn on when the first and second transistors are in the recovery state. In this example, the first recovery voltage terminal can always output a first recovery voltage signal, or it can change based on the states of the first and second transistors. That is, it can provide a first recovery voltage signal when the first and second transistors are in the recovery state and provide an invalid recovery signal, such as 0V, when the first and second transistors are in the operating state.

[0068] One end of the second switch is connected to the second node, and the other end is connected to the second recovery voltage terminal, which provides the second recovery voltage signal. Accordingly, when the first and second transistors are in the operating state, the second switch is off; when the first and second transistors are in the recovery state, the second switch is on to provide the second recovery voltage signal to the second transistor.

[0069] The second switching transistor can be either a MOS transistor or a diode. Using a diode as the second switching transistor simplifies the circuit structure. In this example, a diode is used as the second switching transistor for illustration. (Refer to...) Figure 2 The second switching transistor can be the second diode D2.

[0070] In this configuration, when the second transistor is an NMOS transistor, the anode of the second diode D2 is connected to the second node, and the cathode is connected to the second recovery voltage terminal Vnr. Accordingly, the second recovery voltage terminal Vnr can provide a second recovery voltage signal (e.g., -1V) when both the first and second transistors are in a recovery state. At this time, the second switch is turned on, allowing the second recovery voltage signal to be transmitted through the second node to the gate of the second transistor, enabling the second transistor to perform positive bias temperature instability recovery.

[0071] It should be noted that when the first transistor and the second transistor are in the working state, the second recovery voltage terminal Vnr can provide a second shutdown signal, for example, it can be 1V. The second shutdown signal is used to turn off the second diode, thereby preventing the branch line from affecting the normal operation of the inverter.

[0072] When the second switch is a MOSFET, its source can be connected to the second node, its drain to the second recovery voltage terminal, and its gate to the corresponding second switch control terminal. Based on this control terminal, the second switch is controlled to turn off when the first and second transistors are in the operating state and to turn on when they are in the recovery state. In this example, the second recovery voltage terminal can either always output a second recovery voltage signal, or it can change based on the states of the first and second transistors; that is, it can provide a second recovery voltage signal when the first and second transistors are in the recovery state and a second turn-off signal when they are in the operating state.

[0073] In a further example, the bias temperature instability recovery unit in this embodiment may further include a fourth transistor connected to the third node A2 and the fourth node B2, the fourth transistor having a different conductivity type from the third transistor, for further controlling the on / off state between the third node and the fourth node based on the states of the first transistor and the second transistor.

[0074] Under normal operating conditions, the gate signals of the first transistor P1 and the second transistor N1 switch back and forth between "0" and "1". Considering that a single third transistor may be used for signal transmission, transmission defects may occur. For example, if the third transistor is a PMOS transistor P2, a "0" signal transmission defect may occur; if the third transistor is an NMOS transistor (not shown in the figure), a "1" signal transmission defect may occur. Therefore, this embodiment of the present disclosure provides a fourth transistor with a different conductivity type than the third transistor in the bias temperature instability recovery unit. This utilizes a pair of transistors with different conductivity types (such as PMOS and NMOS) to perform complementary transmission of "1" and "0" signals, ensuring accurate signal transmission.

[0075] Specifically, in the inverter, the third node A2 is the node between the first input terminal and the gate of the first transistor, and the fourth node B2 is the node between the second input terminal and the gate of the second transistor. The third node A2 can be the same node as the first node A1, or it can be a different node on the transmission line between the first input terminal and the gate of the first transistor. Similarly, the fourth node B2 can be the same node as the second node B1, or it can be a different node on the transmission line between the second input terminal and the gate of the second transistor.

[0076] The fourth transistor can control the on / off state between the third node and the fourth node simultaneously with the third transistor, based on the states of the first and second transistors. Specifically, when the first and second transistors are in the working state, the fourth transistor can be in the conducting state, thereby creating a path between the third node and the fourth node. When the first and second transistors are in the restoring state, the fourth transistor can be in the cut-off state, thereby creating an open circuit between the third node and the fourth node.

[0077] In a specific example, the source of the fourth transistor can be connected to the third node, the drain can be connected to the fourth node, and the gate can be connected to the second control terminal; the second control terminal is used to provide a second control signal, wherein the second control signal is used to control the fourth transistor to be in the on state when the first transistor and the second transistor are in the working state, and to control the fourth transistor to be in the off state when the first transistor and the second transistor are in the recovery state.

[0078] In specific examples, refer to Figure 2 As shown, the fourth transistor can be an NMOS transistor N2, and the second control signal can be labeled Vng. Accordingly, Vng can provide an on-state voltage, such as 1V, to control the fourth transistor to turn on when the first transistor and the second transistor are in the working state, and provide an off-state voltage, such as -2V, to control the fourth transistor to turn off when the first transistor and the second transistor are in the recovery state.

[0079] In an optional example, the cutoff voltage (e.g., -2V) provided by the second control signal can control the fourth transistor to turn off while simultaneously enabling the fourth transistor to recover from bias temperature instability.

[0080] Specifically, the body region of the fourth transistor can continuously receive the fourth body region voltage signal Vnb, thereby ensuring the normal operation of the fourth transistor. Specifically, when the first and second transistors are in the operating state, the fourth body region voltage signal Vnb can be 0V; when the first and second transistors are in the recovery state, the fourth body region voltage signal Vnb can be -1V.

[0081] In a further alternative example, the well region where the fourth transistor is located is isolated from the well regions where the first transistor and the second transistor are located. For example, when the first transistor and the second transistor are in the same well region, the well region where the fourth transistor is located is isolated from the well regions where the first transistor and the second transistor are located; when the first transistor and the second transistor are in different well regions, the well region where the fourth transistor is located is isolated from the well regions where the first transistor and the second transistor are located, respectively.

[0082] This is because when the fourth transistor is a transistor of the same conductivity type as the first or second transistor, the conductivity type of their corresponding well regions is the same (for example, the third transistor P2 and the first transistor P1 are PMOS, and their corresponding well regions are both N-type semiconductors). If two well regions of the same type are connected and different well region voltages are applied, a large static leakage current will occur, and the actual voltage of the well region will not be in place. When the fourth transistor is a transistor of a different conductivity type than the first or second transistor, the conductivity types of their corresponding well regions are different. Accordingly, if two different types of well regions are connected, and a high voltage is applied to one well region and a low voltage is applied to the other (for example, a higher voltage is applied to the P region and a lower voltage is applied to the N region), a large static leakage current will also occur, and the actual voltage of the well region will not be in place.

[0083] In view of this, the embodiments of this disclosure isolate the well region where the fourth transistor is located from the well regions where the first transistor and the second transistor are located, thereby avoiding the above-mentioned phenomenon.

[0084] The control method for the inverter is described in further detail below. This control method can be based on the control flow of the inverter structure provided in the above embodiments. Specifically, refer to... Figure 3 The diagram shows an optional flowchart of a control method for an inverter, which may include:

[0085] Step S100: When the first transistor and the second transistor are in the working state, control the first node and the second node to be connected.

[0086] Wherein, the first node is the node between the first input terminal and the gate of the first transistor, and the second node is the node between the second input terminal and the gate of the second transistor.

[0087] When the first transistor and the second transistor are in the working state, the first node and the second node are controlled to be a path, so that the gates of the first transistor and the second transistor share the gate signals of the first input terminal and the second input terminal.

[0088] In specific examples, refer to Figure 4 The circuit control diagram of the inverter in operation shown can control the third transistor P2 to be in the on state. For example, the first control signal Vpg provided to the gate of the third transistor can be the turn-on voltage of the third transistor (such as 0V), so that the first transistor and the second transistor behave as a shared gate.

[0089] Furthermore, the first switch D1 and the second switch D2 can be controlled to be in the off state to avoid the corresponding branch lines affecting the normal operation of the inverter. Specifically, when the first switch can be the first diode D1 and the second switch can be the second diode D2, the first recovery voltage terminal Vpr of the positive terminal of the first diode D1 can be controlled to provide a first shutdown signal (e.g., 0V), and the second recovery voltage terminal Vnr of the negative terminal of the second diode D2 can be controlled to provide a second shutdown signal (e.g., 1V).

[0090] When a fourth transistor N2 is provided, the fourth transistor N2 can be controlled to be in the on state. For example, the second control signal Vng provided to the gate of the fourth transistor can be the turn-on voltage of the fourth transistor (such as 1V), so that the first transistor and the second transistor behave as a shared gate.

[0091] Step S110: When the first transistor and the second transistor are in the recovery state, control the first node and the second node to be disconnected, and provide a first recovery voltage signal to the first node and a second recovery voltage signal to the second node;

[0092] When the first transistor and the second transistor are in the recovery state, the first node and the second node are controlled to be disconnected, thereby isolating the gates of the first transistor and the second transistor. Furthermore, the first recovery voltage signal and the second recovery voltage signal are provided to the device through the first node and the second node, so that both the first transistor and the second transistor can perform bias temperature instability recovery, thereby improving the electrical performance of the inverter and slowing down the aging rate of the inverter.

[0093] In specific examples, refer to Figure 5 The circuit control diagram of the inverter in the recovery state shown can control the third transistor P2 to be in the off state. For example, the first control signal Vpg provided to the gate of the third transistor can be the off voltage of the third transistor (such as 2V) so that the gates of the first transistor and the second transistor are isolated.

[0094] Furthermore, the first and second switching transistors can be controlled to be in the ON state to provide a first recovery voltage signal to the first transistor at the first node and a second recovery voltage signal to the second transistor at the second node. Specifically, when the first switching transistor is the first diode D1 and the second switching transistor is the second diode D2, the first recovery voltage terminal Vpr of the anode of the first diode D1 can be controlled to provide a first recovery voltage signal (e.g., 1V), and the second recovery voltage terminal Vnr of the cathode of the second diode D2 can be controlled to provide a second recovery voltage signal (e.g., -1V). This allows the first transistor to perform negative bias temperature instability recovery based on the first recovery voltage signal, and the second transistor to perform negative bias temperature instability recovery based on the second recovery voltage signal.

[0095] When a fourth transistor N2 is provided, the fourth transistor N2 can be controlled to be in the off state. For example, the second control signal Vng provided to the gate of the fourth transistor can be the cutoff voltage of the fourth transistor (such as -2V) so that the gates of the first transistor and the second transistor are isolated, thereby performing corresponding bias temperature instability recovery respectively.

[0096] In a further example, embodiments of this disclosure also provide an inverter module comprising a plurality of inverters connected in sequence, wherein the input of one inverter is connected to the output of another inverter. Specifically, in terms of the signal transmission path direction, the first output terminal Output_P of the preceding inverter can be connected to the second input terminal Input_P of the following inverter (see...). Figure 5 (The dashed line with a triangle in the middle) The second output terminal Output_N of the previous inverter can be connected to the first input terminal Input_N of the next inverter (see... Figure 5 (A dotted line with a circle in the middle).

[0097] Understandably, when the inverter is in the off state (i.e., in the recovery state), the first diode D1 keeps the voltages at the first node A1, the third node A2, and the first input terminal Input_N at 1V. If the first input terminal Input_N is connected to the first output terminal Output_P of the previous stage inverter, then in the first transistor P1 of the previous stage inverter, a high voltage (1V) is applied to the drain of the P-type transistor and a low voltage (0V) is applied to the body of the N-type transistor, resulting in leakage current from the drain to the body. This causes voltage loss at the first node A1 and the third node A2, resulting in insufficient voltage application. However, in this disclosure, the first input terminal Input_N can only be connected to the second output terminal Output_N of the previous stage inverter, thus avoiding this defect.

[0098] Similarly, in this disclosure, the second input terminal Input_P is connected to the first output terminal Output_P of the previous stage inverter, thereby preventing leakage of the drain of the first transistor or the drain of the second transistor due to the circuit structure in which they are located.

[0099] For more information on the control methods of inverters, please refer to the aforementioned description of inverters, which will not be repeated here.

[0100] While the above disclosure is provided, it is not limited thereto. Any person skilled in the art may make various alterations and modifications without departing from the spirit and scope of this disclosure; therefore, the scope of protection of this disclosure shall be determined by the scope defined in the claims.

Claims

1. An inverter, characterized in that, include: A first transistor and a second transistor with different conductivity types are provided, wherein the gate of the first transistor is connected to a first input terminal, and the gate of the second transistor is connected to a second input terminal; wherein a first node is provided between the first input terminal and the gate of the first transistor, and a second node is provided between the second input terminal and the gate of the second transistor. A bias temperature instability recovery unit is connected to the first node and the second node respectively. It is used to make the first node and the second node a circuit when the first transistor and the second transistor are in the working state; and to make the first node and the second node an open circuit when the first transistor and the second transistor are in the recovery state. It also provides a first recovery voltage signal to the first node and a second recovery voltage signal to the second node.

2. The inverter as described in claim 1, characterized in that, The bias temperature instability recovery unit includes a third transistor connected between the first node and the second node, as well as a first switch connected to the first node and a second switch connected to the second node. The third transistor is used to control the switching between the first node and the second node based on the states of the first transistor and the second transistor; the first switch is used to provide a first recovery voltage signal to the first node when the first transistor and the second transistor are in a recovery state; the second switch is used to provide a second recovery voltage signal to the second node when the first transistor and the second transistor are in a recovery state.

3. The inverter as described in claim 2, characterized in that, The source of the third transistor is connected to the first node, the drain is connected to the second node, and the gate is connected to the first control terminal. The first control terminal is used to provide a first control signal, wherein the first control signal is used to control the third transistor to be in a conducting state when the first transistor and the second transistor are in an operating state, and to control the third transistor to be in a cut-off state when the first transistor and the second transistor are in a recovery state.

4. The inverter as described in claim 2, characterized in that, One end of the first switching transistor is connected to the first node, and the other end is connected to the first recovery voltage terminal, which is used to provide the first recovery voltage signal; one end of the second switching transistor is connected to the second node, and the other end is connected to the second recovery voltage terminal, which is used to provide the second recovery voltage signal. When the first transistor and the second transistor are in the working state, the first switch is turned off; when the first transistor and the second transistor are in the recovery state, the first switch is turned on to provide a first recovery voltage signal to the first transistor. When the first transistor and the second transistor are in the operating state, the second switch is turned off; when the first transistor and the second transistor are in the recovery state, the second switch is turned on to provide a second recovery voltage signal to the second transistor.

5. The inverter as described in claim 4, characterized in that, The first switching transistor is a first diode, and the second switching transistor is a second diode; The first transistor is a PMOS transistor, the anode of the first diode is connected to the first recovery voltage terminal, and the cathode is connected to the first node; the first recovery voltage terminal provides a first recovery voltage signal when the first transistor and the second transistor are in the recovery state, and provides a first shutdown signal when the first transistor and the second transistor are in the working state, the first recovery voltage terminal is used to turn off the first diode; The first transistor is an NMOS transistor, the positive terminal of the second diode is connected to the second node, and the negative terminal is connected to the second recovery voltage terminal; the second recovery voltage terminal provides a second recovery voltage signal when the first transistor and the second transistor are in the recovery state, and provides a second shutdown signal when the first transistor and the second transistor are in the working state, the second recovery voltage terminal is used to turn off the second diode.

6. The inverter as described in claim 2, characterized in that, The bias temperature instability recovery unit further includes a fourth transistor connected to the third node and the fourth node; the third node is the node between the first input terminal and the gate of the first transistor, and the fourth node is the node between the second input terminal and the gate of the second transistor; the fourth transistor is used to control the on / off state between the third node and the fourth node based on the states of the first transistor and the second transistor.

7. The inverter as described in claim 6, characterized in that, The source of the fourth transistor is connected to the third node, the drain is connected to the fourth node, and the gate is connected to the second control terminal. The second control terminal is used to provide a second control signal, wherein the second control signal is used to control the fourth transistor to be in the on state when the first transistor and the second transistor are in the working state, and to control the fourth transistor to be in the off state when the first transistor and the second transistor are in the recovery state.

8. The inverter as described in claim 6, characterized in that, The well region where the third transistor is located is isolated from the well regions where the first transistor and the second transistor are located; the well region where the fourth transistor is located is isolated from the well regions where the first transistor and the second transistor are located.

9. The inverter as claimed in claim 1, characterized in that, The first transistor is a PMOS transistor, and the first recovery voltage signal is used to enable the first transistor to perform negative bias temperature instability recovery. The second transistor is an NMOS transistor, and the second recovery voltage signal is used to enable the second transistor to perform positive bias temperature instability recovery; The source of the first transistor is connected to a first voltage source, and the drain is connected to a first output terminal; the source of the second transistor is connected to a second voltage source, and the drain is connected to a second output terminal.

10. A control method for an inverter, characterized in that, The inverter includes a first transistor and a second transistor with different conductivity types. The gate of the first transistor is connected to a first input terminal, and the gate of the second transistor is connected to a second input terminal. A first node is formed between the first input terminal and the gate of the first transistor, and a second node is formed between the second input terminal and the gate of the second transistor. The method includes: When the first transistor and the second transistor are in the working state, a path is established between the first node and the second node; When the first transistor and the second transistor are in the recovery state, the circuit between the first node and the second node is controlled to be open, and a first recovery voltage signal is provided to the first node and a second recovery voltage signal is provided to the second node.

11. An inverter module, characterized in that, include: A plurality of inverters connected in sequence as described in any one of claims 1 to 9; In the direction of signal transmission path, the first output terminal of the previous inverter is connected to the second input terminal of the next inverter, and the second output terminal of the previous inverter is connected to the first input terminal of the next inverter.

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