Storage device and operating method of storage device

Abstract

A memory device and an operating method of operating the memory device are provided. The method includes: obtaining, by a memory controller, channel selection information indicating positions of data bits and shaping parity bits; generating, by the memory controller, an alignment vector by aligning the data bits and the shaped parity bits having an arbitrary value based on the channel selection information; generating, by the memory controller, second LLR information of the target vector based on the first LLR information related to the alignment vector; determining, by the memory controller, a value of a shaped parity based on the target vector and the second LLR information; performing, by the memory controller, an update operation on the shaped parity based on the determined value; and generating, by the memory controller after performing the update operation, a codeword with respect to the input data based on a first matrix multiplication calculation of the target vector and the first generated matrix.

Description

[0001] Cross-reference to related applications

[0002] This application claims priority to Korean Patent Application No. 10-2024-0162071, filed with the Korean Intellectual Property Office on November 14, 2024, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0003] Some exemplary embodiments of the inventive concept described herein relate to a semiconductor memory, and more specifically, to a storage device including the semiconductor memory and / or a method of operating the storage device. Background Technology

[0004] Storage devices refer to devices that store data under the control of a host device, such as computers, smartphones, and tablets. Storage devices include devices that store data on disks (such as hard disk drives (HDDs)) and / or devices that store data in semiconductor memory (specifically, non-volatile memory) (such as solid-state drives (SSDs) and / or memory cards).

[0005] Non-volatile memory includes read-only memory (ROM), programmable ROM (PROM), electrically programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM), flash memory, phase-change RAM (PRAM), magnetic RAM (MRAM), resistive RAM (RRAM), ferroelectric RAM (FRAM), etc.

[0006] With the development of semiconductor manufacturing technology, the integration and size of memory devices continue to increase. High integration of memory devices allows for a reduction in the cost required to manufacture them. However, high or even higher integration of memory devices may lead to miniaturization and structural changes, resulting in various new problems. These problems may lead to corruption of the data stored in the memory device. Therefore, preventing and / or reducing these problems, as well as improving and / or increasing the reliability of memory devices, can be beneficial. Summary of the Invention

[0007] Some example embodiments provide storage devices and / or methods of operating such storage devices that can reduce power consumption and improve reliability.

[0008] According to some example embodiments, a method of operating a storage device including a non-volatile memory device and a memory controller configured to control the non-volatile memory device includes: obtaining channel selection information by the memory controller indicating the positions of data bits and integer parity bits included in input data; generating an alignment vector by the memory controller by aligning the data bits and integer parity bits having arbitrary values ​​based on the channel selection information; generating second LLR information by the memory controller based on first log-likelihood ratio (LLR) information associated with the alignment vector, including a target vector of integer parity bits; determining the value of the integer parity bits by the memory controller based on the target vector and the second LLR information; performing an update operation on the integer parity bits by the memory controller based on the determined value; and generating a codeword about the input data by the memory controller after performing the update operation, based on a first matrix multiplication of the target vector and a first generator matrix.

[0009] According to some example embodiments, a method of operating a storage device including a non-volatile memory device and a memory controller configured to control the non-volatile memory device includes: obtaining channel selection information by the memory controller indicating the positions of data bits, error correction code (ECC) parity bits, and shaped parity bits included in input data; generating an alignment vector by the memory controller aligning the data bits, ECC parity bits, and shaped parity bits based on the channel selection information; determining the value of the ECC parity bits by the memory controller; generating second LLR information, including the shaped parity bits, by the memory controller based on first log-likelihood ratio (LLR) information associated with the alignment vector; determining the value of the shaped parity bits by the memory controller based on the target vector and the second LLR information; performing an update operation on the shaped parity bits by the memory controller based on the determined value; and generating a codeword about the input data by the memory controller after performing the update operation based on a first matrix multiplication of the target vector and a first generator matrix.

[0010] According to some example embodiments, a storage device includes: a non-volatile memory device; and a memory controller configured to: control the non-volatile memory device; obtain channel selection information indicating the positions of data bits and integer parity bits included in input data; generate an alignment vector by aligning the data bits and integer parity bits based on the channel selection information; generate second LLR information of a target vector including the integer parity bits based on first log-likelihood ratio (LLR) information associated with the alignment vector; determine the value of the integer parity bits based on the target vector and the second LLR information; perform an update operation on the integer parity bits based on the determined value; and generate a codeword about the input data based on a first matrix multiplication calculation of the target vector and a first generator matrix.

[0011] According to some example embodiments, a storage system may include a host device and a storage device, the storage device including a non-volatile memory device and a memory controller configured to control the non-volatile memory device. The memory controller may be configured to: receive first data from the host device as input data; obtain channel selection information indicating the positions of data bits and integer parity bits included in the input data; generate an alignment vector by aligning the data bits and integer parity bits having arbitrary values ​​based on the channel selection information; generate second LLR information including a target vector of integer parity bits based on first log-likelihood ratio (LLR) information associated with the alignment vector; determine the value of the integer parity bits based on the target vector and the second LLR information; perform an update operation on the integer parity bits based on the determined value; after performing the update operation, perform a first matrix multiplication calculation based on the target vector and a first generator matrix to generate a codeword about the input data; and store data associated with the codeword in the non-volatile memory device. Attached Figure Description

[0012] The above and other objects and features of the present invention will become apparent from a detailed description of some exemplary embodiments of the invention with reference to the accompanying drawings.

[0013] Figure 1 A storage device according to some example embodiments is shown.

[0014] Figure 2 A non-volatile memory device according to some example embodiments is shown.

[0015] Figure 3 A memory block according to some example embodiments is shown.

[0016] Figure 4 A memory controller according to some example embodiments is shown.

[0017] Figure 5AThe following are illustrated according to some example embodiments. Figure 4 An example of a flowchart illustrating the operation of an encoder.

[0018] Figure 5B The following are examples of configurations for performing actions according to certain example embodiments. Figure 5A The encoder operates the flowchart.

[0019] Figure 6 An example of an alignment vector according to some example embodiments is shown.

[0020] Figure 7 An example of LLR information based on some example embodiments is shown.

[0021] Figure 8 An example of a generated matrix is ​​shown according to some example embodiments.

[0022] Figure 9 Examples of the results of a matrix multiplication calculator according to some example embodiments are shown.

[0023] Figure 10 The programming states of a non-volatile memory device and the bit mapping for each programming state are shown according to some example embodiments.

[0024] Figure 11 An example of masking data for a first integer encoding is shown according to some example embodiments.

[0025] Figure 12 An example of an alignment vector for second integer encoding is shown according to some example embodiments.

[0026] Figure 13 An example of masking data for second integer encoding is shown according to some example embodiments.

[0027] Figure 14 An example of an alignment vector generator according to some example embodiments is shown.

[0028] Figure 15A The following are illustrated according to some example embodiments. Figure 4 An example of a flowchart illustrating the operation of an encoder.

[0029] Figure 15B The following are examples of configurations based on certain example embodiments. Figure 15A The encoder performs the operation of the flowchart.

[0030] Figure 16 An example of an alignment vector for joint encoding is shown according to some example embodiments.

[0031] Figure 17Examples of operations for describing shaping decoding are shown according to some example embodiments.

[0032] Figure 18 An example of the result of shaping decoding according to some example embodiments is shown.

[0033] Figure 19 A memory system according to some example embodiments is shown.

[0034] Figure 20 A memory system according to some example embodiments is shown. Detailed Implementation

[0035] In the following, some exemplary embodiments will be described in detail and clearly to the extent that those skilled in the art can easily implement the inventive concept.

[0036] In specific implementations, refer to the terms "unit", "module", "block", "~".

[0037] The components described as "device or machine" and the functional blocks shown in the accompanying drawings will be implemented using software, hardware, or a combination thereof. For example, software may be machine code, firmware, embedded code, and / or application software. For example, hardware may include electrical circuits, electronic circuits, processors, computers, integrated circuits, integrated circuit cores, pressure sensors, inertial sensors, microelectromechanical systems (MEMS), passive components, and / or combinations thereof.

[0038] Figure 1 A storage device according to some example embodiments is shown. (Refer to...) Figure 1 The storage device 100 may include a non-volatile memory device 110 and a memory controller 120.

[0039] The non-volatile memory device 110 can perform write operations, read operations, and / or erase operations under the control of the memory controller 120. The non-volatile memory device 110 can exchange first data DATA1 with the memory controller 120. For example, the non-volatile memory device 110 can receive write data from the memory controller 120 and can write the received write data. The non-volatile memory device 110 can perform read operations and can output the read data to the memory controller 120.

[0040] The non-volatile memory device 110 may receive a first command CMD1 and a first address ADDR1 from the memory controller 120. The non-volatile memory device 110 may exchange control signals CTRL with the memory controller 120. For example, the non-volatile memory device 110 may receive at least one of the following signals from the memory controller 120: a chip select signal nCE for selecting at least one semiconductor chip among a plurality of semiconductor chips forming the non-volatile memory device 110; a command latch enable signal CLE for indicating that the signal received from the memory controller 120 is the first command CMD1; an address latch enable signal ALE for indicating that the signal received from the memory controller 120 is the first address ADDR1; a read enable signal nRE for timing alignment during a read operation; a write enable signal nWE for timing alignment during a write operation; and a data strobe signal DQS for synchronizing the input of the first data DATA1. For example, the non-volatile memory device 110 may output to the memory controller 120 at least one of a ready and busy signal R / nB indicating whether the non-volatile memory device 110 is performing a programming operation, an erase operation and / or a read operation, and a data strobe signal DQS for synchronizing the output of the first data DATA1.

[0041] The non-volatile memory device 110 may include a plurality of memory cells. Each of the plurality of memory cells may store two or more bits.

[0042] For example, the non-volatile memory device 110 may include at least one of various non-volatile memory devices (such as flash memory devices, phase change memory devices, ferroelectric memory devices, magnetic memory devices and / or resistive memory devices), but the example embodiments are not limited thereto.

[0043] The memory controller 120 can be configured to control the non-volatile memory device 110. For example, the memory controller 120 can control the non-volatile memory device 110 to perform write, read, and / or erase operations. The memory controller 120 can exchange first data DATA1 and control signal CTRL with the non-volatile memory device 110, and can output a first command CMD1 and a first address ADDR1 to the non-volatile memory device 110.

[0044] The memory controller 120 can control the non-volatile memory device 110 according to the control of an external host device (not shown). The memory controller 120 can exchange second data DATA2 with the host device and can receive second command CMD2 and second address ADDR2 from the host device.

[0045] The memory controller 120 can receive second data DATA2 from the host device, and can encode the second data DATA2 and write it as first data DATA1 into the non-volatile memory device 110. The memory controller 120 can also receive first data DATA1 from the non-volatile memory device 110, and can decode the first data DATA1 and output it as second data DATA2 to the host device. For example, the memory controller 120 can exchange first data DATA1 with the non-volatile memory device 110 in a first unit, and can exchange second data DATA2 with the host device in a second unit different from the first unit.

[0046] The memory controller 120 can exchange first data DATA1 with the non-volatile memory device 110 according to a first format, and can transmit and / or send a first command CMD1 and a first address ADDR1 to the non-volatile memory device 110. The memory controller 120 can exchange second data DATA2 with the host device according to a second format different from the first format, and can receive a second command CMD2 and a second address ADDR2 from the host device.

[0047] The memory controller 120 may include RAM 123 and an encoding and decoding engine (hereinafter referred to as the "E / D engine") 124. RAM 123 may store second data DATA2 received from the host device. RAM 123 may store first data DATA1 encoded by the E / D engine 124. RAM 123 may store the first data DATA1 received from the non-volatile memory device 110. RAM 123 may store second data DATA2 decoded from the first data DATA1. RAM 123 may be used as operational memory, buffer memory, and / or cache memory of the memory controller 120.

[0048] E / D engine 124 can encode the second data DATA2 stored in RAM 123 and output the first data DATA1. E / D engine 124 can decode the first data DATA1 stored in RAM 123 and output the second data DATA2.

[0049] For example, during writing, the second data DATA2 received from the host device can be encoded into the first data DATA1 by the E / D engine 124. The first data DATA1 can be written to the non-volatile memory device 110. During reading, the first data DATA1 read from the non-volatile memory device 110 can be decoded into the second data DATA2 by the E / D engine 124. The second data DATA2 can be output to the host device.

[0050] In some example embodiments, E / D engine 124 can perform integer encoding. Integer encoding can increase or decrease the number of bits containing "1" or "0" among the bits included in the data. For example, E / D engine 124 can perform integer encoding using integer parity bits provided in addition to the bits included in the data.

[0051] In some example embodiments, the E / D engine 124 may perform a first integer coding. The first integer coding may reduce the number of logic states with high error rates and may increase the number of other logic states. For example, the first integer coding may reduce the number of memory cells programmed into a target state among the programming states of a plurality of memory cells included in the non-volatile memory device 110. The target state may refer to the state with the highest level of a threshold voltage distribution range among the programming states. For example, the target state may refer to the programming state with the highest threshold voltage distribution among the programming states.

[0052] In some example embodiments, the E / D engine 124 may perform a second shaping code associated with data bus reversal. The second shaping code may reverse at least one bit included in the data. The second shaping code may be performed to reduce power consumption due to sending and receiving data between the non-volatile memory device 110 and the memory controller 120.

[0053] For example, the second integer encoding can reduce the number of bits with a specific value in the data transmitted and / or sent to the non-volatile memory device 110 (e.g., write data). For example, the second integer encoding can reduce the number of bits with a first value (e.g., "1") in the data transmitted and / or sent to the non-volatile memory device 110. However, the example embodiments are not limited thereto, and in some example embodiments, the second integer encoding can reduce the number of bits with a second value (e.g., "0").

[0054] In some example embodiments, the E / D engine 124 may perform integer encoding based on relaxed polar codes and / or modified polar codes (hereinafter referred to as "modified polar codes" for ease of description).

[0055] Figure 2 A non-volatile memory device 110 according to some example embodiments is shown. (Refer to...) Figure 1 and Figure 2 The non-volatile memory device 110 may include a memory cell array 111, an address decoder circuit 112, a page buffer circuit 113, a data input / output (I / O) circuit 114, and a control logic circuit 115.

[0056] Memory cell array 111 includes multiple memory blocks BLK1 to BLKz. Each of memory blocks BLK1 to BLKz includes multiple memory cells. Each of memory blocks BLK1 to BLKz can be connected to address decoder circuit 112 via at least one ground select line GSL, multiple word lines WL, and at least one string select line SSL. Each of memory blocks BLK1 to BLKz can be connected to page buffer circuit 113 via multiple bit lines BL. The memory cells of the multiple memory blocks BLK1 to BLKz can have the same and / or similar structures.

[0057] Address decoder circuit 112 can be connected to memory cell array 111 via at least one ground select line GSL, multiple word lines WL, and at least one serial select line SSL. Address decoder circuit 112 operates under the control of control logic circuit 115. Address decoder circuit 112 can receive a first address ADDR1 from memory controller 120. Address decoder circuit 112 can decode the received first address ADDR1 and can control the voltage to be applied to word line WL based on the decoded address.

[0058] For example, during a programming operation, the address decoder circuit 112 can apply a programming voltage VPGM to a selected word line in the selected memory block indicated by the first address ADDR1, and can apply a voltage VPASS to an unselected word line in the selected memory block. During a read operation, the address decoder circuit 112 can apply a selected read voltage VRD to a selected word line in the selected memory block indicated by the first address ADDR1, and can apply a non-selected read voltage VREAD to an unselected word line in the selected memory block. During an erase operation, the address decoder circuit 112 can apply an erase voltage (e.g., ground voltage) to a word line in the selected memory block indicated by the first address ADDR1.

[0059] Page buffer circuit 113 is connected to memory cell array 111 via multiple bit lines BL. Page buffer circuit 113 is connected to data input / output circuit 114 via multiple data lines DL. Page buffer circuit 113 operates under the control of control logic circuit 115.

[0060] Page buffer circuit 113 can store data to be programmed into or read from memory cells in memory cell array 111. During programming operations, page buffer circuit 113 stores data to be programmed into memory cells. Page buffer circuit 113 can bias multiple bit lines BL based on the stored data. During programming operations, page buffer circuit 113 can be used as a write driver. During read operations, page buffer circuit 113 can read the voltage of bit line BL and store the read result. During read operations, page buffer circuit 113 can be used as a sense amplifier.

[0061] The data input / output circuit 114 is connected to the page buffer circuit 113 via multiple data lines DL. The data input / output circuit 114 can exchange the first data DATA1 with the memory controller 120.

[0062] Data input / output circuit 114 can temporarily store the first data DATA1 received from memory controller 120. Data input / output circuit 114 can transfer the stored data to page buffer circuit 113. Data input / output circuit 114 can temporarily store data transferred from page buffer circuit 113. Data input / output circuit 114 can transfer the stored data and / or send it to memory controller 120. Data input / output circuit 114 can be used as a buffer memory.

[0063] The control logic circuit 115 receives a first command CMD1 and a control signal CTRL from the memory controller 120. The control logic circuit 115 can decode the received first command CMD1 and control the overall operation of the non-volatile memory device 110 based on the decoded command.

[0064] Figure 3 This is a circuit diagram illustrating a memory block BLKa according to some example embodiments. (Refer to...) Figure 3 The memory block BLKa comprises multiple cell strings CS11 to CS21 and CS12 to CS22. The multiple cell strings CS11 to CS21 and CS12 to CS22 can be arranged along the row and column directions to form rows and columns.

[0065] For example, cell strings CS11 and CS12 arranged along the row direction can form the first row, and cell strings CS21 and CS22 arranged along the row direction can form the second row. Cell strings CS11 and CS21 arranged along the column direction can form the first column, and cell strings CS12 and CS22 arranged along the column direction can form the second column.

[0066] Each cell string may include multiple cell transistors. The multiple cell transistors include ground selection transistors GSTA and GSTb, memory cells MC1 to MC6, and string selection transistors SSTa and SSTb. The ground selection transistors GSTA and GSTb, memory cells MC1 to MC6, and string selection transistors SSTa and SSTb in each cell string may be stacked in a height direction perpendicular to the plane on which cell strings CS11, CS21, CS12, and CS22 are arranged in rows and columns (e.g., a plane on the substrate of the memory block BLKa).

[0067] Each unit transistor can be a charge-trapping unit transistor whose threshold voltage varies according to the amount of charge trapped in its insulating layer.

[0068] The bottom ground selection transistor GSTA can be connected to the common source line CSL.

[0069] The ground selection transistors GSTA and GSTb of multiple cell strings CS11, CS21, CS12 and CS22 can be connected together to the ground selection line GSL.

[0070] In some example embodiments, ground select transistors of the same height (or sequence) can be connected to the same and / or similar ground select lines, and ground select transistors of different heights (or sequences) can be connected to different ground select lines. For example, ground select transistors of a first height, GSTA, can be connected together to a first ground select line, and ground select transistors of a second height, GSTb, can be connected together to a second ground select line.

[0071] For example, ground select transistors in the same row can be connected to the same and / or similar ground select lines, and ground select transistors in different rows can be connected to different ground select lines. For example, the ground select transistors GSTA and GSTb of cell strings CS11 and CS12 in the first row can be connected to the first ground select line, and the ground select transistors GSTA and GSTb of cell strings CS21 and CS22 in the second row can be connected to the second ground select line.

[0072] Memory cells placed at the same and / or similar heights (or in sequence) from the substrate (or ground selection transistor GSTA or GSTb) can be connected to a single word line, and memory cells placed at different heights (or in sequence) can be connected to different word lines WL1 through WL6 respectively. For example, memory cell MC1 is connected to word line WL1. Memory cell MC2 is connected to word line WL2. Memory cell MC3 is connected to word line WL3. Memory cell MC4 is connected to word line WL4. Memory cell MC5 is connected to word line WL5. Memory cell MC6 is connected to word line WL6.

[0073] In multiple cell strings CS11, CS21, CS12, and CS22, the first string select transistors SSTa with the same and / or similar height (or order) are connected to different string select lines SSL1a and SSL2a, respectively. For example, the first string select transistors SSTa of cell strings CS11 and CS12 are jointly connected to string select line SSL1a. The first string select transistors SSTa of cell strings CS21 and CS22 are jointly connected to string select line SSL2a.

[0074] In multiple cell strings CS11, CS21, CS12, and CS22, the second string selection transistors SSTb with the same and / or similar height (or order) are connected to different string selection lines SSL1b and SSL2b, respectively. For example, the second string selection transistors SSTb of cell strings CS11 and CS12 are jointly connected to the string selection line SSL1b. The second string selection transistors SSTb of cell strings CS21 and CS22 are jointly connected to the string selection line SSL2b.

[0075] For example, cell strings in different rows are connected to different select lines. String select transistors with the same height (or order) in a cell string within the same row are connected to the same select line. String select transistors with different heights (or orders) in a cell string within the same row are connected to different select lines.

[0076] In some example embodiments, the string select transistors of cell strings in the same row can be connected together to the string select line. For example, the string select transistors SSTa and SSTb of cell strings CS11 and CS12 in the first row can be connected together to the string select line. Similarly, the string select transistors SSTa and SSTb of cell strings CS21 and CS22 in the second row can be connected together to the string select line.

[0077] Columns of multiple cell strings CS11, CS21, CS12, and CS22 can be connected to different bit lines BL1 and BL2. For example, the string select transistors SSTb of cell strings CS11 and CS21 in the first column can be connected together to bit line BL1. The string select transistors SSTb of cell strings CS12 and CS22 in the second column can be connected together to bit line BL2.

[0078] Unit strings CS11 and C12 can form the first plane. Unit strings CS21 and C22 can form the second plane.

[0079] In memory block BLKa, read and program operations can be performed row by row. For example, a plane of memory block BLKa can be selected via serial select lines SSL1a, SSL1b, SSL2a, and SSL2b. When an on-state voltage is supplied to serial select lines SSL1a and SSL1b and an off-state voltage is supplied to serial select lines SSL2a and SSL2b, cell strings CS11 and CS12 in the first plane can be connected to bit lines BL1 and BL2. For example, the first plane can be selected. When an on-state voltage is supplied to serial select lines SSL2a and SSL2b and an off-state voltage is supplied to serial select lines SSL1a and SSL1b, cell strings CS21 and CS22 in the second plane can be connected to bit lines BL1 and BL2. For example, the second plane can be selected. In the selected plane, a row of memory cells MC can be selected via word lines WL1 to WL6. In the selected row, either a programmable or read operation can be performed.

[0080] In a memory block BLKa, an erase operation can be performed on a per-block or per-subblock basis. When an erase operation is performed on a per-block basis, all memory cells MC in the memory block BLKa can be erased. When an erase operation is performed on a subblock basis, some of the memory cells MC in the memory block BLKa can be erased, while the remaining memory cells are erase-inactive. A low voltage (e.g., ground) can be supplied to the word lines connected to the memory cells to be erased, and the word lines connected to the erase-inactive memory cells can be floated.

[0081] Figure 3 The memory block BLKa shown is provided as an example. However, the example embodiment is not limited to this. Figure 3 The memory block BLKa is shown. For example, the number of rows of cell strings can be increased and / or decreased. As the number of rows of cell strings changes, the number of string select lines or ground select lines connected to the rows of cell strings and the number of cell strings connected to bit lines can also change.

[0082] For example, the number of columns in a unit string can be increased and / or decreased. As the number of columns in a unit string changes, the number of bit lines connected to the columns of the unit string and the number of unit strings connected to the string select line can also change.

[0083] For example, the height of the cell string can be increased and / or decreased. For example, the number of ground select transistors, memory cells, and / or string select transistors stacked in each cell string can be increased and / or decreased.

[0084] Figure 4 A memory controller according to some example embodiments is shown. (Refer to...) Figure 4The memory controller 120 may include a bus 121, a processor 122, RAM 123, an E / D engine 124, a host interface 125, an ECC engine 126, and a memory interface 127.

[0085] Bus 121 is configured to provide a channel between components of memory controller 120.

[0086] Processor 122 can control the overall operation of memory controller 120 and perform logical calculations. Processor 122 can communicate with an external host device through host interface 125. Processor 122 can receive clock signal CLK, second command CMD2, and second address ADDR2 through host interface 125. Processor 122 can exchange second data DATA2 with the external host device through host interface 125. Processor 122 can exchange first data DATA1 and control signal CTRL with non-volatile memory device 110 through memory interface 127. Processor 122 can output first command CMD1 and first address ADDR1 to non-volatile memory device 110.

[0087] Processor 122 can store the second command CMD2 or the second address ADDR2 received through host interface 125 in RAM 123. Processor 122 can also store the second data DATA2 received through host interface 125 in RAM 123. Processor 122 can generate a first command CMD1 based on the second command CMD2 or the second address ADDR2 stored in RAM 123, and can output the generated first command CMD1 and the generated first address ADDR1 through memory interface 127. Processor 122 can also output the first data DATA1 stored in RAM 123 through memory interface 127. Processor 122 can store the first data DATA1 received through memory interface 127 in RAM 123. Processor 122 can also output the second data DATA2 stored in RAM 123 through host interface 125. For example, processor 122 includes DMA (Direct Memory Access) circuitry and can use DMA circuitry to output data.

[0088] RAM 123 can be used as working memory, cache memory, and / or buffer memory of processor 122. RAM 123 can store code and / or commands executed by processor 122. RAM 123 can store data processed by processor 122. RAM 123 may include static RAM (SRAM).

[0089] E / D engine 124 may include encoder (ENC) 124a and decoder (DEC) 124b. Encoder 124a can read second data DATA2 stored in RAM 123, can perform shaping encoding on the read second data DATA2 to generate first data DATA1, and can store the generated first data DATA1 in RAM 123. Decoder 124b can read first data DATA1 stored in RAM 123, can perform shaping decoding on the read first data DATA1 to generate second data DATA2, and can store the generated second data DATA2 in RAM 123. E / D engine 124 may store and / or read information necessary and / or advantageous for performing shaping encoding and / or shaping decoding in RAM 123, and / or may read information from RAM 123. E / D engine 124 may be implemented as hardware and / or software driven by processor 122. Reference will be made to... Figures 5A to 16 A more detailed description of integer coding will be provided, and references will be made. Figure 17 and Figure 18 A more detailed description of the shaping decoding.

[0090] In some example embodiments, encoder 124a and decoder 124b can operate in combination with each other. For example, decoder 124b can share operational information used by encoder 124a. Figure 4 In this example, encoder 124a and decoder 124b are implemented as separate components, but the example embodiment is not limited to this, and in some example embodiments, encoder 124a and decoder 124b may share some components.

[0091] Host interface 125 is configured to communicate with an external host device under the control of processor 122. Host interface 125 can be configured to communicate using at least one of various communication methods, such as Universal Serial Bus (USB), Serial AT Attachment (SATA), Serial Attached SCSI (SAS), High Speed ​​Chip Interconnect (HSIC), Small Computer System Interface (SCSI), FireWire, Peripheral Component Interconnect (PCI), PCIe, Non-Volatile Memory Fast (NVMe), Universal Flash Storage (UFS), Secure Digital (SD), Multimedia Card (MMC), and / or Embedded MMC (eMMC).

[0092] ECC engine 126 can perform error correction coding. ECC engine 126 can generate ECC parity checks for performing error correction coding based on the data to be output to memory interface 127. By performing error correction coding, ECC engine 126 can add ECC parity checks to the data to be output. ECC parity checks include one or more bits and can provide error correction functionality. Data encoded by ECC engine 126 can be transmitted and / or sent to non-volatile memory device 110.

[0093] In some example embodiments, the ECC engine 126 can perform error correction coding on data that has undergone integer coding.

[0094] ECC engine 126 can perform error correction decoding on data received through memory interface 127. By performing error correction decoding using ECC parity checking of the data, ECC engine 126 can correct errors from the received data.

[0095] The ECC engine 126 can store and / or read information necessary for performing error correction encoding and / or error correction decoding in RAM 123. The ECC engine 126 can be implemented as hardware and / or software driven by the processor 122.

[0096] The memory interface 127 is configured to communicate with the non-volatile memory device 110 under the control of the processor 122.

[0097] In some example embodiments, processor 122 may use code to control memory controller 120. Processor 122 may load code from non-volatile memory (e.g., read-only memory) disposed within memory controller 120. In some example embodiments, processor 122 may load code received from memory interface 127.

[0098] Figure 5A The following are illustrated according to some example embodiments. Figure 4 An example of a flowchart illustrating the operation of an encoder. Figure 5B The following are examples of configurations for performing actions according to certain example embodiments. Figure 5A The encoder operates the flowchart.

[0099] In the following description, for the purpose of briefly and clearly depicting some exemplary embodiments of the inventive concept, some data values ​​and / or some bit values ​​are described as being at a specific level or specific bit level (e.g., "1" or "0"). However, the scope of the inventive concept is not limited thereto, and in some exemplary embodiments of the inventive concept, the various data values ​​and / or various bit values ​​used for the inventive concept may be modified differently depending on the implementation method.

[0100] Reference Figure 5Aand Figure 5B In operation S110, encoder 200 can obtain channel selection information (CSI) indicating the positions of the data bits DB and the integer parity bits SPB of the input data IDATA. For example, Figure 5B The channel selector 210 can distinguish multiple channels into good channels and bad channels by channel polarization based on polarity codes. In some example embodiments, a channel can represent the path along which a particular location is transmitted and / or sent. A good channel can represent a channel with low error probability and / or high reliability. A good channel can be used to shape the parity bit SPB, while a bad channel can be used to shape the data bits DB of the input data IDATA.

[0101] In some example embodiments, when performing the first integer encoding, the integer parity bit SPB can be the VSS integer parity bit VSPB. In some example embodiments, when performing the second integer encoding, the integer parity bit SPB can be the DBI integer parity bit DSPB.

[0102] In some example embodiments, channel selector 210 may determine channel selection information (CSI) based on a Bhattacharyya parameter. The Bhattacharyya parameter may be a parameter related to the reliability of the channel. Channel selector 210 may determine the position of the integer parity bit (SPB) based on the values ​​of the Bhattacharyya parameter in ascending order.

[0103] In some example embodiments, the channel selector 210 can determine the channel selection information (CSI) such that the shaped parity bit (SPB) is aligned to a specific or alternatively desired position.

[0104] In operation S120, encoder 200 can generate an alignment vector "u" by aligning the data bits DB and the integer parity bits SPB based on channel selection information CSI. For example, Figure 5B The bit aligner 221 can receive integer parity bits SPB with initial values ​​from the integer parity bit generator 222. In some example embodiments, each of the initial values ​​can be arbitrary. The bit aligner 221 can generate an alignment vector "u" by aligning data bits DB with specific values ​​with integer parity bits SPB with initial values.

[0105] In operation S130, encoder 200 can generate second LLR (log-likelihood ratio) information LLRI2 for a target vector u_TRG that includes an integer parity bit SPB, based on first LLR (log-likelihood ratio) information LLRI1 associated with the alignment vector "u". The target vector u_TRG is a part of the alignment vector "u" and may include the integer parity bit SPB. Each of the first LLR information LLRI1 and the second LLR information LLRI2 may include a different number of LLR values. In some example embodiments, the LLR value may be a value obtained by taking the logarithm of the ratio of the probability that a bit included in the data will correspond to "1" or "0". In other words, the LLR value may indicate information and / or probability values ​​about the probability that a bit included in the data will be "0" or "1".

[0106] For example, Figure 5B The LLR information (LLRI) generator 222a can receive an alignment vector “u” from the bit aligner 221. In some example embodiments, the integer parity bit SPB included in the alignment vector “u” can have arbitrary values. The LLR information generator 222a can generate the LLR values ​​included in the second LLR information LLRI2 based on the sum of the LLR values ​​included in the first LLR information LLRI 1. For example, the LLR information generator 222a can generate the second LLR information LLRI2, which includes the first LLR information LLRI 1, based on the summation calculation.

[0107] In some example embodiments, the LLR values ​​included in the first LLR information LLRI 1 may correspond to bits included in the alignment vector "u". For example, the number of LLR values ​​included in the first LLR information LLRI 1 may be the same as the number of bits included in the alignment vector "u". In some example embodiments, the LLR values ​​included in the second LLR information LLRI 2 may correspond to bits included in the target vector u_TRG. For example, the number of LLR values ​​included in the second LLR information LLRI 2 may be the same as the number of bits included in the target vector u_TRG.

[0108] In some example embodiments, the LLR information generator 222a may obtain the first LLR information LLRI 1 based on the alignment vector "u".

[0109] In operation S140, encoder 200 can determine the value of the integer parity bit SPB based on the target vector u_TRG and the second LLR information LLRI2. For example, Figure 5B The Integer Parity Bit Value (SPBV) Determiner 222b can determine the value of the Integer Parity Bit SPB based on the target vector u_TRG and the second LLR information LLRI2.

[0110] For example, the integer parity bit determiner 222b can use a parity value search algorithm to determine the value of the integer parity bit SPB from the target vector u_TRG and the second LLR information LLRI2. In some example embodiments, the integer parity bit determiner 222b can use a polarity decoding algorithm to determine the value of the integer parity bit SPB. For example, the integer parity bit determiner 222b can use an SC (continuous elimination) algorithm, a list SC (list continuous elimination) algorithm, and / or a brute-force search algorithm to determine the value of the integer parity bit SPB.

[0111] In operation S150, encoder 200 can perform an update operation on the integer parity bit SPB based on a determined value. For example, Figure 5B The bit aligner 221 can receive a determined value from the integer parity bit value determiner 222b. The bit aligner 221 can perform an update operation on the integer parity bit SPB based on the determined value. As a result of the operation, the value of the integer parity bit SPB can be updated from the initial value to the determined value.

[0112] In operation S160, after the update operation, encoder 200 can perform a first matrix multiplication based on the target vector u_TRG and the first generator matrix GM1 to generate a codeword CW for the alignment vector “u”. For example, Figure 5B The first matrix multiplication calculator 230 can receive the alignment vector "u" from the alignment vector generator 220 after the update operation. The first matrix multiplication calculator 230 can generate a codeword CW for the alignment vector "u" based on a first matrix multiplication calculation using the target vector u_TRG, which is part of the alignment vector "u", and the first generator matrix GM1. The first generator matrix GM1 can refer to the sub-generator matrix SGM included in the generator matrix GM based on the modified polar code. Figure 8 and Figure 9 The operation S160 is described in more detail below.

[0113] In some example embodiments, encoder 200 may also include masking data generator 240. Masking data generator 240 can generate masking data MDATA. Masking data MDATA can represent data to be referenced during shaping encoding. Masking data generator 240 can update masking data MDATA. Figure 10 , Figure 11 and Figure 13 A more detailed description of the masking data MDATA.

[0114] In some example embodiments, when masking data MDATA is present, in operation S130, LLR information generator 222a can obtain first LLR information LLRI 1 based on the alignment vector "u" and the masking data MDATA received from masking data generator 240. For example, LLR information generator 222a can obtain first LLR information LLRI 1 whose LLR value corresponds to the bit with a value of "0" in the masking data MDATA.

[0115] In some example embodiments, when masking data MDATA is present, in operation S140, the integer parity bit determiner 222b can determine the value of the integer parity bit SPB based on the target vector u_TRG, the second LLR information LLRI2, and the masking data MDATA.

[0116] Figure 6 Examples of alignment vectors according to some example embodiments are shown. Figure 6 In this context, we assume that the alignment vector “u” is the alignment vector “u” before performing the update operation for the integer parity bit SPB.

[0117] Reference Figure 6 The alignment vector "u" can include "n" digits (where "n" is a natural number greater than "1"). The alignment vector "u" can include the first sub-vector u1 to the m-th sub-vector um (where "m" is a natural number greater than "1" and less than "n"). Each of the first sub-vector u1 to the m-th sub-vector um can include "k" digits (where "k" is a natural number greater than "1" and less than "n").

[0118] The first subvectors u1 to the m-th subvector um can be arranged sequentially along the row direction within the alignment vector "u". The last subvector um among the first subvectors u1 to the m-th subvector um can include at least one integer parity bit SPB. In some example embodiments, the target vector u_TRG can indicate the last subvector um among the first subvectors u1 to the m-th subvector um. In other words, the target vector u_TRG can indicate a subvector that includes at least one integer parity bit.

[0119] In some example embodiments, the number of subvectors u1 to um can correspond to an exponent of "2".

[0120] In some example embodiments, the number of bits included in each of the sub-vectors u1 to um can be determined based on Channel Selection Information (CSI). For example, the length of the target vector u_TRG, including the Shaped Parity Bits (SPBs), can be determined based on at least some of the channels classified as good channels by channel polarization. For example, when there are a large number of channels identified as good channels, the number of SPBs can be increased, and the length of the target vector u_TRG can be increased. When there are a small number of channels identified as good channels, the number of SPBs can be decreased, and the length of the target vector u_TRG can be decreased.

[0121] In some example embodiments, the alignment vector “u” may be referred to as a row matrix of size “1” × “n”. In some example embodiments, each of the first subvector u1 to the m-th subvector um may be referred to as a row matrix of size “1” × “k”.

[0122] In some example embodiments, the alignment vector "u" may be referred to as a simplified row matrix of size "1" × "m". For example, the alignment vector "u" may be referred to as a simplified row matrix comprising a first row and first sub-columns through m-th sub-columns. Each of the first sub-columns through m-th sub-columns may comprise "k" columns.

[0123] Figure 7 Examples of LLR information according to some example embodiments are shown. (Refer to...) Figure 5B and Figure 7 The LLR information generator 222a can generate the second LLR information LLRI2 of the target vector u_TRG based on the first LLR information LLRI1 associated with the alignment vector "u".

[0124] The first LLR information LLRI 1 may include LLR values ​​corresponding to the bits included in the alignment vector "u". The number of LLR values ​​included in the first LLR information LLRI 1 may be the same as the number of bits included in the alignment vector "u". For example, the number of LLR values ​​included in the first LLR information LLRI 1 may be "m" × "k". The second LLR information LLRI 2 may include LLR values ​​corresponding to the bits included in the target vector u_TRG. The number of LLR values ​​included in the second LLR information LLRI 2 may be the same as the number of bits included in the target vector u_TRG. For example, the number of LLR values ​​included in the second LLR information LLRI 2 may be "k".

[0125] In some example embodiments, the LLR information generator 222a can generate the LLR values ​​included in the second LLR information LLRI2 based on the sum of the LLR values ​​included in the first LLR information LLRI 1. For example, the LLR information generator 222a can generate the second LLR information LLRI2, which includes the first LLR information LLRI 1, based on the summation calculation.

[0126] For example, LLR information generator 222a can generate an LLR value b1 corresponding to the first position of the target vector u_TRG by accumulating the LLR values ​​a1_1, a2_1, ..., am_1 corresponding to the first position of the first sub-vector u1 to the m-th sub-vector um. Similarly, LLR information generator 222a can generate an LLR value b2 corresponding to the second position of the target vector u_TRG by accumulating the LLR values ​​a1_2, a2_2, ..., am_2 corresponding to the second position of the first sub-vector u1 to the m-th sub-vector um. Likewise, LLR information generator 222a can generate an LLR value bk corresponding to the k-th position of the target vector u_TRG by accumulating the LLR values ​​a1_k, a2_k, ..., am_k corresponding to the k-th position of the first sub-vector u1 to the m-th sub-vector um. However, the example embodiments are not limited thereto, and in some example embodiments, the LLR information generator 222a may generate a second LLR information LLRI2, including the first LLR information LLRI 1, through various cumulative calculations.

[0127] Figure 8 An example of a generated matrix according to some example embodiments is shown. (Refer to...) Figure 5B , Figure 6 and Figure 8 The first matrix multiplier calculator 230 can generate the codeword CW of the alignment vector "u" by performing a second matrix multiplication of the alignment vector "u" and the generator matrix GM. In some example embodiments, the generator matrix GM may be based on a modified polar code.

[0128] The generating matrix GM can have a size of ("m" × "k") × ("m" × "k"). For example, the generating matrix GM can have a size of "n" × "n". In some example embodiments, the generating matrix GM can be represented as a simplified matrix of size "m" × "m". For example, the generating matrix GM can be represented as a simplified matrix comprising first sub-rows SR1 to m-th sub-rows SRm and first sub-columns SC1 to m-th sub-columns SCm. Each of the first sub-rows SR1 to m-th sub-rows SRm can include "k" rows, and each of the first sub-columns SC1 to m-th sub-columns SCm can include "k" columns.

[0129] The generating matrix GM can include multiple column generating matrices CGM1 to CGMm. Each of the multiple column generating matrices CGM1 to CGMm can have a size of "m" × "1". The first column generating matrix CGM1 can correspond to the first sub-column SC1 of the first sub-column SC1 to the m-th sub-column SCm of the generating matrix GM. The second column generating matrix CGM2 can correspond to the second sub-column SC2 of the first sub-column SC1 to the m-th sub-column SCm of the generating matrix GM. As described above, the m-th column generating matrix CGMm can correspond to the m-th sub-column SCm of the first sub-column SC1 to the m-th sub-column SCm of the generating matrix GM.

[0130] The generating matrix GM can include diagonal elements and the lowest row element, and the remaining elements can have zero values.

[0131] For example, the first column of the generated matrix CGM1 may include the first element CGM1e1 to the m-th element CGM1em. The first element CGM1e1 may have a unit value. The m-th element CGM1em may have generated values. In some example embodiments, the remaining elements may have zero values.

[0132] The second column of the generated matrix CGM2 may include the first element CGM2e1 to the m-th element CGM2em. The second element CGM2e2 may have a unit value. The m-th element CGM2em may have the generated value. In some example embodiments, the remaining elements may have zero values.

[0133] As described above, in some example embodiments, the (m-1)th column of the generated matrix CGM(m-1) may include the first element CGM(m-1)e1 to the m-th element CGM(m-1)em. The (m-1)th element CGM(m-1)e(m-1) may have a unit value. The m-th element CGM(m-1)em may have the generated value. In some example embodiments, the remaining elements may have zero values.

[0134] Meanwhile, the generated matrix CGMM in the m-th column can include the first element CGMme1 to the m-th element CGMmem. The m-th element CGMmem can have generated values. In some example embodiments, the remaining elements can have zero values.

[0135] In some example embodiments, the unit value of the generating matrix GM can be an identity matrix (IM) of size "k" × "k", the generated value of the generating matrix GM can be a sub-generating matrix SGM of size "k" × "k", and the zero value of the generating matrix GM can be a zero matrix of size "k" × "k".

[0136] In some example embodiments, the sub-generating matrix SGM can be expressed as Equation 1 below.

[0137] [Equation 1]

[0138]

[0139]

[0140] In Equation 1, G k "F" can refer to the sub-generating matrix, and "F" can refer to the kernel matrix. It can refer to the Kronecker exponentiation, and "k" can refer to the number of bits included in each of the subvectors.

[0141] According to some example embodiments, the result of the second matrix multiplication of the alignment vector "u" and the generator matrix GM can be the same as the result of performing the logical calculation of each of the first subvectors u1 to (m-1)th subvectors u(m-1) and the result of the first matrix multiplication of the m-th subvector um as the target vector u_TRG and the subgenerator matrix SGM. In other words, when performing the second matrix multiplication calculation using the generator matrix GM based on the modified polar code according to some example embodiments, the codeword CW of the alignment vector "u" can be generated with a small amount of computation.

[0142] Figure 9 Examples of the results from a matrix multiplication calculator based on some example embodiments are shown. Figure 9 In this context, we assume that the alignment vector “u” includes the first sub-vector u1 to the fourth sub-vector u4.

[0143] Reference Figure 5B , Figure 6 , Figure 8 and Figure 9 The first matrix multiplication calculator 230 can generate the codeword CW of the aligned vector "u" by performing a first matrix multiplication calculation based on the fourth sub-vector u4, which is the target vector u_TRG, and the sub-generator matrix SGM. The codeword CW can include the first codeword CW1 to the fourth codeword CW4.

[0144] For example, the first codeword CW1 can be obtained by logically calculating the result R1 of the first matrix multiplication of the fourth sub-vector u4 and the sub-generating matrix SGM, and the first sub-vector u1. The second codeword CW2 can be obtained by logically calculating the result R1 of the first matrix multiplication and the second sub-vector u2. The third codeword CW3 can be obtained by logically calculating the result R1 of the first matrix multiplication and the third sub-vector u3. The fourth codeword CW4 can be the result R1 of the first matrix multiplication.

[0145] In some example embodiments, a logical computation may represent an XOR logical computation.

[0146] like Figure 9 As shown, the first matrix multiplication calculator 230 can generate the codeword CW of the aligned vector "u" based on the result R1 of the first matrix multiplication calculation of the target vector u_TRG and the sub-generating matrix SGM, and the logical calculation of each of the remaining sub-vectors u1 to u3 (excluding the target vector u_TRG) with the result R1 of the first matrix multiplication calculation of the first matrix multiplication calculation of the multiple sub-vectors u1 to u4.

[0147] Figure 10 The programming states of a non-volatile memory device and the bit mapping for each programming state are shown according to some example embodiments. Figure 10 In the upper graph, the horizontal axis indicates the threshold voltage Vth of the memory cell, and the vertical axis indicates the number of memory cells. Figure 10 The table at the bottom shows the bit patterns BP associated with the erase state "E" and the first programming states P1 through the fifteenth programming states P15. For example, in Figure 10 In this example, it is assumed that four bits are programmed in a memory cell. However, the example embodiment is not limited to this and can be extended and applied to programming “N” bits (where “N” is a positive integer) in a memory cell.

[0148] Reference Figure 4 and 10 The four bits programmed in a memory cell can have 16 different modes corresponding to "2" raised to the power of "4". These 16 different modes can be mapped to the erase state "E" and the first programming states P1 through P15, respectively. The erase state "E" and the first programming states P1 through P15 can be distinguished by the threshold voltage Vth of the memory cell MC.

[0149] For example, a memory cell MC whose threshold voltage is less than the first read voltage VR1 can be determined to be in the erase state "E". A memory cell MC whose threshold voltage is greater than the first read voltage VR1 and less than the second read voltage VR2 can be determined to be in the first programming state P1. Similarly, a memory cell MC whose threshold voltage is greater than the kth read voltage VRk (where "K" is an integer greater than or equal to "1" and less than "15") and less than the (k+1)th read voltage VRk+1 can be determined to be in the kth programming state Pk. A memory cell MC whose threshold voltage is greater than the fifteenth read voltage VR15 can be determined to be in the fifteenth programming state P15.

[0150] exist Figure 10In this architecture, four bits can be programmed in each memory cell. These four bits can be called LSB, ESB, USB, and MSB, respectively. LSB represents the least significant bit, ESB represents the second least significant bit, USB represents the second most significant bit, and MSB represents the most significant bit.

[0151] like Figure 10 As shown, the bit pattern of the erase state "E" can be "1111", the bit pattern of the first programming state P1 can be "1110", the bit pattern of the second programming state P2 can be "0110", the bit pattern of the third programming state P3 can be "0100", the bit pattern of the fourth programming state P4 can be "1100", the bit pattern of the fifth programming state P5 can be "1000", the bit pattern of the sixth programming state P6 can be "0000", the bit pattern of the seventh programming state P7 can be "0001", and the bit pattern of the eighth programming state... The bit pattern of state P8 can be "0101", the bit pattern of the ninth programming state P9 can be "0111", the bit pattern of the tenth programming state P10 can be "0011", the bit pattern of the eleventh programming state P11 can be "0010", the bit pattern of the twelfth programming state P12 can be "1010", the bit pattern of the thirteenth programming state P13 can be "1011", the bit pattern of the fourteenth programming state P14 can be "1001", and the bit pattern of the fifteenth programming state P15 can be "1101".

[0152] and Figure 10 The values ​​of the LSB, ESB, USB, and MSB corresponding to each of the erase state "E" and the first programming states P1 to the fifteenth programming states P15 are presented as examples to aid in understanding some exemplary embodiments of the inventive concept, but these exemplary embodiments are not limited thereto. For example, the values ​​of the LSB, ESB, USB, and MSB corresponding to each of the erase state "E" and the first programming states P1 to the fifteenth programming states P15 may be varied differently.

[0153] In the erase state "E" and the first programming states P1 to the fifteenth programming states P15, the memory cell in the fifteenth programming state P15 can have the highest threshold voltage distribution range.

[0154] Reference Figure 4 and Figure 10 Both, according to some example embodiments, the E / D engine 124 can perform a first integer encoding on the written data, such that the data corresponding to the erase state "E" and the fifteenth programming state P15 among the first programming states P1 to the fifteenth programming state P15 is reduced.

[0155] In some example embodiments, the write data written as an LSB can be encoded such that the number of bits corresponding to the value of the LSB of the highest fifteenth programming state P15 is reduced. For example, the write data can be encoded such that the number of bits with a value of "1" (which is the value of the LSB of the highest fifteenth programming state P15) is reduced. For example, some bits with a value of "1" in the write data can be converted to have a value of "0".

[0156] The LSB values ​​in erase state "E" and in the first programming states P1 through fifteenth programming states P15 are all "1". When the number of bits with a value of "1" is reduced due to the conversion of the write data, the number of memory cells in erase state "E", first programming state P1, fourth programming state P4, fifth programming state P5, and twelfth programming states P12 through fifteenth programming states P15 decreases. In some example embodiments, the number of memory cells in second programming states P2 and third programming states P3, and sixth programming states P6 through eleventh programming states P11 increases because the number of bits with a value of "0" in the write data increases.

[0157] In some example embodiments, the write data written as an ESB can be encoded such that the number of bits corresponding to the value of the ESB of the highest fifteenth programming state P15 is reduced. For example, the write data can be encoded such that the number of bits with a value of "1" (which is the value of the ESB of the highest fifteenth programming state P15) is reduced. For example, some bits with a value of "1" in the write data can be converted to have a value of "0".

[0158] The ESB values ​​of erase state "E" and the first programming states P1 through fifteenth programming states P15, the first programming states P1 through fourth programming states P4, the eighth programming state P8, and the ninth programming state P9 match the highest ESB value of the fifteenth programming state P15 (which is "1"). Therefore, the number of memory cells having erase state "E", the first programming states P1 through fourth programming states P4, the eighth programming state P8, the ninth programming state P9, and the fifteenth programming state P15 is reduced. In some example embodiments, the number of memory cells MC having erase state "E" and the remaining programming states from the first programming states P1 through fifteenth programming states P15 other than erase state "E", the first programming states P1 through fourth programming states P4, the eighth programming state P8, the ninth programming state P9, and the fifteenth programming state P15 is increased.

[0159] As described above, according to some example embodiments, in the write data that serves as a USB write memory unit, the write data can be encoded to reduce the number of bits corresponding to the USB value of the highest fifteenth programming state P15, and in the write data that serves as an MSB write memory unit, the write data can be encoded to reduce the number of bits corresponding to the MSB value of the highest fifteenth programming state P15.

[0160] In some example embodiments, the first integer encoding for the written data can be performed as a reference encoding based on the masking data MDATA. The masking data MDATA can be associated with the encoded data of the lower-order bits of the written data. For example, the masking data MDATA can be associated with the encoded data of the lower-order bits and the bit pattern of the highest fifteenth programming state P15.

[0161] For example, in write data written as an LSB, low-order bits may be absent. When the write data is LSB data, first masking data can be generated. The value of the bits included in the first masking data can be "1". The write data can be encoded such that the number of bits with the highest fifteenth programming state P15 of the LSB value is reduced. After encoding, the first masking data can be updated to second masking data based on the first masking data and the LSB data (e.g., encoded data). For example, in the LSB data to be written (or written) to the memory cell MC, the bits with the highest fifteenth programming state P15 of the LSB value can be detected. The first masking data can be updated to the second masking data such that the bits corresponding to the detected bits have a value of "1", and the bits not corresponding to the detected bits have a value of "0".

[0162] For example, reference encoding can be performed on write data written as an ESB. In an example of reference encoding, the write data can be encoded such that bits corresponding to bits with a value of "1" in the second masking data and bits with a value of "1" (which is the value of the ESB of the highest fifteenth programming state P15) are reduced. After encoding, the second masking data can be updated based on the second masking data and the ESB data (e.g., encoded data). For example, in the LSB data and ESB data to be written (or written) to the memory cell MC, bits with the value of the LSB of the highest fifteenth programming state P15 and the value of the ESB can be detected. For example, in the LSB data, the position of the LSB with the value of the highest fifteenth programming state P15 can be detected, and in the ESB data, the position of the ESB with the value of the highest fifteenth programming state P15 can be detected. The second masking data can be updated to third masking data such that bits corresponding to the detected positions have a value of "1", and bits not corresponding to the detected positions have a value of "0".

[0163] In some example implementations, the second masking data can be updated based on the ESB data and the LSB data, which is the low-order data of the written data.

[0164] As described above, according to some example embodiments, reference encoding can be performed in the write data as USB writes. In the write data, the write data can be encoded such that bits corresponding to the bits with a value of "1" in the third masking data and bits with a value of "0" (which is the USB value of the highest fifteenth programming state P15) are reduced. After encoding, the third masking data can be updated to fourth masking data based on the third masking data and the USB data (e.g., encoded data).

[0165] In some example embodiments, the third masking data can be updated based on the USB data and the LSB and ESB data, which are low-order data of the data being written.

[0166] As described above, according to some example embodiments, reference encoding can be performed in the write data written as an MSB. In the write data, the write data can be encoded such that the bits corresponding to the bits of the fourth masking data that have a value of "1" and the bits that have a value of "1" (which is the USB value of the highest fifteenth programming state P15) are reduced. In some example embodiments, after encoding, the fourth masking data can be deleted, or the bits included in the fourth masking data can be initialized to have a value of "1".

[0167] Figure 11 An example of masking data for a first integer encoding is shown according to some example embodiments. Figure 11 Assume the first integer encoding is for the write data written as the MSB. Figure 11 In this context, masking data MDATA can be combined with... Figure 10 This corresponds to the fourth masking data in [the dataset]. Figure 11 In the example, assume that the bit pattern of the fifteenth programming state P15 is "1101".

[0168] Reference Figure 4 , Figure 10 and Figure 11 The first integer encoding can be performed as a reference encoding based on the masked data MDATA. In the written data, the written data can be encoded such that the bits corresponding to the bits with a value of "1" in the masked data MDATA and the bits with a value of "1" (which is the MSB value of the highest fifteenth programming state P15) are reduced.

[0169] For example, in the LSB data, ESB data, and USB data to be written (or written) to memory cells (e.g., memory cells corresponding to a page), the positions of the bits having the LSB value, ESB value, and USB value of the fifteenth programming state P15 can be detected. Among the bits MB1 to MB16 included in the masking data MDATA, the second bit MB2, the sixth bit MB6, the seventh bit MB7, and the fourteenth bit MB14 corresponding to the detected positions can have a value of "1". The remaining bits MB1, MB3, MB4, MB5, MB8, MB9, MB10, MB11, MB12, MB13, MB15, and MB16 not corresponding to the detected positions can have a value of "0". In the encoded data, the bits corresponding to the second bit MB2, the sixth bit MB6, the seventh bit MB7, and the fourteenth bit MB14 of the masking data MDATA can have a value of "0", where the value "0" is different from the value of the MSB of the fifteenth programming state P15.

[0170] Figure 12 An example of an alignment vector for second integer encoding is shown according to some example embodiments. Figure 12 In the example, we assume that the alignment vector “u” is shown for the second integer encoding.

[0171] Reference Figure 1 and Figure 12 The alignment vector “u” may include a first subvector u1 to a fourth subvector u4, and the number of bits in each of the first subvector u1 to the fourth subvector u4 may be 64, and the fourth subvector u4 may include a first integer parity bit SPB1 to an eighth integer parity bit SPB8.

[0172] In the data bus conversion encoding, an integer parity bit (SPB) is added for every eight data bits (DB) or sixteen data bits (DB).

[0173] According to some example embodiments, the second integer encoding can reduce power consumption caused by sending and receiving data between the non-volatile memory device 110 and the memory controller 120 by using a small number of integer parity bits (SPB). Therefore, the performance of the data bus conversion encoding can be improved.

[0174] Figure 13 An example of masking data for second integer encoding is shown according to some example embodiments. Figure 13 In this context, we assume that the alignment vector “u” is the updated alignment vector.

[0175] Reference Figure 1 , Figure 4 and Figure 13The second integer encoding can be performed as a reference encoding based on the masking data MDATA. The second integer encoding can be performed by referencing the masking data MDATA, thereby reducing the number of bits with a value of "1" in the encoded data.

[0176] E / D engine 124 can determine at least one bit (hereinafter referred to as a "candidate bit") in the alignment vector "u" whose bit value may be inverted as a result of the second integer encoding. For example, E / D engine 124 can determine at least one candidate bit in the alignment vector "u". In some example embodiments, at least one candidate bit can be determined from the bits in the alignment vector "u" that have a value of "1". Figure 13 In this context, the candidate bits can be the first data bit DB1, the second data bit DB2, the fourth data bit DB4, and the sixth data bit DB6 included in the alignment vector "u".

[0177] E / D engine 124 can generate masking data MDATA based on at least one determined candidate bit. The masking data MDATA can indicate the position of the candidate bit. For example, in the masking data MDATA, a bit with a value of "1" can indicate the position of a candidate bit, and a bit with a value of "0" can indicate the position of a bit that is not a candidate bit. Figure 13 In the masking data MDATA, the first bit MB1, the second bit MB2, the fourth bit MB4, and the sixth bit MB6 can indicate the position of the candidate bit.

[0178] E / D engine 124 can perform a second integer encoding based on the alignment vector "u" and the masking data MDATA. In the encoded data, the bits corresponding to the first bit MB1, the second bit MB2, the fourth bit MB4, and the sixth bit MB6 of the masking data MDATA can have a value of "0".

[0179] In some example embodiments, the E / D engine 124 may determine at least one candidate bit of data to be transmitted and / or sent to the non-volatile memory device 110.

[0180] Figure 14 An example of an alignment vector generator according to some example embodiments is shown. (See reference...) Figure 5B and Figure 14 The alignment vector generator 300 may include a bit aligner 310, an integer parity bit (SPB) generator 320, a second matrix multiplier calculator 330, a counter 340, and a comparator 350. Figure 14 In the middle, the alignment unit 310 and the LLR information generator 321 perform the operation with... Figure 5B The bit aligner 221 and the LLR information generator 222a operate the same way. Therefore, for ease of description, additional descriptions are omitted to avoid redundancy.

[0181] The integer parity bit value (SPBV) determiner 322 can generate one or more candidate sets, each representing a combination of integer parity bit values. For example, the integer parity bit value determiner 322 can use a parity value search algorithm to generate a first candidate alignment vector CDu1 that includes a first combination of integer parity bit SPB values. The integer parity bit value determiner 322 can generate a second candidate alignment vector CDu2 that includes a second combination of integer parity bit SPB values. As described above, in some example embodiments, the integer parity bit value determiner 322 can generate a p-th candidate alignment vector CDup that includes the p-th combination (where p is a natural number greater than "1").

[0182] The second matrix multiplication calculator 330 can perform matrix multiplication calculations for each of one or more candidate groups. For example, the second matrix multiplication calculator 330 can perform a second matrix multiplication calculation between a first candidate alignment vector CDU1 and a generator matrix GM based on a modified polar code. The second matrix multiplication calculator 330 can perform a second matrix multiplication calculation between a second candidate alignment vector CDU2 and a generator matrix GM based on a modified polar code. As described above, in some example embodiments, the second matrix multiplication calculator 330 can perform a second matrix multiplication calculation between a p-th candidate alignment vector CDup and a generator matrix GM based on a modified polar code.

[0183] Counter 340 can count the number of bits that satisfy a specific or alternatively desired bit value based on the result of a second matrix multiplication calculation for each of a plurality of candidate alignment vectors.

[0184] For example, counter 340 can count the number of bits with values ​​of "1" or "0" in the result of the second matrix multiplication of each of the plurality of candidate alignment vectors. In some example embodiments, when performing the first integer encoding, counter 340 can count the number of bits associated with the fifteenth programming state P15, which is the target state. In some example embodiments, when performing the second integer encoding, counter 340 can count the number of bits with values ​​of "1".

[0185] Comparator 350 can compare the counting result of counter 340. Comparator 350 can select one of one or more candidate groups based on the comparison result. For example, when performing the first integer encoding, comparator 350 can select the candidate alignment vector with the fewest bits associated with the fifteenth programming state P15 from the first candidate alignment vector CDu1 to the p-th candidate alignment vector CDup. For example, when performing the second integer encoding, comparator 350 can select the candidate alignment vector with the fewest bits with a value of "1" from the first candidate alignment vector CDu1 to the p-th candidate alignment vector CDup.

[0186] Comparator 350 can output the selected candidate alignment vector to the first matrix multiplier calculator 230.

[0187] In some example embodiments, comparator 350 may output the result of a second matrix multiplication computation with respect to the selected candidate alignment vector and the generator matrix GM based on the modified polar code. For example, the first matrix multiplication calculator 230 may not perform the second matrix multiplication computation on the data output from comparator 350.

[0188] Figure 15A The following are illustrated according to some example embodiments. Figure 4 An example of a flowchart illustrating the operation of an encoder. Figure 15B The following are examples of configurations based on certain example embodiments. Figure 15A The encoder performs the operation according to the flowchart. (Refer to...) Figure 15A and Figure 15B The encoder 400 can perform joint encoding that combines error correction coding and shaping coding.

[0189] For example, in operation S210, encoder 400 can obtain channel selection information (CSI) indicating the position of the data bit DB and the position of the integer parity bit SPB in the input data IDATA. Figure 15B The channel selector 410 can distinguish multiple channels into good channels and bad channels by channel polarization based on polarity codes. Good channels can be used to shape the parity bit SPB, and bad channels can be used to shape the ECC parity bit EPB and the data bits DB of the input data IDATA.

[0190] In operation S220, encoder 400 can generate an alignment vector "u" by aligning the data bits DB, ECC parity bits EPB, and shaped parity bits SPB based on channel selection information CSI. For example, Figure 15B The bit aligner 421 can receive ECC parity bit EPBs with initial values ​​from ECC parity bit generator 422, and can receive integer parity bit SPBs with initial values ​​from integer parity bit generator 423. In some example embodiments, each of the initial values ​​can be arbitrary. The bit aligner 421 can generate an alignment vector “u” by aligning data bits DB with specific values, ECC parity bit EPBs with initial values, and integer parity bit SPBs with initial values.

[0191] In operation S230, encoder 400 can determine the value of the ECC parity bit EPB. For example, Figure 15BThe ECC parity bit determiner 422a can determine the value of the ECC parity bit EPB based on the generator matrix GM, which is based on the modified polarity code. For example, the ECC parity bit value (EPBV) determiner 422a can perform a matrix multiplication of the generator matrix GM, which has a size of “n” × “n”, and the transpose of the parity matrix HM, which has a size of “1” × “n” (where “n” is a natural number greater than “1”). The ECC parity bit determiner 422a can determine the value of the ECC parity bit EPB based on the result of the matrix multiplication of the generator matrix GM and the transpose of the parity matrix HM. For example, the alignment vector “u”, the generator matrix GM, and the transpose of the parity matrix HM can satisfy the following Equation 2.

[0192] [Equation 2]

[0193] u*GM*HM T =0

[0194] In Equation 2, "u" represents the alignment vector "u", GM represents the generating matrix GM, and HM T It can represent the transpose of the parity check matrix HM.

[0195] In operation S240, encoder 400 can generate second LLR information LLRI2, including integer parity bit SPB, for a target vector u_TRG based on first LLR (log-likelihood ratio) information LLRI1 associated with the alignment vector "u". The target vector u_TRG is a part of the alignment vector "u" and may include the integer parity bit SPB. Each of the first LLR information LLRI1 and the second LLR information LLRI2 may include a different number of LLR values. For example, Figure 15B The LLR information generator 423a can generate a second LLR information LLRI2 based on the accumulation of the first LLR information LLRI1. The LLR information generator 423a can generate the second LLR information LLRI2, which includes the first LLR information LLRI1, based on the accumulation calculation.

[0196] In operation S250, encoder 400 can determine the value of the integer parity bit SPB based on the target vector u_TRG and the second LLR information LLRI2. For example, Figure 15B The integer parity bit value determiner 423b can determine the value of the integer parity bit SPB based on the target vector u_TRG and the second LLR information LLRI2.

[0197] For example, the integer parity bit determiner 423b can use a parity value search algorithm to determine the value of the integer parity bit SPB from the target vector u_TRG and the second LLR information LLRI2. In some example embodiments, the integer parity bit determiner 423b can use a polarity decoding algorithm to determine the value of the integer parity bit SPB. For example, the integer parity bit determiner 423b can use the SC (continuous elimination) algorithm, the list SC (list continuous elimination) algorithm, the brute-force search algorithm, etc., to determine the value of the integer parity bit SPB.

[0198] In operation S260, encoder 400 can perform an update operation on the integer parity bit SPB based on a determined value. For example, Figure 15B The bit aligner 421 can receive a determined value from the integer parity bit value determiner 423b. The bit aligner 421 can perform an update operation on the integer parity bit SPB based on the determined value. As a result of the operation, the value of the integer parity bit SPB can be updated from the initial value to the determined value.

[0199] In operation S270, after the update operation, encoder 400 can generate a codeword CW about the alignment vector "u" based on the first matrix multiplication of the target vector u_TRG and the first generator matrix GM1. For example, Figure 15B The matrix multiplication calculator 430 can receive the alignment vector "u" from the alignment vector generator 420 after the update operation. The matrix multiplication calculator 430 can generate a codeword CW for the alignment vector "u" based on a first matrix multiplication of the target vector u_TRG, which is part of the alignment vector "u", and the first generator matrix GM1. The first generator matrix GM1 can refer to the sub-generator matrix SGM included in the generator matrix GM based on the modified polar code.

[0200] In some example embodiments, encoder 400 may also include masking data generator 440. Masking data generator 440 may correspond to Figure 5B The masking data generator 240. Therefore, for ease of description, additional descriptions are omitted to avoid redundancy.

[0201] Figure 16 An example of an alignment vector for joint encoding is shown according to some example embodiments.

[0202] Reference Figure 16The alignment vector "u" can include first sub-vectors u1 to fourth sub-vectors u4. The first sub-vector u1 can include first data bits DB1 to fifth data bits DB5, the second sub-vector u2 can include sixth data bits DB6 to eighth data bits DB8, first ECC parity bit EPB1 and ninth data bit DB9, the third sub-vector u3 can include tenth data bits DB10 and eleventh data bits DB11, second ECC parity bit EPB2, and twelfth data bits DB12 and thirteenth data bits DB13, and the fourth sub-vector u4 can include fourteenth data bits DB14 to sixteenth data bits DB16, first integer parity bit SPB1 and second integer parity bit SPB2.

[0203] When error correction coding and integer coding are performed sequentially, there may be a performance degradation issue in integer coding because the ECC parity bit is not subjected to integer coding. According to some example embodiments, joint coding can reduce or prevent performance degradation caused by the sequential operation of error correction coding and integer coding by combining error correction coding and integer coding.

[0204] Figure 17 Examples of operations for describing shaping decoding are shown according to some example embodiments.

[0205] Reference Figure 1 , Figure 6 , Figure 8 and Figure 17 The E / D engine 124 can perform integer decoding on the third data DATA3. The data after integer decoding can be the same as the data before integer encoding. For example, the E / D engine 124 can recover data by performing integer decoding.

[0206] Integer decoding can be performed in a manner similar to integer encoding. For example, integer decoding can be performed based on the third matrix multiplication of the target subdata SD_TRG and the sub-generator matrix SGM.

[0207] exist Figure 17 In this context, the third data DATA3 can include "n" bits. The third data DATA3 can include the first sub-data SD1 to the m-th sub-data SDm. Each of the first sub-data SD1 to the m-th sub-data SDm can include "k" bits.

[0208] The first sub-data SD1 to the m-th sub-data SDm can be arranged sequentially along the row direction within the third data DATA3. The last sub-data SDm in the first sub-data SD1 to the m-th sub-data SDm can be the target sub-data SD_TRG.

[0209] In some example embodiments, the third data DATA3 may be associated with data that has undergone integer encoding (e.g., codeword CW). For example, the third data DATA3 may be read data output from the non-volatile memory device 110. For example, the memory controller 120 may transmit and / or send integer-encoded data to the non-volatile memory device 110. The non-volatile memory device 110 may write data received from the memory controller 120. The non-volatile memory device 110 may perform a read operation on the written data and may output the read data as the third data DATA3 to the memory controller 120.

[0210] For example, the third data DATA3 may be data that has undergone error correction coding. In some example embodiments, the memory controller 120 may perform error correction coding on the data that has undergone integer coding. The memory controller 120 may transmit and / or send the error-corrected data to the non-volatile memory device 110. The non-volatile memory device 110 may write data received from the memory controller 120. The non-volatile memory device 110 may perform a read operation on the written data and may output the read data to the memory controller 120. The memory controller 120 may perform error correction decoding on the data output from the non-volatile memory device 110. The memory controller 120 may perform integer decoding on the data that has undergone error correction decoding.

[0211] According to some example embodiments, memory controller 120 can perform joint encoding combining shaping encoding and error correction encoding. Memory controller 120 can transmit and / or send the jointly encoded data to non-volatile memory device 110. Non-volatile memory device 110 can write data received from memory controller 120. Non-volatile memory device 110 can perform read operations on the written data and can output the read data to memory controller 120. Memory controller 120 can perform error correction decoding on the data output from non-volatile memory device 110. Memory controller 120 can perform shaping decoding on the data that has undergone error correction decoding.

[0212] However, the example embodiments are not limited thereto, and in some example embodiments, the third data DATA3 may be associated with integer-encoded data and may represent various data received from the non-volatile memory device 110.

[0213] In some example embodiments, the memory controller 120 may perform iterative decoding when performing error correction decoding and shaping decoding. For example, when an error is detected by CRC (Cyclic Redundancy Check) verification, the memory controller 120 may iteratively perform error correction decoding and shaping decoding until the termination condition of iterative decoding is met. In some example embodiments, the termination condition of iterative decoding may be preset. For example, iterative decoding may be terminated when the number of iterations reaches the maximum number of iterations. For example, iterative decoding may be terminated when no error is detected by CRC verification.

[0214] Figure 18 An example of the result of shaping decoding according to some example embodiments is shown. Figure 18 In this context, it is assumed that the encoded data EDATA includes the first sub-data SD1 to the fourth sub-data SD4.

[0215] Reference Figure 1 , Figure 8 , Figure 17 and Figure 18 Integer decoding can be performed based on the third matrix multiplication of the fourth sub-data SD4 (which serves as the target sub-data SD_TRG) and the sub-generator matrix SGM. As a result of the integer decoding, decoded data DDATA can be generated. Decoded data DDATA can include the first decoded data DD1 through the fourth decoded data DD4.

[0216] For example, the first decoded data DD1 can be obtained by logically calculating the result R3 of the third matrix multiplication of the fourth sub-data SD4 and the sub-generator matrix SGM with the first sub-data SD1. The second decoded data DD2 can be obtained by logically calculating the result R3 of the third matrix multiplication and the second sub-data SD2. The third decoded data DD3 can be obtained by logically calculating the result R3 of the third matrix multiplication and the third sub-data SD3. The fourth decoded data DD4 can be the result R3 of the third matrix multiplication.

[0217] In some example embodiments, a logical computation may represent an XOR logical computation.

[0218] like Figure 18 As shown, decoded data DDATA can be generated based on the third matrix multiplication calculation of the target sub-data SD_TRG and the sub-generator matrix SGM, and the logical calculation of each of the remaining sub-data SD1 to SD3 (excluding the target sub-data SD_TRG) with the result R3 of the third matrix multiplication calculation.

[0219] Figure 19 A memory system according to some example embodiments is illustrated. (Refer to...) Figure 19The memory system 1000 may include a memory controller 1100, an E / D circuit 1200, and a memory device 1300. The memory controller 1100 may store data in the memory device 1300 and / or may read data stored in the memory device 1300.

[0220] In some example embodiments, the E / D circuit 1200 may be located in the data path between the memory controller 1100 and the memory device 1300. The E / D circuit 1200 may be configured to perform shaping encoding or shaping decoding on data transmitted and / or sent and received between the memory controller 1100 and the memory device 1300. In some example embodiments, the E / D circuit 1200 may be configured to perform error correction encoding or error correction decoding on data transmitted and / or sent and received between the memory controller 1100 and the memory device 1300.

[0221] In some example embodiments, the E / D circuit 1200 may be based on a reference. Figures 1 to 18 The described operation method performs integer encoding and / or integer decoding.

[0222] Figure 20 This is a block diagram illustrating a memory system according to some example embodiments. (Refer to...) Figure 20 The memory system 2000 may include a memory controller 2100 and a memory device 2200. The memory controller 2100 may include a controller E / D circuit 2110. The controller E / D circuit 2110 may perform shaping encoding on write data to be stored in the memory device 2200 and shaping decoding on read data received from the memory device 2200. In some example embodiments, the controller E / D circuit 2110 may perform error correction encoding on write data to be stored in the memory device 2200 and error correction decoding on read data received from the memory device 2200.

[0223] Memory device 2200 may include memory E / D circuitry 2210. Memory E / D circuitry 2210 may perform shaping decoding on write data received from memory controller 2100 and shaping encoding on read data stored in memory device 2200. In some example embodiments, memory E / D circuitry 2210 may perform error correction decoding on write data received from memory controller 2100 and error correction encoding on read data stored in memory device 2200.

[0224] In some example embodiments, each of the controller E / D circuit 2110 and the memory E / D circuit 2210 may be based on a reference. Figures 1 to 18 The described method performs integer encoding or integer decoding.

[0225] In some exemplary embodiments, components according to this disclosure are described using the terms "first," "second," "third," etc. However, the terms "first," "second," "third," etc., may be used to distinguish components from each other and do not limit this disclosure. For example, the terms "first," "second," and "third" do not imply any form of order or numerical meaning.

[0226] According to some example embodiments, the storage device can reduce computational complexity based on calculations based on modified polarity codes. In some example embodiments, since error correction coding can be performed concurrently with data shaping coding, a storage device and a method of operating the storage device are provided with improved performance and improved reliability.

[0227] As described herein, any device, electronic device, module, unit, and / or a portion thereof, and / or any part thereof, according to any example embodiment, may include processing circuitry such as hardware including logic circuitry; hardware / software combinations such as processors executing software; or one or more instances of any combination thereof, which may be included in, and / or implemented by, said one or more instances. For example, the processing circuitry may more specifically include, but is not limited to, a central processing unit (CPU), an arithmetic logic unit (ALU), a graphics processing unit (GPU), an application processor (AP), a digital signal processor (DSP), a microcomputer, a field-programmable gate array (FPGA) and programmable logic units, a microprocessor, an application-specific integrated circuit (ASIC), a neural network processing unit (NPU), an electronic control unit (ECU), an image signal processor (ISP), etc. In some example embodiments, the processing circuitry may include a non-transitory computer-readable storage device (e.g., memory), such as a solid-state drive (SSD) storing instructions for a program, and a processor (e.g., CPU) configured to execute instructions to implement functions and / or methods performed by some or all of any device, electronic device, module, unit, and / or a portion thereof according to any example embodiment.

[0228] As described herein, any memory described herein may be non-volatile memory (such as flash memory, phase-change random access memory (PRAM), magnetoresistive RAM (MRAM), resistive RAM (ReRAM) or ferroelectric RAM (FRAM)) or volatile memory (such as static RAM (SRAM), dynamic RAM (DRAM) or synchronous DRAM (SDRAM)).

[0229] As described herein, any or all elements described with reference to the accompanying drawings may communicate with any or all other elements described with reference to the accompanying drawings. For example, any element may communicate unidirectionally and / or bidirectionally and / or broadcastly with any or all other elements in the drawings to transmit and / or exchange and / or receive information (such as, but not limited to, data and / or commands) via a bus (not shown), such as a wireless and / or wired bus, in a manner such as serial and / or parallel. The information may be in various encoded formats, such as analog and / or digital formats.

[0230] The above description provides some exemplary embodiments for implementing the inventive concept. Some exemplary embodiments that can be simply or easily modified may be included in the inventive concept and the above-described exemplary embodiments. Techniques that can be easily modified and implemented using the above-described exemplary embodiments may be included in the inventive concept.

Claims

1. A method of operating a storage device, the storage device comprising a non-volatile memory device and a memory controller configured to control the non-volatile memory device, the method comprising: The memory controller obtains channel selection information, which indicates the position of data bits and the position of integer parity bits included in the input data; The memory controller generates an alignment vector by aligning the data bits and the integer parity bits with arbitrary values ​​based on the channel selection information. The memory controller generates a second log-likelihood ratio information for the target vector, which includes the shaped parity bit, based on a first log-likelihood ratio information associated with the alignment vector. The memory controller determines the value of the integer parity bit based on the target vector and the second log-likelihood ratio information; The memory controller performs an update operation on the integer parity bit based on the determined value; as well as The memory controller generates codewords for the input data based on a first matrix multiplication of the target vector and the first generating matrix after performing the update operation.

2. The method according to claim 1, wherein, The alignment vector comprises multiple sub-vectors arranged in a sequential order. Wherein, the target vector represents the last sub-vector in the plurality of sub-vectors, and Generating the codeword for the input data includes performing a logical calculation on the result of multiplying each of the plurality of sub-vectors other than the target vector with the first matrix.

3. The method according to claim 2, wherein, The first matrix multiplication and the logical computation are performed based on a second matrix multiplication calculation relating the alignment vector following the update operation and a second generation matrix including the first generation matrix. The second generating matrix has an size of "n" × "n", where "n" is the number of bits included in the alignment vector. The second generating matrix comprises matrices from the first column to the m-th column, where "m" is the number of the sub-vectors, and The first generating matrix has a size of "k"×"k", where "k" is the number of bits included in each of the plurality of sub-vectors.

4. The method according to claim 1, wherein, Generating the second log-likelihood ratio information includes: generating probability values ​​included in the second log-likelihood ratio information that are included in the first log-likelihood ratio information based on the cumulative calculation of probability values ​​included in the first log-likelihood ratio information.

5. The method according to claim 1, wherein, The non-volatile memory device includes multiple memory cells, and Specifically, the process involves determining the value of the integer parity bit to reduce the number of memory cells in the target state of the programming states programmed into the plurality of memory cells.

6. The method according to claim 5, further comprising: Data associated with the codeword is written by the non-volatile memory device; Data read and written by the non-volatile memory device; as well as The input data is recovered by the memory controller based on the target data in the read data and the third matrix multiplication of the first generated matrix.

7. The method according to claim 1, wherein, The value of the integer parity check bit is determined to reduce the number of bits in the codeword that have the first value.

8. The method according to claim 7, further comprising: The non-volatile memory device receives data associated with the codeword from the memory controller; as well as The non-volatile memory device calculates the received data back to the input data based on the target data in the received data and the third matrix multiplication of the first generating matrix.

9. A method of operating a storage device, the storage device comprising a non-volatile memory device and a memory controller configured to control the non-volatile memory device, the method comprising: The memory controller obtains channel selection information, which indicates the position of data bits, error correction code parity bits, and integer parity bits included in the input data. The memory controller generates an alignment vector by aligning the data bits, the error correction code parity bits, and the shaped parity bits based on the channel selection information. The value of the parity bit of the error correction code is determined by the memory controller; The memory controller generates a second log-likelihood ratio information for the target vector, which includes the shaped parity bit, based on a first log-likelihood ratio information associated with the alignment vector. The memory controller determines the value of the integer parity bit based on the target vector and the second log-likelihood ratio information; The memory controller performs an update operation on the integer parity bit based on the determined value; as well as The memory controller generates codewords for the input data based on a first matrix multiplication of the target vector and the first generating matrix after performing the update operation.

10. The method according to claim 9, wherein, The alignment vector comprises multiple sub-vectors arranged in a sequential order. Wherein, the target vector represents the last sub-vector in the plurality of sub-vectors, and Generating the codeword for the input data includes performing a logical calculation on each of the remaining sub-vectors (excluding the target vector) and the result of the first matrix multiplication.

11. The method according to claim 10, wherein, The first matrix multiplication and the logical computation are performed based on a second matrix multiplication calculation relating the alignment vector following the update operation and a second generation matrix including the first generation matrix. The second generating matrix has an size of "n" × "n", where "n" is the number of bits included in the alignment vector. The second generating matrix comprises matrices from the first column to the m-th column, where "m" is the number of the sub-vectors, and The first generating matrix has a size of "k"×"k", where "k" is the number of bits included in each of the plurality of sub-vectors.

12. The method according to claim 9, wherein, Generating the second log-likelihood ratio information includes: generating probability values ​​included in the second log-likelihood ratio information that are included in the first log-likelihood ratio information based on the cumulative calculation of probability values ​​included in the first log-likelihood ratio information.

13. The method according to claim 9, wherein, The non-volatile memory device includes multiple memory cells, and Specifically, the process involves determining the value of the integer parity bit to reduce the number of memory cells in the target state of the programming states programmed into the plurality of memory cells.

14. The method of claim 13, further comprising: Data associated with the codeword is written by the non-volatile memory device; Data read and written by the non-volatile memory device; The memory controller performs error correction decoding on the read data, and The input data is recovered by the memory controller based on the target data in the error-corrected decoded data and the third matrix multiplication of the first generated matrix.

15. The method according to claim 9, wherein, The value of the integer parity check bit is determined to reduce the number of bits in the codeword that have the first value.

16. The method of claim 15, further comprising: The codeword is received from the memory controller by the non-volatile memory device; The non-volatile memory device performs error correction decoding on the received codewords; as well as The non-volatile memory device calculates the third matrix multiplication of the target data in the error-corrected decoded data and the first generating matrix to restore the input data.

17. The method according to claim 9, wherein, The value of the parity bit of the error correction code is determined by a fourth matrix multiplication based on the transpose of the second generator matrix, which includes the first generator matrix, and the parity check matrix.

18. A storage device, comprising: Non-volatile memory devices; as well as The memory controller is configured as follows: Control the non-volatile memory device, Obtain channel selection information indicating the positions of data bits and integer parity bits in the input data. An alignment vector is generated by aligning the data bits and the integer parity bits based on the channel selection information. A second log-likelihood ratio is generated based on the first log-likelihood ratio information associated with the alignment vector, which includes the integer parity bit. The value of the integer parity bit is determined based on the target vector and the second log-likelihood ratio information. An update operation is performed on the integer parity bit based on the determined value, and Based on the target vector and the first matrix multiplication of the first generating matrix, codewords for the input data are generated.

19. The storage device according to claim 18, wherein, The alignment vector comprises multiple sub-vectors arranged in a sequential order. Wherein, the target vector represents the last sub-vector in the plurality of sub-vectors, and The memory controller is configured to generate the codeword based on a logical calculation of the result of the first matrix multiplication with respect to each of the plurality of subvectors other than the target vector.

20. The storage device according to claim 19, wherein, The first matrix multiplication and the logical computation are performed based on a second matrix multiplication calculation relating the alignment vector following the update operation and a second generation matrix including the first generation matrix. The second generating matrix has an size of "n" × "n", where "n" is the number of bits included in the alignment vector. The second generating matrix comprises matrices from the first column to the m-th column, where "m" is the number of the sub-vectors, and The first generating matrix has a size of "k"×"k", where "k" is the number of bits included in each of the plurality of sub-vectors.

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