Methods, devices, media, and products for reducing branch prediction error overhead

Abstract

This application discloses a method, apparatus, medium, and product for reducing branch prediction error overhead. The method includes: in response to a signal indicating that both instructions are conditional jumps, obtaining a first target instruction, a second target instruction, and an update opcode of the first target instruction with identical physical registers; when the first target instruction is triggered again, if the prediction result of the first target instruction is a jump and the prediction is incorrect, obtaining the target register based on the update opcode, obtaining the branch jump target result accordingly, and re-fetching the second target instruction based on this result after pipeline flushing. This method can, when the first target instruction is triggered again and a predicted jump occurs with an error, obtain the branch jump target result corresponding to the associated second target instruction based on the corresponding register information, discarding the prediction result of the prediction module itself, effectively avoiding the overhead of a single branch prediction error and pipeline flushing.

Description

Technical Field

[0001] This disclosure relates to the field of computer technology, and in particular to a method, apparatus, medium, or product for reducing branch prediction error overhead. Background Technology

[0002] In high-level programming languages, conditional branching structures are a core means of implementing logical control. Their function is to execute different code blocks based on the results of variable comparisons. At the low-level assembly level, these structures typically calculate operand differences using comparison instructions and set flag registers (such as the sign bit SF, overflow bit OF, and zero flag ZF). Then, conditional jump instructions determine the program flow based on the flag status. The direction of the branch jump directly depends on the comparison result, which in turn comes from real-time calculations of register values ​​or memory data, exhibiting dynamic uncertainty. For branches that rely on real-time computation or memory access results, the jump direction cannot be determined by static analysis before instruction execution. The branch prediction module needs to guess the jump direction based on historical behavior or heuristic rules. However, the conditions of such branches depend on dynamic data (such as variable values ​​and memory contents), and their jump patterns will lack regularity due to changes in input data. In this case, the branch prediction module has difficulty accurately capturing the jump pattern, resulting in a significant increase in the branch prediction error rate.

[0003] Branch prediction errors trigger CPU pipeline flushing operations. For example, if an incorrect path instruction that has been prefetched, decoded, or partially executed is discarded, the CPU needs to fetch, decode, and fill the pipeline again from the correct jump target. This process introduces additional clock cycle overhead and interrupts the continuous execution of the instruction stream. When such unpredictable branches occur frequently, frequent pipeline flushing will severely reduce the CPU's instruction throughput and become the main bottleneck of system performance. Summary of the Invention

[0004] In view of this, the present disclosure provides a method, apparatus, medium, and product for reducing branch prediction error overhead, which can solve the problems in the prior art where conditional branches that rely on dynamic comparison results are difficult to predict in terms of jump direction, resulting in high branch prediction error rate and large error overhead.

[0005] In a first aspect, embodiments of this disclosure provide a method for reducing branch prediction error overhead, including: In response to the occurrence of a conditional jump signal for both instructions, a first target instruction and a second target instruction with consistent physical registers are obtained; the first target instruction is executed before the second target instruction, and the prediction result of the first target instruction is no jump; Obtain the update opcode of the first target instruction; When the first target instruction is triggered again, in response to the signal that the prediction result of the first target instruction is a jump and the prediction is wrong, the target register is obtained based on the update opcode; The branch jump target result is obtained based on the target register, and the second target instruction is re-fetched based on the branch jump target result after pipeline flushing.

[0006] Secondly, this disclosure also provides a computer device, which adopts the following technical solution: The computer device includes: At least one processor; and, A memory communicatively connected to the at least one processor; wherein, The memory stores instructions that can be executed by the at least one processor to enable the at least one processor to perform any of the above-described methods for reducing branch prediction error overhead.

[0007] Thirdly, embodiments of this disclosure also provide a computer-readable storage medium storing computer instructions; the computer instructions are used to cause a computer to perform any of the methods described above for reducing branch prediction error overhead.

[0008] Fourthly, embodiments of this disclosure also provide a computer program product, including a computer program / instructions that, when executed by a processor, implement the steps of any of the methods described above.

[0009] The method for reducing branch prediction error overhead provided in this disclosure, in response to the occurrence signal of two instructions both being conditional jumps, obtains a first target instruction and a second target instruction with consistent physical registers, i.e., obtains two related conditional branch instructions; then obtains the update opcode of the first target instruction; when the first target instruction is triggered again, in response to the signal that the prediction result of the first target instruction is a jump and the prediction is wrong, obtains the target register based on the update opcode; obtains the branch jump target result based on the target register, and after pipeline flushing, executes the re-fetching of the second target instruction based on the branch jump target result, abandoning the prediction result of the prediction module itself, ensuring that the branch jump target result is always correct. This method can intervene and analyze the second instruction in a timely manner to obtain the correct result when both conditional branch instructions have branch prediction errors, effectively reducing the number of branch prediction errors and avoiding unnecessary misprediction overhead.

[0010] The above description is merely an overview of the technical solution disclosed herein. In order to better understand the technical means of this disclosure and to implement it in accordance with the contents of the specification, and to make the above and other objects, features and advantages of this disclosure more apparent and understandable, preferred embodiments are described below in detail with reference to the accompanying drawings. Attached Figure Description

[0011] To more clearly illustrate the technical solutions of the embodiments of this disclosure, the drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this disclosure. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0012] Figure 1 This is a flowchart illustrating a method for reducing branch prediction error overhead provided in an embodiment of this disclosure.

[0013] Figure 2 This is a flowchart illustrating the method for obtaining the first target instruction and the second target instruction provided in the embodiments of this disclosure.

[0014] Figure 3 This is a flowchart illustrating a method for re-fetching instructions based on the branch jump target result after pipeline flushing, as provided in an embodiment of this disclosure.

[0015] Figure 4 This is a schematic diagram illustrating the execution of jl and jnle according to the prediction results in the embodiments of this disclosure.

[0016] Figure 5 This is a schematic diagram illustrating the execution of jnle according to the optimization scheme in an embodiment of this disclosure.

[0017] Figure 6 This is a schematic diagram of the structure of a computer device provided in an embodiment of the present disclosure. Detailed Implementation

[0018] The embodiments of this disclosure will now be described in detail with reference to the accompanying drawings.

[0019] It should be understood that the following specific examples illustrate the implementation of this disclosure, and those skilled in the art can easily understand other advantages and effects of this disclosure from the content disclosed in this specification. Obviously, the described embodiments are only a part of the embodiments of this disclosure, and not all of them. This disclosure can also be implemented or applied through other different specific implementation methods, and the details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of this disclosure. It should be noted that, in the absence of conflict, the following embodiments and features in the embodiments can be combined with each other. Based on the embodiments in this disclosure, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this disclosure.

[0020] It should be noted that various aspects of embodiments within the scope of the appended claims are described below. It will be apparent that the aspects described herein can be embodied in a wide variety of forms, and any particular structure and / or function described herein is merely illustrative. Based on this disclosure, those skilled in the art will understand that one aspect described herein can be implemented independently of any other aspect, and two or more of these aspects can be combined in various ways. For example, any number of aspects set forth herein can be used to implement the device and / or practice the method. Additionally, this device and / or method can be implemented using structures and / or functionalities other than one or more of the aspects set forth herein.

[0021] It should also be noted that the illustrations provided in the following embodiments are only schematic representations of the basic concept of this disclosure. The drawings only show the components related to this disclosure and are not drawn according to the number, shape and size of the components in actual implementation. In actual implementation, the form, quantity and proportion of each component can be arbitrarily changed, and the layout of the components may also be more complex.

[0022] Furthermore, specific details are provided in the following description to facilitate a thorough understanding of the examples. However, those skilled in the art will understand that the described aspects can be practiced without these specific details.

[0023] Reference Figure 1 This application discloses a method for reducing branch prediction error overhead, comprising: S100, in response to the occurrence signal of the conditional jump for both instructions, obtains the first target instruction and the second target instruction that are consistent with the physical registers.

[0024] In this case, the first target instruction is executed before the second target instruction, and the prediction result of the first target instruction is no jump.

[0025] Physical register consistency means that the flag register results corresponding to the first target instruction and the second target instruction are generated by the same calculation instruction.

[0026] In this embodiment, the first target instruction and the second target instruction constitute a set of target instruction pairs. In this application, at least one set of target instruction pairs with such characteristics can be obtained.

[0027] S200, obtain the update opcode of the first target instruction.

[0028] S300: When the first target instruction is triggered again, in response to the signal that the prediction result of the first target instruction is a jump and the prediction is wrong, the target register is obtained based on the update opcode.

[0029] S400 obtains the branch jump target result based on the target register, and after pipeline flushing, executes the second target instruction re-fetch based on the branch jump target result.

[0030] In this embodiment, S100 and S200 can be understood as the training phase, the purpose of which is to acquire all such target instruction pairs; S300 and S400 can be understood as the optimization phase. For program execution, for example, such target instruction pairs can be identified in the first N rounds of execution. In subsequent rounds, whenever the prediction result of the first target instruction in the target instruction pair is a jump and the prediction is incorrect, the jump direction of the second target instruction in the target instruction pair can be obtained based on the existing flag register result. This direction is the correct branch direction, and it is not necessary to predict the direction of the second target instruction in the target instruction pair. That is, the prediction result of the prediction module itself is abandoned, ensuring that the branch jump target result is always correct. For two related conditional branch instructions, if both conditional branch instructions are predicted incorrectly, one branch misprediction is reduced, thereby achieving performance improvement and power saving.

[0031] Reference Figure 2 For S100, the methods for obtaining the first target instruction and the second target instruction specifically include: S110, in response to the instruction length decoding completion signal, identifies the opcode of the instruction.

[0032] Specifically, when the decoder parses the instruction, it extracts the opcode field from the instruction stream, that is, it identifies the opcode of the instruction.

[0033] S120 determines the instruction type of the corresponding instruction based on the opcode.

[0034] In this embodiment, the opcode of the conditional jump instruction (jcc) includes short jump (8-bit offset) and long jump (32-bit offset). The main opcode range of short jump (short jcc) is 0x70~0x7F (16 types in total, corresponding to 16 conditions); long jump (long jcc): opcode prefix 0x0F and main opcode is 0x80~0x8F (16 types in total, corresponding one-to-one with short jump conditions).

[0035] S130, in response to the occurrence signal of the two instructions being both conditional jumps, retrieves the first physical register and the second physical register corresponding to the two instructions respectively.

[0036] Specifically, by consulting the renaming table (which records the mapping from architecture registers to physical registers), you can obtain the physical registers corresponding to the source operands (flag registers) of each of the two JCC instructions.

[0037] S140, if the second physical register is consistent with the first physical register, and the prediction result of the first instruction of the two instructions is no jump and the prediction is correct, the two instructions are recorded as the first target instruction and the second target instruction respectively.

[0038] In this embodiment, there is no jump instruction between the first target instruction and the second target instruction in the program sequence.

[0039] For each instruction, the operation follows the logic of prediction, fetch, decoding, renaming, and execution. If this embodiment addresses the case of two consecutive conditional jump instructions, a detection device is added during the renaming stage. This device identifies the instruction's opcode after decoding the instruction length, compares the opcodes, and detects whether it belongs to the opcode of a conditional jump instruction, thereby identifying two consecutive JCC instructions.

[0040] If this embodiment addresses the case where two conditional jump instructions are not consecutive, a detection device is added during the decoding stage. This device identifies the opcode of the instruction after the instruction length is decoded, compares the opcodes of the instructions, and detects whether it belongs to the opcode of a conditional jump instruction.

[0041] In this embodiment, the same calculation instruction refers to the same cmp instruction, which is used to compare two operands (e.g., cmpA, B). It actually performs a subtraction operation (AB), but does not save the result; it only sets the flag register based on the result.

[0042] In this application, SOC stands for System-on-a-Chip. SoC, also known as a system-on-a-chip, refers to a product, a dedicated integrated circuit containing a complete system and embedded software. Conditional instructions determine different operations based on whether a condition is true or false. Similar instructions exist in different instruction sets. For example, in the x86 instruction set, JCC determines whether to jump based on a flag bit result.

[0043] The flag register sets different flags based on the instruction execution result. Taking x86 instructions as an example, the commonly used flag register definitions are as follows: 1) ZF (Zero Flag): Checks if the result is 0. If the result is zero (i.e., A=B), it is set to 1; 2) SF (Sign Flag): Checks if the result is negative. If the result is negative, it is set to 1; 3) OF (Overflow Flag): Checks if the result of a signed calculation overflows. If the result overflows, it is set to 1; 4) CF: The range that the overflow register can represent; 5) AF: Auxiliary carry, if the 4-bit register cannot hold the result, a carry occurs; 6) PF: The number of 1s in the result. In the code, a cmp instruction is usually executed first to compare two values, and then multiple conditional jump instructions can be used to branch based on the result of this comparison.

[0044] The method for "obtaining the update opcode of the first target instruction" in S200 specifically includes: Obtain the initial opcode of the first target instruction; The initial opcode is processed according to a preset method to obtain the updated opcode.

[0045] The preset methods include adding or replacing opcode codes. After a conditional jump, the original comparison result is lost and cannot be reused in subsequent code. Therefore, after the detection passes, the detection result is saved by adding or replacing the opcode for the first target instruction.

[0046] Specifically, the newly added opcode encoding can include 1 bit enable, where 1 represents that optimization can be intervened; it can also encode all instructions, such as 4 bit encoding. For the 16 types of JCC instructions, this encoding represents the encoding of the second JCC instruction, which is used to determine which flag registers need to be read to obtain the jump result of the second JCC instruction during optimization.

[0047] The opcode replacement can include opcode, 77, and D8. opcode indicates the instruction meaning, 77 represents the ja instruction, and D8 represents enabling the optimized jcc instructions of this application. The first jcc instruction is ja, and the second jcc instruction is jc. Whether to replace all 256(16) opcodes depends on the remaining opcode encoding space for different instruction sets. 16) Both the jcc + jcc combinations are encoded. If the remaining space is limited, only the common combinations can be encoded.

[0048] After obtaining the update opcode, it further includes: Determine whether there is a target cache in the current system microarchitecture for storing the decoded instruction information; If so, save the update opcode based on the first policy. Specifically, save the update opcode to the opcode cache corresponding to the first target instruction.

[0049] If not, save the update opcode based on the second policy. Specifically, write the update opcode to the cache line corresponding to the first target instruction through the self - modify code technique.

[0050] In this embodiment, both of the above two methods can ensure the effect of one - time detection and multiple optimizations.

[0051] For S300, when the first target instruction is triggered again, in response to the prediction result of the first target instruction being a jump and the prediction - error signal, obtain the target register in the execution module based on the update opcode, which is the register corresponding to the second target instruction. Because the second target instruction and the first target instruction identified in S100 are two instructions with an associated relationship, and the results of the flag - bit registers they depend on are both generated by the same cmp instruction. That is to say, when correcting the jump direction of the first target instruction for the first time, based on the existing results of the flag - bit registers, the CPU can actually determine the jump direction of the second target instruction.

[0052] Taking jl and jnle as examples, jl depends on: SF ≠ OF; jnle depends on: ZF = 0 and SF = OF. Both depend on the flag bits set by the same cmp instruction. For comparing a and b (assuming both are integers): jl is true → a < b, jnle is true → a > b. If jl is not true → a ≥ b, if jl is true → a < b (at this time jnle must not be true). In this embodiment, the two conditional jumps depend on the same flag - bit source. Through this dependency pair, the inference logic of the second jump can be recorded. That is, in this embodiment, the two conditional jumps depend on the same flag - bit source (the same cmp), and the flag - bit status generated by the same cmp is determined. Directly use the execution result of the first jump to obtain the second jump direction, effectively reducing the chained prediction errors and reducing the pipeline flush frequency.

[0053] Refer to Figure 3 , for the method of S400 "obtain the branch - jump target result based on the target register and perform the re - fetch of the second target instruction after the pipeline flush", it specifically includes: S410 obtains the branch jump target result based on the target register, passes the branch jump target result to the prediction module, and sets the corresponding enable signal.

[0054] Specifically, for example, 0 means not taken, and 1 means taken.

[0055] S420, according to the enable signal, controls the prediction module to re-fetch the second target instruction based on the branch jump target result after pipeline flushing, that is, to abandon the prediction result of the prediction module itself.

[0056] Reference Figure 4 Taking jl+jnle as an example, in existing technologies, when fetching the jl instruction after cmp, a jump to jl is predicted, so codeA is fetched; if the jl direction prediction is incorrect, all codeA instructions are flushed, and the instruction is fetched and decoded again from jnle; if the jump direction of jnle is predicted to be a jump, codeB is fetched; if the jnle direction prediction is incorrect, all codeB instructions are flushed, and the instruction is fetched and decoded again from codeC. In the worst case, the branch prediction module will continuously guess the directions of jl and jnle incorrectly. Branch prediction errors will trigger a flushing operation in the CPU pipeline. For example, incorrect path instructions that have been prefetched, decoded, or partially executed are discarded. The CPU needs to fetch, decode, and fill the pipeline again from the correct jump target. This process introduces additional clock cycle overhead and interrupts the continuous execution of the instruction stream. When such unpredictable branches occur frequently, frequent pipeline flushing will severely reduce the CPU's instruction throughput and become the main bottleneck of system performance.

[0057] Reference Figure 5 The method disclosed in this application, namely the intervention optimization method, means that when the jl_opt instruction appears after instruction fetching cmp, and the predicted jump is incorrect, the jnle instruction in the same target instruction pair will not again incorrectly predict a jump to codeB. Instead, when the jl_opt instruction reaches the execution stage, it knows that the correct branch direction of the subsequent jnle instruction is codeC, and passes information from the execution stage to the prediction stage, allowing the prediction stage to accurately predict the branch direction as codeC. When re-fetching jnle, the result predicted by the branch prediction module is not used; instead, a newly added signal result is used for instruction fetching, ensuring that the prediction result is always correct, effectively avoiding a single branch prediction error and the overhead of flushing the pipeline. Timeline comparison: Traditional: cmp → jl execution → flushing → jnle execution → possible flushing again; Optimized: cmp → jl execution → simultaneously determine jnle direction → one flush completes two corrections.

[0058] Furthermore, after the second target instruction is re-fetched, the destination address of the re-fetched second target instruction is determined again based on the method disclosed in this application. This process is continuously analyzed and optimized during program execution, thereby reducing the overhead of branch prediction errors.

[0059] This method reduces recovery overhead when branch prediction errors occur by dynamically optimizing related conditional jump instruction pairs. Specifically, it identifies dependent jump instruction pairs by detecting physical register consistency (e.g., using the same condition code register). Such dependencies often appear in nested loops or continuous conditional judgments, which are high-risk scenarios for prediction errors. When the first target instruction is predicted not to jump, the processor can continue executing the second target instruction, recording this execution mode to provide context for subsequent dynamic optimization, helping to reduce real-time detection overhead and achieve targeted optimization. The updated opcode of the first target instruction is obtained, and when a prediction error occurs, the target register is quickly retrieved using this updated opcode. That is, when the first target instruction is triggered again and predicted as a jump but an error occurs, the target register is retrieved based on the updated opcode. The target register obtains the branch jump target result. After pipeline flushing, the second target instruction is re-fetched. Based on this result, the destination address of the second target instruction is determined. That is, using the target register provided by the first target instruction, the correct fetch address of the second target instruction is directly calculated, avoiding the prediction error that occurs after fetching and executing based on the prediction result corresponding to the second target instruction. This reduces one pipeline flush. Traditional branch prediction errors require pipeline flushing and re-fetching, which usually takes more than ten cycles. This solution shortens the re-fetching latency through pre-computation and fast path recovery, which is particularly effective for continuous conditional jump scenarios. By identifying relevant jump instruction pairs and dynamically optimizing them, pipeline idle time caused by prediction errors is reduced, improving the utilization rate of hardware resources such as execution units and instruction fetch units. This solution adjusts the instruction opcode according to the actual execution behavior of the program, achieving hardware-level just-in-time compilation. It is especially suitable for stable loop and conditional branch code, and long-term operation can accumulate optimization benefits.

[0060] The method disclosed in this application is optimized only for specific instruction patterns (conditional jump pairs with consistent physical registers), requiring no global modification to the branch prediction mechanism and incurring limited hardware additions (such as adding opcode update logic or fast path circuitry), thus offering high cost-effectiveness. Traditional predictors are prone to failure in complex control flows such as nested branches and circular dependencies. This solution enhances the processor's ability to handle complex logic and improves overall performance through instruction pair co-optimization. This method effectively reduces branch prediction error overhead and improves processor performance under branch-intensive workloads through a collaborative design of detection, optimization, and fast recovery.

[0061] A computer device according to embodiments of the present disclosure includes a memory and a processor. The memory is used to store non-transitory computer-readable instructions. Specifically, the memory may include one or more computer program products, which may include various forms of computer-readable storage media, such as volatile memory and / or non-volatile memory. The volatile memory may, for example, include random access memory (RAM) and / or cache memory. The non-volatile memory may, for example, include read-only memory (ROM), hard disk, flash memory, etc.

[0062] The processor may be a central processing unit (CPU) or other form of processing unit with data processing capabilities and / or instruction execution capabilities, and may control other components in the computer device to perform desired functions. In one embodiment of this disclosure, the processor is used to execute computer-readable instructions stored in the memory, causing the computer device to perform all or part of the steps of the methods for reducing branch prediction error overhead described in the foregoing embodiments of this disclosure.

[0063] Those skilled in the art will understand that, in order to solve the technical problem of how to achieve a good user experience, this embodiment may also include well-known structures such as communication buses and interfaces, and these well-known structures should also be included within the protection scope of this disclosure.

[0064] like Figure 6 This is a schematic diagram of a computer device provided for an embodiment of the present disclosure. It illustrates a structural schematic diagram suitable for implementing the computer device in the embodiments of the present disclosure. Figure 6 The computer device shown is merely an example and should not be construed as limiting the functionality and scope of the embodiments disclosed herein.

[0065] like Figure 6 As shown, a computer device may include a processor (such as a central processing unit, graphics processing unit, etc.), which can perform various appropriate actions and processes based on programs stored in read-only memory (ROM) or programs loaded from storage devices into random access memory (RAM). The RAM also stores various programs and data required for the operation of the computer device. The processor, ROM, and RAM are interconnected via a bus. Input / output (I / O) interfaces are also connected to the bus.

[0066] Typically, the following devices can be connected to the I / O interface: input devices, such as sensors or visual information acquisition devices; output devices, such as displays; storage devices, such as magnetic tapes or hard drives; and communication devices. Communication devices allow the computer device to communicate wirelessly or wiredly with other devices (such as edge computing devices) to exchange data. Although Figure 6A computer apparatus with various devices is shown, but it should be understood that it is not required to implement or have all of the devices shown. More or fewer devices may be implemented or included alternatively.

[0067] In particular, according to embodiments of this disclosure, the processes described above with reference to the flowcharts can be implemented as computer software programs. For example, embodiments of this disclosure include a computer program product comprising a computer program carried on a non-transitory computer-readable medium, the computer program containing program code for performing the methods shown in the flowcharts. In such embodiments, the computer program can be downloaded and installed from a network via a communication device, or installed from a storage device, or installed from ROM. When the computer program is executed by a processor, all or part of the steps of the method for reducing branch prediction error overhead according to embodiments of this disclosure are performed.

[0068] For a detailed description of this embodiment, please refer to the corresponding descriptions in the foregoing embodiments, which will not be repeated here.

[0069] A computer-readable storage medium according to embodiments of the present disclosure stores non-transitory computer-readable instructions. When the non-transitory computer-readable instructions are executed by a processor, all or part of the steps of the methods for reducing branch prediction error overhead described in the foregoing embodiments of the present disclosure are performed.

[0070] The aforementioned computer-readable storage media include, but are not limited to: optical storage media (e.g., CD-ROM and DVD), magneto-optical storage media (e.g., MO), magnetic storage media (e.g., magnetic tape or portable hard drive), media with built-in rewritable non-volatile memory (e.g., memory card), and media with built-in ROM (e.g., ROM cartridge).

[0071] For a detailed description of this embodiment, please refer to the corresponding descriptions in the foregoing embodiments, which will not be repeated here.

[0072] The basic principles of this disclosure have been described above with reference to specific embodiments. However, it should be noted that the advantages, benefits, and effects mentioned in this disclosure are merely examples and not limitations, and should not be considered as essential features of each embodiment of this disclosure. Furthermore, the specific details disclosed above are for illustrative and facilitative purposes only, and are not limitations. These details do not limit the scope of this disclosure to the necessity of employing the aforementioned specific details for implementation.

[0073] In this disclosure, relational terms such as "first" and "second" are used merely to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. The block diagrams of devices, apparatuses, devices, and systems involved in this disclosure are merely illustrative examples and are not intended to require or imply that they must be connected, arranged, or configured in the manner shown in the block diagrams. As those skilled in the art will recognize, these devices, apparatuses, devices, and systems can be connected, arranged, and configured in any manner. Words such as "comprising," "including," "having," etc., are open-ended terms meaning "including but not limited to," and are used interchangeably with them. The terms "or" and "and" as used herein refer to the terms "and / or," and are used interchangeably with them unless the context clearly indicates otherwise. The term "such as" as used herein refers to the phrase "such as but not limited to," and is used interchangeably with it.

[0074] Additionally, as used herein, the "or" used in a list of items beginning with "at least one" indicates a separate list, such that a list of, for example, "at least one of A, B, or C" means A or B or C, or AB or AC or BC, or ABC (i.e., A and B and C). Furthermore, the word "exemplary" does not imply that the described example is preferred or better than other examples.

[0075] It should also be noted that in the systems and methods of this disclosure, the components or steps can be decomposed and / or recombined. These decompositions and / or recombinations should be considered as equivalent solutions to this disclosure.

[0076] Various changes, substitutions, and modifications can be made to the technology described herein without departing from the teachings defined by the appended claims. Furthermore, the scope of the claims of this disclosure is not limited to the specific aspects of the processes, machines, manufactures, events, means, methods, and actions described above. Currently existing or later-developed processes, machines, manufactures, events, means, methods, or actions that perform substantially the same function or achieve substantially the same result as the corresponding aspects described herein can be utilized. Therefore, the appended claims include such processes, machines, manufactures, events, means, methods, or actions within their scope.

[0077] The above description of the disclosed aspects is provided to enable any person skilled in the art to make or use this disclosure. Various modifications to these aspects will be readily apparent to those skilled in the art, and the general principles defined herein may be applied to other aspects without departing from the scope of this disclosure. Therefore, this disclosure is not intended to be limited to the aspects shown herein, but rather to be carried out within the widest scope consistent with the principles and novel features disclosed herein.

[0078] The above description has been given for purposes of illustration and description. Furthermore, this description is not intended to limit the embodiments of this disclosure to the forms disclosed herein. Although numerous exemplary aspects and embodiments have been discussed above, those skilled in the art will recognize certain variations, modifications, alterations, additions, and sub-combinations thereof.

Claims

1. A method for reducing branch prediction error overhead, characterized in that, include: In response to the occurrence of a conditional jump signal for both instructions, the first target instruction and the second target instruction, which are consistent with the physical registers, are obtained. The first target instruction is executed before the second target instruction, and the prediction result of the first target instruction is no jump; Obtain the update opcode of the first target instruction; When the first target instruction is triggered again, in response to the signal that the prediction result of the first target instruction is a jump and the prediction is wrong, the target register is obtained based on the update opcode; The branch jump target result is obtained based on the target register, and the second target instruction is re-fetched based on the branch jump target result after pipeline flushing.

2. The method for reducing branch prediction error overhead according to claim 1, characterized in that, The response to the occurrence signal of conditional jump for both instructions, acquiring the first target instruction and the second target instruction with consistent physical registers, includes: Identify the opcode of the instruction; The instruction type of the corresponding instruction is determined based on the opcode; In response to the occurrence signal of the conditional jump for both instructions, the first physical register and the second physical register corresponding to the two instructions are obtained respectively; If the second physical register is the same as the first physical register, and the prediction result of the first instruction of the two instructions is no jump and the prediction is correct, the two instructions are recorded as the first target instruction and the second target instruction, respectively. There is no jump instruction between the first target instruction and the second target instruction in the program sequence.

3. The method for reducing branch prediction error overhead according to claim 1, characterized in that, Obtaining the update opcode of the first target instruction includes: Obtain the initial opcode of the first target instruction; The initial opcode is processed according to a preset method to obtain an update opcode; The preset method includes adding or replacing operation codes.

4. The method for reducing branch prediction error overhead according to claim 3, characterized in that, After obtaining the update opcode, the process also includes: Determine whether a target cache exists in the current system microarchitecture to store decoded instruction information; If so, save the update opcode based on the first strategy; If not, save the update opcode based on the second strategy.

5. The method for reducing branch prediction error overhead according to claim 4, characterized in that, The step of saving the update opcode based on the first strategy includes: The update opcode is saved to the opcode cache corresponding to the first target instruction.

6. The method for reducing branch prediction error overhead according to claim 4, characterized in that, The process of saving the update opcode based on the second strategy includes: The update opcode is written to the cache line corresponding to the first target instruction using code self-modification technology.

7. The method for reducing branch prediction error overhead according to claim 1, characterized in that, The step of obtaining the branch jump target result based on the target register and re-fetching the second target instruction based on the branch jump target result after pipeline flushing includes: The branch jump target result is obtained based on the target register, and the branch jump target result is transmitted to the prediction module, and the corresponding enable signal is set; The enable signal controls the prediction module to re-fetch the second target instruction based on the branch jump target result after pipeline flushing.

8. A computer device, characterized in that, The computer device includes: At least one processor; and, A memory communicatively connected to the at least one processor; wherein, The memory stores instructions that can be executed by the at least one processor to enable the at least one processor to perform the method for reducing branch prediction error overhead as described in any one of claims 1-7.

9. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores computer instructions for causing the computer to perform the method for reducing branch prediction error overhead as described in any one of claims 1-7.

10. A computer program product comprising computer instructions, characterized in that, When executed by a processor, the computer instructions implement the steps of the method according to any one of claims 1-7.

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