Semiconductor device, wafer and wafer processing method

Abstract

The invention relates to the technical field of semiconductor devices, and discloses a semiconductor device, a wafer and a wafer processing method. The semiconductor device includes: a substrate; an epitaxial layer; an ohmic contact layer; the device electrode layer is located on the side, away from the substrate, of the ohmic contact layer; the at least one interconnection layer is electrically connected with the device electrode layer in the device area and located on the side, away from the substrate, of the device electrode layer, and the at least one interconnection layer comprises a top interconnection layer farthest away from the substrate; the dielectric layer is located between the top interconnection layer and the device electrode layer; the heat absorption layer is located on the side, away from the substrate, of the dielectric layer, the heat absorption layer is at least located in the cutting edge area, and the absorptivity of the heat absorption layer to light of the preset wave band is larger than that of the dielectric layer to the light of the preset wave band. According to the semiconductor device provided by the embodiment of the invention, the problem of non-uniform heat distribution in the thickness direction during laser cutting in the process of manufacturing the semiconductor device can be relieved, so that the problem of cutting thermal damage to the edge of the semiconductor device is relieved.

Description

Technical Field

[0001] This application relates to the field of semiconductor device technology, and in particular to a semiconductor device, a wafer, and a wafer processing method. Background Technology

[0002] In the manufacturing process of semiconductor devices, multiple device regions of semiconductor devices are usually formed on the substrate of a wafer first. There are dicing regions between adjacent device regions. Then, the dicing regions of the wafer are cut by laser, so that the whole wafer is transformed into multiple separate semiconductor devices.

[0003] In related technologies, during the laser-cutting process of wafers, there is often a large temperature difference between the wafer surface away from the substrate and the wafer bottom layer near the substrate. This means that there is a severe uneven heat distribution in the wafer thickness direction at the cutting point, which can easily cause cutting thermal damage on the wafer and make the edges of the resulting semiconductor devices susceptible to cutting thermal damage. Summary of the Invention

[0004] This application provides a semiconductor device, a wafer, and a wafer processing method that can alleviate the problem of uneven heat distribution in the thickness direction during laser cutting in the process of manufacturing semiconductor devices, thereby mitigating the problem of cutting thermal damage at the edges of semiconductor devices.

[0005] In a first aspect, embodiments of this application provide a semiconductor device having a device region and a dicing edge region located on the periphery of the device region and extending along at least a portion of the edge of the semiconductor device. The semiconductor device includes: a substrate; an epitaxial layer located on the substrate, the epitaxial layer including a functional layer for forming transistors; an ohmic contact layer disposed in the device region and located on the side of the epitaxial layer away from the substrate; a device electrode layer connected to the ohmic contact layer in the device region and located on the side of the ohmic contact layer away from the substrate; at least one interconnect layer electrically connected to the device electrode layer in the device region and located on the side of the device electrode layer away from the substrate, the at least one interconnect layer including a top interconnect layer furthest from the substrate; a dielectric layer located between the top interconnect layer and the device electrode layer; and a heat-absorbing layer located on the side of the dielectric layer away from the substrate, the heat-absorbing layer being at least located in the dicing edge region, the heat-absorbing layer having an absorbance of light of a predetermined wavelength band greater than the absorbance of the dielectric layer for the predetermined wavelength band.

[0006] According to some embodiments of the first aspect of this application, the semiconductor device further includes: a passivation layer located on the side of the top interconnect layer away from the substrate; and a first opening located in the dicing edge region, the first opening penetrating the passivation layer and exposing the heat-absorbing layer.

[0007] According to some embodiments of the first aspect of this application, the semiconductor device includes a sealing ring extending around the device region, the first opening being located outside the sealing ring.

[0008] According to some embodiments of the first aspect of this application, the top interconnect layer includes a pad portion, and the semiconductor device further includes: a second opening located in the device region, the second opening penetrating the passivation layer, the second opening exposing the pad portion.

[0009] According to some of the foregoing embodiments of the first aspect of this application, the heat-absorbing layer is further disposed in the device region; the semiconductor device further includes: a first sacrificial layer, which is located in the device region and between the top interconnect layer and the heat-absorbing layer.

[0010] According to some embodiments of the first aspect of this application, the material of the first sacrificial layer is configured to serve as an etching stop layer when the passivation layer is etched; the material of the heat-absorbing layer is configured to serve as an etching stop layer when the first sacrificial layer is etched.

[0011] According to some embodiments of the first aspect of this application, the semiconductor device further includes: a second sacrificial layer, the second sacrificial layer being located in the device region and between the top interconnect layer and the first sacrificial layer.

[0012] According to some embodiments of the first aspect of this application, the dielectric layer is an oxide insulating layer; the heat-absorbing layer is a silicon nitride layer; the first sacrificial layer is an aluminum nitride layer; and the second sacrificial layer is an oxide insulating layer.

[0013] According to some of the foregoing embodiments of the first aspect of this application, the preset wavelength band is 315nm to 400nm.

[0014] According to some embodiments of the first aspect of this application, the at least one interconnect layer further includes a non-top interconnect layer located between the top interconnect layer and the device electrode layer, and the dielectric layer includes at least two dielectric sublayers, each of which is located between the non-top interconnect layer and the device electrode layer, or between adjacent interconnect layers.

[0015] Secondly, embodiments of this application provide a wafer including multiple device regions and dicing regions located between adjacent device regions. The wafer includes: a substrate; an epitaxial layer located on the substrate, the epitaxial layer including a functional layer for forming transistors; an ohmic contact layer disposed in the device regions and located on the side of the epitaxial layer away from the substrate; a device electrode layer connected to the ohmic contact layer in the device regions and located on the side of the ohmic contact layer away from the substrate; at least one interconnect layer electrically connected to the device electrode layer in the device regions and located on the side of the device electrode layer away from the substrate, the at least one interconnect layer including a top interconnect layer furthest from the substrate; a dielectric layer located between the top interconnect layer and the device electrode layer; and a heat-absorbing layer located on the side of the dielectric layer away from the substrate, the heat-absorbing layer being at least located in the dicing region, the heat-absorbing layer having an absorption rate for light of a preset wavelength band greater than the absorption rate of the dielectric layer for light of the preset wavelength band, wherein the wavelength of the laser used to dicing the dicing region is within the preset wavelength band.

[0016] According to some embodiments of the second aspect of this application, the wafer further includes: a passivation layer located on the side of the top interconnect layer away from the substrate; and a first opening located in the dicing region, the first opening penetrating the passivation layer, the first opening exposing the heat-absorbing layer.

[0017] According to some of the foregoing embodiments of the second aspect of this application, the heat-absorbing layer is further disposed in the device region; the wafer further includes: a first sacrificial layer, the first sacrificial layer being located in the device region and between the top interconnect layer and the heat-absorbing layer.

[0018] According to some embodiments of the second aspect of this application, the material of the first sacrificial layer is configured to serve as an etching stop layer when the passivation layer is etched; the material of the heat-absorbing layer is configured to serve as an etching stop layer when the first sacrificial layer is etched.

[0019] According to some embodiments of the second aspect of this application, the wafer further includes: a second sacrificial layer, the second sacrificial layer being located in the device region and between the top interconnect layer and the first sacrificial layer.

[0020] Thirdly, embodiments of this application provide a wafer fabrication method, comprising: providing a substrate having a plurality of device regions and dicing regions located between adjacent device regions; forming an epitaxial layer on the substrate, the epitaxial layer including a functional layer for forming transistors; forming an ohmic contact layer on a side of the epitaxial layer away from the substrate, the ohmic contact layer being located in the device regions; forming a device electrode layer on the side of the ohmic contact layer away from the substrate, the device electrode layer being located in the device regions and connected to the ohmic contact layer; forming a dielectric layer on the side of the device electrode layer away from the substrate; and forming a heat-absorbing layer on the side of the dielectric layer away from the substrate. The heat-absorbing layer is located at least in the dicing region. The heat-absorbing layer has a higher absorption rate for light of a preset wavelength band than the dielectric layer has for light of the preset wavelength band. The wavelength of the laser used to dicing the dicing region is within the preset wavelength band. A top interconnect layer is formed on the side of the heat-absorbing layer away from the substrate, and the top interconnect layer is located in the device region. A passivation layer is formed on the side of the top interconnect layer away from the substrate, and the passivation layer covers the device region and the dicing region. A first opening is formed on the surface of the passivation layer, which penetrates the passivation layer and exposes the heat-absorbing layer.

[0021] According to some of the embodiments described in the third aspect of this application, the wafer processing method further includes: cutting the dicing area with a laser to obtain a plurality of semiconductor devices.

[0022] According to some embodiments of the third aspect of this application, before the step of forming a top interconnect layer on the side of the heat-absorbing layer away from the substrate, the wafer processing method further includes: forming a first sacrificial layer on the side of the heat-absorbing layer away from the substrate, the first sacrificial layer being located in the device region and the dicing region; the step of patterning from the surface of the passivation layer to form a first opening in the dicing region includes: using the first sacrificial layer as an etch stop layer, performing a first etching from the surface of the passivation layer to obtain a first sub-opening in the dicing region, the first sub-opening penetrating the passivation layer; using the heat-absorbing layer as an etch stop layer, performing a second etching on the first sub-opening to obtain a second sub-opening penetrating the first sacrificial layer, the second sub-opening communicating with the first sub-opening to form the first opening.

[0023] According to some embodiments of the third aspect of this application, before the step of forming a top interconnect layer on the side of the heat absorption layer away from the substrate, the wafer processing method further includes: forming a second sacrificial layer on the side of the first sacrificial layer away from the substrate, the second sacrificial layer being located in the device region and the dicing region; in the step of performing a first etching from the surface of the passivation layer with the first sacrificial layer as the etching stop layer, the first sub-opening also penetrates the second sacrificial layer.

[0024] According to embodiments of the semiconductor device of this application, at least one interconnect layer includes a top interconnect layer furthest from the substrate, and a dielectric layer is located between the top interconnect layer and the device electrode layer. The semiconductor device of this application includes a heat-absorbing layer located on the side of the dielectric layer furthest from the substrate, and the heat-absorbing layer is located at least in the dicing edge region. The heat-absorbing layer has a higher absorption rate for light of a predetermined wavelength than the dielectric layer. During the manufacturing process of the semiconductor device, the wafer is laser-cut into multiple separate semiconductor devices by cutting the wafer's dicing area. After cutting, the dicing area becomes an edge dicing area located at the edge of each semiconductor device. During laser cutting, the dicing point is in the wafer thickness direction. The wafer's bottom layer near the substrate has an epitaxial layer, which has a higher absorption rate for laser light, resulting in a higher temperature at the wafer's bottom layer near the substrate. In this application embodiment, the edge dicing area has a heat-absorbing layer located on the side of the dielectric layer furthest from the substrate. Therefore, when cutting the wafer, the wafer surface furthest from the substrate has a heat-absorbing layer, which also has a higher absorption rate for laser light, resulting in a higher temperature at the wafer surface furthest from the substrate. Therefore, the heat distribution at the cutting point is more uniform in the thickness direction of the wafer or semiconductor device, which alleviates the problem of cutting thermal damage on the wafer, thereby alleviating the problem of cutting thermal damage at the edge of the obtained semiconductor device. Attached Figure Description

[0025] The accompanying drawings, which are incorporated in and form a part of this specification, illustrate embodiments consistent with this disclosure and, together with the description, serve to explain the principles of this disclosure.

[0026] Figure 1 This is a cross-sectional schematic diagram of one embodiment of the semiconductor device according to this application; Figure 2 This is a cross-sectional schematic diagram of another embodiment of the semiconductor device according to this application; Figure 3 This is a cross-sectional schematic diagram of one embodiment of the wafer according to this application; Figure 4 This is a partially enlarged cross-sectional schematic diagram of one embodiment of the wafer according to this application; Figures 5 to 12 This is a partially enlarged cross-sectional schematic diagram of each stage of an embodiment of the wafer fabrication method according to this application; Figure 13 This is a cross-sectional schematic diagram of another embodiment of the wafer according to this application; Figure 14 This is a partially enlarged cross-sectional schematic diagram of another embodiment of the wafer according to this application; Figures 15 to 21 This is a partially enlarged cross-sectional schematic diagram of each stage of another embodiment of the wafer fabrication method according to this application. Detailed Implementation

[0027] The technical solutions in the embodiments (or "implementations") of this application will be clearly and completely described herein with reference to the accompanying drawings. When the following description relates to the drawings, unless otherwise indicated, the same numbers in different drawings represent the same or similar elements.

[0028] If the embodiments of this application contain terms relating to directional indications or positional relationships (such as up, down, left, right, front, back, inside, outside, top, bottom, center, vertical, horizontal, longitudinal, transverse, length, width, counterclockwise, clockwise, axial, radial, circumferential, etc.), such terms are only used to explain the relative positional relationships and movement of the components in a specific posture (as shown in the attached figures); if the specific posture changes, the directional indications or positional relationships will also change accordingly. Furthermore, the terms "first" and "second" used in the embodiments of this application are only for descriptive convenience and should not be construed as indicating or implying relative importance.

[0029] In related technologies, a wafer used to manufacture semiconductor devices includes multiple device regions and dicing regions located between adjacent device regions. The wafer includes a substrate, an epitaxial layer, an ohmic contact layer, a device electrode layer, at least one interconnect layer, and a dielectric layer. The epitaxial layer is located on the substrate and includes a functional layer for forming transistors. The ohmic contact layer is disposed in the device region and is located on the side of the epitaxial layer away from the substrate. The device electrode layer is connected to the ohmic contact layer in the device region and is located on the side of the ohmic contact layer away from the substrate. At least one interconnect layer is electrically connected to the device electrode layer in the device region and is located on the side of the device electrode layer away from the substrate. The at least one interconnect layer includes a top interconnect layer furthest from the substrate. The dielectric layer is located between the top interconnect layer and the device electrode layer. When the wafer is laser-diced, the dielectric layer is exposed on the surface of the dicing region. During laser cutting, in the cutting area, the wafer bottom layer near the substrate has an epitaxial layer, which has a high laser absorption rate, resulting in a higher temperature at this location. The wafer surface away from the substrate has a dielectric layer, which has a lower laser absorption rate than the epitaxial layer, resulting in a lower temperature at this location. This significant temperature difference between the wafer surface away from the substrate and the wafer bottom layer near the substrate leads to severe uneven heat distribution along the wafer thickness at the cutting point. This can easily cause thermal damage during cutting, making the edges of the resulting semiconductor device susceptible to thermal damage.

[0030] The aforementioned cutting thermal damage is, for example, burst point damage. Burst point damage refers to microcracks, material fractures, or structural damage caused by uneven heat distribution and thermal stress concentration at the laser cutting site.

[0031] This application provides a semiconductor device and a wafer that can alleviate the problem of uneven heat distribution in the thickness direction during laser cutting in the wafer processing process, i.e., semiconductor manufacturing process, thereby alleviating the problem of cutting thermal damage on the wafer and the problem of cutting thermal damage at the edge of the semiconductor device.

[0032] Figure 1 This is a cross-sectional schematic diagram of an embodiment of a semiconductor device according to this application. The semiconductor device 100 has a device region D1 and a diced edge region D5 located on the outer periphery of the device region D1 and extending along at least a portion of the edge of the semiconductor device 100. The semiconductor device 100 includes: a substrate 110, an epitaxial layer 120, an ohmic contact layer 130, a device electrode layer 140, at least one interconnect layer 150, a dielectric layer 160, and a heat-absorbing layer 171.

[0033] The substrate 110 may contain, but is not limited to, semiconductor substrate materials such as silicon (Si), doped Si, silicon carbide (SiC), germanium silicide (SiGe), and gallium arsenide (GaAs). The substrate 110 may contain, but is not limited to, sapphire, silicon-on-insulator (SOI), or other suitable substrate materials.

[0034] Epitaxial layer 120 is located on substrate 110, and epitaxial layer 120 includes a functional layer for forming transistors.

[0035] In one example, device region D1 of semiconductor device 100 is used to form a high electron mobility transistor (HEMT). In this case, epitaxial layer 120 includes sublayers such as a channel layer and a barrier layer. The channel layer and barrier layer can each comprise nitrides or III-V compounds. For example, the channel layer and barrier layer can include, but are not limited to, gallium nitride (GaN), aluminum nitride (AlN), aluminum gallium nitride (AlGaN), and indium aluminum gallium nitride (InAlGaN). The band gap (i.e., band width) of the barrier layer is larger than that of the channel layer, which makes the electron affinity different from each other, forming a heterojunction between the GaN layers. In this embodiment, the example is a GaN layer as the channel layer and an AlGaN layer as the barrier layer. In this case, the transistor is, for example, a GaN-based HEMT. A triangular well potential is generated at the interface between the barrier layer and the channel layer, causing electrons to accumulate in the triangular well, thereby generating a two-dimensional electron gas (2DEG) region near the heterojunction. The epitaxial layer 120 may also include other functional layers for forming transistors, such as buffer layers, barrier modulation layers, etc.

[0036] An ohmic contact layer 130 is disposed in device region D1 and located on the side of epitaxial layer 120 away from substrate 110. The ohmic contact layer 130 is used to reduce the ohmic contact resistance of the ohmic contact region. In one example, the ohmic contact layer 130 is formed in the source and drain regions of the transistor.

[0037] Device electrode layer 140 is connected to ohmic contact layer 130 in device region D1 and is located on the side of ohmic contact layer 130 away from substrate 110. In one example, device electrode layer 140 includes a source electrode SE and a drain electrode DE. The source electrode SE is located in the source region and is connected to ohmic contact layer 130 located in the source region. The drain electrode DE is located in the drain region and is connected to ohmic contact layer 130 located in the drain region. In some embodiments, device electrode layer 140 may further include a gate electrode GE, which is located in the gate region of the transistor.

[0038] In some embodiments, the epitaxial layer 120 further includes a doped nitride-based semiconductor layer, and the semiconductor device 100 further includes a gate metal GM. The doped nitride-based semiconductor layer is located in the gate region and on the side of the barrier layer away from the substrate 110, and the gate metal GM is located in the gate region and on the side of the doped nitride-based semiconductor layer away from the substrate 110.

[0039] The material of the doped nitride-based semiconductor layer may include, but is not limited to, p-doped III-V group nitride semiconductor materials, such as p-type GaN, p-type AlGaN, p-type InN, p-type AlInN, p-type InGaN, p-type AlInGaN, or combinations thereof. In one example, a barrier layer is located on the side of the channel layer away from the substrate 110, the channel layer being, for example, a GaN layer, the barrier layer being, for example, an AlGaN layer, and the doped nitride-based semiconductor layer being, for example, a p-type GaN layer. The doped nitride-based semiconductor layer forms a depletion region in the 2DEG region of its coverage area, blocking the 2DEG and thereby placing the semiconductor device 100 in a cutoff state.

[0040] At least one interconnect layer 150 is electrically connected to the device electrode layer 140 in the device region D1 and is located on the side of the device electrode layer 140 away from the substrate 110. The at least one interconnect layer 150 includes a top interconnect layer 150a that is furthest from the substrate 110. The interconnect layers 150 are used to electrically connect at least one electrode of the transistor to other circuit structures. The number of interconnect layers 150 can be one, two, three, or other numbers.

[0041] The dielectric layer 160 is located between the top interconnect layer 150a and the device electrode layer 140. The dielectric layer 160 exists between the interconnect layer 150 closest to the device electrode layer 140 and that device electrode layer 140. When there are two or more interconnect layers 150, the dielectric layer 160 also exists between two adjacent interconnect layers 150.

[0042] The interconnect layer 150 and the device electrode layer 140 can be connected through vias. In some embodiments, there are two or more interconnect layers 150, and the two interconnect layers 150 can be connected through vias.

[0043] The heat-absorbing layer 171 is located on the side of the dielectric layer 160 away from the substrate 110. The heat-absorbing layer 171 is located at least in the dicing edge region D5, and the light absorption rate of the heat-absorbing layer 171 for light of a preset wavelength is greater than that of the dielectric layer 160 for light of a preset wavelength. In this embodiment, during the manufacturing process of the semiconductor device 100, the dicing edge region D5 is obtained by laser cutting of the dicing area on the wafer. In some embodiments, the wavelength of the laser used to cut the dicing edge region D5 is within the aforementioned preset wavelength range.

[0044] According to an embodiment of the present application, the semiconductor device 100 includes at least one interconnect layer 150, which includes a top interconnect layer 150a furthest from the substrate, and a dielectric layer 160 located between the top interconnect layer 150a and the device electrode layer 140. The semiconductor device 100 also includes a heat-absorbing layer 171 located on the side of the dielectric layer 160 furthest from the substrate 110, and the heat-absorbing layer 171 is located at least in the dicing edge region D5. The heat-absorbing layer 171 has a higher absorption rate for a preset wavelength of light than the dielectric layer 160. During the manufacturing process of the semiconductor device 100, a laser cuts the wafer's dicing area, transforming the entire wafer into multiple separate semiconductor devices 100. After dicing, the dicing area becomes the edge dicing area D5 located at the edge of each semiconductor device 100. During laser cutting, the wafer bottom layer near the substrate 110 has an epitaxial layer 120 along the wafer thickness direction. This epitaxial layer 120 has a high laser absorption rate, resulting in a higher temperature near the substrate 110. In this embodiment, the edge cutting region D5 has a heat-absorbing layer 171 located on the side of the dielectric layer 160 away from the substrate 110. Therefore, during wafer cutting, the wafer surface away from the substrate 110 has a heat-absorbing layer 171, which also has a high laser absorption rate, resulting in a higher temperature on the wafer surface away from the substrate 110. Thus, the heat distribution along the wafer or semiconductor device 100 thickness direction at the cutting point is more uniform, alleviating the cutting thermal damage problem on the wafer and thereby mitigating the cutting thermal damage problem at the edge of the resulting semiconductor device 100.

[0045] In some embodiments, the preset wavelength range is 315 nm to 400 nm, meaning the absorber layer 171 has a higher absorbance for light with wavelengths of 315 nm to 400 nm than the dielectric layer 160. In one example, the wavelength of the laser used to cut the cutting edge region D5 is 355 nm, which falls within the aforementioned preset wavelength range. In some embodiments, the preset wavelength range is 100 nm to 400 nm.

[0046] It should be noted that the limitation that "the absorption rate of the heat-absorbing layer 171 for light of the preset wavelength band is greater than the absorption rate of the dielectric layer 160 for light of the preset wavelength band" is only a limitation on the comparison of the absorption rates of the heat-absorbing layer 171 and the dielectric layer 160 within the preset wavelength band. It does not limit the absorption rate of light outside the preset wavelength band. Therefore, the absorption rate of the heat-absorbing layer 171 for light outside the preset wavelength band can still be greater than the absorption rate of the dielectric layer 160 for light of the same wavelength band.

[0047] In some embodiments, the semiconductor device 100 further includes an interlayer insulating layer 180 located on the side of the ohmic contact layer 130 away from the substrate 110 and between the device electrode layer 140 and the ohmic contact layer 130. The device electrode layer 140 can be connected to the ohmic contact layer 130 through a via penetrating the interlayer insulating layer 180. In some embodiments, the material of the interlayer insulating layer 180 is the same as the material of the dielectric layer 160.

[0048] In some embodiments, the semiconductor device 100 further includes a passivation layer 190 located on the side of the top interconnect layer 150a away from the substrate 110. In some embodiments, the semiconductor device 100 further includes a first opening K1 located in the dicing edge region D5, the first opening K1 penetrating the passivation layer 190, and the first opening K1 exposing the heat-absorbing layer 171.

[0049] In some embodiments, the passivation layer 190 may include at least two sub-passivation layers stacked together. In one example, the passivation layer 190 includes a first sub-passivation layer and a second sub-passivation layer stacked sequentially in a direction away from the substrate 110. For example, the first sub-passivation layer is a silicon oxide (SiO) layer and the second sub-passivation layer is a silicon nitride (SiN) layer.

[0050] In some embodiments, the semiconductor device 100 includes a source region, a drain region, and a gate region in the device region D1. The semiconductor device 100 includes a sealing ring SR extending around the device region D1, with the source region, drain region, and gate region located within the region surrounded by the sealing ring SR. A first opening K1 is located outside the sealing ring SR. The sealing ring SR further prevents cutting damage from the cutting edge region D5 and moisture intrusion into the device region D1, ensuring the operational stability of the semiconductor device 100.

[0051] In some embodiments, the top interconnect layer 150a includes pad portions. The semiconductor device 100 also includes a second opening K2 located in the device region D1, penetrating the passivation layer 190, and exposing the pad portions. In the above embodiments, the second opening K2 exposes the pad portions, thereby facilitating electrical connection between the pad portions of the device region D1 and other components. In some embodiments, at least a portion of the second opening K2 and at least a portion of the first opening K1 are formed in the same patterning process, thereby improving wafer fabrication efficiency and facilitating improved transistor manufacturing efficiency.

[0052] In some embodiments, the dielectric layer 160 is an oxide insulating layer; the heat-absorbing layer 171 is a silicon nitride layer. In this embodiment, the dielectric layer 160 is a SiO layer. The heat-absorbing layer 171 is, for example, a SiN layer. The absorption rate of the SiN layer for the cutting laser is greater than that of the SiO layer for the cutting laser.

[0053] In one example, the thickness of the heat-absorbing layer 171 in the cut region D2 is 600 nanometers to 800 nanometers, for example, the thickness of the heat-absorbing layer 171 is 700 nanometers.

[0054] As mentioned above, the number of interconnect layers 150 can be one, two, three, or other numbers. In some embodiments, at least one interconnect layer 150 further includes a non-top-level interconnect layer 150b located between the top interconnect layer 150a and the device electrode layer 140, and the dielectric layer 160 includes at least two dielectric sublayers 161, each dielectric sublayer 161 located between the non-top interconnect layer 150b and the device electrode layer 140, or located between adjacent interconnect layers 150. Exemplarily, in this embodiment, at least one interconnect layer 150 includes a top interconnect layer 150a and a non-top interconnect layer 150b, and the dielectric layer 160 includes two dielectric sublayers 161, one dielectric sublayer 161 located between the non-top interconnect layer 150b and the device electrode layer 140, and the other dielectric sublayer 161 located between the non-top interconnect layer 150b and the top interconnect layer 150a. In some other embodiments, at least one interconnect layer 150 may not include a non-top interconnect layer 150b, or in some other embodiments, at least one interconnect layer 150 may include two or more non-top interconnect layers 150b.

[0055] Figure 2 This is a cross-sectional schematic diagram of another embodiment of the semiconductor device according to this application. The semiconductor device 100 has a device region D1 and a dicing edge region D5 located on the outer periphery of the device region D1 and extending along at least a portion of the edge of the semiconductor device 100. The semiconductor device 100 includes: a substrate 110, an epitaxial layer 120, an ohmic contact layer 130, a device electrode layer 140, at least one interconnect layer 150, a dielectric layer 160, and a heat-absorbing layer 171. Part of the structure of the semiconductor device 100 of the other embodiment is the same as that of the semiconductor device 100 of the aforementioned embodiment. The differences between the two will be described in detail below, while the similarities will not be described in detail.

[0056] At least one interconnect layer 150 includes a top interconnect layer 150a furthest from the substrate 110. A dielectric layer 160 is located between the top interconnect layer 150a and the device electrode layer 140. A heat-absorbing layer 171 is located on the side of the dielectric layer 160 furthest from the substrate 110. The heat-absorbing layer 171 is located at least in the dicing edge region D5, and the absorption rate of the heat-absorbing layer 171 for light of a predetermined wavelength is greater than that of the dielectric layer 160 for light of the predetermined wavelength. In this embodiment, during the manufacturing process of the semiconductor device 100, the dicing edge region D5 is obtained by laser cutting of a dicing area on a wafer. In some embodiments, the wavelength of the laser used to cut the dicing edge region D5 is within the aforementioned predetermined wavelength range.

[0057] The semiconductor device 100 also includes a passivation layer 190 located on the side of the top interconnect layer 150a away from the substrate 110. The semiconductor device 100 also includes a first opening K1 located in the dicing edge region D5, the first opening K1 penetrating the passivation layer 190, and the first opening K1 exposing the heat-absorbing layer 171.

[0058] In this embodiment, the heat-absorbing layer 171 is also disposed in the device region D1. In this embodiment, the semiconductor device 100 further includes a first sacrificial layer 172. The first sacrificial layer 172 is located in the device region D1 and is located between the top interconnect layer 150a and the heat-absorbing layer 171.

[0059] In some embodiments, the material of the first sacrificial layer 172 is configured to serve as an etching stop layer when the passivation layer 190 is etched; the material of the heat-absorbing layer 171 is configured to serve as an etching stop layer when the first sacrificial layer 172 is etched.

[0060] In some embodiments, during the manufacturing of the semiconductor device 100, when forming the first opening K1, a first etching can be performed using the first sacrificial layer 172 as an etch stop layer. This first etching forms the first sub-opening. Since the first sacrificial layer 172 serves as an etch stop layer, the etching depth at each location within the first sub-opening is relatively uniform. Then, using the heat-absorbing layer 171 as an etch stop layer, a second etching is performed on the first sub-opening to obtain a second sub-opening penetrating the first sacrificial layer 172. The second sub-opening connects with the first sub-opening to form the first opening K1. Through the selection of the aforementioned materials, after etching to form the first opening K1, the etching depth at each location within the first opening K1 is relatively uniform.

[0061] In this embodiment, the semiconductor device 100 further includes a second sacrificial layer 173. The second sacrificial layer 173 is located in device region D1 and between the top interconnect layer 150a and the first sacrificial layer 172.

[0062] In some embodiments, the dielectric layer 160 is an oxide insulating layer; the heat-absorbing layer 171 is a silicon nitride layer; the first sacrificial layer 172 is an aluminum nitride layer; and the second sacrificial layer 173 is an oxide insulating layer.

[0063] In one example, the dielectric layer 160 is a SiO layer. The heat-absorbing layer 171 is, for example, a SiN layer. The first sacrificial layer 172 is, for example, an AlN layer. The second sacrificial layer 173 is, for example, a SiO layer.

[0064] In one example, the thickness of the heat-absorbing layer 171 is 600 nm to 800 nm, the thickness of the first sacrificial layer 172 is 1 nm to 4 nm, and the thickness of the second sacrificial layer 173 is 300 nm to 600 nm. For example, the thickness of the heat-absorbing layer 171 is 700 nm, the thickness of the first sacrificial layer 172 is 2 nm, and the thickness of the second sacrificial layer 173 is 400 nm.

[0065] According to an embodiment of the present application, the semiconductor device 100 includes at least one interconnect layer 150, which includes a top interconnect layer 150a furthest from the substrate, and a dielectric layer 160 located between the top interconnect layer 150a and the device electrode layer 140. The semiconductor device 100 also includes a heat-absorbing layer 171 located on the side of the dielectric layer 160 furthest from the substrate 110, and the heat-absorbing layer 171 is located at least in the dicing edge region D5. The heat-absorbing layer 171 has a higher absorption rate for a preset wavelength of light than the dielectric layer 160. During the manufacturing process of the semiconductor device 100, a laser cuts the wafer's dicing area, transforming the entire wafer into multiple separate semiconductor devices 100. After dicing, the dicing area becomes the edge dicing area D5 located at the edge of each semiconductor device 100. During laser cutting, the wafer bottom layer near the substrate 110 has an epitaxial layer 120 along the wafer thickness direction. This epitaxial layer 120 has a high laser absorption rate, resulting in a higher temperature near the substrate 110. In this embodiment, the edge cutting region D5 has a heat-absorbing layer 171 located on the side of the dielectric layer 160 away from the substrate 110. Therefore, during wafer cutting, the wafer surface away from the substrate 110 has a heat-absorbing layer 171, which also has a high laser absorption rate, resulting in a higher temperature on the wafer surface away from the substrate 110. Thus, the heat distribution along the wafer or semiconductor device 100 thickness direction at the cutting point is more uniform, alleviating the cutting thermal damage problem on the wafer and thereby mitigating the cutting thermal damage problem at the edge of the resulting semiconductor device 100.

[0066] Figure 3 This is a cross-sectional schematic diagram of a wafer according to one embodiment of the present application. Figure 4 This is a partially enlarged cross-sectional schematic diagram of a wafer according to an embodiment of this application, wherein... Figure 4 Will Figure 3 A magnified view of a portion of region Q1. In this application, the term "wafer" can refer to the entire wafer formed in the various steps of wafer fabrication, including all layers or regions that have been formed. A wafer includes multiple device regions D1 and dicing regions D2 located between adjacent device regions D1. A wafer actually includes a relatively large number of device regions D1 arranged on the substrate plane. Figure 3 The diagram illustrates two adjacent device regions, D1.

[0067] The wafer includes a substrate 110, an epitaxial layer 120, an ohmic contact layer 130, a device electrode layer 140, at least one interconnect layer 150, a dielectric layer 160, and a heat-absorbing layer 171.

[0068] The substrate 110 may contain, but is not limited to, semiconductor substrate materials such as Si, doped Si, SiC, SiGe, and GaAs. The substrate 110 may contain, but is not limited to, sapphire, SOI, or other suitable substrate materials.

[0069] Epitaxial layer 120 is located on substrate 110, and epitaxial layer 120 includes a functional layer for forming transistors.

[0070] In one example, device region D1 of the wafer is used to form a HEMT. In this case, epitaxial layer 120 includes sublayers such as a channel layer and a barrier layer. The channel layer and barrier layer can each comprise nitrides or III-V compounds. For example, the channel layer and barrier layer can include, but are not limited to, GaN, AlN, AlGaN, and InAlGaN. The band gap (i.e., band width) of the barrier layer is larger than that of the channel layer, which makes the electron affinity different and allows the GaN layer to form a heterojunction in between. In this embodiment, the example is a GaN layer as the channel layer and an AlGaN layer as the barrier layer. In this case, the transistor is, for example, a GaN-based HEMT. A triangular well potential is generated at the interface between the barrier layer and the channel layer, causing electrons to accumulate in the triangular well, thereby generating a two-dimensional electron gas (2DEG) region near the heterojunction. Epitaxial layer 120 may also include other functional layers for forming the transistor, such as buffer layers, barrier modulation layers, etc.

[0071] An ohmic contact layer 130 is disposed in device region D1 and located on the side of epitaxial layer 120 away from substrate 110. The ohmic contact layer 130 is used to reduce the ohmic contact resistance of the ohmic contact region. In one example, the ohmic contact layer 130 is formed in the source and drain regions of the transistor.

[0072] Device electrode layer 140 is connected to ohmic contact layer 130 in device region D1 and is located on the side of ohmic contact layer 130 away from substrate 110. In one example, device electrode layer 140 includes a source electrode SE and a drain electrode DE. The source electrode SE is located in the source region and is connected to ohmic contact layer 130 located in the source region. The drain electrode DE is located in the drain region and is connected to ohmic contact layer 130 located in the drain region. In some embodiments, device electrode layer 140 may further include a gate electrode GE, which is located in the gate region of the transistor.

[0073] In some embodiments, the epitaxial layer 120 further includes a doped nitride-based semiconductor layer, and the wafer further includes a gate metal GM. The doped nitride-based semiconductor layer is located in the gate region and on the side of the barrier layer away from the substrate 110, and the gate metal GM is located in the gate region and on the side of the doped nitride-based semiconductor layer away from the substrate 110.

[0074] The material of the doped nitride-based semiconductor layer can include, but is not limited to, p-doped III-V group nitride semiconductor materials, such as p-type GaN, p-type AlGaN, p-type InN, p-type AlInN, p-type InGaN, p-type AlInGaN, or combinations thereof. In one example, a barrier layer is located on the side of the channel layer away from the substrate 110, the channel layer being, for example, a GaN layer, the barrier layer being, for example, an AlGaN layer, and the doped nitride-based semiconductor layer being, for example, a p-type GaN layer. The doped nitride-based semiconductor layer causes the 2DEG region at its coverage location to form a depletion region, blocking the 2DEG and thus placing the HEMT in a cutoff state.

[0075] At least one interconnect layer 150 is electrically connected to the device electrode layer 140 in the device region D1 and is located on the side of the device electrode layer 140 away from the substrate 110. The at least one interconnect layer 150 includes a top interconnect layer 150a that is furthest from the substrate 110. The interconnect layers 150 are used to electrically connect at least one electrode of the transistor to other circuit structures. The number of interconnect layers 150 can be one, two, three, or other numbers.

[0076] The dielectric layer 160 is located between the top interconnect layer 150a and the device electrode layer 140. The dielectric layer 160 exists between the interconnect layer 150 closest to the device electrode layer 140 and that device electrode layer 140. When there are two or more interconnect layers 150, the dielectric layer 160 also exists between two adjacent interconnect layers 150.

[0077] The interconnect layer 150 and the device electrode layer 140 can be connected through vias. In some embodiments, there are two or more interconnect layers 150, and the two interconnect layers 150 can be connected through vias.

[0078] The heat-absorbing layer 171 is located on the side of the dielectric layer 160 away from the substrate 110. The heat-absorbing layer 171 is located at least in the dicing area D2. The light absorption rate of the heat-absorbing layer 171 for light of a preset wavelength is greater than that of the dielectric layer 160 for light of a preset wavelength. The wavelength of the laser used to dicing the wafer dicing area D2 is within the preset wavelength.

[0079] According to an embodiment of this application, the wafer includes at least one interconnect layer 150, which includes a top interconnect layer 150a furthest from the substrate 110, and a dielectric layer 160 located between the top interconnect layer 150a and the device electrode layer 140. The wafer also includes a heat-absorbing layer 171 located on the side of the dielectric layer 160 furthest from the substrate 110, and at least located in the dicing region D2. The heat-absorbing layer 171 has a higher absorption rate for light of a predetermined wavelength than the dielectric layer 160, wherein the wavelength of the laser used to dicing the wafer dicing region D2 is within the predetermined wavelength range. In subsequent wafer processing, by laser dicing the wafer dicing region D2, multiple device regions D1 can be separated and transformed into multiple semiconductor devices. During laser cutting, the wafer bottom layer 120, located near the substrate 110 along the wafer thickness direction, has a high laser absorption rate, resulting in a higher temperature at this location. Conversely, the wafer surface away from the substrate 110 has a heat-absorbing layer 171, which also has a high laser absorption rate, leading to a higher temperature at this location as well. Therefore, the heat distribution at the cutting location is more uniform along the wafer thickness direction, thus mitigating the problem of thermal damage during wafer cutting.

[0080] In some embodiments, the wafer further includes an interlayer insulating layer 180 located on the side of the ohmic contact layer 130 away from the substrate 110 and between the device electrode layer 140 and the ohmic contact layer 130. The device electrode layer 140 can be connected to the ohmic contact layer 130 through vias penetrating the interlayer insulating layer 180. In some embodiments, the material of the interlayer insulating layer 180 is the same as the material of the dielectric layer 160.

[0081] In some embodiments, the wafer further includes a passivation layer 190 located on the side of the top interconnect layer 150a away from the substrate 110. In some embodiments, the wafer further includes a first opening K1 located in the dicing region D2, the first opening K1 penetrating the passivation layer 190, and the first opening K1 exposing the heat-absorbing layer 171.

[0082] In some embodiments, the passivation layer 190 may include at least two sub-passivation layers stacked together. In one example, the passivation layer 190 includes a first sub-passivation layer and a second sub-passivation layer stacked sequentially in a direction away from the substrate 110. For example, the first sub-passivation layer is a SiO layer and the second sub-passivation layer is a SiN layer.

[0083] In some embodiments, the top interconnect layer 150a includes pad portions. The wafer also includes a second opening K2 located in device region D1, penetrating the passivation layer 190, and exposing the pad portions. In the above embodiments, the second opening K2 exposes the pad portions, thereby facilitating electrical connection between the pad portions of device region D1 and other components. In some embodiments, at least a portion of the second opening K2 and at least a portion of the first opening K1 are formed in the same patterning process, thereby improving wafer fabrication efficiency and facilitating improved transistor manufacturing efficiency.

[0084] In some embodiments, the dielectric layer 160 is an oxide insulating layer; the heat-absorbing layer 171 is a silicon nitride layer. In this embodiment, the dielectric layer 160 is a SiO layer. The heat-absorbing layer 171 is, for example, a SiN layer. The absorption rate of the SiN layer for the cutting laser is greater than that of the SiO layer for the cutting laser.

[0085] In one example, the thickness of the heat-absorbing layer 171 in the cut region D2 is 600 nanometers to 800 nanometers, for example, the thickness of the heat-absorbing layer 171 is 700 nanometers.

[0086] As mentioned above, the number of interconnect layers 150 can be one, two, three, or other numbers. In some embodiments, at least one interconnect layer 150 further includes a non-top-level interconnect layer 150b located between the top interconnect layer 150a and the device electrode layer 140, and the dielectric layer 160 includes at least two dielectric sublayers 161, each dielectric sublayer 161 located between the non-top interconnect layer 150b and the device electrode layer 140, or located between adjacent interconnect layers 150. Exemplarily, in this embodiment, at least one interconnect layer 150 includes a top interconnect layer 150a and a non-top interconnect layer 150b, and the dielectric layer 160 includes two dielectric sublayers 161, one dielectric sublayer 161 located between the non-top interconnect layer 150b and the device electrode layer 140, and the other dielectric sublayer 161 located between the non-top interconnect layer 150b and the top interconnect layer 150a. In some other embodiments, at least one interconnect layer 150 may not include a non-top interconnect layer 150b, or in some other embodiments, at least one interconnect layer 150 may include two or more non-top interconnect layers 150b.

[0087] This application also provides a wafer fabrication method that can form the wafer described in the above embodiments.

[0088] Figures 5 to 12 This is a partially enlarged cross-sectional schematic diagram of each stage of an embodiment of the wafer fabrication method according to this application. In this embodiment, the wafer fabrication method includes the following steps S101 to S111.

[0089] In step S101, a substrate 110 is provided, the substrate 110 having a plurality of device regions D1 and a dicing region D2 located between adjacent device regions D1.

[0090] like Figure 5 In step S102, an epitaxial layer 120 is formed on the substrate 110, the epitaxial layer 120 including a functional layer for forming a transistor.

[0091] like Figure 6 In step S103, an ohmic contact layer 130 is formed on the side of the epitaxial layer 120 away from the substrate 110, and the ohmic contact layer 130 is located in device region D1. In some embodiments, after the ohmic contact layer 130 is formed on the side of the epitaxial layer 120 away from the substrate 110, an interlayer insulating layer 180 is formed on the side of the ohmic contact layer 130 away from the substrate 110.

[0092] like Figure 7 In step S105, a device electrode layer 140 is formed on the side of the ohmic contact layer 130 away from the substrate 110. The device electrode layer 140 is located in the device region D1 and is connected to the ohmic contact layer 130. In this embodiment, step S105 is: forming the device electrode layer 140 on the side of the interlayer insulating layer 180 away from the substrate 110.

[0093] Next, at least one interconnect layer 150 and a dielectric layer 160 are formed on the side of the interlayer device electrode layer 140 away from the substrate 110. The interconnect layer 150 is used to electrically connect at least one electrode of the transistor to other circuit structures. The number of interconnect layers 150 can be one, two, three, or other numbers. The dielectric layer 160 exists between the interconnect layer 150 closest to the device electrode layer 140 and that device electrode layer 140. When there are two or more interconnect layers 150, the dielectric layer 160 also exists between two adjacent interconnect layers 150. The interconnect layers 150 and the device electrode layer 140 can be connected by vias. In some embodiments, there are two or more interconnect layers 150, and two interconnect layers 150 can be connected by vias. The at least one interconnect layer 150 includes the top interconnect layer 150a furthest from the substrate 110.

[0094] like Figure 8 In step S105, a dielectric layer 160 is formed on the side of the device electrode layer 140 away from the substrate 110. In step S105, in addition to forming the dielectric layer 160, when there are two or more interconnect layers 150, other interconnect layers 150 other than the top interconnect layer 150a are also formed.

[0095] In this embodiment, the example is given where there are two interconnect layers 150. For example, at least one interconnect layer 150 may also include a non-top interconnect layer 150b, in which case the dielectric layer 160 includes two dielectric sublayers 161. Specifically, step S105 may include: forming a first dielectric sublayer 161 on the side of the device electrode layer 140 away from the substrate 110; forming a non-top interconnect layer 150b on the side of the first dielectric sublayer 161 away from the substrate 110; and forming a second dielectric sublayer 161 on the side of the non-top interconnect layer 150b away from the substrate 110, thereby forming all dielectric layers 160.

[0096] like Figure 9 In step S106, a heat-absorbing layer 171 is formed on the side of the dielectric layer 160 away from the substrate 110. The heat-absorbing layer 171 is located at least in the dicing area D2. The light absorption rate of the heat-absorbing layer 171 for a preset wavelength band is greater than that of the dielectric layer 160 for a preset wavelength band. The wavelength of the laser used to dicing the wafer dicing area D2 is within the preset wavelength band.

[0097] In some embodiments, the dielectric layer 160 is an oxide insulating layer; the heat-absorbing layer 171 is a silicon nitride layer. In this embodiment, the dielectric layer 160 is a SiO layer. The heat-absorbing layer 171 is, for example, a SiN layer. The absorption rate of the SiN layer for the cutting laser is greater than that of the SiO layer for the cutting laser.

[0098] like Figure 10 In step S109, a top interconnect layer 150a is formed on the side of the heat absorption layer 171 away from the substrate 110, and the top interconnect layer 150a is located in the device region D1.

[0099] like Figure 11 In step S110, a passivation layer 190 is formed on the side of the top interconnect layer 150a away from the substrate 110, and the passivation layer 190 covers the device region D1 and the diced region D2. In some embodiments, the passivation layer 190 may include at least two sub-passivation layers stacked together. In one example, the passivation layer 190 includes a first sub-passivation layer and a second sub-passivation layer stacked sequentially in the direction away from the substrate 110. For example, the first sub-passivation layer is a SiO layer and the second sub-passivation layer is a SiN layer.

[0100] like Figure 12 In step S111, the surface of the passivation layer 190 is patterned to form a first opening K1 located in the cutting area D2. The first opening K1 penetrates the passivation layer 190 and exposes the heat-absorbing layer 171.

[0101] In some embodiments, step S111 further includes: forming a second opening K2 located in device region D1, the second opening K2 penetrating the passivation layer 190, the second opening K2 exposing the pad portion of the top interconnect layer 150a.

[0102] According to the wafer fabrication method of this application embodiment, a heat-absorbing layer 171 is formed on the side of the dielectric layer 160 away from the substrate 110. The heat-absorbing layer 171 is located at least in the dicing region D2. The light absorption rate of the heat-absorbing layer 171 for a preset wavelength band is greater than that of the dielectric layer 160 for the preset wavelength band. The wavelength of the laser used to dicing the wafer dicing region D2 is within the preset wavelength band. Then, a top interconnect layer 150a is formed on the side of the heat-absorbing layer 171 away from the substrate 110, and a passivation layer 190 is formed on the side of the top interconnect layer 150a away from the substrate 110. Patterning is performed on the surface of the passivation layer 190 to form a first opening K1 located in the dicing region D2. The first opening K1 penetrates the passivation layer 190, exposing the heat-absorbing layer 171. In subsequent wafer processing, by laser dicing the dicing region D2 of the wafer, multiple device regions D1 can be separated from each other and transformed into multiple semiconductor devices. During laser cutting, the wafer bottom layer 120, located near the substrate 110 along the wafer thickness direction, has a high laser absorption rate, resulting in a higher temperature at this location. Conversely, the wafer surface away from the substrate 110 has a heat-absorbing layer 171, which also has a high laser absorption rate, leading to a higher temperature at this location as well. Therefore, the heat distribution at the cutting location is more uniform along the wafer thickness direction, thus mitigating the problem of thermal damage during wafer cutting.

[0103] Optionally, the wafer processing method may further include: cutting the dicing area D2 with a laser to obtain multiple semiconductor devices. As mentioned above, the wavelength of the laser used to cut the wafer dicing area D2 is within a preset wavelength band. After the dicing area D2 is cut by the laser, the original multiple device areas D1 are separated from each other to form multiple semiconductor devices.

[0104] Figure 13 This is a cross-sectional schematic diagram of another embodiment of the wafer according to this application. Figure 14 This is a partially enlarged cross-sectional schematic diagram of another embodiment of the wafer according to this application, wherein... Figure 14 Will Figure 13 A magnified view of a portion of region Q2. The wafer includes multiple device regions D1 and dicing regions D2 located between adjacent device regions D1. The wafer includes a substrate 110, an epitaxial layer 120, an ohmic contact layer 130, a device electrode layer 140, at least one interconnect layer 150, a dielectric layer 160, and a heat-absorbing layer 171.

[0105] An epitaxial layer 120 is located on a substrate 110 and includes a functional layer for forming a transistor. An ohmic contact layer 130 is disposed in a device region D1 and located on the side of the epitaxial layer 120 away from the substrate 110. The ohmic contact layer 130 is used to reduce the ohmic contact resistance of the ohmic contact region. A device electrode layer 140 is connected to the ohmic contact layer 130 in the device region D1 and is located on the side of the ohmic contact layer 130 away from the substrate 110. At least one interconnect layer 150 is electrically connected to the device electrode layer 140 in the device region D1 and is located on the side of the device electrode layer 140 away from the substrate 110. The at least one interconnect layer 150 includes a top interconnect layer 150a that is furthest from the substrate 110. A dielectric layer 160 is located between the top interconnect layer 150a and the device electrode layer 140. The dielectric layer 160 exists between the interconnect layer 150 closest to the device electrode layer 140 and the device electrode layer 140. When there are two or more interconnect layers 150, a dielectric layer 160 also exists between two adjacent interconnect layers 150. The interconnect layers 150 and the device electrode layers 140 can be connected through vias. In some embodiments, there are two or more interconnect layers 150, and two interconnect layers 150 can be connected through vias.

[0106] The heat-absorbing layer 171 is located on the side of the dielectric layer 160 away from the substrate 110. The heat-absorbing layer 171 is located at least in the dicing area D2. The light absorption rate of the heat-absorbing layer 171 for light of a preset wavelength is greater than that of the dielectric layer 160 for light of a preset wavelength. The wavelength of the laser used to dicing the wafer dicing area D2 is within the preset wavelength.

[0107] In this embodiment, at least one interconnect layer 150 further includes a non-top interconnect layer 150b located between the top interconnect layer 150a and the device electrode layer 140, and the dielectric layer 160 includes at least two dielectric sublayers 161, each dielectric sublayer 161 being located between the non-top interconnect layer 150b and the device electrode layer 140, or between adjacent interconnect layers 150.

[0108] The wafer may also include an interlayer insulating layer 180 located on the side of the ohmic contact layer 130 away from the substrate 110 and between the device electrode layer 140 and the ohmic contact layer 130.

[0109] The wafer may further include a passivation layer 190 located on the side of the top interconnect layer 150a away from the substrate 110. In some embodiments, the wafer further includes a first opening K1 located in a dicing region D2, penetrating the passivation layer 190, and exposing a heat-absorbing layer 171. The top interconnect layer 150a includes pad portions. The wafer may further include a second opening K2 located in a device region D1, penetrating the passivation layer 190, and exposing pad portions.

[0110] In some embodiments, the heat-absorbing layer 171 is also disposed in the device region D1. For example... Figure 10 In this embodiment, the wafer further includes a first sacrificial layer 172. The first sacrificial layer 172 is located in the device region D1 and between the top interconnect layer 150a and the heat absorption layer 171.

[0111] In some embodiments, the material of the first sacrificial layer 172 is configured to serve as an etching stop layer when the passivation layer 190 is etched; the material of the heat-absorbing layer 171 is configured to serve as an etching stop layer when the first sacrificial layer 172 is etched.

[0112] In some embodiments, during the formation of the first opening K1 located in the dicing region D2, a first etching can be performed using the first sacrificial layer 172 as an etching stop layer. This first etching forms the first sub-opening in the dicing region D2. Since the first sacrificial layer 172 serves as the etching stop layer, the etching depth at each location within the first sub-opening is relatively uniform. Then, using the heat-absorbing layer 171 as the etching stop layer, a second etching is performed on the first sub-opening to obtain a second sub-opening penetrating the first sacrificial layer 172. The second sub-opening connects with the first sub-opening to form the first opening K1. Through the selection of the aforementioned materials, after etching to form the first opening K1, the etching depth at each location within the first opening K1 is relatively uniform, solving the technical problem of uneven etching depth at the dicing opening in the wafer dicing region D2 in related technologies.

[0113] like Figure 13 , Figure 14 In this embodiment, the wafer also includes a second sacrificial layer 173. The second sacrificial layer 173 is located in the device region D1 and between the top interconnect layer 150a and the first sacrificial layer 172.

[0114] In some embodiments, the dielectric layer 160 is an oxide insulating layer; the heat-absorbing layer 171 is a silicon nitride layer; the first sacrificial layer 172 is an aluminum nitride layer; and the second sacrificial layer 173 is an oxide insulating layer.

[0115] In one example, the dielectric layer 160 is a SiO layer. The heat-absorbing layer 171 is, for example, a SiN layer. The first sacrificial layer 172 is, for example, an AlN layer. The second sacrificial layer 173 is, for example, a SiO layer.

[0116] In one example, the thickness of the heat-absorbing layer 171 is 600 nm to 800 nm, the thickness of the first sacrificial layer 172 is 1 nm to 4 nm, and the thickness of the second sacrificial layer 173 is 300 nm to 600 nm. For example, the thickness of the heat-absorbing layer 171 is 700 nm, the thickness of the first sacrificial layer 172 is 2 nm, and the thickness of the second sacrificial layer 173 is 400 nm.

[0117] According to an embodiment of this application, the wafer includes at least one interconnect layer 150, which includes a top interconnect layer 150a furthest from the substrate 110, and a dielectric layer 160 located between the top interconnect layer 150a and the device electrode layer 140. The wafer also includes a heat-absorbing layer 171 located on the side of the dielectric layer 160 furthest from the substrate 110, and at least located in the dicing region D2. The heat-absorbing layer 171 has a higher absorption rate for light of a predetermined wavelength than the dielectric layer 160, wherein the wavelength of the laser used to dicing the wafer dicing region D2 is within the predetermined wavelength range. In subsequent wafer processing, by laser dicing the wafer dicing region D2, multiple device regions D1 can be separated and transformed into multiple semiconductor devices. During laser cutting, the wafer bottom layer 120, located near the substrate 110 along the wafer thickness direction, has a high laser absorption rate, resulting in a higher temperature at this location. Conversely, the wafer surface away from the substrate 110 has a heat-absorbing layer 171, which also has a high laser absorption rate, leading to a higher temperature at this location as well. Therefore, the heat distribution at the cutting location is more uniform along the wafer thickness direction, thus mitigating the problem of thermal damage during wafer cutting.

[0118] In some embodiments, the heat-absorbing layer 171 is further disposed in the device region D1, and the wafer further includes a first sacrificial layer 172, which is located in the device region D1 and between the top interconnect layer 150a and the heat-absorbing layer 171. The material of the first sacrificial layer 172 is configured to serve as an etching stop layer when the passivation layer 190 is etched; the material of the heat-absorbing layer 171 is configured to serve as an etching stop layer when the first sacrificial layer 172 is etched. In the above embodiments, by selecting the above materials, after etching to form the first opening K1, the etching depth at each position in the first opening K1 is relatively uniform, solving the technical problem of uneven etching depth of the dicing opening in the wafer dicing region D2 in related technologies.

[0119] The wafer processing method of another embodiment of this application will be described below by describing the wafer processing process of another embodiment described above. Figures 15 to 21 This is a cross-sectional schematic diagram of each stage of another embodiment of the wafer fabrication method according to this application. In this embodiment, the wafer fabrication method includes the following steps S201 to S211.

[0120] Steps S201 to S206 in this embodiment are basically the same as steps S101 to S106 in the previous embodiment, and will not be described in detail here.

[0121] like Figure 15 In step S201, a substrate 110 is provided, which has a plurality of device regions D1 and a dicing region D2 located between adjacent device regions D1.

[0122] In step S202, an epitaxial layer 120 is formed on the substrate 110, the epitaxial layer 120 including a functional layer for forming a transistor.

[0123] In step S203, an ohmic contact layer 130 is formed on the side of the epitaxial layer 120 away from the substrate 110, and the ohmic contact layer 130 is located in the device region D1.

[0124] In step S204, a device electrode layer 140 is formed on the side of the ohmic contact layer 130 away from the substrate 110. The device electrode layer 140 is located in the device region D1 and is connected to the ohmic contact layer 130.

[0125] In step S205, a dielectric layer 160 is formed on the side of the device electrode layer 140 away from the substrate 110.

[0126] In step S206, a heat-absorbing layer 171 is formed on the side of the dielectric layer 160 away from the substrate 110. The heat-absorbing layer 171 is located at least in the dicing area D2. The light absorption rate of the heat-absorbing layer 171 for light of a preset wavelength is greater than that of the dielectric layer 160 for light of a preset wavelength. The wavelength of the laser used to dicing the wafer dicing area D2 is within the preset wavelength.

[0127] In this embodiment, step S207 may be included before step S209.

[0128] like Figure 16 In step S207, a first sacrificial layer 172 is formed on the side of the heat-absorbing layer 171 away from the substrate 110. The first sacrificial layer 172 is located in the device region D1 and the dicing region D2.

[0129] In this embodiment, step S208 may be included before step S209.

[0130] like Figure 17 In step S208, a second sacrificial layer 173 is formed on the side of the first sacrificial layer 172 away from the substrate 110. The second sacrificial layer 173 is located in the device region D1 and the dicing region D2.

[0131] like Figure 18 In step S209, a top interconnect layer 150a is formed on the side of the heat absorption layer 171 away from the substrate 110, and the top interconnect layer 150a is located in the device region D1.

[0132] like Figure 19 In step S210, a passivation layer 190 is formed on the side of the top interconnect layer 150a away from the substrate 110, and the passivation layer 190 covers the device region D1 and the dicing region D2.

[0133] In step S211, the surface of the passivation layer 190 is patterned to form a first opening K1 located in the cutting area D2. The first opening K1 penetrates the passivation layer 190 and exposes the heat-absorbing layer 171.

[0134] In this embodiment, the step S211 of patterning the surface of the self-passivation layer 190 to form the first opening K1 located in the cutting region D2 may include the following steps: like Figure 20 Using the first sacrificial layer 172 as the etching stop layer, a first etching is performed from the surface of the passivation layer 190 to obtain a first sub-opening K11 located in the cutting region D2. The first sub-opening K11 penetrates the passivation layer 190. In this embodiment, during the step of performing the first etching from the surface of the passivation layer 190 using the first sacrificial layer 172 as the etching stop layer, the first sub-opening K11 also penetrates the second sacrificial layer 173.

[0135] like Figure 21 Using the heat-absorbing layer 171 as the etching stop layer, a second etching is performed on the first sub-opening K11 to obtain a second sub-opening K12 that penetrates the first sacrificial layer 172. The second sub-opening K12 is connected to the first sub-opening K11 to form the first opening K1.

[0136] In some embodiments, the dielectric layer 160 is an oxide insulating layer; the heat-absorbing layer 171 is a silicon nitride layer; the first sacrificial layer 172 is an aluminum nitride layer; and the second sacrificial layer 173 is an oxide insulating layer. In one example, the dielectric layer 160 is a SiO layer. The heat-absorbing layer 171 is, for example, a SiN layer. The first sacrificial layer 172 is, for example, an AlN layer. The second sacrificial layer 173 is, for example, a SiO layer.

[0137] According to the wafer fabrication method of this application embodiment, a heat-absorbing layer 171 is formed on the side of the dielectric layer 160 away from the substrate 110. The heat-absorbing layer 171 is located at least in the dicing region D2. The light absorption rate of the heat-absorbing layer 171 for a preset wavelength band is greater than that of the dielectric layer 160 for the preset wavelength band. The wavelength of the laser used to dicing the wafer dicing region D2 is within the preset wavelength band. Then, a top interconnect layer 150a is formed on the side of the heat-absorbing layer 171 away from the substrate 110, and a passivation layer 190 is formed on the side of the top interconnect layer 150a away from the substrate 110. Patterning is performed on the surface of the passivation layer 190 to form a first opening K1 located in the dicing region D2. The first opening K1 penetrates the passivation layer 190, exposing the heat-absorbing layer 171. In subsequent wafer processing, by laser dicing the dicing region D2 of the wafer, multiple device regions D1 can be separated from each other and transformed into multiple semiconductor devices. During laser cutting, the wafer bottom layer 120, located near the substrate 110 along the wafer thickness direction, has a high laser absorption rate, resulting in a higher temperature at this location. Conversely, the wafer surface away from the substrate 110 has a heat-absorbing layer 171, which also has a high laser absorption rate, leading to a higher temperature at this location as well. Therefore, the heat distribution at the cutting location is more uniform along the wafer thickness direction, thus mitigating the problem of thermal damage during wafer cutting.

[0138] In some embodiments, prior to the step of forming the top interconnect layer 150a on the side of the heat-absorbing layer 171 away from the substrate 110, the wafer fabrication method further includes: forming a first sacrificial layer 172 on the side of the heat-absorbing layer 171 away from the substrate 110, the first sacrificial layer 172 being located in the device region D1 and the dicing region D2. The subsequent step of patterning from the surface of the passivation layer 190 to form a first opening K1 located in the dicing region D2 may include: using the first sacrificial layer 172 as an etch stop layer, performing a first etching from the surface of the passivation layer 190 to obtain a first sub-opening K11 located in the dicing region D2, the first sub-opening K11 penetrating the passivation layer 190; using the heat-absorbing layer 171 as an etch stop layer, performing a second etching on the first sub-opening K11 to obtain a second sub-opening K12 penetrating the first sacrificial layer 172, the second sub-opening K12 communicating with the first sub-opening K11 to form the first opening K1. After etching to form the first opening K1, the etching depth at each position in the first opening K1 is relatively uniform, which solves the technical problem of uneven etching depth of the cutting opening of the wafer cutting area D2 in related technologies.

[0139] Optionally, the wafer processing method may further include: cutting the dicing area D2 with a laser to obtain multiple semiconductor devices. As mentioned above, the wavelength of the laser used to cut the wafer dicing area D2 is within a preset wavelength band. After the dicing area D2 is cut by the laser, the original multiple device areas D1 are separated from each other to form multiple semiconductor devices.

[0140] It should be noted that the technical solutions or features described in the above embodiments can be combined or supplemented with each other without conflict. The scope of protection of this application is not limited to the precise structures described in the above embodiments and shown in the accompanying drawings; all modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the scope of protection of this application.

Claims

1. A semiconductor device, characterized in that, The semiconductor device has a device region and a diced edge region located on the periphery of the device region and extending along at least a portion of the edge of the semiconductor device, the semiconductor device comprising: Substrate; An epitaxial layer is located on the substrate, the epitaxial layer including a functional layer for forming a transistor; An ohmic contact layer is disposed in the device region and located on the side of the epitaxial layer away from the substrate; A device electrode layer is connected to the ohmic contact layer in the device region and is located on the side of the ohmic contact layer away from the substrate; At least one interconnect layer is electrically connected to the device electrode layer in the device region and is located on the side of the device electrode layer away from the substrate, wherein the at least one interconnect layer includes the top interconnect layer that is furthest from the substrate; A dielectric layer is located between the top interconnect layer and the device electrode layer; A heat-absorbing layer is located on the side of the dielectric layer away from the substrate. The heat-absorbing layer is located at least in the cutting edge region. The light absorption rate of the heat-absorbing layer for a preset wavelength band is greater than that of the dielectric layer for the preset wavelength band.

2. The semiconductor device according to claim 1, characterized in that, Also includes: A passivation layer is located on the side of the top interconnect layer away from the substrate; A first opening is located in the cut edge region, the first opening penetrates the passivation layer, and the first opening exposes the heat-absorbing layer.

3. The semiconductor device according to claim 2, characterized in that, The semiconductor device includes a sealing ring extending around the device region, with the first opening located outside the sealing ring.

4. The semiconductor device according to claim 2, characterized in that, The top interconnect layer includes pads, and the semiconductor device further includes: A second opening is located in the device area, the second opening penetrates the passivation layer, and the second opening exposes the pad portion.

5. The semiconductor device according to claim 2, characterized in that, The heat-absorbing layer is further disposed in the device region; the semiconductor device further includes: A first sacrificial layer is located in the device region and between the top interconnect layer and the heat absorption layer.

6. The semiconductor device according to claim 5, characterized in that, The material of the first sacrificial layer is set to serve as an etching stop layer when the passivation layer is etched; The material of the heat-absorbing layer is configured to serve as an etching stop layer during the etching of the first sacrificial layer.

7. The semiconductor device according to claim 5, characterized in that, Also includes: The second sacrificial layer is located in the device region and between the top interconnect layer and the first sacrificial layer.

8. The semiconductor device according to claim 7, characterized in that, The dielectric layer is an oxide insulating layer; the heat-absorbing layer is a silicon nitride layer; the first sacrificial layer is an aluminum nitride layer; and the second sacrificial layer is an oxide insulating layer.

9. The semiconductor device according to claim 1, characterized in that, The preset wavelength band is 315nm to 400nm.

10. The semiconductor device according to claim 1, characterized in that, The at least one interconnect layer further includes a non-top interconnect layer located between the top interconnect layer and the device electrode layer, and the dielectric layer includes at least two dielectric sublayers, each of which is located between the non-top interconnect layer and the device electrode layer, or between adjacent interconnect layers.

11. A wafer, characterized in that, The wafer includes multiple device regions and dicing regions located between adjacent device regions. Substrate; An epitaxial layer is located on the substrate, the epitaxial layer including a functional layer for forming a transistor; An ohmic contact layer is disposed in the device region and located on the side of the epitaxial layer away from the substrate; A device electrode layer is connected to the ohmic contact layer in the device region and is located on the side of the ohmic contact layer away from the substrate; At least one interconnect layer is electrically connected to the device electrode layer in the device region and is located on the side of the device electrode layer away from the substrate, wherein the at least one interconnect layer includes the top interconnect layer that is furthest from the substrate; A dielectric layer is located between the top interconnect layer and the device electrode layer; A heat-absorbing layer is located on the side of the dielectric layer away from the substrate. The heat-absorbing layer is at least located in the cutting area. The heat-absorbing layer has a light absorption rate of a preset wavelength band that is greater than that of the dielectric layer for the preset wavelength band. The wavelength of the laser used to cut the cutting area is within the preset wavelength band.

12. The wafer according to claim 11, characterized in that, Also includes: A passivation layer is located on the side of the top interconnect layer away from the substrate; A first opening is located in the cutting area, the first opening penetrates the passivation layer, and the first opening exposes the heat-absorbing layer.

13. The wafer according to claim 12, characterized in that, The heat-absorbing layer is also disposed in the device region; the wafer further includes: A first sacrificial layer is located in the device region and between the top interconnect layer and the heat absorption layer.

14. The wafer according to claim 13, characterized in that, The material of the first sacrificial layer is set to serve as an etching stop layer when the passivation layer is etched; The material of the heat-absorbing layer is configured to serve as an etching stop layer during the etching of the first sacrificial layer.

15. The wafer according to claim 13, characterized in that, Also includes: The second sacrificial layer is located in the device region and between the top interconnect layer and the first sacrificial layer.

16. A wafer fabrication method, characterized in that, include: A substrate is provided having a plurality of device regions and a dicing region located between adjacent device regions; An epitaxial layer is formed on a substrate, the epitaxial layer including a functional layer for forming a transistor; An ohmic contact layer is formed on the side of the epitaxial layer away from the substrate, and the ohmic contact layer is located in the device region; A device electrode layer is formed on the side of the ohmic contact layer away from the substrate. The device electrode layer is located in the device region and is connected to the ohmic contact layer. A dielectric layer is formed on the side of the device electrode layer away from the substrate; A heat-absorbing layer is formed on the side of the dielectric layer away from the substrate. The heat-absorbing layer is located at least in the cutting area. The light absorption rate of the heat-absorbing layer for light of a preset wavelength band is greater than that of the dielectric layer for light of the preset wavelength band. The wavelength of the laser used to cut the cutting area is within the preset wavelength band. A top interconnect layer is formed on the side of the heat-absorbing layer away from the substrate, and the top interconnect layer is located in the device region; A passivation layer is formed on the side of the top interconnect layer away from the substrate, the passivation layer covering the device region and the diced region; Patterning is performed on the surface of the passivation layer to form a first opening located in the cutting area, the first opening penetrating the passivation layer and exposing the heat-absorbing layer.

17. The wafer fabrication method according to claim 16, characterized in that, Also includes: Multiple semiconductor devices are obtained by cutting the cutting area with a laser.

18. The wafer fabrication method according to claim 16, characterized in that, Prior to the step of forming the top interconnect layer on the side of the heat-absorbing layer away from the substrate, the wafer fabrication method further includes: A first sacrificial layer is formed on the side of the heat-absorbing layer away from the substrate, and the first sacrificial layer is located in the device region and the dicing region; The process of patterning from the surface of the passivation layer to form a first opening located in the cutting area includes: Using the first sacrificial layer as the etching stop layer, a first etching is performed from the surface of the passivation layer to obtain a first sub-opening located in the cutting area, and the first sub-opening penetrates the passivation layer. Using the heat-absorbing layer as the etching stop layer, a second etching is performed on the first sub-opening to obtain a second sub-opening that penetrates the first sacrificial layer. The second sub-opening is connected to the first sub-opening to form the first opening.

19. The wafer fabrication method according to claim 18, characterized in that, Prior to the step of forming the top interconnect layer on the side of the heat-absorbing layer away from the substrate, the wafer fabrication method further includes: A second sacrificial layer is formed on the side of the first sacrificial layer away from the substrate, and the second sacrificial layer is located in the device region and the dicing region; In the step of performing the first etching from the surface of the passivation layer with the first sacrificial layer as the etching stop layer, the first sub-opening also penetrates the second sacrificial layer.

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