A semiconductor device and a method of fabricating the same

By setting a deep buried layer in the SGT MOSFET device, the electric field distribution is modulated and flattened, solving the problem of electric field concentration, achieving higher breakdown voltage and lower on-resistance, and improving the device's operating performance and reliability.

CN122121230AActive Publication Date: 2026-05-29THING ELEMENT SEMICON TECH (QINGDAO) CO LTD
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Patent Information

Application Number
CN202610580489.7
Authority / Receiving Office
CN · China
Patent Type
Applications(China)
Current Assignee / Owner
Filing Date
2026-04-29
Publication Date
2026-05-29
Estimated Expiration
2046-04-29

AI Technical Summary

Technical Problem

Existing SGT MOSFET devices suffer from charge balance and electric field distribution optimization issues in high-voltage applications, which leads to the electric field concentrating at the bottom of the trench, making them prone to premature breakdown and reducing the device's reliability and lifespan.

Method used

A deep-buried layer is set in the epitaxial layer, located on opposite sides of the trench, forming a depleted electric field shielding layer, modulating and flattening the electric field distribution, and preventing the electric field from concentrating at the bottom of the trench.

Benefits of technology

It improves the electric field distribution inside the device, increases the breakdown voltage, reduces the on-resistance, and enhances the device's withstand voltage performance and operational reliability.

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Abstract

The application belongs to the technical field of semiconductor manufacturing, and provides a semiconductor device and a preparation method thereof. The semiconductor device comprises a substrate, an epitaxial layer, a shielding gate, a gate, a body region, an injection region and a deep buried layer. The epitaxial layer is located on the front surface of the substrate. A plurality of grooves are arranged in the epitaxial layer. The shielding gate and the gate are arranged at intervals and located in the grooves. The body region is located on the side of the epitaxial layer away from the substrate. The injection region is located on the side of the body region away from the epitaxial layer. The deep buried layer is located in the epitaxial layer and on the opposite sides of the grooves along a first direction. By introducing the deep buried layer, a depleted electric field shielding layer can be formed on both sides below the grooves, thereby avoiding the concentration of the electric field in the weak areas such as the bottom of the grooves, reducing the high peak electric field around the shielding gate, making the electric field distribution in the device more uniform, and improving the breakdown voltage of the device.
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Citation Information

Patent Citations

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  • Silicon carbide field effect transistor

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  • Trench mosfet and method for manufacturing the same

    US20210184009A1

  • Shielded gate trench mosfets with improved performance structures

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