An LDMOS device and a manufacturing method thereof
By setting a drain field plate on the surface of the drain drift region of the LDMOS chip and connecting the drain field plate with an ohmic contact metal layer, the problems of complex process and high cost in the prior art are solved, the breakdown voltage is improved and the source-drain parasitic capacitance is controlled, and the performance and reliability of the device are maintained.
Patent Information
- Application Number
- CN202411710782.8
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-11-27
- Publication Date
- 2026-05-29
AI Technical Summary
Existing technologies for improving the breakdown voltage of LDMOS chips have problems such as complex process adjustments, high costs, and potential impact on device performance and reliability. In particular, increasing the length of the drain drift region and adding a metal field plate can easily lead to an increase in source-drain parasitic capacitance and a limitation on the breakdown voltage.
A drain field plate is set on the surface of the epitaxial layer in the drain drift region. The drain field plate is connected by an ohmic contact metal layer to form a transverse electric field component opposite to the original electric field, so as to cancel the electric field peak and improve the breakdown voltage without increasing the source-drain parasitic capacitance.
This effectively improves the breakdown voltage of LDMOS chips, simplifies the process flow, reduces costs, and maintains the performance and reliability of the devices.
Smart Images
Figure CN122121246A_ABST
Abstract
Description
Technical Field
[0001] This invention belongs to the field of LDMOS device technology, and specifically relates to a low-cost LDMOS device and its manufacturing method. Background Technology
[0002] As the applications of RF power amplifiers continue to expand, the operating voltage of LDMOS devices needs to be continuously increased, which necessitates a continuous improvement in the breakdown voltage of LDMOS chips. Increasing the breakdown voltage of LDMOS chips requires both expanding the depletion region and reducing the peak electric field on the surface of the drain drift region. A common method is to lengthen the drain drift region and place one or more grounded metal field plates near the gate, which significantly reduces the peak electric field in the drift region below the metal field plate. However, with the continuous increase in drain voltage and the length of the metal field plate, the electric field peak region near the high-concentration ion implantation region of the drain drift region becomes a weak point affecting the device's breakdown voltage, thus limiting further increases in the breakdown voltage of LDMOS chips.
[0003] Existing improvement methods typically involve adjusting the ion concentration and thickness of the epitaxial layer, then increasing the ion implantation concentration in the drain drift region to reduce the concentration variation at the boundary between the drain drift region and the high-concentration ion implantation region. This method modulates the longitudinal and lateral electric field components in the drain region to reduce the peak surface electric field in the drift region. However, this method involves adjusting too many process parameters, resulting in a long experimental verification cycle and high cost. It may also affect the performance and reliability of the original device.
[0004] Another method involves setting one or more drain field plates in the drain region, which are placed on the oxide layer. However, in order to suppress the surface peak electric field in the drain drift region of the chip, the drain field plate usually needs to be long enough. However, this will increase the source-drain parasitic capacitance, which will affect the performance and reliability of the device. Summary of the Invention
[0005] To address the aforementioned technical problems, the present invention aims to provide an LDMOS device and its manufacturing method, wherein a drain field plate is disposed on the surface of the epitaxial layer in the drain drift region. Since the drain field plate is directly disposed on the silicon semiconductor, it does not need to be very long to achieve good electric field suppression and will not cause an increase in source-drain parasitic capacitance.
[0006] To address these problems in the prior art, the technical solution provided by this invention is as follows: An LDMOS device includes a substrate and an epitaxial layer. An active region is disposed on the epitaxial layer, including a source region, a gate region, and a drain region. A drain drift region and a high-concentration ion implantation region are disposed in the drain region. An ohmic contact metal layer is disposed on the surface of the epitaxial layer in the high-concentration ion implantation region. The ohmic contact metal layer is connected to an upper metal layer through a via. A drain field plate is disposed on the surface of the epitaxial layer in the drain drift region.
[0007] In a preferred embodiment, the depth and length of the high-concentration ion implantation region are both smaller than the drain drift region.
[0008] In a preferred embodiment, the drain drift region surrounds the high-concentration ion implantation region.
[0009] In a preferred embodiment, the drain field plate is connected to the ohmic contact metal layer, and the drain field plate is obtained by extending a certain length from the ohmic contact metal layer toward the drain drift region.
[0010] In a preferred embodiment, the length of the drain field plate is less than 1 μm.
[0011] In a preferred embodiment, at least one grounded metal field plate is provided above the drain drift region.
[0012] This invention also discloses a method for manufacturing an LDMOS device, comprising the following steps: S01: An epitaxial layer is formed by epitaxial growth on the substrate surface; S02: An active region is formed on the epitaxial layer, which includes a source region, a gate region, and a drain region; S03: Low-concentration ion implantation is performed on the drain region to form a drain drift region; high-concentration ion implantation is performed on the drain region to form a high-concentration ion implantation region; S04: A metal layer is deposited on the surface of the epitaxial layer in the high-concentration ion implantation region by physical vapor deposition, and then subjected to a second thermal annealing process to finally form a low-resistivity metal silicide on the surface of the active region to form an ohmic contact metal layer; the ohmic contact metal layer is connected to the upper metal layer through vias. S05: A drain field plate is placed on the surface of the epitaxial layer in the drain drift region.
[0013] In a preferred embodiment, the drain field plate is connected to the ohmic contact metal layer, and the drain field plate is obtained by extending a certain length from the ohmic contact metal layer toward the drain drift region.
[0014] In a preferred embodiment, the method for fabricating the ohmic contact metal layer and the drain field plate includes: A silicon dioxide dielectric is deposited on the surface of the epitaxial layer, and then photoresist is applied. Photolithography is performed using a mask to remove the photoresist in the area where ohmic contact metal needs to be set. Dry etching and wet etching are used to remove the silicon dioxide layer in the area not covered by photoresist, exposing the active semiconductor region where self-aligned silicides need to be formed. A layer of Ti and TiN is deposited by physical vapor deposition. Nitrogen gas is introduced at a temperature of 450~750℃ to cause the active region semiconductor silicon and Ti to react and form a high-resistivity Ti2Si metal silicide, which is then rapidly thermally annealed. TiN is removed, and then the mixture is placed in an environment of 750~950℃ and nitrogen is introduced for a second thermal annealing, so that the high-resistivity Ti2Si is transformed into the low-resistivity TiSi2.
[0015] In a preferred embodiment, the length of the drain field plate is less than 1 μm.
[0016] Compared with existing solutions, the advantages of this invention are: 1. A drain field plate is placed on the surface of the epitaxial layer in the drain drift region. This creates a transverse electric field component within the drift region that is opposite in direction to the original electric field. Because the electric fields cancel each other out, the peak electric field near the boundary of the high-concentration ion implantation region in the drain drift region is effectively reduced, thus improving the breakdown voltage of the product chip. Since this drain field plate is directly placed on the silicon semiconductor, its length does not need to be very long to achieve good electric field suppression, and it does not cause an increase in source-drain parasitic capacitance.
[0017] 2. The drain field plate of the present invention can be obtained by extending the ohmic contact metal layer of the original high-concentration ion implantation region of the drain to the drain drift region, without adding additional processes or increasing costs excessively. This makes the product more competitive. Attached Figure Description
[0018] The present invention will be further described below with reference to the accompanying drawings and embodiments: Figure 1 This is a schematic diagram of the structure of an LDMOS device according to an embodiment of the present invention; Figure 2 This is a flowchart of the manufacturing method of the LDMOS device of the present invention. Detailed Implementation
[0019] The above-described solution will be further illustrated below with reference to specific embodiments. It should be understood that these embodiments are for illustrative purposes only and are not intended to limit the scope of the invention. The implementation conditions used in the embodiments may be further adjusted according to the conditions of specific manufacturers, and the implementation conditions not specified are generally those in routine experiments.
[0020] Example
[0021] like Figure 1As shown, an LDMOS device includes a substrate 100 and an epitaxial layer 101. An active region is disposed on the epitaxial layer 101, including a source region 102, a gate region 106, and a drain region. A drain drift region 103 and a high-concentration ion implantation region 104 are disposed in the drain region. An ohmic contact metal layer 105 is disposed on the surface of the epitaxial layer 101 within the high-concentration ion implantation region 104. The ohmic contact metal layer 105 is connected to an upper metal layer 111 through a via 110. The upper metal layer 111 is connected to a drain metal pad. A drain field plate 1051 is disposed on the surface of the epitaxial layer 101 in the drain drift region 103.
[0022] The drain field plate 1051 is directly disposed on the surface of the epitaxial layer (semiconductor silicon surface) without a dielectric layer in between. Because the metal is directly disposed on the semiconductor silicon surface, its electric field suppression is significant, and the length of the field plate can be reduced. This improves the breakdown voltage of the device, and because the length of the drain metal field plate is not very long, it has little impact on the source-drain parasitic capacitance.
[0023] The substrate 100 is made of single-crystal or polycrystalline silicon, and the epitaxial layer 101 is made of the same material as the substrate 100, or it can be made of different materials.
[0024] The drain drift region 103 is implanted with a low concentration of ions, typically below 3E12 cm⁻¹. -3 .
[0025] The high-concentration ion implantation region 104 is implanted with a high concentration of ions, typically exceeding 1E15 cm⁻¹. -3 .
[0026] A preferred embodiment, such as Figure 1 As shown, the depth and length of the high-concentration ion implantation region 104 are both smaller than those of the drain drift region 103.
[0027] In a preferred embodiment, the drain drift region 103 surrounds the high-concentration ion implantation region 104.
[0028] In a preferred embodiment, the drain field plate 1051 is connected to the ohmic contact metal layer 105, and the drain field plate 1051 is obtained by extending a certain length from the ohmic contact metal layer 105 to the drain drift region 103.
[0029] The ion concentration in the drain drift region 103 is relatively low, and the ohmic metal layer above it has a field plate effect. By adjusting the appropriate drain field plate length, a transverse electric field component opposite to the original electric field direction will be formed inside this drift region. Since the electric fields cancel each other out, the peak electric field at the boundary between the low-concentration ion implantation region (drain drift region 103) and the high-concentration ion implantation region 104 is effectively reduced, thereby improving the breakdown voltage of the product chip.
[0030] In a preferred embodiment, the length L of the drain field plate 1051 needs to be determined by simulation or other means, and is generally less than 1 μm. Since the drain field plate 1051 can reduce the peak electric field at the junction of high and low concentrations at the drain, thereby improving the breakdown voltage of the device, and because the length of the drain metal field plate is not very long, it has little impact on the source-drain parasitic capacitance.
[0031] Specifically, a dielectric layer 112 is also provided on the epitaxial layer 101. The dielectric layer 112 is generally composed of oxide. The gate region 106, the via 110 and the upper metal layer 111 are all disposed on the dielectric layer 112.
[0032] Preferably, the dielectric layer 112 above the drain drift region 103 is provided with at least one grounded metal field plate. Figure 1 The device is equipped with three metal field plates, which are, from bottom to top, the first metal field plate 107, the second metal field plate 108, and the third metal field plate 109.
[0033] In another embodiment, such as Figure 2 As shown, a method for manufacturing an LDMOS device includes the following steps: S01: An epitaxial layer is formed by epitaxial growth on the substrate surface; S02: An active region is formed on the epitaxial layer, which includes a source region, a gate region, and a drain region; S03: Low-concentration ion implantation is performed on the drain region to form a drain drift region; high-concentration ion implantation is performed on the drain region to form a high-concentration ion implantation region; S04: A metal layer is deposited on the surface of the epitaxial layer in the high-concentration ion implantation region by physical vapor deposition, and then subjected to a second thermal annealing process to finally form a low-resistivity metal silicide on the surface of the active region to form an ohmic contact metal layer; the ohmic contact metal layer is connected to the upper metal layer through vias. S05: A drain field plate is placed on the surface of the epitaxial layer in the drain drift region.
[0034] In a preferred embodiment, the drain field plate is connected to the ohmic contact metal layer, and the drain field plate is obtained by extending a certain length from the ohmic contact metal layer toward the drain drift region.
[0035] Specifically, the drain field plate and the ohmic contact metal layer are generated using a standard CMOS self-aligned silicide process. Typically, a self-aligned block (SAB) silicide barrier layer is first used to cover the areas where the ohmic contact metal does not need to be grown with a protective oxide layer. Then, a metal layer (Ti, Co, NiPt, etc.) is deposited in the areas where the ohmic contact metal needs to be grown using physical vapor deposition. This is followed by two rapid thermal annealing processes and one selective wet etching process. Finally, a metal silicide is formed on the surface of the epitaxial layer where the ohmic contact needs to be grown.
[0036] The detailed steps are as follows: First, a silicon dioxide dielectric layer is deposited on the surface of the epitaxial layer, then photoresist is applied. Using a photomask, the photoresist in the areas where ohmic contact metal needs to be set is removed. A combination of dry and wet etching is used to remove the silicon dioxide layer in areas not covered by the photoresist, exposing the active semiconductor region where salicide will form. Then, a layer of Ti and TiN is deposited using physical vapor deposition. Nitrogen gas is introduced at a high temperature of approximately 450~750℃ to cause the active semiconductor silicon and Ti to react, forming a high-resistivity Ti2Si metal silicide, which is then rapidly thermally annealed. The TiN is then removed, and the mixture is placed in an environment of 750~950℃ with nitrogen gas for a second thermal annealing, transforming the high-resistivity Ti2Si into a low-resistivity TiSi2.
[0037] It utilizes existing chip manufacturing processes. Compared to existing methods such as adjusting epitaxial density and thickness, it reduces development costs and shortens the R&D cycle. Since the basic device process remains largely unchanged, the chip's characteristics will not change significantly, ensuring better device performance.
[0038] It should be understood that the specific embodiments described above are merely illustrative or explanatory of the principles of the invention and do not constitute a limitation thereof. Therefore, any modifications, equivalent substitutions, improvements, etc., made without departing from the spirit and scope of the invention should be included within the protection scope of the invention. Furthermore, the appended claims are intended to cover all variations and modifications falling within the scope and boundaries of the appended claims, or equivalent forms of such scope and boundaries.
Claims
1. An LDMOS device, comprising a substrate and an epitaxial layer, an active region disposed on the epitaxial layer, the active region including a source region, a gate region and a drain region, and a drain drift region and a high-concentration ion implantation region disposed in the drain region, characterized in that, An ohmic contact metal layer is disposed on the surface of the epitaxial layer in the high-concentration ion implantation region. The ohmic contact metal layer is connected to the upper metal layer through vias. A drain field plate is disposed on the surface of the epitaxial layer in the drain drift region.
2. The LDMOS device according to claim 1, characterized in that, The depth and length of the high-concentration ion implantation region are both smaller than those of the drain drift region.
3. The LDMOS device according to claim 2, characterized in that, The drain drift region surrounds the high-concentration ion implantation region.
4. The LDMOS device according to claim 1, characterized in that, The drain field plate is connected to the ohmic contact metal layer, and the drain field plate is obtained by extending a certain length from the ohmic contact metal layer into the drain drift region.
5. The LDMOS device according to claim 1, characterized in that, The length of the drain field plate is less than 1 μm.
6. The LDMOS device according to claim 1, characterized in that, At least one grounded metal field plate is provided above the drain drift region.
7. A method for manufacturing an LDMOS device, characterized in that, Includes the following steps: S01: An epitaxial layer is formed by epitaxial growth on the substrate surface; S02: An active region is formed on the epitaxial layer, which includes a source region, a gate region, and a drain region; S03: Low-concentration ion implantation is performed on the drain region to form a drain drift region; high-concentration ion implantation is performed on the drain region to form a high-concentration ion implantation region; S04: A metal layer is deposited on the surface of the epitaxial layer in the high-concentration ion implantation region by physical vapor deposition, and then subjected to a second thermal annealing process to finally form a low-resistivity metal silicide on the surface of the active region to form an ohmic contact metal layer; the ohmic contact metal layer is connected to the upper metal layer through vias. S05: A drain field plate is placed on the surface of the epitaxial layer in the drain drift region.
8. The method for manufacturing an LDMOS device according to claim 7, characterized in that, The drain field plate is connected to the ohmic contact metal layer, and the drain field plate is obtained by extending a certain length from the ohmic contact metal layer into the drain drift region.
9. The method for manufacturing an LDMOS device according to claim 8, characterized in that, The method for fabricating the ohmic contact metal layer and the drain field plate includes: A silicon dioxide dielectric is deposited on the surface of the epitaxial layer, and then photoresist is applied. Photolithography is performed using a mask to remove the photoresist in the area where ohmic contact metal needs to be set. Dry etching and wet etching are used to remove the silicon dioxide layer in the area not covered by photoresist, exposing the active semiconductor region where self-aligned silicides need to be formed. A layer of Ti and TiN is deposited by physical vapor deposition. Nitrogen gas is introduced at a temperature of 450~750℃ to cause the active region semiconductor silicon and Ti to react and form a high-resistivity Ti2Si metal silicide, which is then rapidly thermally annealed. TiN is removed, and then the mixture is placed in an environment of 750~950℃ and nitrogen is introduced for a second thermal annealing, so that the high-resistivity Ti2Si is transformed into the low-resistivity TiSi2.
10. The method for manufacturing an LDMOS device according to claim 7, characterized in that, The length of the drain field plate is less than 1 μm.