Graphics processor, ray tracing method, electronic device, and computer storage medium

Abstract

The application discloses a graphics processor, a ray tracing method, an electronic device and a computer storage medium. The graphics processor comprises a ray distribution assembly unit, which determines a shader type and an SBT record index corresponding to a ray according to hit information output by a ray tracing core, allocates an SBT slot to rays with the same SBT record index and shader type, and initiates a prefetch request to a ray thread constructor at a moment before a thread start trigger condition of the SBT slot is met; the ray thread constructor determines a storage address of a shader record corresponding to the SBT slot in response to the prefetch request, reads, from a storage unit, shader record data corresponding to the SBT slot based on the storage address in a case where the SBT cache area is not written with the shader record data corresponding to the SBT slot, and writes the shader record data into the SBT cache area. According to the embodiment of the application, the thread start efficiency can be improved.

Description

Technical Field

[0001] This application belongs to the field of graphics processing technology, and in particular relates to a graphics processor, a ray tracing method, an electronic device, and a computer storage medium. Background Technology

[0002] Ray tracing is a rendering technique that generates realistic images by simulating the propagation path of light rays in a 3D scene. Unlike traditional rasterization-based rendering pipelines, ray tracing systems cannot know in advance what geometry each ray will intersect with or which shader should be executed during rendering. To address this, the ray tracing system of a Graphics Processing Unit (GPU) introduces a Shader Binding Table (SBT) data structure.

[0003] In a ray tracing system, the shader record (SBT) is stored in an external memory unit and consists of several shader records. When a ray hits the geometry, the system calculates the corresponding shader record index based on the hit information, and then reads the shader record data to start the corresponding shader.

[0004] In related technologies, when the ray thread constructor in a ray tracing system is notified to start the thread, it looks up the corresponding shader record data in the SBT cache. If a cache miss occurs, the data needs to be read from external storage, which introduces a delay, hindering thread startup, reducing thread startup efficiency, and consequently reducing the GPU's ray tracing efficiency. Summary of the Invention

[0005] This application provides a graphics processor, a ray tracing method, an electronic device, and a computer storage medium, which can improve the thread startup efficiency of a ray tracing system, thereby improving the ray tracing efficiency of the GPU.

[0006] In a first aspect, embodiments of this application provide a graphics processor, including: a ray tracing system and a storage unit; The storage unit is used to store the shader binding table (SBT). The ray tracing system includes a ray tracing core, a ray distribution assembly unit, and a ray thread constructor; The ray thread constructor includes an SBT buffer; The ray tracing core is configured to perform intersection tests between rays and scene geometry and output hit information to the ray distribution assembly unit; the hit information is the intersection point information obtained in the intersection test; The ray distribution assembly unit is configured to determine the SBT record index and shader type corresponding to the ray based on the hit information, and allocate an SBT slot for rays with the same SBT record index and shader type; and send a prefetch request to the ray thread constructor before the thread start triggering condition of the SBT slot is met. The ray thread constructor is configured to, in response to a prefetch request, determine the storage address of the shader record corresponding to the SBT slot; if the shader record data corresponding to the SBT slot has not been written to the SBT buffer, it reads the shader record data corresponding to the SBT slot from the storage unit based on the storage address and writes the shader record data to the SBT buffer.

[0007] Secondly, embodiments of this application provide a ray tracing method for a graphics processor. The graphics processor includes a ray tracing system and a storage unit. The storage unit stores ray tracing blocks (SBTs). The ray tracing system includes a ray tracing core, a ray distribution and assembly unit, and a ray thread constructor. The ray thread constructor includes an SBT cache. The method is applied to the ray tracing system and includes: The ray tracing core performs intersection tests between rays and scene geometry, and outputs hit information to the ray distribution assembly unit; the hit information is the intersection point information obtained in the intersection test. The ray distribution assembly unit determines the SBT record index and shader type corresponding to the ray based on the hit information, and allocates an SBT slot for rays with the same SBT record index and shader type; before the thread start triggering condition of the SBT slot is met, a prefetch request is sent to the ray thread constructor. In response to a prefetch request, the ray thread constructor determines the storage address of the shader record corresponding to the SBT slot. If the shader record data corresponding to the SBT slot has not been written to the SBT cache, the shader record data corresponding to the SBT slot is read from the storage unit based on the storage address and written to the SBT cache.

[0008] Thirdly, embodiments of this application provide an electronic device, which includes: a graphics processor as described in the first aspect.

[0009] Fourthly, embodiments of this application provide a computer-readable storage medium storing computer program instructions, which, when executed by a processor, implement the steps of the ray tracing method of the graphics processor as described in the second aspect.

[0010] In this embodiment, the ray distribution and assembly unit initiates a prefetch request to the ray thread constructor before the thread start triggering condition of the SBT slot is met. This allows the ray thread constructor to read the shader record data corresponding to the slot from the external storage unit in advance and write it into the SBT buffer. Compared to conventional technology, where the ray thread constructor only reads the shader record data from the external storage unit after receiving the thread start notification, this embodiment allows for the prefetching of shader record data from the external storage unit within the ray assembly time window between receiving the first ray from the slot and meeting the thread start triggering condition. This time window can completely or partially cover the read latency of the external storage unit, thereby shortening the thread start waiting time and improving thread start efficiency and ray tracing efficiency. Attached Figure Description

[0011] To more clearly illustrate the technical solutions of the embodiments of this application, the accompanying drawings used in the embodiments of this application will be briefly introduced below. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0012] Figure 1 This is a schematic diagram of a conventional ray tracing system pipeline provided in this application; Figure 2 This is a schematic diagram of the pipeline of a ray tracing system in a graphics processor provided in some embodiments of this application; Figure 3 This is a flowchart illustrating a ray tracing method for a graphics processor provided in some embodiments of this application; Figure 4 These are schematic diagrams of the structure of electronic devices provided in some embodiments of this application. Detailed Implementation

[0013] The features and exemplary embodiments of various aspects of this application will be described in detail below. To make the objectives, technical solutions, and advantages of this application clearer, the application will be further described in detail below with reference to the accompanying drawings and specific embodiments. It should be understood that the specific embodiments described herein are only intended to explain this application and not to limit it. For those skilled in the art, this application can be implemented without some of these specific details. The following description of the embodiments is merely to provide a better understanding of this application by illustrating examples.

[0014] It should be noted that, in this document, relational terms such as "first" and "second" are used merely to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising..." does not exclude the presence of additional identical elements in the process, method, article, or apparatus that includes said element.

[0015] Before providing a further detailed description of the embodiments of this application, the nouns and terms involved in the embodiments of this application will be explained, and the nouns and terms involved in the embodiments of this application shall be interpreted as follows.

[0016] Graphics Processing Unit (GPU): A processor specifically designed for parallel graphics rendering and general-purpose computing.

[0017] Shader Binding Table (SBT): An array stored in GPU memory. Each entry in the SBT, representing a Shader Record, corresponds to shader information for a specific hit condition. When a ray hits an object, the SBT quickly locates the shader to be executed.

[0018] Shader: A small program that runs on the GPU and is responsible for calculating pixel color, lighting, shadows, etc.

[0019] The Shader Record is a fixed-size entry in the Shader Bitmap (SBT). It mainly contains two parts: the shader identifier and the Local Root Argument.

[0020] Shader Identifier: Information that uniquely identifies a shader. At the hardware level, it is usually a handle or address pointing to the shader's memory base address, such as the shader base address.

[0021] Shader Base: The shader identifier from a hardware perspective, used to locate the shader entry point when a thread starts.

[0022] Local Root Argument: Resource parameters passed to the shader, including texture addresses, pointers to constant buffers, or small data blocks.

[0023] SBT record index (Sbtid): This is the sequence number of the Shader Record, used to locate the corresponding ShaderRecord in the SBT.

[0024] Anyhit Shader: A shader type that is called when a ray intersects a transparent / semi-transparent object to determine whether a true hit has occurred.

[0025] Intersection Shader: A shader type used for custom geometry ray intersection calculations, replacing the default triangle intersection.

[0026] Closest Hit Shader: A shader type that is called when a ray finds the nearest intersection point and is responsible for calculating the color, lighting, etc. of that point.

[0027] Miss Shader: A shader type that is invoked when a ray does not hit any geometry, and typically returns the background color or the environment map color.

[0028] Ray Index: Used to distinguish rays for different purposes, such as primary rays, shadow rays, reflected rays, and refracted rays. Different ray types may be mapped to different shaders in SBT.

[0029] Instance Index: A unique identifier for multiple geometric instances in the scene. This value is returned when a ray hits an instance, used to distinguish between them.

[0030] Geometry Index: An instance may contain multiple geometries, and this index is used to identify which specific geometry was hit.

[0031] Cache: Used to temporarily store recently accessed data.

[0032] Cache line: The smallest unit of data exchanged between the cache and memory.

[0033] Hit / miss test: Used to check if the required data is already in the cache. A hit result indicates that the data is present and can be used immediately; a miss result indicates that the data is missing.

[0034] Flush: This refers to forcibly writing back or discarding data in the cache and clearing the cache lines.

[0035] Cache line address (Line Addr): Identifies which address in the memory cell needs to be read into the cache.

[0036] Stride: refers to the fixed byte size of each Shader Record in SBT, that is, the size of each ShaderRecord.

[0037] SBT base address (Base Va): This refers to the starting address of the SBT in the GPU virtual address space. It is stored in the Sbt Base register.

[0038] Virtual address (Va Address): refers to the logical address used by the GPU / CPU, which is translated into a physical address to access video memory or system memory.

[0039] SBT slot: A logical storage unit in the light distribution assembly unit, used to temporarily store and count the same type of light rays.

[0040] Thread: The smallest scheduling unit in a GPU that executes a shader. One thread can process all the rays in a slot.

[0041] Before providing a more detailed description of the embodiments of this application, relevant background technology will be introduced for ease of understanding.

[0042] Traditional GPU rendering pipelines use statically bound shaders, meaning that the shader is bound only when the desired image is known in advance. However, in ray tracing systems, when a ray is emitted, it has no idea what it will hit—it might hit metal, glass, or nothing at all. Therefore, the corresponding shader cannot be predicted. SBT (Synchronous Lookup Table) provides a real-time lookup table for these unpredictable dynamic encounters, ensuring that the correct shader calculation is triggered on every hit.

[0043] The Shader Bitmap (SBT) is stored in external memory units of the ray tracing system. Essentially, an SBT is a buffer; an SBT consists of a series of shader records, each of the same size. A shader record comprises a shader identifier and a local root parameter. The shader identifier identifies shader information such as the shader base address, while the local root parameter identifies the resource information required to run the shader.

[0044] See Figure 1 This is a schematic diagram of the pipeline of a ray tracing system in related technologies, such as... Figure 1As shown, the ray distribution and assembly unit is responsible for collecting and distributing hit information from the ray tracing core. This hit information includes the shader type corresponding to the ray, as well as instance index, geometry index, and ray type. Based on this hit information, the shader type and SBT record index corresponding to the ray can be determined. Different SBT slots are allocated for different SBT record indices and shader types. These SBT slots store the SBT record index, shader type, and ray, and the number of rays is accumulated. When the number of rays in an SBT slot reaches a certain level, the ray thread constructor is notified to start a thread for the shader corresponding to that SBT slot. The ray thread constructor internally has an SBT cache to cache shader identifier data for different SBT record indices and shader types. Before starting a thread, the ray constructor needs to send the shader base address to the scheduling execution core; therefore, it performs a hit check on the SBT cache. When data is missing from the SBT cache, the shader base address needs to be read back from external storage. Reading data back from external storage requires a long latency, which reduces the efficiency of the ray thread constructor in starting threads, thereby reducing the ray tracing efficiency of the GPU.

[0045] In view of this, in order to improve the efficiency of the ray thread constructor in starting the thread, and thus improve the efficiency of the GPU ray tracing system, embodiments of this application provide a graphics processor, a ray tracing method, an electronic device, and a computer storage medium. The aim is to use prefetching technology to read back the shader base address from an external memory unit before the thread starts, thereby shortening the thread startup time, improving the efficiency of the ray thread constructor in starting the thread, and thus improving ray tracing efficiency.

[0046] See Figure 2 This is a schematic diagram of the pipeline of a ray tracing system in an image processor provided in an embodiment of this application, as shown below. Figure 2 As shown, the image processor includes a ray tracing system and a storage unit.

[0047] The storage unit is located outside the ray tracing system and serves as the external storage unit for storing SBTs.

[0048] In some embodiments of this application, the storage unit may be the video memory of a GPU.

[0049] The ray tracing system comprises a ray tracing core, a ray distribution and assembly unit, a ray thread constructor, and a scheduling and execution core. The ray thread constructor includes an SBT cache.

[0050] The SBT cache is used to cache shader identifier data corresponding to different SBT record indices and shader types. The shader identifier data includes, but is not limited to, shader base addresses.

[0051] The ray tracing core is configured to perform intersection tests between rays and scene geometry and output hit information to the ray distribution assembly unit. The hit information consists of intersection point information obtained during the intersection test. This intersection point information includes various data related to the intersection points determined by the intersection test, where an intersection point refers to the location where a ray intersects with the surface of a geometric object in the scene. Specifically, the hit information may include, but is not limited to, ray information, intersection object information, and the type of shader that should be executed. The shader type can be any hit shader, an intersection shader, a recently hit shader, or a missed shader. The intersection object information includes an instance index and a geometry index, where the instance index identifies which geometric instance the ray hit, and the geometry index identifies which geometry within that instance was hit. The ray information includes the ray type, which identifies the type of the current ray.

[0052] The ray distribution assembly unit is configured to determine the shader type and SBT record index corresponding to the ray based on the hit information output by the ray tracing core, and allocate an SBT slot for rays with the same SBT record index and shader type; for each SBT slot, before the thread start triggering condition of the SBT slot is met, a prefetch request is sent to the ray thread constructor to request the ray thread constructor to write the shader record data corresponding to the SBT slot into the SBT buffer in advance.

[0053] The scheduling execution core is a streaming multiprocessor of the graphics processor, which is configured to execute the shader corresponding to the shader identifier to process the rays in the SBT slot.

[0054] In practical applications, when an SBT slot meets the set thread start triggering conditions, the ray distribution and assembly unit notifies the ray thread constructor to start the thread, so as to schedule the shader corresponding to the SBT slot to process the rays in the SBT slot. Therefore, after receiving the thread start notification, the ray thread constructor needs to read the shader identifier from the shader record data corresponding to the SBT slot in the SBT buffer and send the shader identifier to the scheduling execution core to start the thread. In view of this, in order to reduce the reduction in thread start efficiency caused by data loss in the SBT buffer when starting the thread, in this embodiment, a prefetch request is sent to the ray thread constructor before the SBT slot meets the thread start triggering conditions, so as to request the ray thread constructor to write the shader record data corresponding to the SBT slot into the SBT buffer in advance, thereby reducing the latency caused by data loss in the SBT buffer.

[0055] Specifically, the ray thread constructor is configured to determine the storage address of the shader record corresponding to the SBT slot in response to a prefetch request; if the shader record data corresponding to the SBT slot has not been written to the SBT cache, the shader record data corresponding to the SBT slot is read from the storage unit based on the aforementioned storage address, and then written to the SBT cache. This reduces the likelihood of data loss in the SBT cache during thread startup.

[0056] In this embodiment, a novel SBT cache data prefetching mechanism is introduced. Before the SBT slot meets the thread start triggering condition, a prefetch request is sent to the ray thread constructor. This allows the ray thread constructor to read the shader record data corresponding to the slot from the external storage unit in advance and write it into the SBT cache. Compared to the conventional technology, where the ray thread constructor only reads the shader record data from the external storage unit after receiving the thread start notification, this embodiment utilizes the ray assembly time window from receiving the first ray from the SBT slot to meeting the thread start triggering condition to prefetch the shader record data from the external storage unit. This time window completely or partially covers the read latency of the external storage unit, thereby shortening the thread start waiting time and improving thread start efficiency and ray tracing efficiency.

[0057] In some embodiments of this application, the time before the thread start triggering condition of the SBT slot is met can be any time within the ray assembly time window of the SBT slot. Based on this, for each SBT slot, the ray distribution and assembly unit can initiate a prefetch request to the ray thread constructor at any time within the ray assembly time window of that slot, in order to request the ray thread constructor to pre-write the shader record data corresponding to that slot into the SBT buffer.

[0058] Optionally, to maximize the coverage of external storage read latency within the ray assembly time window and increase the probability that the shader record data corresponding to the SBT slot has been written to the SBT cache when the thread starts, the time before the thread start trigger condition of the SBT slot is met can be configured to be the moment when the SBT slot receives the first ray. Specifically, the ray distribution and assembly unit can be configured to initiate a prefetch request to the ray thread constructor when the SBT slot receives the first ray. This fully utilizes the ray assembly time from the arrival of the first ray to the slot meeting the thread start condition, allowing ample time for the prefetched data to return from external storage, increasing the probability of cache hits when the thread starts. Thus, when the slot meets the thread start condition and needs to start a thread, the ray thread constructor can directly read the shader identifier corresponding to that slot from the SBT cache without waiting for a response from external storage, shortening the thread start waiting time. This allows the ray thread constructor to start more threads per unit time, reducing the idle ratio of the scheduling execution core and improving the overall ray processing capability of the ray tracing system.

[0059] In some embodiments of this application, the ray thread constructor can determine whether the shader record data corresponding to the SBT slot has been written to the SBT cache by performing a hit check in the SBT cache. Specifically, the ray thread constructor can be configured to perform a hit check on the shader record data in the SBT cache based on the storage address before reading the shader record data corresponding to the SBT slot from the SBT of the storage unit based on the storage address; if the detection result is missing, it is determined that the shader record data corresponding to the SBT slot has not been written to the SBT cache, and thus the shader record data corresponding to the SBT slot is read from the SBT of the storage unit based on the storage address.

[0060] In addition, if the detection result is a hit, it is determined that the shader record data corresponding to the SBT slot has been written to the SBT cache. Therefore, there is no need for the storage unit to read the shader record data corresponding to the SBT slot. When the thread starts, the shader record data corresponding to the SBT slot can be read directly from the SBT cache.

[0061] In some embodiments of this application, the ray distribution and assembly unit may include multiple SBT slots. When one SBT slot needs to prefetch data, other SBT slots may need to start threads. To avoid interference between data prefetching and thread startup, a prefetch interface can be provided between the ray thread constructor and the ray distribution and assembly unit. This prefetch interface is used to transmit prefetch requests. Based on this, the ray distribution and assembly unit initiates a prefetch request to the ray thread constructor through this prefetch interface. In this way, the prefetch request and thread startup notification are decoupled in time, allowing prefetching to be initiated independently and improving the parallelism between units within the ray tracing system.

[0062] In some embodiments of this application, the prefetch request initiated by the ray distribution assembly unit to the ray thread constructor carries the SBT record index of the SBT slot. The ray thread constructor is also configured to determine the storage address of the shader record corresponding to the SBT slot based on the SBT record index, the base address of the SBT, and the fixed size of each shader record. This storage address points to the starting position of the shader record in the storage unit. The SBT record index indicates the sequence number of the shader record corresponding to the SBT slot within the SBT. The SBT base address refers to the starting address of the SBT in the GPU virtual address space. This base address can be configured by the driver and stored in a register, and the ray thread constructor can directly read the SBT base address from the register. The shader record size identifies the number of bytes occupied by each shader record in the SBT. Each shader record has a consistent size, and the size of the shader record remains unchanged throughout the entire ray tracing pipeline's lifecycle. The shader record size can be determined by the driver based on the actual layout of the shader records during ray tracing pipeline creation and stored in a register. The ray thread constructor can directly obtain this value by reading the register.

[0063] The ray thread constructor can calculate the storage address of the shader record corresponding to the SBT slot based on the following formula (1).

[0064]

[0065] In the above formula (1), Shader Record Va represents the storage address of the shader record, Base Va represents the SBT base address, Sbtid represents the SBT record index, and Stride represents the step size, which is the fixed size of the shader record.

[0066] In some embodiments of this application, when the ray thread constructor reads shader record data corresponding to an SBT slot from a storage unit based on a storage address, it can generate a read request carrying the storage address, cache line address, and shader type of the target shader record, and send the read request to an external storage unit via an internal bus. The target shader record is the shader record corresponding to the SBT slot. The SBT cache is organized in units of cache lines. The cache line address identifies the index or tag of the target cache line to be filled by the read request, and its function is to identify the write position of the data returned by the storage unit in the SBT cache. The cache line address can be the cache line number in the SBT cache where the shader record data to be read is expected to be stored, calculated based on the aforementioned storage address, or the cache line address can be the starting alignment address of the shader record data to be read in the storage unit. The shader type can be used by the storage unit to distinguish data for different purposes and can also be used to update the metadata of the cache line.

[0067] Upon receiving a read request, the storage unit reads a contiguous block of data from the specified address based on the storage address of the target shader record. The length of the read data can be the size of one cache line. The read raw data is used as shader record data. The shader record data contains the shader identifier and a portion of any possible local root parameters. The storage unit returns the read shader record data and the cache line address to the ray thread constructor. The cache line address returned by the storage unit is the same as the cache line address carried in the read request, and is used to identify the write position of the returned shader record data in the SBT cache.

[0068] After receiving the data returned by the storage unit, the SBT cache can locate the specific cache line based on the returned cache line address, write the returned shader record data into the data storage part of the cache line, and update the tag and validity bit of the cache line to mark the cache line as valid.

[0069] In some embodiments of this application, in addition to data and tags, the cache line may also include shader type tags. Therefore, after writing shader record data into the cache line, the shader type in the read request can also be written into the metadata area of ​​the cache line to accelerate the matching of shader types during subsequent hit detection.

[0070] In some embodiments of this application, the thread initiation triggering condition may include at least one of the following: The number of light rays in the SBT slot has reached the set threshold; The SBT slot has been replaced; The SBT slot has been refreshed.

[0071] In this embodiment of the application, the threshold is set to a value greater than 1.

[0072] In some embodiments of this application, the GPU scheduler distributes instructions in units of thread bundles. If only some threads in a thread bundle are actually working when a thread bundle is started, the remaining threads in the bundle will be idle, resulting in a waste of computing resources. Therefore, in order to fully utilize the parallel processing capabilities of the GPU, a threshold can be set to be consistent with the GPU hardware thread bundle size to improve resource utilization.

[0073] Based on the graphics processor provided in the above embodiments, this application also provides a specific implementation of a ray tracing method for the graphics processor, which is applied to the graphics processor provided in the embodiments of this application.

[0074] See Figure 3 This is a flowchart illustrating the ray tracing method for a graphics processor provided in an embodiment of this application. Figure 3 As shown, the method includes the following steps 310-330.

[0075] Step 310. Perform an intersection test between the ray and the scene geometry using the ray tracing core, and output the hit information to the ray distribution assembly unit.

[0076] Step 320. Calculate the SBT record index based on the hit information using the ray distribution assembly unit, and allocate an SBT slot for rays with the same SBT record index and shader type; before the thread start triggering condition of the SBT slot is met, send a prefetch request to the ray thread constructor. Step 330. In response to the prefetch request, the ray thread constructor determines the storage address of the shader record corresponding to the SBT slot. If the shader record data corresponding to the SBT slot has not been written to the SBT cache, the shader record data corresponding to the SBT slot is read from the storage unit based on the storage address and written to the SBT cache.

[0077] In this embodiment, the ray distribution and assembly unit initiates a prefetch request to the ray thread constructor before the SBT slot meets the thread start triggering condition. This allows the ray thread constructor to read the shader record data corresponding to the slot from the external storage unit in advance and write it into the SBT buffer. Compared to conventional technology, where the ray thread constructor only reads the shader record data from the external storage unit after receiving the thread start notification, this embodiment utilizes the ray assembly time window between receiving the first ray from the slot and meeting the thread start triggering condition to prefetch the shader record data from the external storage unit. This time window completely or partially covers the read latency of the external storage unit, thereby shortening the thread start waiting time and improving thread start efficiency and ray tracing efficiency.

[0078] In some embodiments of this application, the time before the thread start triggering condition of the SBT slot is met is the time when the SBT slot receives the first light beam.

[0079] In some embodiments of this application, the method further includes: Before reading the shader record data corresponding to the SBT slot from the storage unit based on the storage address, a hit check is performed on the shader record data in the SBT cache based on the storage address; if the detection result is missing, it is determined that the shader record data corresponding to the SBT slot has not been written to the SBT cache.

[0080] In some embodiments of this application, a prefetch interface is provided between the ray thread constructor and the ray distribution assembly unit, which initiates a prefetch request to the ray thread constructor, including: A prefetch request is sent to the ray thread constructor via the prefetch interface.

[0081] In some embodiments of this application, the prefetch request carries an SBT record index; in response to the prefetch request, determining the storage address of the shader record corresponding to the SBT slot includes: Based on the SBT record index, the base address of the SBT, and the fixed size of each shader record, the storage address of the shader record corresponding to the SBT slot is determined.

[0082] In some embodiments of this application, the ray tracing system further includes a scheduling execution core; the method further includes: The ray distribution assembly unit notifies the ray thread constructor to start the thread when the SBT slot meets the thread start triggering conditions. The ray thread constructor reads the shader identifier from the shader record data in the SBT buffer and sends the shader identifier to the scheduling execution core to start the thread.

[0083] In some embodiments of this application, the thread initiation triggering condition includes at least one of the following: The number of light rays in the SBT slot has reached the set threshold; The SBT slot has been replaced; The SBT slot has been refreshed.

[0084] Figure 4 A schematic diagram of the hardware structure of the electronic device provided in an embodiment of this application is shown.

[0085] Electronic device 400 may include processor 401 and memory 402 storing computer program instructions.

[0086] Specifically, the processor 401 may include the graphics processor, central processing unit (CPU), or application specific integrated circuit (ASIC) provided in the embodiments of this application, or one or more integrated circuits that can be configured to implement the embodiments of this application.

[0087] Memory 402 may include mass storage for data or instructions. For example, and not limitingly, memory 402 may include a hard disk drive (HDD), floppy disk drive, flash memory, optical disk, magneto-optical disk, magnetic tape, or Universal Serial Bus (USB) drive, or a combination of two or more of these. Where appropriate, memory 402 may include removable or non-removable (or fixed) media. Where appropriate, memory 402 may be internal or external to electronic device 400. In a particular embodiment, memory 402 is non-volatile solid-state memory. Memory 402 may include read-only memory (ROM), random access memory (RAM), disk storage media device, optical storage media device, flash memory device, electrical, optical, or other physical / tangible memory storage device. Therefore, typically, memory 402 includes one or more tangible (non-transitory) computer-readable storage media (e.g., memory devices) encoded with software including computer-executable instructions, and when the software is executed (e.g., by one or more processors), it can perform the operations described in the ray tracing method of any of the graphics processors in the above embodiments.

[0088] The processor 401 implements any of the ray tracing methods of the graphics processor in the above embodiments by reading and executing computer program instructions stored in the memory 402.

[0089] In one example, electronic device 400 may also include communication interface 403 and bus 410. For example, Figure 4 As shown, the processor 401, memory 402, and communication interface 403 are connected through bus 410 and complete communication with each other.

[0090] The communication interface 403 is mainly used to realize communication between various modules, devices, units and / or equipment in the embodiments of this application.

[0091] Bus 410 includes hardware, software, or both, that couples components of electronic device 400 together. For example, and not limitingly, the bus may include an Accelerated Graphics Port (AGP) or other graphics bus, an Extended Industry Standard Architecture (EISA) bus, a Front-Side Bus (FSB), a HyperTransport (HT) interconnect, an Industry Standard Architecture (ISA) bus, an Infinite Bandwidth Interconnect, a Low Pin Count (LPC) bus, a memory bus, a Micro Channel Architecture (MCA) bus, a Peripheral Component Interconnect (PCI) bus, a PCI-Express (PCI-X) bus, a Serial Advanced Technology Attachment (SATA) bus, a Video Electronics Standards Association Local Bus (VESA Local Bus, VLB) bus, or other suitable buses, or a combination of two or more of these. Where appropriate, bus 410 may include one or more buses. Although specific buses are described and illustrated in the embodiments of this application, this application considers any suitable bus or interconnection.

[0092] Furthermore, in conjunction with the ray tracing methods of the graphics processor in the above embodiments, this application embodiment can provide a computer storage medium for implementation. The computer storage medium stores computer program instructions; when these computer program instructions are executed by a processor, they implement any of the ray tracing methods of the graphics processor in the above embodiments.

[0093] This application also provides a computer program product, including a computer program that, when executed by a processor, implements any of the ray tracing methods of the graphics processor described in the above embodiments.

[0094] It should be clarified that this application is not limited to the specific configurations and processes described above and shown in the figures. For the sake of brevity, detailed descriptions of known methods are omitted here. In the above embodiments, several specific steps are described and shown as examples. However, the method process of this application is not limited to the specific steps described and shown. Those skilled in the art can make various changes, modifications, and additions, or change the order of steps, after understanding the spirit of this application.

[0095] The functional blocks shown in the above-described block diagram can be implemented as hardware, software, firmware, or a combination thereof. When implemented in hardware, they can be, for example, electronic circuits, application-specific integrated circuits (ASICs), appropriate firmware, plug-ins, function cards, etc. When implemented in software, the elements of this application are programs or code segments used to perform the required tasks. Programs or code segments can be stored on a machine-readable medium or transmitted over a transmission medium or communication link via data signals carried on a carrier wave. "Machine-readable medium" can include any medium capable of storing or transmitting information. Examples of machine-readable media include electronic circuits, semiconductor memory devices, ROM, flash memory, erasable ROM (EROM), floppy disks, compact disc read-only memory (CD-ROM), optical disks, hard disks, fiber optic media, radio frequency (RF) links, etc. Code segments can be downloaded via computer networks such as the Internet, intranets, etc.

[0096] It should also be noted that the exemplary embodiments mentioned in this application describe methods or systems based on a series of steps or apparatus. However, this application is not limited to the order of the above steps; that is, the steps can be performed in the order mentioned in the embodiments, or in a different order, or several steps can be performed simultaneously.

[0097] The aspects of this disclosure have been described above with reference to flowchart illustrations and / or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of this disclosure. It should be understood that each block in the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, or other programmable data processing apparatus to produce a machine such that these instructions, executable via the processor of the computer or other programmable data processing apparatus, enable the implementation of the functions / actions specified in one or more blocks of the flowchart illustrations and / or block diagrams. Such a processor can be, but is not limited to, a general-purpose processor, a special-purpose processor, a special application processor, or a field-programmable logic circuit. It is also understood that each block in the block diagrams and / or flowcharts, and combinations of blocks in the block diagrams and / or flowcharts, can also be implemented by special-purpose hardware performing the specified functions or actions, or can be implemented by a combination of special-purpose hardware and computer instructions.

[0098] The above description is merely a specific implementation of this application. Those skilled in the art will clearly understand that, for the sake of convenience and brevity, the specific working processes of the systems, modules, and units described above can be referred to the corresponding processes in the foregoing method embodiments, and will not be repeated here. It should be understood that the protection scope of this application is not limited thereto. Any person skilled in the art can easily conceive of various equivalent modifications or substitutions within the technical scope disclosed in this application, and these modifications or substitutions should all be covered within the protection scope of this application.

Claims

1. A graphics processor, characterized in that, include: Ray tracing system and storage unit; The storage unit is used to store the shader binding table SBT; The ray tracing system includes a ray tracing core, a ray distribution and assembly unit, and a ray thread constructor; The ray thread constructor includes an SBT cache; The ray tracing core is configured to perform intersection tests between rays and scene geometry, and output hit information to the ray distribution and assembly unit; wherein the hit information is the intersection point information obtained in the intersection test; The ray distribution assembly unit is configured to determine the SBT record index and shader type corresponding to the ray based on the hit information, and allocate an SBT slot for rays with the same SBT record index and shader type; and send a prefetch request to the ray thread constructor before the thread start triggering condition of the SBT slot is met. The ray thread constructor is configured to determine the storage address of the shader record corresponding to the SBT slot in response to the prefetch request. If the shader record data corresponding to the SBT slot has not been written to the SBT cache, the shader record data corresponding to the SBT slot is read from the storage unit based on the storage address, and the shader record data is written to the SBT cache.

2. The graphics processor according to claim 1, characterized in that, The time before the thread start trigger condition of the SBT slot is met is the time when the SBT slot receives the first light beam.

3. The graphics processor according to claim 1, characterized in that, The ray thread constructor is further configured to perform a hit check on the shader record data in the SBT cache based on the storage address before reading the shader record data corresponding to the SBT slot from the storage unit based on the storage address; if the detection result is missing, it is determined that the SBT cache has not been written with the shader record data corresponding to the SBT slot.

4. The graphics processor according to claim 1, characterized in that, A prefetch interface is provided between the ray thread constructor and the ray distribution assembly unit; The prefetch interface is used to transmit the prefetch request.

5. The graphics processor according to claim 1, characterized in that, The prefetch request carries the SBT record index; The ray thread constructor is also configured to determine the storage address of the shader record corresponding to the SBT slot based on the SBT record index, the base address of the SBT, and the fixed size of each shader record.

6. The graphics processor according to claim 1, characterized in that, The ray tracing system also includes a scheduling execution core; The light distribution assembly unit is also configured to notify the light thread constructor to start the thread when the SBT slot meets the thread start triggering condition; The ray thread constructor is also configured to read the shader identifier from the shader record data in the SBT buffer and send the shader identifier to the scheduling execution core to start the thread.

7. The graphics processor according to any one of claims 1-6, characterized in that, The thread initiation triggering condition includes at least one of the following: The number of light rays in the SBT slot reaches a set threshold. The SBT slot was replaced; The SBT slot was refreshed.

8. A ray tracing method for a graphics processor, characterized in that, The graphics processor includes a ray tracing system and a storage unit. The storage unit is used to store ray tracing blocks (SBTs). The ray tracing system includes a ray tracing core, a ray distribution and assembly unit, and a ray thread constructor. The ray thread constructor includes an SBT cache. The method is applied to the ray tracing system, and the method includes: The ray tracing core performs an intersection test between the ray and the scene geometry, and outputs hit information to the ray distribution and assembly unit; wherein, the hit information is the intersection point information obtained in the intersection test; The ray distribution assembly unit determines the SBT record index and shader type corresponding to the ray based on the hit information, and allocates an SBT slot for rays with the same SBT record index and shader type; before the thread start triggering condition of the SBT slot is met, a prefetch request is sent to the ray thread constructor. In response to the prefetch request, the ray thread constructor determines the storage address of the shader record corresponding to the SBT slot. If the shader record data corresponding to the SBT slot has not been written to the SBT cache, the shader record data corresponding to the SBT slot is read from the storage unit based on the storage address, and the shader record data is written to the SBT cache.

9. The method according to claim 8, characterized in that, The time before the thread start trigger condition of the SBT slot is met is the time when the SBT slot receives the first light beam.

10. An electronic device, characterized in that, The electronic device includes: a graphics processor as described in any one of claims 1-7.

11. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores computer program instructions that, when executed by a processor, implement the steps of the ray tracing method of the graphics processor as described in any one of claims 8-9.

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