Analog circuit for implementing power-down detection memory

Abstract

The application belongs to the field of power-off detection, and discloses an analog circuit for realizing power-off detection memory, which comprises an initialization control module, a state latching module and an output buffer module; the initialization control module is used for enabling the state latching module after receiving an erasing control signal sent by a master control chip; the state latching module is used for receiving a measured signal, latching and memorizing a power-off detection signal through a disconnector logic; when the power supply of the measured signal is not powered off and the state latching module receives an enabling signal of the initialization control module, the state latching module enters a self-locking on state; when the power supply of the measured signal is powered off, the state latching module enters a locking off state; and the output buffer module is used for converting an analog voltage of the state latching module into a digital logic level. In this way, the detection and memory functions are completely separated from the master control chip, complete decoupling at the hardware level is realized, and repeated erasing and writing operations on the nonvolatile memory of the master control chip are avoided.

Description

Technical Field

[0001] This application relates to the field of power-down detection memory technology, specifically to an analog circuit for implementing power-down detection memory. Background Technology

[0002] In electronic systems, especially in automotive electronics and other applications with extremely high reliability requirements, accurate detection and reliable memorization of power-down states are crucial. Recording the event of an unexpected power outage is critical for subsequent fault diagnosis, safety strategy execution, and ensuring the system returns to its correct operating state after power is restored. Therefore, designing a circuit capable of effectively detecting and memorizing power-down states is a key aspect of ensuring the stability and safety of electronic products. However, power outages place high demands on the information that needs to be processed and memorized before the power failure, and the redundancy is poor.

[0003] To achieve power-down memory functionality, existing technologies typically employ active memory solutions centered around a microcontroller unit (MCU). One common method is the MCU-delayed power-down detection memory method. This method uses capacitor redundancy to create a time difference in the MCU's power-down timing. Within this time difference, the MCU performs the detection operation and writes the power-down state into the non-power-down lost memory area. However, this method has significant drawbacks: differences between redundant capacitor boards make window timing control difficult; large redundant capacitors result in long power-on times, making it difficult to simultaneously meet the requirements of both power-on and power-off durations; large redundant capacitors introduce large startup inrush currents; and storing the power-down state in the MCU's non-power-down lost memory space requires repeated erasing and rewriting, affecting the MCU's lifespan.

[0004] Another approach is the main control chip detection and memory method implemented under backup power switching. This method constructs a dual-power supply for the main control chip, actively switching to the backup power supply after detecting a main power failure, keeping the main control chip always operational. This ensures that the main control chip can detect the main power failure and write the power failure status to the non-power-loss memory area. However, this solution has poor versatility, requiring an additional backup power supply in most applications. This significantly increases hardware costs and complicates software maintenance, making it difficult to handle extreme cases where both main and backup power supplies fail simultaneously. Furthermore, this solution faces issues such as high standby power consumption, limited backup power supply lifespan, and the risk of program crashes due to prolonged main control chip power-on. More importantly, similar to the aforementioned methods, this approach also relies on the main control chip's non-volatile memory to record power failure status; frequent erase and write operations will also shorten the reliable lifespan of the main control chip.

[0005] In summary, existing power-down detection memory solutions generally suffer from problems such as reliance on the main control chip for storage, high hardware costs, limited applicability, and impact on the lifespan of the core controller. Therefore, there is an urgent need for a power-down detection memory solution that can be decoupled from the main control chip, has lower costs, and is more reliable. Summary of the Invention

[0006] The purpose of this application is to provide an analog circuit for implementing power-down detection memory. The detection and memory functions of the analog circuit for implementing power-down detection memory are completely separated from the main control chip, achieving complete decoupling at the hardware level. This avoids repeated erase and write operations on the non-volatile memory inside the main control chip, greatly extending the reliability and service life of the main control chip.

[0007] One advantage of this application is that it provides an analog circuit for implementing power-down detection memory. The analog circuit for implementing power-down detection memory greatly simplifies the corresponding software implementation logic. Developers only need to complete all functions through a write operation (for erasing) and a read operation (for obtaining results) on one port, which reduces the complexity of software development and the cost of later maintenance.

[0008] One advantage of this application is that it provides an analog circuit for implementing power-down detection memory. The analog circuit for implementing power-down detection memory uses basic discrete components, has low hardware cost, and does not rely on large-capacity capacitors or backup power supplies. This makes it easy to adapt to application scenarios with stringent requirements for power-up and power-down timing, low power consumption, and dark current. It is especially suitable for high-standard fields such as automotive electronics and has strong versatility and market competitiveness.

[0009] This application provides an analog circuit for implementing power-down detection memory, which includes: an initialization control module, a state latch module, and an output buffer module; The initialization control module is used to enable the state latch module after receiving the erase control signal from the main control chip. The state latch module is used to receive the measured signal and the enable signal of the initialization control module, and latches and memorizes the power failure detection signal through the disconnector logic. The measured signal is used to detect whether the power supply of the measured signal is down. The detection circuit for outputting the measured signal is independent of the main control chip. When the power supply of the measured signal is not down and the state latch module receives the enable signal of the initialization control module, it enters the self-locking conduction state. When the power supply of the measured signal is down, the state latch module enters the locked cutoff state. The output buffer module is used to convert the analog voltage of the state latch module into digital logic level.

[0010] In one embodiment of the analog circuit for implementing power-down detection memory according to this application, the initialization control module includes a first switching transistor; the base of the first switching transistor is connected to the pin of the main control chip that outputs the erase control signal, the collector of the equivalent transistor is connected to the input terminal of the state latch module, and the emitter of the equivalent transistor is grounded.

[0011] In one embodiment of the analog circuit for implementing power-down detection memory according to this application, the state latch module includes a second switching transistor and a third switching transistor connected in parallel. The emitter of the equivalent transistor of the second switching transistor is connected to a detection circuit for outputting the measured signal, the base of the equivalent transistor is connected to the collector of the equivalent transistor of the third switching transistor, and the collector of the equivalent transistor is connected to the base of the equivalent transistor of the third switching transistor. The collector of the equivalent transistor of the second switching transistor is connected to the collector of the first switching transistor and the base of the second switching transistor, respectively. The emitter of the equivalent transistor is grounded, and the base of the equivalent transistor is connected to the input terminal of the output buffer module.

[0012] In one embodiment of the analog circuit for implementing power-down detection memory according to this application, the state latch module further includes a diode, the anode of which is connected to a detection circuit for outputting the measured signal, and the cathode of which is connected to the emitter of the equivalent transistor of the second switching transistor.

[0013] In one embodiment of the analog circuit for implementing power-down detection memory according to this application, the output buffer module includes a fourth switching transistor, wherein the base of the equivalent transistor of the fourth switching transistor is connected to the base of the equivalent transistor of the third switching transistor, the collector of the equivalent transistor is connected to the pin of the main control chip outputting the reference level, and the emitter of the equivalent transistor is grounded.

[0014] In one embodiment of the analog circuit for implementing power-down detection memory according to this application, the output buffer module further includes a pull-up resistor. The pull-up resistor is connected between the collector of the equivalent transistor of the fourth switching transistor and the pin of the main control chip outputting the reference level.

[0015] In one embodiment of the analog circuit for implementing power-down detection memory according to this application, when the measured signal indicates that the power supply of the measured signal is in a non-power-down state and the first switching transistor is turned on, the first switching transistor enables the third switching transistor to turn on, the second switching transistor is turned on, and the memory output signal output by the fourth switching transistor is pulled to ground, resulting in a low-level output; when the measured signal indicates that the power supply of the measured signal is in a power-down state, the second switching transistor and the third switching transistor are turned off, the first switching transistor and the fourth switching transistor are also turned off, and the memory output signal output by the fourth switching transistor is pulled to a reference level through the pull-up resistor, resulting in a high-level output. Attached Figure Description

[0016] Figure 1 This is a circuit diagram of an analog circuit for implementing power-down detection memory, as disclosed in an embodiment of this application.

[0017] Figure 2 This is a timing diagram of the implementation logic of an analog circuit for implementing power-down detection memory, as disclosed in an embodiment of this application. Detailed Implementation

[0018] Hereinafter, exemplary embodiments according to this application will be described in detail with reference to the accompanying drawings. Obviously, the described embodiments are merely some embodiments of this application, and not all embodiments of this application. It should be understood that this application is not limited to the exemplary embodiments described herein.

[0019] It is understood that the term "one" should be interpreted as "at least one or more," meaning that in one embodiment, the number of an element can be one, while in another embodiment, the number of the element can be multiple. The term "one" should not be construed as a limitation on the number. "Multiple" means two or more.

[0020] While ordinal numbers such as first, second, etc., will be used to describe various components, there is no limitation on which components are used herein. The term is used only to distinguish one component from another; for example, a first component may be referred to as a second component, and similarly, a second component may be referred to as a first component, without departing from the teachings of this application. The terms used herein and / or include any and all combinations of one or more of the associated listed items.

[0021] The terminology used herein is for the purpose of describing various embodiments only and is not intended to be limiting. As used herein, the singular form also includes the plural form, unless the context clearly indicates otherwise. It will also be understood that the terminology includes and / or has the features, numbers, operations, components, elements or combinations thereof specified as used in this specification, without excluding the presence or addition of one or more other features, numbers, operations, components, elements or combinations thereof.

[0022] As mentioned above, to achieve power-down memory functionality, existing technologies typically employ a solution centered around a microcontroller unit (MCU). One common method is the MCU-delayed power-down detection and memory method. This method uses a large-capacity capacitor connected in parallel to the MCU's power supply circuit to provide a brief delayed power supply window when the main power supply is disconnected. During this window, the MCU detects the power-down event and writes the state into its internal non-volatile memory. However, this method has significant drawbacks: individual differences and aging of redundant capacitors can affect the consistency of the delay window time, leading to reduced detection reliability; large capacitors prolong the system's power-on time and generate large inrush currents, making it unsuitable for applications with strict power-on / off timing requirements; and repeated erasing and writing of the MCU's internal memory severely shortens its lifespan. Another method is the backup power switching method, which equips the MCU with both main and backup power supplies. When a main power failure is detected, the system automatically switches to the backup power supply, ensuring that the MCU can continue to operate and record the power-down state. However, this solution has poor versatility, requiring an additional backup power supply in most applications. This significantly increases hardware costs and complicates software maintenance, making it difficult to handle extreme situations where both primary and backup power supplies fail simultaneously. Furthermore, this solution faces challenges such as high standby power consumption, limited backup power supply lifespan, and the risk of program crashes due to prolonged power supply to the main control chip. More importantly, similar to the methods mentioned above, this approach relies on the main control chip's non-volatile memory to record power-down states; frequent erase and write operations will also shorten the reliable lifespan of the main control chip.

[0023] In summary, existing power-down detection memory solutions generally suffer from problems such as reliance on the main control chip for storage, high hardware costs, limited applicability, and impact on the lifespan of the core controller. Therefore, there is an urgent need for a power-down detection memory solution that can be decoupled from the main control chip, has lower costs, and is more reliable.

[0024] Based on this, the present invention proposes a novel technical concept, the core of which lies in constructing a purely hardware power-down detection and memory circuit independent of the main control chip. This circuit realizes power-down detection through low-level trigger logic and latches and remembers the power-down detection signal through disconnector logic. The main control chip only needs to actively pick up the power-down detection memory signal stored in the circuit when needed. The stored information is completely independent of the main control chip, realizing complete decoupling of detection memory storage and erasure from the main control chip.

[0025] Specifically, the circuit mainly consists of an initialization control module, a state latch module, and an output buffer module. Its operating logic is as follows: First, the main control chip sends a pulse erase signal through the initialization control module to enable the state latch module, putting it into a normal conduction state ready for detection. Subsequently, the state latch module continuously monitors the state of the signal being tested. Once a power failure is detected, the module uses its internal latching logic, similar to a circuit breaker, to automatically toggle the output signal and enter a stable signal output state. This state is locked by the hardware itself, and its state will not change even if the measured signal recovers subsequently. Finally, the output buffer module converts this latched analog voltage state into clear digital logic high and low level signals for the main control chip to read whenever needed. The entire power failure detection and memory process is completed autonomously by the external analog circuit; the main control chip only plays the role of erasing and reading when necessary.

[0026] By adopting the above-mentioned technical concept, this invention brings significant beneficial effects. First, since the detection and memory functions are completely separated from the main control chip, complete decoupling at the hardware level is achieved, thereby avoiding repeated erase and write operations on the non-volatile memory inside the main control chip, greatly extending the reliability and lifespan of the main control chip. In other words, the hardware decoupling design eliminates the need for the main control chip to erase and write memory, improving its lifespan. Second, the software implementation logic of this solution is greatly simplified. Developers only need to complete all functions through a GPIO write operation (for erasing) and a GPIO read operation (for obtaining results), reducing the complexity of software development and subsequent maintenance costs. Furthermore, the hardware decoupling design results in low hardware cost and simple implementation. Since the circuit uses basic discrete components, the hardware cost is low, and it does not rely on large-capacity capacitors or backup power supplies, making it suitable for various application scenarios with stringent requirements for power-on / off timing, low power consumption, and dark current. It is particularly suitable for high-standard fields such as automotive electronics, possessing strong versatility and market competitiveness.

[0027] Compared to commonly used power-down detection memory circuits on the market, this method offers significant improvements in both hardware and software implementation costs and the range of applicable scenarios. Moreover, the innovatively designed circuit detects and latches power-down signals using discrete circuits, eliminating the requirement of existing solutions for non-power-down memory space on the main control chip. This solution also achieves lower standby power consumption, simpler sleep / wake-up logic, and lower dark current, making it suitable even for demanding automotive electronic applications.

[0028] Accordingly, such as Figures 1 to 2As shown, an analog circuit for implementing power-down detection memory according to an embodiment of this application is illustrated. The analog circuit for implementing power-down detection memory includes an initialization control module 10, a state latch module 20, and an output buffer module 30. The initialization control module 10 enables the state latch module 20 after receiving an erase control signal from the main control chip. The state latch module 20 receives the measured signal and the enable signal from the initialization control module 10, and latches and remembers the power-down detection signal through the circuit breaker logic. The measured signal is used to detect whether the power supply to the measured signal is down. The detection circuit for outputting the measured signal is independent of the main control chip. When the power supply to the measured signal is not down and the state latch module 20 receives the enable signal from the initialization control module 10, it enters a self-locking conduction state. When the power supply to the measured signal is down, the state latch module 20 enters a locked off state. The output buffer module 30 converts the analog voltage of the state latch module 20 into a digital logic level, and then outputs a memory output signal. When the state latch module 20 is in the self-locking conduction state, the output buffer module 30 outputs a low level. When the state latch module 20 enters the locked off state, the output buffer module 30 outputs a high level.

[0029] Specifically, the initialization control module 10 includes a first switching transistor Q2; the base of the first switching transistor Q2 is connected to the pin of the main control chip that outputs the erase control signal, the collector of the equivalent transistor is connected to the input terminal of the state latch module 20, and the emitter of the equivalent transistor is grounded. The state latch module 20 includes a diode D, a second switching transistor Q1, and a third switching transistor Q3. The anode of the diode D is connected to a detection circuit for outputting the measured signal, and the cathode is connected to the emitter of the equivalent transistor of the second switching transistor Q1. The second switching transistor Q1 and the third switching transistor Q3 are connected in parallel. The emitter of the equivalent transistor of the second switching transistor Q1 is connected to the detection circuit for outputting the measured signal through the diode D. The base of the equivalent transistor is connected to the collector of the equivalent transistor of the third switching transistor Q3, and the collector of the equivalent transistor is connected to the base of the equivalent transistor of the third switching transistor Q3. The collector of the equivalent transistor of the second switching transistor Q1 is connected to the collector of the equivalent transistor of the first switching transistor Q2 and the base of the equivalent transistor of the second switching transistor Q1. The emitter of the equivalent transistor is grounded, and the base of the equivalent transistor is connected to the input terminal of the output buffer module 30. The output buffer module 30 includes a fourth switching transistor Q4 and a pull-up resistor R0. The base of the fourth switching transistor Q4 is connected to the base of the third switching transistor Q3, the collector of the equivalent transistor is connected to the pin of the main control chip's output reference level VCC, and the emitter of the equivalent transistor is grounded. The pull-up resistor R0 is connected between the collector of the fourth switching transistor Q4 and the pin of the main control chip's output reference level VCC.

[0030] The first switching transistor Q2, the second switching transistor Q1, the third switching transistor Q3, and the fourth switching transistor Q4 can be, but are not limited to, transistors, such as MOSFETs or other switching devices. The equivalent transistor base is the terminal that functions equivalently to the base of a transistor; it is the control terminal. For example, when the switching transistor is implemented as a field-effect transistor, the equivalent transistor base is the gate. The equivalent transistor emitter is the terminal that functions equivalently to the emitter of a transistor; it is the input terminal. For example, when the switching transistor is implemented as a field-effect transistor, the equivalent transistor emitter is the source. The equivalent transistor collector is the terminal that functions equivalently to the collector of a transistor; it is the output terminal. For example, when the switching transistor is implemented as a field-effect transistor, the equivalent transistor emitter is the drain.

[0031] The OR logic for the switching states of the first switching transistor Q2, the second switching transistor Q1, and the third switching transistor Q3 is shown in the table below: Table 1

[0032] The specific circuit implementation logic is as follows: First, the main control chip outputs a short-time high-level pulse erase control signal to enable the aforementioned power-down memory latch circuit. During this process, the first switching transistor Q2 conducts the second switching transistor Q1 after receiving the high-level signal from the main control chip. After the second switching transistor Q1 conducts and outputs a voltage, the third switching transistor Q3 and the fourth switching transistor Q4 are passively turned on due to the output voltage of the second switching transistor Q1. According to the OR logic relationship between the first switching transistor Q2 and the third switching transistor Q3, the first switching transistor Q2 turning off alone will not affect the conduction of the second switching transistor Q1. Therefore, when the short-time high-level pulse erase control signal output by the main control chip ends, the first switching transistor Q2 turns off (the erase control signal is a single operation). The third switching transistor Q3 and the second switching transistor Q1 form an interlocked circuit breaker logic, and the memory output signal is locked at a low level. Afterwards, even if the main control chip loses power and is powered on again, it will not affect the memory signal output of the circuit. The implementation logic timing diagram is as follows. Figure 2 As shown.

[0033] Referring to the above circuit breaker logic, when the first switching transistor Q2 remains off, the output voltage of the second switching transistor Q1 determines the switching state of the third switching transistor Q3. The switching state of the third switching transistor Q3 directly determines the switching state of the second switching transistor Q1. Therefore, when the measured signal is powered off or disconnected, when the output voltage of the second switching transistor Q1 drops to the cutoff voltage threshold of the third switching transistor Q3, the third switching transistor Q3 is turned off, and the second switching transistor Q1 is also turned off. The memory output signal is locked at a high level. Even if the measured signal is powered on again, it will not change the memory output signal until the main control chip obtains the memory output signal and re-enables the power-down memory latch circuit.

[0034] In general, the circuit's operating logic can be divided into three main stages: initialization / reset, normal operation (self-locking), and power-down detection and memory. Initialization / Reset Stage: The main control chip outputs a brief high-level pulse to the erase control signal port, causing the base of the first switching transistor Q2 to become high, turning on Q2. After Q2 turns on, its collector is pulled to ground (low level). This low level is applied to the base of the second switching transistor Q1. Since the emitter of the second switching transistor Q1 is connected to a high-level measured signal, its base is pulled low, turning on Q1. After Q1 turns on, current flows from its emitter to its collector, causing its collector to output a high level (close to the measured signal voltage). This high level is applied to the base of the third switching transistor Q3, turning it on. This high level is also applied to the base of the fourth switching transistor Q4, turning it on. When the third switching transistor Q3 turns on, its collector also pulls the base of the second switching transistor Q1 low. At this time, even if the reset pulse of the main control chip ends (the erase control signal returns to a low level, and the first switching transistor Q2 is turned off), the third switching transistor Q3 can still maintain the base of the second switching transistor Q1 at a low level, thus keeping the second switching transistor Q1 on. The second switching transistor Q1 and the third switching transistor Q3 are self-locking. Since the fourth switching transistor Q4 is on in this state, its collector (memory output signal) is pulled to ground, so the output is low.

[0035] Normal operation / locking phase: After reset, the circuit is in a stable monitoring state. The measured signal is powered normally. The second switching transistor Q1 and the third switching transistor Q3 maintain each other's on state (locking). The fourth switching transistor Q4 remains on. The memory output signal remains low.

[0036] Power-down detection and memory stage (writing power-down state): When the measured signal experiences a power outage or low voltage: Third switching transistor Q3 is turned off: The voltage of the measured signal decreases, causing the voltage applied to the base of the equivalent transistor of the third switching transistor Q3 to also decrease. When this voltage is lower than the conduction threshold of the third switching transistor Q3, the third switching transistor Q3 is turned off. Latch latching: After the third switching transistor Q3 is turned off, it can no longer pull the base of the equivalent transistor of the second switching transistor Q1 low. At the same time, the first switching transistor Q2 is already turned off. At this time, there is no other path to pull the base of the equivalent transistor of the second switching transistor Q1 low. Second switching transistor Q1 is turned off: Since there is no low-level equivalent transistor base drive signal, the second switching transistor Q1 is turned off. Fourth switching transistor Q4 is turned off: After the second switching transistor Q1 is turned off, its equivalent transistor collector no longer has a high-level output (becomes low-level), therefore the base of the equivalent transistor of the fourth switching transistor Q4 becomes low-level, and the fourth switching transistor Q4 is turned off. Output becomes high: After the fourth switching transistor Q4 is turned off, it acts like an open switch, and its equivalent transistor collector (memory output signal) is no longer pulled to ground. At this time, the reference chip pulls the memory output signal high through the pull-up resistor R0. State is remembered: At this time, even if the measured signal is restored to power, without an active control signal to erase the memory state, the second switching transistor Q1 cannot be actively turned on, and the third switching transistor Q3 cannot be turned on either. The entire circuit will remain in a state where the second switching transistor Q1, the third switching transistor Q3, and the fourth switching transistor Q4 are all turned off. The memory output signal will be locked at a high level until the main control chip issues an erase control signal to reset the circuit. Therefore, once the measured signal experiences a power outage or disconnection, the detection circuit will flip its state, and the memory output signal will be locked at a high level. The main controller can confirm that the measured signal has experienced a power outage by picking up the memory output state as high at any time after being controlled.

[0037] In one example of this application, the initialization control module 10 further includes a first current-limiting resistor R1, a first pull-down resistor R2, and a current-limiting voltage divider resistor R3. The first current-limiting resistor R1 is an equivalent transistor base-limiting current resistor, connected in series between the erase control signal input terminal and the equivalent transistor base of the first switching transistor Q2. When the external main control chip sends a high-level erase pulse signal, the main function of the first current-limiting resistor R1 is to limit the current flowing into the equivalent transistor base of the first switching transistor Q2, preventing excessive current from damaging the first switching transistor Q2, while ensuring that the first switching transistor Q2 operates in a saturated conduction state. The first pull-down resistor R2 is an equivalent transistor base-pull-down resistor, connected between the equivalent transistor base of the first switching transistor Q2 and ground, its core function being to provide a defined low-level state. When the erase control signal is at a low level or in a high-impedance state (i.e., floating), the first pull-down resistor R2 reliably pulls the base potential of the first switching transistor Q2 to ground, ensuring that the first switching transistor Q2 is in a stable off state, thereby avoiding false triggering caused by signal interference or floating levels. The first pull-down resistor R2 and the first current-limiting resistor R1 form a voltage divider circuit, which together determine the base bias of the first switching transistor Q2. The current-limiting voltage divider resistor R3 is connected between the collector of the first switching transistor Q2 and the base of the second switching transistor Q1, specifically between the collector of the first switching transistor Q2 and the cathode of the diode D, and its function is to transmit the control effect of the initialization control module 10 to the state latch module 20. When the first switching transistor Q2 is turned on, its equivalent transistor collector is pulled to ground. The current-limiting voltage divider resistor R3 transmits this low level to the equivalent transistor base of the second switching transistor Q1, forcing the second switching transistor Q1 to turn on, thereby realizing the initialization of the circuit (erasing memory).

[0038] The state latch module 20 further includes a capacitor C, a bias resistor R4, a first feedback resistor R5, a second feedback resistor R6, and a second pull-down resistor R7. The capacitor C is connected in parallel between the base and emitter of the third switching transistor Q3 to suppress high-frequency noise. The bias resistor R4 is a start-up resistor providing initial bias for the second switching transistor Q1, connected between the input terminal of the measured signal and the base of the second switching transistor Q1. Under normal operating conditions (first switching transistor Q2 is off), if the measured signal is present (i.e., the power supply is not down), the bias resistor R4 draws current from the measured signal, providing a negative bias (relative to its emitter) to the base of the second switching transistor Q1, keeping the second switching transistor Q1 in the off state. The first feedback resistor R5 and the second feedback resistor R6 are key feedback resistors constituting the latch structure. The first feedback resistor R5 is connected between the collector of the second switching transistor Q1 and the base of the third switching transistor Q3. When the second switching transistor Q1 is turned on, current flows through the first feedback resistor R5 into the base of the third switching transistor Q3, providing a bias for its conduction. The first feedback resistor R5 also limits this current. The second feedback resistor R6 is connected between the collector of the third switching transistor Q3 and the base of the second switching transistor Q1. When the third switching transistor Q3 is turned on, its collector potential decreases, further lowering the base potential of the second switching transistor Q1 through the second feedback resistor R6, thus keeping the second switching transistor Q1 on. The second switching transistor Q1, the third switching transistor Q3, and the first and second feedback resistors R5 and R6 together form a positive feedback latch structure similar to a thyristor (SCR). Once triggered to conduct, they maintain each other's conduction state, thereby achieving a memory function. The second pull-down resistor R7 is an equivalent transistor base pull-down resistor that provides a stable bias for the third switching transistor Q3. It is connected between the equivalent transistor base of the third switching transistor Q3 and ground. Its function is to ensure that when the second switching transistor Q1 is not turned on or not sufficiently turned on, the equivalent transistor base potential of the third switching transistor Q3 is reliably pulled low, keeping the third switching transistor Q3 off and preventing the latch circuit from being falsely triggered by noise signals. The second pull-down resistor R7 and the first feedback resistor R5 form a voltage divider relationship.

[0039] The output buffer module 30 further includes a second current-limiting resistor R8 and a third pull-down resistor R9. The second current-limiting resistor R8 is a current-limiting resistor that provides bias to the fourth switching transistor Q4 in the output stage. It is connected between the core node of the state latch module 20 (the collector of the equivalent transistor of the third switching transistor Q3) and the base of the equivalent transistor of the fourth switching transistor Q4. It transmits the state of the latch module (the level of the collector of the equivalent transistor Q3) to the output module and limits the current flowing into the base of the equivalent transistor Q4, protecting the fourth switching transistor Q4. The third pull-down resistor R9 is a pull-down resistor that provides stable bias to the base of the equivalent transistor Q4. It is connected between the base of the equivalent transistor Q4 and ground. Its function is to ensure that when the third switching transistor Q3 is off (not latched down), the base of the equivalent transistor Q4 is reliably pulled low, keeping the fourth switching transistor Q4 in the off state and outputting a high level through the pull-up resistor R0.

[0040] In summary, the analog circuit used to implement power-down detection memory has been elucidated. The detection and memory functions of this analog circuit are completely separated from the main control chip, achieving thorough hardware decoupling. This avoids repeated erase and write operations on the main control chip's internal non-volatile memory, significantly extending the chip's reliability and lifespan. The software implementation logic matching this circuit is greatly simplified. Developers only need one GPIO write operation (for erasing) and one GPIO read operation (for obtaining results) to implement the complete power-down detection memory function, reducing software development complexity and subsequent maintenance costs. Because the circuit uses basic discrete components, its hardware cost is low, and it does not rely on large-capacity capacitors or backup power supplies. This allows it to easily adapt to applications with stringent requirements for power-up / down timing, low power consumption, and dark current, making it particularly suitable for high-standard fields such as automotive electronics. It possesses strong versatility and market competitiveness.

[0041] The above are only some embodiments of this application and do not limit the patent scope of this application. All equivalent structural transformations made under the technical concept of this application and using the contents of the specification and drawings of this application, or direct / indirect applications in other related technical fields, are included in the patent protection scope of this application.

Claims

1. An analog circuit for implementing power-down detection and memory, characterized in that, include: Initialize the control module, state latch module, and output buffer module; The initialization control module is used to enable the state latch module after receiving the erase control signal from the main control chip. The state latch module is used to receive the measured signal and the enable signal of the initialization control module, and latches and memorizes the power failure detection signal through the disconnector logic. The measured signal is used to detect whether the power supply of the measured signal is down. The detection circuit for outputting the measured signal is independent of the main control chip. When the power supply of the measured signal is not down and the state latch module receives the enable signal of the initialization control module, it enters the self-locking conduction state. When the power supply of the measured signal is down, the state latch module enters the locked cutoff state. The output buffer module is used to convert the analog voltage of the state latch module into digital logic level.

2. The analog circuit for implementing power-down detection and memory according to claim 1, characterized in that, The initialization control module includes a first switching transistor; the base of the first switching transistor is connected to the pin of the main control chip that outputs the erase control signal, the collector of the equivalent transistor is connected to the input terminal of the state latch module, and the emitter of the equivalent transistor is grounded.

3. The analog circuit for implementing power-down detection and memory according to claim 2, characterized in that, The state latching module includes a second switching transistor and a third switching transistor connected in parallel. The emitter of the second switching transistor is connected to a detection circuit for outputting the measured signal, the base of the second switching transistor is connected to the collector of the third switching transistor, and the collector of the second switching transistor is connected to the base of the third switching transistor. The collector of the second switching transistor is connected to both the collector of the first switching transistor and the base of the second switching transistor. The emitter of the second switching transistor is grounded, and the base of the second switching transistor is connected to the input terminal of the output buffer module.

4. The analog circuit for implementing power-down detection and memory according to claim 3, characterized in that, The output buffer module includes a fourth switching transistor, wherein the base of the fourth switching transistor is connected to the base of the equivalent transistor of the third switching transistor, the collector of the equivalent transistor is connected to the pin of the main control chip that outputs the reference level, and the emitter of the equivalent transistor is grounded.

5. The analog circuit for implementing power-down detection and memory according to claim 4, characterized in that, The output buffer module also includes a pull-up resistor. The pull-up resistor is connected between the collector of the equivalent transistor of the fourth switching transistor and the pin of the main control chip that outputs the reference level.

6. The analog circuit for implementing power-down detection memory according to claim 5, characterized in that, When the measured signal indicates that the power supply to the measured signal is not powered off and the first switching transistor is turned on, the first switching transistor enables the third switching transistor to turn on, the second switching transistor is turned on, and the memory output signal output by the fourth switching transistor is pulled to ground, resulting in a low-level output. When the measured signal indicates that the power supply to the measured signal is powered off, the second and third switching transistors are turned off, and the first and fourth switching transistors are also turned off. The memory output signal output by the fourth switching transistor is pulled to the reference level through the pull-up resistor, resulting in a high-level output.

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