Lead frame structure and package structure for SOW10 package of hall current sensor chip

Abstract

The application relates to the technical field of semiconductor chip packaging, and discloses a lead frame structure and a packaging structure for SOW10 packaging of a Hall current sensor chip, which comprises a lead frame base island, the thickness of the lead frame base island is greater than that of a conventional SOW16 lead frame base island, so as to compensate for the loss of the cross-sectional area of the original side current path caused by the reduction in the number of pins in a first pin group; the lead frame pins comprise a first pin group and a second pin group; the first pin group is directly arranged on the lead frame base island and is electrically connected to the lead frame base island, is located at the opposite side of the side where the protruding part is located, and is used for leading in and out the original side current; the second pin group is connected to a die through a lead wire; an isolation device is arranged between the die and the lead frame base island, and the isolation device completely covers the area where the lead wire passes through the lead frame base island on a projection plane. The application provides the lead frame structure with lower conduction resistance, and the structure has lower conduction impedance.

Description

Technical Field

[0001] This invention relates to the field of semiconductor chip packaging technology, and specifically to a lead frame structure and packaging structure for an SOW10 package of a Hall current sensor chip. Background Technology

[0002] Hall effect current sensor chips utilize the Hall effect for current measurement. Due to their advantages such as small size, high accuracy, and non-contact operation, they are widely used in home appliances, photovoltaics, and new energy electric vehicles. SOW (Small Outline Wing) packaging is one of the mainstream packaging forms for this type of chip.

[0003] In existing technologies, the SOW16 package is widely used. For example, Chinese patent CN116153897A discloses a lead frame structure, a packaging structure and method for a Hall current sensor chip. This solution achieves low on-resistance and high magnetic gain by setting a protrusion on the lead frame base island, an inverted trapezoidal first lower slot, and area completion design on both sides of the protrusion, and integrating isolation devices, thus providing a high-performance solution for the SOW16 package.

[0004] However, as end products increasingly demand miniaturization and high power density, the size of the SOW16 package is no longer sufficient for some compact applications. The market urgently needs solutions with smaller packages, such as the SOW10 package with fewer pins. However, simply reducing the number of pins and shrinking the package size presents a series of new technical challenges:

[0005] 1. Sharply Increased Primary-Side On-Resistance: The SOW10 package typically has only two primary-side pins (e.g., PIN1 and PIN2), far fewer than the eight pins of the SOW16 (e.g., PIN1-PIN8). This results in a significant reduction in the effective cross-sectional area of ​​the primary-side path that can carry large currents. Without special design, the on-resistance will increase significantly, leading to severe heat generation and power loss, greatly limiting the maximum current that the sensor can measure.

[0006] II. Structural Strength and Heat Dissipation Challenges: How to ensure the bonding strength between the molding compound and the frame to prevent delamination on a smaller base island area, and how to optimize the heat dissipation path to cope with the heat brought by higher current density are all problems that need to be solved.

[0007] III. Challenges in Maintaining Performance: Within a compact space, how to retain or even optimize structural designs that enhance magnetic gain, such as the inverted trapezoidal groove and protrusions described in CN116153897A, while ensuring sensor sensitivity and miniaturization, presents a very high technical challenge.

[0008] Therefore, those skilled in the art face a clear technical hurdle: how to successfully port and optimize the high-performance design from the SOW16 package to the SOW10 package, and solve entirely new problems such as the surge in on-resistance, heat dissipation difficulties, and structural reliability caused by the sharp reduction in pins. This is not a simple scaling up, but a process of reinvention tailored to the specific constraints of the SOW10 package. Summary of the Invention

[0009] The purpose of this invention is to overcome the shortcomings of existing SOW10 packages, such as a sharp increase in on-resistance, decreased structural reliability, and difficulty in maintaining magnetic gain due to the drastic reduction in the number of pins. This invention provides a leadframe structure, a SOW10 package structure for a Hall current sensor chip, and a corresponding method. Through collaborative innovation in the thickness and shape of the leadframe base island and the integrated isolation device, this solution successfully achieves industry-leading low on-resistance, high magnetic gain, and high isolation withstand voltage within the SOW10 package size.

[0010] This invention is achieved through the following technical solution:

[0011] In a first aspect, the present invention provides a lead frame structure for a SOW10 package of a Hall current sensor chip. The first pin group of the SOW10 package consists of two pins, innovatively including:

[0012] The core improvement of the leadframe base island lies in its significantly increased thickness, specifically exceeding that of the conventional SOW16 leadframe base island. This compensates for the loss of primary-side current path cross-sectional area caused by the reduction of the number of pins in the first pin group from multiple in the SOW16 to two, thus solving the low-resistance problem of the SOW10 package from a structural perspective.

[0013] Along the x-axis direction of the lead frame base island, a protrusion extending towards the positive y-axis is provided in its middle, and the area of ​​the protrusion is supplemented on both sides in the x-axis direction. This design further widens the current path within the limited SOW10 space, and works in conjunction with the thickened base island to reduce on-resistance.

[0014] The lead frame base island has a first upper slot and a first lower slot along the y-axis in the middle for placing the two Hall discs of the die. The first upper slot is located on the protrusion, and the first lower slot is an inverted trapezoidal slot whose width gradually decreases along the y-axis away from the protrusion. This inverted trapezoidal design optimizes the magnetic field distribution, making the magnetic field lines more concentrated at the Hall discs, thereby enhancing the magnetic gain.

[0015] The lead frame pins include a first pin group and a second pin group. The first pin group is directly disposed and electrically connected to the lead frame base island, and is located on the opposite side of the side where the protrusion is located, for introducing and extracting primary current. The second pin group is connected to the die via a lead.

[0016] An isolation device is disposed between the die and the lead frame base island, and the isolation device completely covers the area where the lead passes through the lead frame base island on its projected plane. This design ensures high isolation withstand voltage performance and effectively suppresses electromagnetic interference.

[0017] As an optimization, the thickness of the lead frame base island is 0.5 mm. This specific thickness is the optimal embodiment for achieving low on-resistance.

[0018] As an optimization, several first through holes are provided along the z-axis through the lead frame base island. This design enhances the mechanical bonding between the molding compound and the base island, effectively preventing delamination (popcorn effect) caused by thermal and moisture stress.

[0019] As an optimization, several second through holes are provided along the z-axis through several pins of the second pin group, and the edges of the pins of the second pin group are all rounded. The second through holes enhance the bonding strength, and the rounded transitions can prevent tip discharge and improve product reliability.

[0020] As an optimization, the isolation device includes a metal shielding layer and an intermediate dielectric layer. In the z-axis direction, the intermediate dielectric layer is located below the metal shielding layer, and the metal shielding layer has a second upper slot and a second lower slot in the y-axis direction to avoid interference from the two Hall disks of the die. This structure provides isolation while preventing eddy current interference from the metal layer on the Hall sensor.

[0021] As an optimization, the intermediate dielectric layer is made of polyimide (PI). Polyimide has extremely high dielectric strength (≥200KV / mm), which can meet the isolation withstand voltage requirement of greater than 5KV RMS.

[0022] As an optimization, the length of the first lower slot in the y-axis direction is greater than the length of the first upper slot in the y-axis direction. This design can make full use of the space in the y-axis direction provided by the protrusion, and significantly enhance the magnetic gain of the die at the Hall disk.

[0023] Secondly, the present invention provides a SOW10 package structure for a Hall current sensor chip, including the aforementioned lead frame structure, die, and molding compound. The die is bonded and fixed to the isolation device with insulating adhesive, and its two Hall pads are precisely located at the upper and lower slot areas of the base island and the isolation device. The molding compound covers all internal structures and is embedded in the first through-hole and / or the second through-hole to form a robust whole.

[0024] Thirdly, the present invention provides a packaging method for the above-described SOW10 package structure. In the conventional SOW10 packaging process, before the first optical inspection, the following steps are performed: preparing the above-described dedicated lead frame structure; and then using insulating adhesive to bond and fix the isolation device to a designated position on the lead frame base island. As an optimization, the curing conditions of the insulating adhesive are: curing at a temperature of 150°C to 200°C for 30 to 90 minutes.

[0025] Compared with the prior art, the present invention has the following advantages and beneficial effects:

[0026] 1. This invention provides a lead frame structure with lower on-resistance. Compared to the traditional SOW16 package, it has a thicker primary copper busbar and a larger primary current-carrying area, resulting in a lower on-resistance at the structural level. Furthermore, in the SOW10 package with the same structure, through the design and optimization of the base island shape, this patent achieves the lowest on-resistance in the industry for the same package.

[0027] 2. This invention provides a packaging method for a Hall current sensor chip packaging structure, which internally encapsulates an isolation device structure. The isolation device structure is bonded to the die using insulating adhesive, achieving high isolation withstand voltage. It can withstand an isolation withstand voltage greater than 5KV RMS and a surge voltage of 11KV, achieving industry-leading performance.

[0028] 3. Depending on the different withstand voltage requirements, the substrate material of the isolation device that can be packaged in the SOW10 package structure includes a polyimide film of ≤150um. The polyimide film has excellent withstand voltage performance and can meet the dielectric strength of ≥200KV / mm. At the same time, the isolation device also includes an upper electrolytic copper shielding layer. This shielding layer has two benefits. First, the shielding layer has a slotted structure, which ensures that the Hall point of the die corresponds to the slotted position, which can prevent the metal film from forming eddy currents under high-frequency magnetic fields, thereby interfering with the normal operation of the Hall sensing point of the sensor silicon chip and reducing the bandwidth of the differential Hall sensor. Second, the shielding layer of the FPC isolation device structure can be connected to ground by wire bonding, reducing the impact of electromagnetic interference on the sensor chip. Attached Figure Description

[0029] The accompanying drawings, which are included to provide a further understanding of embodiments of the invention and form part of this application, do not constitute a limitation thereof. In the drawings:

[0030] Figure 1 This is a perspective view of a lead frame structure according to the present invention;

[0031] Figure 2This is a front view of the packaging structure of a Hall current sensor chip according to the present invention;

[0032] Figure 3 This is a top view of the isolation device;

[0033] Figure 4 This is a front view of the isolation device.

[0034] The attached diagram shows the markings and corresponding component names:

[0035] 1-Lead frame base island, 2-Lead frame pin, 3-First through hole, 4-Second through hole, 5-Base island slot, 6-Lead, 7-Isolation device, 8-Die, 9-Molded body, 10-Electrolytic copper shielding layer, 11-Intermediate dielectric layer, 12-Shielding layer slot. Detailed Implementation

[0036] To make the objectives, technical solutions, and beneficial effects of this invention clearer, the invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are for illustrative purposes only and are not intended to limit the invention. The x-axis, y-axis, and z-axis directions described in this invention follow the accompanying drawings. Figure 1 The established coordinate system.

[0037] Example 1:

[0038] like Figure 1 As shown, this embodiment provides a lead frame structure for a SOW10 package used in Hall current sensor chips.

[0039] The core of the leadframe structure lies in its leadframe base island 1. The thickness of this leadframe base island 1 is designed to be 0.5 mm. This thickness, significantly greater than that of a conventional SOW16 leadframe base island, is one of the key innovations of this invention. Its purpose is to compensate for the loss of primary-side current path cross-sectional area caused by the reduction of the number of pins in the first pin group of the SOW10 package to two, thereby structurally ensuring a low on-resistance (below 300 μΩ).

[0040] Along the x-axis direction of the lead frame base island 1, a protrusion extending in the positive y-axis direction is provided in the middle. In the x-axis direction, the area of ​​the protrusion is supplemented on both sides, which widens the lateral conduction path of the primary current and works in conjunction with the thickened base island to reduce the on-resistance.

[0041] The lead frame base island 1 has a first upper slot and a first lower slot 5 formed along the y-axis in the middle for precisely placing the two Hall disks of the die. These two slots can be collectively referred to as base island slots. The first upper slot is located on the protrusion. The first lower slot 5 is configured as an inverted trapezoidal slot with its width gradually decreasing in the y-axis direction away from the protrusion. This inverted trapezoidal design optimizes the magnetic field distribution, making the magnetic field lines more concentrated at the Hall disks, thereby enhancing the magnetic gain. Specifically, the shortest distance between the first upper slot and the first lower slot is designed to be 1.61 mm. By setting the protrusion, while ensuring that the die is fully supported on the frame and that the first upper slot can precisely place the Hall disks, the length of the first lower slot 5 in the y-axis direction is maximized to 2.94 mm. This length is greater than that of the first upper slot, which significantly enhances the magnetic gain of the die at the Hall disks, achieving a sensitivity of 4.5 GS / A.

[0042] To improve packaging reliability, several first through holes 3 are provided along the z-axis through the lead frame base island 1. In this embodiment, the first through holes 3 are designed to be elliptical, with dimensions of 0.55 mm in length and 0.35 mm in width. During injection molding, the molding compound will embed into these through holes, forming a mechanical interlock, effectively enhancing the bonding strength between the molding compound and the lead frame base island, and avoiding delamination (i.e., the "popcorn" phenomenon) caused by thermal and moisture stress.

[0043] The lead frame pins 2 include a first pin group and a second pin group. The first pin group consists of two pins (PIN1 and PIN2), which are directly disposed and electrically connected to the lead frame base island 1 and located on the opposite side of the protrusion, serving as the input IP+ and output IP- of the primary current, respectively. The second pin group (PIN3-PIN10, not shown in the figure, i.e., the 8 pins corresponding to PIN1 and PIN2 in the y-axis direction) is connected to the die 8 via a lead 6 for signal transmission. Several pins of the second pin group passing through it along the z-axis are provided with several second through holes 4. In this embodiment, the second through holes 4 are designed as circles with a radius of 0.2 mm to enhance the bonding strength between the second pin group and the molding compound. In addition, all pin edges of the second pin group adopt a rounded transition design, which can effectively avoid tip discharge and improve product reliability.

[0044] Example 2:

[0045] like Figure 2 , Figure 3 and Figure 4 As shown, this embodiment provides a complete SOW10 package structure for a Hall current sensor chip.

[0046] The structure includes the lead frame structure described in Embodiment 1. An isolation device 7 (i.e., an FPC isolation device structure) is disposed between the die 8 and the lead frame base island 1. The isolation device 7 is precisely cut into a regular shape of 4.6mm * 3.4mm on the projection plane, and its installation position must ensure that it completely covers the area on the projection plane where all leads 6 pass through the lead frame base island 1, in order to achieve excellent isolation and withstand voltage.

[0047] The isolation device 7 comprises a metal shielding layer 10 and an intermediate dielectric layer 11. The metal shielding layer 10 is an electrolytic copper layer with a thickness of 12µm, serving as electromagnetic shielding. The intermediate dielectric layer 11 is made of polyimide (PI) with a thickness of 75µm (the thickness of this PI layer can be selected between 30µm and 150µm depending on requirements). It possesses extremely high dielectric strength, which is crucial for achieving high isolation withstand voltage (>5KV RMS). In the z-axis direction, the intermediate dielectric layer 11 is located below the metal shielding layer 10. The metal shielding layer 10 also has a second upper slot and a second lower slot 12 (collectively referred to as shielding layer slots) in the y-axis direction to avoid interference with the two Hall pads of the die. Their positions correspond one-to-one with the slots 5 on the base island, ensuring that the Hall points of the die are located at the slot positions, preventing the metal film from forming eddy currents under high-frequency magnetic fields, which could interfere with the normal operation of the Hall sensing points of the sensor chip.

[0048] The core 8 has a thickness of 140 μm. It is bonded to the metal shielding layer 10 of the isolation device 7 with insulating adhesive.

[0049] Finally, an epoxy resin molding compound is used to form a molding compound 9 that encapsulates the lead frame structure, the isolator 7, and the die 8 through an injection molding process. The lead frame pins 2 extend outside the molding compound 9 for connection to external circuitry. During injection molding, some of the molding compound is embedded in the first through-hole 3 and the second through-hole 4, greatly enhancing the bonding strength between the lead frame and the molding compound 9.

[0050] Example 3:

[0051] This embodiment provides a dedicated packaging method for the aforementioned SOW10 package structure. Based on the conventional SOW10 packaging process (which includes: lead frame preparation → first optical inspection → wafer preparation → grinding → wafer dicing → wafer cleaning → second optical inspection → die bonding → wire bonding → third optical inspection → injection molding → high-temperature curing → flash removal / electroplating → laser marking → lead trimming / forming → fourth optical inspection), it creatively adds two key steps before the first optical inspection:

[0052] S1. Custom Leadframe Fabrication: First, according to the design requirements of Example 1, a dedicated SOW10 leadframe structure was fabricated. This step specifically includes:

[0053] S11. Base island shape design: A first upper slot with a distance of 1.61mm and an inverted trapezoidal first lower slot 5 are opened on the base island, forming a protrusion in the middle and area completion design on both sides, so that the length of the first lower slot 5 in the y-axis direction reaches 2.94mm.

[0054] S12. Pin Design: Define PIN1 and PIN2 as the first pin group connected to the base island, define PIN3 to PIN10 as the second pin group connected to the die through leads, and form a second through hole (4) with a radius of 0.2mm and a rounded transition edge on the second pin group.

[0055] S13. Anti-delamination design: An elliptical first through hole 3 with a size of 0.55mm x 0.35mm is formed on the lead frame base island 1.

[0056] S2. Isolator mounting and curing: The pre-cut isolator 7 is bonded and fixed to the designated position of the lead frame base island 1 using insulating adhesive. As an optimization, the insulating adhesive is cured at a temperature of 150°C to 200°C for 30 to 90 minutes (a typical preferred condition is curing at 180°C for 60 minutes) to achieve a strong bond between the isolator 7 and the lead frame base island (1).

[0057] After completing the above steps, the entire semi-finished product then enters the conventional SOW10 packaging process, where subsequent operations such as die bonding, wire bonding, and molding are performed in sequence.

[0058] Example 4:

[0059] This embodiment aims to illustrate in detail how to use a genetic algorithm to automatically and optimally design the key dimensional parameters of the lead frame structure described in claims 1-7, so as to systematically balance and improve its electrical performance (low on-resistance), magnetic performance (high magnetic gain) and mechanical reliability.

[0060] S4.1 Determination of Optimization Objective and Construction of Fitness Function:

[0061] The core of this optimization is a multi-objective optimization problem. To address the issue of inconsistent dimensions among the performance indicators, this invention employs a linear weighted sum method and introduces normalization processing to construct the fitness function.

[0062] First, through preliminary simulations and experiments, a reasonable expected range is determined for each optimization objective. Then, a benefit-type sub-function (i.e., a function where a larger value is better) is defined for each performance index, as follows:

[0063] 1. On-resistance (R) subfunction The objective is to minimize on-resistance, therefore it is transformed into a performance-based indicator. A reference upper limit is set. (e.g., 400 uΩ), its sub-function is defined as:

[0064] ;

[0065] Where R is the simulated resistance value of the current individual. The desired minimum resistance (e.g., 250 uΩ). When R approaches... hour, Approaching 1; when R approaches hour, Close to 0.

[0066] 2. Magnetic sensitivity (S) subfunction The goal is to maximize sensitivity. A lower reference limit is set. (e.g., 4.0GS / A) and expected upper limit (e.g., 5.0 GS / A), its sub-function is defined as:

[0067] ;

[0068] When S approaches hour, Approaching 1; when S approaches hour, Close to 0.

[0069] 3. Binding strength (A) subfunction This index obtains the maximum equivalent stress at the interface between the molding compound and the substrate island through simulation. This is used to indirectly characterize (the lower the stress, the more reliable the bond). The goal is to minimize... Set a lower stress limit. and upper limit Its sub-function is defined as:

[0070] ;

[0071] when The smaller, The closer it is to 1, the higher the reliability.

[0072] The final fitness function (F) is the weighted sum of the three normalization subfunctions mentioned above:

[0073] ;

[0074] Where w1, w2, and w3 are weighting coefficients, and w1 + w2 + w3 = 1. The weight values ​​can be adjusted according to the product focus; for example, if the goal is to achieve extremely low resistance, w1 = 0.6, w2 = 0.3, and w3 = 0.1 can be set. The optimization objective is to maximize the fitness function F.

[0075] S4.2, Coding of Design Variables:

[0076] The key structural parameters that need to be optimized are defined as genes in the genetic algorithm. These variables include:

[0077] The thickness of the lead frame base island 1 is set within a search range of [0.40, 0.60] mm.

[0078] The width of the inverted trapezoidal upper base of the first lower slot 5 has a search range of [0.80, 1.50] mm.

[0079] The length of the first lower slot 5 in the y-axis direction is searched within the range of [2.80, 3.20] mm.

[0080] The longitudinal spacing of the first through hole (3) is searched within the range of [1.00, 2.00] mm.

[0081] The horizontal expansion width of the area completion design has a search range of [0.50, 1.50] mm.

[0082] Each individual (i.e., a complete design scheme) is composed of this set of genes.

[0083] S4.3 Execution flow of genetic algorithm:

[0084] Initialization: Randomly generate an initial population containing 100 individuals (i.e., 100 different combinations of parameters).

[0085] Fitness assessment:

[0086] Each individual (parameter combination) is input into the parameterized electromagnetic-thermal-structural multiphysics simulation model.

[0087] The simulation model automatically calculates R, S, and S under this parameter combination. index.

[0088] Calculate the fitness value F for each individual based on the objective function F in S4.1.

[0089] Selection: Using tournament selection, k individuals are randomly selected, and the individual with the highest fitness is selected for the next generation, which can effectively maintain population diversity.

[0090] Crossover: Selected individuals are paired up and simulated binary crossover (SBX) is used to generate new offspring individuals with a certain crossover probability (e.g., 0.8).

[0091] Mutation: Using polynomial mutation, the offspring genes are perturbed with a small mutation probability (e.g., 0.05) to avoid premature convergence.

[0092] Iteration: Repeat steps 2 to 5 until the optimal fitness of the population no longer shows a significant improvement after 50 consecutive generations, or until the preset maximum number of iterations (e.g., 200 generations) is reached.

[0093] S4.4 Optimization Results and Validation:

[0094] After iterative optimization using the genetic algorithm described above, the algorithm converges to an optimal solution set. One of the optimal individual's parameter combinations is as follows:

[0095] Base island thickness: 0.52 mm

[0096] Width of the top edge of the first groove: 1.12 mm

[0097] Length of the first groove in the y direction: 2.98 mm

[0098] Longitudinal spacing of the first through hole: 1.45 mm

[0099] Area completion width: 0.95 mm

[0100] Simulation verification and sample production were conducted on the optimized parameter combination. The final product's on-resistance was measured to be 275 μΩ, and its magnetic sensitivity reached 4.62 GS / A. Furthermore, its excellent anti-delamination capability was verified through thermal cycling tests. The results indicate that the parameters designed using a genetic algorithm in this invention exhibit superior overall performance compared to initial designs based on experience (such as in Example 1).

[0101] The specific embodiments described above further illustrate the purpose, technical solution, and beneficial effects of the present invention. It should be understood that the above description is only a specific embodiment of the present invention and is not intended to limit the scope of protection of the present invention. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the scope of protection of the present invention.

Claims

1. A lead frame structure for a SOW10 package used in a Hall current sensor chip, characterized in that, The first pin group of the SOW10 package consists of two pins, including: The lead frame base island (1) has a thickness greater than that of a conventional SOW16 lead frame base island to compensate for the loss of cross-sectional area of ​​the primary current path caused by the reduction in the number of pins in the first pin group; along the x-axis direction of the lead frame base island (1), the middle part of the lead frame base island (1) is provided with a protrusion extending in the positive y-axis direction, and in the x-axis direction, the two sides of the protrusion are designed to make up for the area; the middle part of the lead frame base island (1) is provided with a first upper slot and a first lower slot (5) for placing two Hall disks of the die along the y-axis direction, the first upper slot is provided on the protrusion, and the first lower slot (5) is an inverted trapezoidal slot whose slot width gradually decreases in the y-axis direction away from the protrusion. The lead frame pins (2) include the first pin group and the second pin group; the first pin group is directly disposed and electrically connected to the lead frame base island (1) and located on the opposite side of the side where the protrusion is located, for passing in and drawing out the primary side current; the second pin group is connected to the die (8) through the lead wire (6); An isolation device (7) is disposed between the die (8) and the lead frame base island (1), and the isolation device (7) completely covers the area where the lead (6) passes through the lead frame base island (1) on the projection plane.

2. The lead frame structure for a SOW10 package of a Hall current sensor chip according to claim 1, characterized in that, The thickness of the lead frame base island (1) is 0.5 mm.

3. The lead frame structure for a SOW10 package of a Hall current sensor chip according to claim 1, characterized in that, Several first through holes (3) are provided in the lead frame base island (1) along the z-axis direction.

4. The lead frame structure for a SOW10 package of a Hall current sensor chip according to claim 1, characterized in that, Several second through holes (4) are provided along the z-axis through several pins of the second pin group, and the edges of the pins of the second pin group are all rounded.

5. The lead frame structure for a SOW10 package of a Hall current sensor chip according to claim 1, characterized in that, The isolation device (7) includes a metal shielding layer (10) and an intermediate dielectric layer (11). In the z-axis direction, the intermediate dielectric layer (11) is located below the metal shielding layer (10), and the metal shielding layer (10) has a second upper slot and a second lower slot (12) in the y-axis direction to avoid the two Hall disks of the die.

6. The lead frame structure for a SOW10 package of a Hall current sensor chip according to claim 5, characterized in that, The intermediate medium layer (11) is made of polyimide (PI).

7. The lead frame structure for a SOW10 package of a Hall current sensor chip according to claim 1, characterized in that, The length of the first lower slot (5) in the y-axis direction is greater than the length of the first upper slot in the y-axis direction.

8. A SOW10 package structure for a Hall current sensor chip, characterized in that, include: The lead frame structure as described in any one of claims 1-7; The core (8) is bonded and fixed to the isolation device (7) with insulating adhesive, and its two Hall disks are respectively located in the areas of the first upper slot, the first lower slot (5) and the second upper slot and the second lower slot (12); A molding compound (9) covers the lead frame structure, the isolation device (7) and the die (8), and the lead frame pins (2) extend out of the molding compound (9); a portion of the molding compound (9) is embedded in the first through hole (3) and / or the second through hole (4).

9. A packaging method for a SOW10 package structure of a Hall current sensor chip as described in claim 8, characterized in that, In the standard SOW10 packaging process, the following steps are performed before the first optical inspection: S1. Prepare the lead frame structure as described in any one of claims 1-7; S2. Use insulating adhesive to bond and fix the isolation device (7) to the designated position of the lead frame base island (1).

10. The packaging method according to claim 9, characterized in that, The curing conditions for the insulating adhesive in step S2 are: curing at a temperature of 150°C to 200°C for 30 to 90 minutes.

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