Semiconductor element and method for forming the same

Abstract

This invention discloses a semiconductor device and a method for forming the same, wherein the semiconductor device includes: a semiconductor substrate; a gate structure located on the semiconductor substrate; a source region and a drain region located in the semiconductor substrate and on opposite sides of the gate structure; a sacrificial oxide layer located on the semiconductor substrate; a contact etch stop layer located on the sacrificial oxide layer; a lower interlayer dielectric layer located on the contact etch stop layer; a high-resistivity dielectric layer located on the gate structure and the lower interlayer dielectric layer; and a high-resistivity field plate, wherein the high-resistivity field plate is at least partially located on the high-resistivity dielectric layer.

Description

Technical Field

[0001] This invention relates to a semiconductor device, and more particularly to a semiconductor device and a method for forming the same. Background Technology

[0002] In semiconductor devices, contact field plates (CFPs) can be used to increase the breakdown voltage (VBD) of high-voltage devices and reduce the resistance (Rdson) between the source and drain when the device is in the on state.

[0003] However, in the drain region of high-voltage components, it is difficult to control the contact field plate that passes through the contact etch stop layer (CESL) to be accurately positioned on the sacrificial oxide layer. Often, the contact field plate will pass through the sacrificial oxide layer because the position of the contact field plate is too low. Therefore, the use of contact field plates is often accompanied by the risk of reduced performance of high-voltage components. Summary of the Invention

[0004] The present invention provides a semiconductor element and a method for forming the same, in order to solve the problem that the performance of high voltage elements is reduced due to the difficulty in accurately controlling the position of the contact field plate.

[0005] This invention provides a semiconductor device comprising: a semiconductor substrate; a gate structure located on the semiconductor substrate; a source region and a drain region located in the semiconductor substrate and on opposite sides of the gate structure; a sacrificial oxide layer located on the semiconductor substrate; a contact etch stop layer located on the sacrificial oxide layer; a lower interlayer dielectric layer located on the contact etch stop layer; a high-resistivity dielectric layer located on the gate structure and the lower interlayer dielectric layer; and a high-resistivity field plate, wherein the high-resistivity field plate is at least partially located on the high-resistivity dielectric layer.

[0006] According to one embodiment of the present invention, the high-resistivity field plate is entirely located on the high-resistivity dielectric layer.

[0007] According to one embodiment of the present invention, another portion of the high-resistivity field plate is located between the high-resistivity dielectric layer and the lower interlayer dielectric layer.

[0008] According to one embodiment of the present invention, the bottom of another portion of the high-resistivity field plate is located directly on the sacrificial oxide layer.

[0009] According to one embodiment of the present invention, the bottom of another portion of the high-resistivity field plate is directly located on the contact etch stop layer.

[0010] According to one embodiment of the present invention, the bottom of another portion of the high-resistivity field plate is located between the contact etch stop layer and the high-resistivity dielectric layer.

[0011] According to one embodiment of the present invention, the device further includes: an upper interlayer dielectric layer located between a high-resistivity dielectric layer and a high-resistivity field plate; a source contact plug located in the upper interlayer dielectric layer, the high-resistivity dielectric layer, the lower interlayer dielectric layer, and the contact etch stop layer, and electrically contacting the source region; a drain contact plug located in the upper interlayer dielectric layer, the high-resistivity dielectric layer, the lower interlayer dielectric layer, and the contact etch stop layer, and electrically contacting the drain region; and a high-voltage component contact plug located in the upper interlayer dielectric layer and electrically contacting the high-resistivity field plate, wherein the high-voltage component contact plug and the drain contact plug are electrically connected by a metal layer.

[0012] According to one embodiment of the present invention, the device further includes: an upper interlayer dielectric layer located between a high-resistivity dielectric layer and a high-resistivity field plate; a source contact plug located in the upper interlayer dielectric layer, the high-resistivity dielectric layer, the lower interlayer dielectric layer, and the contact etch stop layer, and electrically contacting the source region; a drain contact plug located in the upper interlayer dielectric layer, the high-resistivity dielectric layer, the lower interlayer dielectric layer, and the contact etch stop layer, and electrically contacting the drain region; and a high-voltage component contact plug located in the upper interlayer dielectric layer and electrically contacting the high-resistivity field plate, wherein the high-voltage component contact plug and the source contact plug are electrically connected by a metal layer.

[0013] According to one embodiment of the present invention, it further includes: an upper interlayer dielectric layer located between a high-resistivity dielectric layer and a high-resistivity field plate; a source contact plug located in the upper interlayer dielectric layer, the high-resistivity dielectric layer, the lower interlayer dielectric layer and the contact etch stop layer, and electrically contacting the source region; and a drain contact plug located in the upper interlayer dielectric layer, the high-resistivity dielectric layer, the lower interlayer dielectric layer and the contact etch stop layer, and electrically contacting the drain region, wherein the high-resistivity field plate is not electrically connected to the source contact plug or the drain contact plug.

[0014] According to one embodiment of the present invention, the gate structure includes a metal gate.

[0015] According to one embodiment of the present invention, the high-resistivity field plate comprises titanium nitride (TiN).

[0016] This invention proposes a method for forming a semiconductor device, comprising: providing a semiconductor substrate; forming a gate structure on the semiconductor substrate; forming a source region and a drain region in the semiconductor substrate and on opposite sides of the gate structure; forming a sacrificial oxide layer on the semiconductor substrate; forming a contact etch stop layer on the sacrificial oxide layer; forming a lower interlayer dielectric layer on the contact etch stop layer; forming a high-resistivity dielectric layer on the gate structure and the lower interlayer dielectric layer; and forming a high-resistivity field plate, wherein at least a portion of the high-resistivity field plate is located on the high-resistivity dielectric layer, and another portion of the high-resistivity field plate is located in the high-resistivity dielectric layer and the lower interlayer dielectric layer.

[0017] According to one embodiment of the present invention, the bottom of another portion of the high-resistivity field plate is located directly on the sacrificial oxide layer.

[0018] According to one embodiment of the present invention, the bottom of another portion of the high-resistivity field plate is directly located on the contact etch stop layer.

[0019] According to one embodiment of the present invention, the bottom of another portion of the high-resistivity field plate is located between the contact etch stop layer and the high-resistivity dielectric layer.

[0020] According to one embodiment of the present invention, the method further includes: forming an upper interlayer dielectric layer on a high-resistivity dielectric layer and a high-resistivity field plate; forming a source contact plug in the upper interlayer dielectric layer, the high-resistivity dielectric layer, the lower interlayer dielectric layer and the contact etch stop layer, and electrically contacting the source region; forming a drain contact plug in the upper interlayer dielectric layer, the high-resistivity dielectric layer, the lower interlayer dielectric layer and the contact etch stop layer, and electrically contacting the drain region; and forming a high-voltage component contact plug in the upper interlayer dielectric layer and electrically contacting the high-resistivity field plate, wherein the high-voltage component contact plug and the drain contact plug are electrically connected by a metal layer.

[0021] According to one embodiment of the present invention, the method further includes: forming an upper interlayer dielectric layer on a high-resistivity dielectric layer and a high-resistivity field plate; forming a source contact plug in the upper interlayer dielectric layer, the high-resistivity dielectric layer, the lower interlayer dielectric layer and the contact etch stop layer, and electrically contacting the source region; forming a drain contact plug in the upper interlayer dielectric layer, the high-resistivity dielectric layer, the lower interlayer dielectric layer and the contact etch stop layer, and electrically contacting the drain region; and forming a high-voltage component contact plug in the upper interlayer dielectric layer and electrically contacting the high-resistivity field plate, wherein the high-voltage component contact plug and the source contact plug are electrically connected by a metal layer.

[0022] According to one embodiment of the present invention, the method further includes: forming an upper interlayer dielectric layer on a high-resistivity dielectric layer and a high-resistivity field plate; forming a source contact plug in the upper interlayer dielectric layer, the high-resistivity dielectric layer, the lower interlayer dielectric layer and the contact etch stop layer, and electrically contacting the source region; and forming a drain contact plug in the upper interlayer dielectric layer, the high-resistivity dielectric layer, the lower interlayer dielectric layer and the contact etch stop layer, and electrically contacting the drain region, wherein the high-resistivity field plate is not electrically connected to the source contact plug or the drain contact plug.

[0023] According to one embodiment of the present invention, the gate structure includes a metal gate.

[0024] According to one embodiment of the present invention, the high-resistivity field plate comprises titanium nitride (TiN).

[0025] Based on the above, in the semiconductor device proposed in this invention, replacing the traditional contact field plate with a high-resistivity field plate can not only solve the problem of the high voltage device performance being reduced due to the difficulty in controlling the position of the contact field plate, but also increase the breakdown voltage of the high voltage device and reduce Rdson.

[0026] Furthermore, the semiconductor device formation method proposed in this invention has advantages such as compatibility with high-k metal gate (HKMG) fabrication processes and the ability to form the aforementioned semiconductor devices without additional masks.

[0027] Furthermore, the aforementioned semiconductor devices and their formation methods can also be applied to various advanced manufacturing processes, such as high-k metal gate planar field-effect transistors (HKMG planar FETs), fin field-effect transistors (FinFETs), and gate-all-around nanosheets (GAA nanosheets).

[0028] To make the above features and advantages of the present invention more apparent and understandable, specific embodiments are described below in conjunction with the accompanying drawings. Attached Figure Description

[0029] Figures 1A to 1J This is a flow cross-sectional view of a method for forming a semiconductor element according to an embodiment of the present invention;

[0030] Figure 2 This is a cross-sectional view of a semiconductor device according to an embodiment of the present invention;

[0031] Figure 3 This is a cross-sectional view of a semiconductor element according to another embodiment of the present invention;

[0032] Figure 4 This is a cross-sectional view of a semiconductor element according to another embodiment of the present invention;

[0033] Figures 5A to 5B This is a flow cross-sectional view of a method for forming a semiconductor element according to another embodiment of the present invention;

[0034] Figure 6 This is a cross-sectional view of a semiconductor element according to another embodiment of the present invention;

[0035] Figure 7 This is a cross-sectional view of a semiconductor element according to another embodiment of the present invention;

[0036] Figure 8This is a cross-sectional view of a semiconductor element according to another embodiment of the present invention;

[0037] Figures 9A to 9B This is a flow cross-sectional view of a method for forming a semiconductor element according to another embodiment of the present invention;

[0038] Figure 10 This is a cross-sectional view of a semiconductor element according to another embodiment of the present invention;

[0039] Figure 11 This is a cross-sectional view of a semiconductor element according to another embodiment of the present invention;

[0040] Figure 12 This is a cross-sectional view of a semiconductor element according to another embodiment of the present invention;

[0041] Figures 13A to 13B This is a flow cross-sectional view of a method for forming a semiconductor element according to another embodiment of the present invention;

[0042] Figure 14 This is a cross-sectional view of a semiconductor element according to another embodiment of the present invention;

[0043] Figure 15 This is a cross-sectional view of a semiconductor element according to another embodiment of the present invention;

[0044] Figure 16 This is a cross-sectional view of a semiconductor element according to another embodiment of the present invention.

[0045] Symbol Explanation

[0046] 100: Semiconductor substrate

[0047] 110: Isolation Zone

[0048] 120: Trap Injection Region

[0049] 130: High-voltage lightly doped drain region

[0050] 140, 140': Dummy gate structure

[0051] 142: Dielectric layer

[0052] 144: High dielectric constant layer

[0053] 146: Nitride layer

[0054] 148: Dummy gate layer, dummy gate

[0055] 150: Hard mask layer, patterned hard mask

[0056] 160: Lightly doped drain region

[0057] 170: Mesophyllary layer

[0058] 180: Sacrificial oxide layer

[0059] 192: N+ doped region

[0060] 194: P+ doped region

[0061] 200: Metal silicide layer

[0062] 210: Contact Etching Stop Layer

[0063] 220: Lower interlayer dielectric layer

[0064] 230, 230': Gate structure

[0065] 232: Metal gate

[0066] 240: High-resistivity dielectric layer

[0067] 250, 250B: High resistivity layer

[0068] 250C: High-resistivity MOSFET

[0069] 260: Upper interlayer dielectric layer

[0070] 270: Contact plug

[0071] 270S: Source Contact Plug

[0072] 270D: Drain Contact Plug

[0073] 270B: High-resistance component contact plug

[0074] 270C: High-voltage component contact plug

[0075] A: Core components

[0076] B: High resistance components

[0077] B1, B2, B3: Bottom

[0078] C, C1, C2, C3, D, D1, D2, D3, E, E1, E2, E3, F, F1, F2, F3: High-voltage components

[0079] D: Drain region

[0080] MCD, MCS, MD, MS: Metallic layer

[0081] S: Source region

[0082] T1, T2, T3: Trench Detailed Implementation

[0083] The following examples are described in detail with reference to the accompanying drawings, but the examples provided are not intended to limit the scope of the invention.

[0084] For ease of understanding, the same components will be indicated by the same symbols in the following descriptions, and will not be repeated in the following paragraphs.

[0085] Furthermore, the accompanying drawings are for illustrative purposes only and are not drawn to their original dimensions. In fact, for clarity of explanation, the dimensions of various features may be increased or decreased as appropriate.

[0086] Furthermore, for ease of description, the terms "above," "below," and similar spatial relative terms are used herein to describe the relative relationship between one component and another as shown in the accompanying drawings, and are not intended to limit the invention. Therefore, it should be understood that "above" and "below" are used interchangeably, and when a component is located "above" another component, the component may be placed directly on the other component, or there may be an intermediate component. On the other hand, when a component is said to be placed "directly" on another component, there is no intermediate component between them.

[0087] The terminology used herein is for illustrative purposes only and is not intended to limit the invention. In this context, the singular form includes the plural form unless the context otherwise requires.

[0088] The various manufacturing steps described below include applications such as deposition processes, removal processes, and patterning processes.

[0089] The deposition process refers to the process of forming one material onto another material, which may include, but is not limited to, spin coating, sputtering, chemical vapor deposition (CVD), physical vapor deposition (PVD), plasma-enhanced chemical vapor deposition (PE-CVD), atomic layer deposition (ALD), molecular beam deposition (MBD), pulsed laser deposition (PLD), and liquid source misted chemical deposition (LSMCD).

[0090] Removal processes may include, but are not limited to, wet etching, dry etching, chemical mechanical planarization (CMP), etc.

[0091] Patterning processes include techniques that use photolithography and etching to transfer layout patterns from a mask to a material layer.

[0092] First, to illustrate that the semiconductor element formation method of the present invention has the advantage of being compatible with the high-k metal gate (HKMG) fabrication process, the semiconductor element formation method described below is illustrated by taking the formation of high voltage elements C, C1, C2, C3, D, D1, D2, D3, E, E1, E2, E3, F, F1, F2, and F3 on a semiconductor substrate 100, and simultaneously forming a core element A and a high-resistance element B at different locations. However, the actual application is not limited to these elements.

[0093] Furthermore, the description of this invention uses high-voltage components C, C1, C2, C3, D, D1, D2, D3, E, E1, E2, E3, F, F1, F2, and F3 as examples, but its application is not limited to these. Instead, it can be applied to various advanced manufacturing processes, such as high-k metal gate planar field-effect transistors (HKMGplanar FETs), fin field-effect transistors (FinFETs), and gate-all-around nanosheets (GAA nanosheets).

[0094] Please see Figure 1A Depending on the different requirements of the core component A, the high-resistance component B, and the high-voltage component C, isolation regions 100 of various sizes and spacings are formed in the semiconductor substrate 100.

[0095] In some embodiments, the isolation zone 100 may be an isolation structure such as shallow trench isolation (STI), but is not limited thereto.

[0096] Next, please refer to Figure 1BDepending on the requirements, ion implantation of the semiconductor substrate 100 of the core element A, high-resistivity element B, and high-voltage element C can be performed simultaneously or separately at various energies and ranges. For example, ion implantation of the semiconductor substrate 100 of the core element A, high-resistivity element B, and high-voltage element C with relatively large energy and range can be performed simultaneously to form a trap implantation region 120; then, ion implantation of the semiconductor substrate 100 of the high-voltage element C with relatively small energy and range can be performed only to form a high-voltage lightly doped drain region 130, but this is not limited to this.

[0097] Please see Figure 1C The dielectric layer 142 can be formed on the core component A and the high-voltage component C first. Then, a high dielectric constant layer 144, a nitride layer 146, a dummy gate layer 148 and a hard mask layer 150 are stacked sequentially in the core component A, the high-resistivity component and the high-voltage component C.

[0098] In some embodiments, the nitride layer 146 may include a material such as titanium nitride (TiN).

[0099] Next, please refer to... Figure 1C The hard mask layer 150 is patterned according to the layout pattern to form a patterned hard mask 150. Then, based on this patterned hard mask 150, the dummy gate layer 148, nitride layer 146, high dielectric constant layer 144, and dielectric layer 142 of the core element A and the high voltage element C are etched to define a dummy gate structure 140 including the dummy gate 148 on the semiconductor substrate 100 between the isolation regions 110. At the same time, based on this patterned hard mask 150, the dummy gate layer 148, nitride layer 146, and high dielectric constant layer 144 of the high resistance element B are etched to define a dummy gate structure 140' including the dummy gate 148 on the semiconductor substrate 100 of the isolation region 110.

[0100] To make the accompanying symbols concise and easy to understand, the descriptions of each material layer of the gate etching above are labeled with the same reference numerals.

[0101] Please refer to Figure 1C If necessary, a lightly doped drain (LDD) region 160 may be formed in the well injection region 120 of the core element A and the high-voltage element C. If necessary, a spacer layer 170 may be formed on the sidewalls of the dummy gate structure 140 of the core element A and the high-voltage element C and on the sidewalls of the dummy gate structure 140' of the high-resistance element B.

[0102] Next, a sacrificial oxide layer 180 is formed on the semiconductor substrate 100 of the high-voltage device C. This sacrificial oxide layer 180 may, for example, be formed on a portion of the high-voltage lightly doped drain region 130 of the high-voltage device C, on the side of the partition layer 170 near the high-voltage lightly doped drain region 130, and on the top portion of the dummy gate structure 140, such as... Figure 1D As shown.

[0103] Next, please refer to [link / reference]. Figure 1D Source / drain implantation can be performed on core element A, high-resistance element B, and high-voltage element C to form source region S and drain region D in semiconductor substrate 100 and on opposite sides of dummy gate structures 140 and 140'. For example, N+ type ion implantation can be performed on the lightly doped drain region 160 of core element A, the lightly doped drain region 160 of high-voltage element C, and the high-voltage lightly doped drain region 130, and P+ type ion implantation can be performed on the well implantation region 120 of high-resistance element B to form source region S and drain region D.

[0104] Please refer to Figure 1D Depending on the requirements, a series of fabrication processes and reactions can be selectively performed on the source region S and drain region D of the core component A, high-resistance component B, and high-voltage component C to form a metal silicide layer 200 on the surface of the source region S and drain region D, thereby reducing the contact resistance of the source region S and drain region D. This ensures that when the subsequent contact plug is electrically connected to the source region S and drain region D, the component characteristics will not be degraded due to the increase in series resistance.

[0105] Please refer to the following. Figure 1E First, the patterned hard mask 150 of the core component A, high-resistance component B and high-voltage component C is removed, and the top of the partition layer 170 is made to be on the same plane as the top of the dummy gate 148.

[0106] Then, a contact etch stop layer (CESL) 210 is conformally formed on the core component A, the high-resistance component B, and the high-voltage component C to protect the components from etching damage during the subsequent formation of contact vias.

[0107] In the high-voltage component C, at least a partial contact etch stop layer 210 is located on the sacrificial oxide layer 180.

[0108] Next, a lower interlayer dielectric layer 220 is formed on the contact etch stop layer 210, such as... Figure 1E As shown.

[0109] Please also refer to Figure 1E and Figure 1FThe core component A, high-resistance component B, and high-voltage component C are planarized using methods such as chemical mechanical polishing (CMP) to make the top of the lower interlayer dielectric layer 220, contact etch stop layer 210, partition layer 170, and dummy gate 148 coplanar.

[0110] Next, the dummy gate 148 is removed, and a metal gate 232 is formed in the same location thereon, so that a gate structure 230 including the metal gate 232 and located on the semiconductor substrate 100 is formed on the core element A and the high-voltage element C, and a gate structure 230' including the metal gate 232 and located on the semiconductor substrate 100 is formed on the high-resistance element B. Figure 1F As shown, the gate structure 230 of the core element A and the high voltage element C may sequentially include a dielectric layer 142, a high dielectric constant layer 144, a nitride layer 146 and a metal gate 232; the gate structure 230' of the high resistance element B may sequentially include a high dielectric constant layer 144, a nitride layer 146 and a metal gate 232.

[0111] Then, as Figure 1G As shown, in the core element A, the high-resistivity element B and the high-voltage element C, a high-resistivity dielectric layer 240 is formed comprehensively on the gate structures 230, 230' and the lower interlayer dielectric layer 220.

[0112] For example Figure 1H As shown, a high-resistance layer 250 is comprehensively used in the core component A, the high-resistance component B, and the high-voltage component C. The high-resistance layer 250 can be a high-resistance material such as titanium nitride (TiN), but is not limited to this.

[0113] like Figure 1I As shown, the high-resistivity layer 250 is patterned by photolithography or other methods to form the required high-resistivity layer 250B and high-resistivity field plate 250C at the high-resistivity element B and the high-voltage element C, respectively.

[0114] Then, as Figure 1J As shown, an upper interlayer dielectric layer 260 is formed on the high-resistance dielectric layer 240 of the core component A, the high-resistance dielectric layer 240 and the high-resistance layer 250B of the high-resistance component B, and the high-resistance dielectric layer 240 and the high-resistance field plate 250C of the high-voltage component C.

[0115] Then, as before Figure 1J As shown, contact plugs 270 can be formed in core component A, high-resistance component B, and high-voltage component C using various photolithography etching methods.

[0116] These contact plugs 270 may be included in the core element A, the high-resistivity element B, and the high-voltage element C, located in the upper interlayer dielectric layer 260, the high-resistivity dielectric layer 240, the lower interlayer dielectric layer 220, and the contact etch stop layer 210 as source contact plugs 270S and drain contact plugs 270D, respectively. These source contact plugs 270S and drain contact plugs 270D are electrically connected to the source region S and drain region D of the core element A, the high-resistivity element B, and the high-voltage element C, respectively. Figure 1J As shown.

[0117] Furthermore, these contact plugs 270 may also include a high-resistance element contact plug 270B located in the upper interlayer dielectric layer 260 within the high-resistance element B, and this high-resistance element contact plug 270B is in electrical contact with the high-resistance layer 250B of the high-resistance element B, such as... Figure 1J As shown.

[0118] Furthermore, these contact plugs 270 may also include high-voltage component contact plugs 270C located in the upper interlayer dielectric layer 260 within the high-voltage component C, and these high-voltage component contact plugs 270C are in electrical contact with the high-resistivity field plate 250C of the high-voltage component C, such as... Figure 1J As shown. Alternatively, it is also possible to choose not to form a high-voltage component contact plug 270C (not shown).

[0119] The following will be as follows Figure 1J A patterned metal layer is formed on the contact plug 270 of the core component A, high-resistance component B, and high-voltage component C shown. To focus on the semiconductor element of this invention and its formation, the following description pertains only to... Figure 1J The subsequent fabrication process of the high-voltage component C shown is explained, especially the design for electrical connection of the high-resistivity field plate 250C which is located entirely on the high-resistivity dielectric layer 240.

[0120] in Figure 2 The high-voltage component C1 has a metal layer MS formed on the source contact plug 270S and a metal layer MCD formed on the high-voltage component contact plug 270C and the drain contact plug 270D. In other words, the high-voltage component contact plug 270C and the drain contact plug 270C are electrically connected by the metal layer MCD.

[0121] in Figure 3 The high-voltage component C2 has a metal layer MCS formed on the high-voltage component contact plug 270C and the source contact plug 270S, and a metal layer MD formed on the drain contact plug 270D. In other words, the high-voltage component contact plug 270C and the source contact plug and 270S are electrically connected by the metal layer MCS.

[0122] in Figure 4 The high-voltage component C3, as mentioned above, is not in Figure 1JThe illustration shows that when the source contact plug 270S and drain contact plug 270D are only formed in the high voltage element C, and the high voltage element contact plug 270C is not formed therein, the metal layer MC and the metal layer MD are formed on the source contact plug 270S and the drain contact plug 270D respectively. That is, the high resistance field plate 250C is not electrically connected to the source contact plug 270S or the drain contact plug 270D.

[0123] That is, as Figure 1J The high-voltage component C shown can be manufactured as follows: Figure 2 The high-voltage component C1, which is electrically connected to the high-resistivity field plate 250C and the drain region D, is fabricated as shown. Figure 3 The high-resistivity field plate 250C shown is electrically connected to the source D, and the high-voltage component C2 is fabricated as follows. Figure 4 The high-resistivity field plate 250C shown represents three different high-voltage components of the high-voltage component C3 in a floating state. Since the high-resistivity field plate 250C of these three high-voltage components C1, C2, and C3 is located on the high-resistivity dielectric layer 240 and has a certain distance from the sacrificial oxide layer 180, it will not penetrate the contact etch stop layer 180 during the formation of the high-resistivity field plate 250C, thus preventing damage to the high-voltage component C1. Furthermore, as mentioned above, its formation method is compatible with the fabrication process of high-k metal gate (HKMG) and can be completed without additional masks.

[0124] In addition to the high-resistivity field plate 250C that is entirely located on the high-resistivity dielectric layer 240, it is also possible to perform, for example Figures 1A to 1G After the fabrication process, high-resistivity dielectric layer 240 and lower interlayer dielectric layer 220 can be formed respectively as shown in the figure. Figure 5A The high-voltage component D shown is shown. Figure 9A The high-voltage component E shown is... Figure 13A The high-voltage component F shown contains trenches T1, T2, and T3, and the bottoms B1, B2, and B3 of these trenches T1, T2, and T3 are respectively located on the sacrificial oxide layer 180, the contact etch stop layer 210, and between the contact etch stop layer 210 and the high-resistivity dielectric layer 240. Then, a trench-type high-resistivity field plate 250C is formed on the bottom, sidewalls, and top of the trenches T1, T2, and T3, as shown. Figure 5A , Figure 9A and Figure 13A As shown.

[0125] That is, such as Figure 5A The bottom B1 of the high-resistivity field plate 250C of the high-voltage component D shown is directly located on the sacrificial oxide layer 180; Figure 9AThe bottom B2 of the high-resistivity field plate 250C of the high-voltage component E shown is directly located on the etch stop layer 210; Figure 13A The bottom B3 of the high-resistivity field plate 250C of the high-voltage component F shown is located between the contact etch stop layer 210 and the high-resistivity dielectric layer 240.

[0126] Then, in a similar way Figure 1J To form as shown Figure 5B , Figure 9B and Figure 13B The diagram shows an upper interlayer dielectric layer 260, a source contact plug 270S, a high-voltage component contact plug 270C, and a drain contact plug 270D, wherein there may be more than one high-voltage component contact plug 270C. Alternatively, as described above, only the upper interlayer dielectric layer 260, the source contact plug 270S, and the drain contact plug 270D may be formed as needed, without forming the high-voltage component contact plug 270C.

[0127] Next, please refer to the following: Figure 5B and Figures 6-8 Its utilization relative to Figure 1J and Figures 2-4 The manufacturing process, specifically the design for electrically connecting the high-resistivity field plate 250C directly on the sacrificial oxide layer 180 at the bottom B1, forms a high-voltage component D1 electrically connected to the high-voltage component contact plug 270C and the drain contact plug 270C via a metal layer MCD. Figure 6 As shown; or, a high-voltage component D2, forming a high-voltage component contact plug 270C and a source contact plug 270S electrically connected by a metal layer MCS, such as Figure 7 As shown; or, metal layers MC and MD are formed only on the source contact plug 270S and drain contact plug 270D respectively, and the high-resistivity field plate 250C is not electrically connected to the source contact plug 270S or drain contact plug 270D, so that the high-resistivity field plate 250C is in a floating state as a high-voltage component D3, such as... Figure 8 As shown.

[0128] Alternatively, please also refer to Figure 9B and Figures 10-12 Its utilization relative to Figure 1J and Figures 2-4 The manufacturing process, specifically the design for electrically connecting the high-resistivity field plate 250C directly located on the contact etch stop layer 210 at the bottom B2, forms a high-voltage component E1 electrically connected to the high-voltage component contact plug 270C and the drain contact plug 270C via a metal layer MCD, such as... Figure 10 As shown; or, a high-voltage component E2, which forms a high-voltage component contact plug 270C and a source contact plug 270S electrically connected by a metal layer MCS, such as Figure 11As shown; or, metal layers MC and MD are formed only on the source contact plug 270S and drain contact plug 270D respectively, and the high-resistivity field plate 250C is not electrically connected to the source contact plug 270S or drain contact plug 270D, so that the high-resistivity field plate 250C presents as a floating high-voltage component E3, such as Figure 12 As shown.

[0129] Alternatively, please also refer to Figure 13B and Figures 14-16 Its utilization relative to Figure 1J and Figures 2-4 The manufacturing process involves an electrical connection between the bottom B3 and the high-resistivity field plate 250C located between the contact etch stop layer 210 and the high-resistivity dielectric layer 240. This results in a high-voltage component F1 formed by electrically connecting the high-voltage component contact plug 270C and the drain contact plug 270C via a metal layer MCD. Figure 14 As shown; or, a high-voltage component F2, which forms a high-voltage component contact plug 270C and a source contact plug 270S electrically connected by a metal layer MCS, such as Figure 15 As shown; or, metal layers MC and MD are formed only on the source contact plug 270S and drain contact plug 270D respectively, and the high-resistivity field plate 250C is not electrically connected to the source contact plug 270S or drain contact plug 270D, so that the high-resistivity field plate 250C presents as a floating high-voltage component F3, such as... Figure 16 As shown.

[0130] The high-voltage components D1, D2, D3, E1, E2, E3, F1, F2, and F3 with the aforementioned trench-type high-resistivity field plate 250C have a larger process window at their bottom edges B1, B2, and B3. Compared to contact field plates, they have a smaller chance of penetrating the sacrificial oxide layer 180 during manufacturing, thus reducing the likelihood of performance degradation issues associated with using contact field plates. Furthermore, because the trench-type high-resistivity field plate 250C can compress a high-resistivity field plate 250C of a specific length into a smaller space than a high-resistivity field plate 250C formed only on the high-resistivity dielectric layer 240, the component pitch can be reduced, achieving the goal of forming even smaller components.

[0131] In summary, the semiconductor device of the present invention replaces the traditional contact field plate with a high-resistivity field plate, which not only solves the problem of reduced performance of high-voltage devices caused by the difficulty in controlling the position of the contact field plate, but also increases the breakdown voltage of high-voltage devices and reduces Rdson.

[0132] Furthermore, the semiconductor device formation method proposed in this invention has the advantages of being compatible with high-k metal gate (HKMG) fabrication processes and being able to form the aforementioned semiconductor devices without additional masks.

[0133] Furthermore, the aforementioned semiconductor devices and their formation methods can also be applied to various advanced manufacturing processes, such as high-k metal gate planar field-effect transistors (HKMG planar FETs), fin field-effect transistors (FinFETs), and gate-all-around nanosheets (GAA nanosheets).

[0134] Although the present invention has been disclosed above by way of embodiments, it is not intended to limit the present invention. Any person skilled in the art can make some modifications and refinements without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention shall be defined by the appended claims.

Claims

1. A semiconductor element, comprising: Semiconductor substrate; A gate structure is located on the semiconductor substrate; The source and drain regions are located in the semiconductor substrate and on opposite sides of the gate structure; A sacrificial oxide layer is located on the semiconductor substrate; A contact etch stop layer is located on the sacrificial oxide layer; The lower interlayer dielectric layer is located on the contact etch stop layer; A high-resistivity dielectric layer is located on the gate structure and the lower interlayer dielectric layer; and A high-resistivity field plate, wherein the high-resistivity field plate is at least partially located on the high-resistivity dielectric layer.

2. The semiconductor device of claim 1, wherein the high-resistivity field plate is entirely located on the high-resistivity dielectric layer.

3. The semiconductor device of claim 1, wherein another portion of the high-resistivity field plate is located between the high-resistivity dielectric layer and the lower interlayer dielectric layer.

4. The semiconductor device of claim 3, wherein the bottom of the other portion of the high-resistivity field plate is directly located on the sacrificial oxide layer.

5. The semiconductor device of claim 3, wherein the bottom of the other portion of the high-resistivity field plate is directly located on the contact etch stop layer.

6. The semiconductor device of claim 3, wherein the bottom of the other portion of the high-resistivity field plate is located between the contact etch stop layer and the high-resistivity dielectric layer.

7. The semiconductor device of claim 1, further comprising: The upper interlayer dielectric layer is located between the high-resistivity dielectric layer and the high-resistivity field plate; The source contact plug is located in the upper interlayer dielectric layer, the high-resistivity dielectric layer, the lower interlayer dielectric layer and the contact etch stop layer, and is in electrical contact with the source region; The drain contact plug is located in the upper interlayer dielectric layer, the high-resistivity dielectric layer, the lower interlayer dielectric layer and the contact etch stop layer, and is in electrical contact with the drain region; as well as The high-voltage component contact plug is located in the upper interlayer dielectric layer and is in electrical contact with the high-resistivity field plate. The high-voltage component contact plug and the drain contact plug are electrically connected by a metal layer.

8. The semiconductor device of claim 1, further comprising: The upper interlayer dielectric layer is located between the high-resistivity dielectric layer and the high-resistivity field plate; The source contact plug is located in the upper interlayer dielectric layer, the high-resistivity dielectric layer, the lower interlayer dielectric layer and the contact etch stop layer, and is in electrical contact with the source region; The drain contact plug is located in the upper interlayer dielectric layer, the high-resistivity dielectric layer, the lower interlayer dielectric layer and the contact etch stop layer, and is in electrical contact with the drain region; as well as The high-voltage component contact plug is located in the upper interlayer dielectric layer and is in electrical contact with the high-resistivity field plate. The high-voltage component contact plug and the source contact plug are electrically connected by a metal layer.

9. The semiconductor device of claim 1, further comprising: The upper interlayer dielectric (ILD) layer is located between the high-resistivity dielectric layer and the high-resistivity field plate; A source contact plug is located in the upper interlayer dielectric layer, the high-resistivity dielectric layer, the lower interlayer dielectric layer, and the contact etch stop layer, and is in electrical contact with the source region; and The drain contact plug is located in the upper interlayer dielectric layer, the high-resistivity dielectric layer, the lower interlayer dielectric layer, and the contact etch stop layer, and is in electrical contact with the drain region. The high-resistivity field plate is not electrically connected to the source contact plug or the drain contact plug.

10. The semiconductor device of claim 1, wherein the gate structure comprises a metal gate.

11. The semiconductor device of claim 1, wherein the high-resistivity field plate comprises titanium nitride (TiN).

12. A method for forming a semiconductor device, comprising: Provide semiconductor substrates; A gate structure is formed on the semiconductor substrate; Source and drain regions are formed in the semiconductor substrate and on opposite sides of the gate structure; A sacrificial oxide layer is formed on the semiconductor substrate; A contact etch stop layer is formed on the sacrificial oxide layer; A lower interlayer dielectric layer is formed on the contact etch stop layer; A high-resistivity dielectric layer is formed on the gate structure and the lower interlayer dielectric layer; as well as A high-resistivity field plate is formed, wherein at least a portion of the high-resistivity field plate is located on the high-resistivity dielectric layer, and another portion of the high-resistivity field plate is located between the high-resistivity dielectric layer and the lower interlayer dielectric layer.

13. The method of forming a semiconductor element as claimed in claim 12, wherein the bottom of the other portion of the high-resistivity field plate is directly located on the sacrificial oxide layer.

14. The method of forming a semiconductor element as claimed in claim 12, wherein the bottom of the other portion of the high-resistivity field plate is directly located on the contact etch stop layer.

15. The method of forming a semiconductor element as claimed in claim 12, wherein the bottom of the other portion of the high-resistivity field plate is located between the contact etch stop layer and the high-resistivity dielectric layer.

16. The method for forming a semiconductor element as claimed in claim 12, further comprising: An upper interlayer dielectric layer is formed on the high-resistivity dielectric layer and the high-resistivity field plate; A source contact plug is formed in the upper interlayer dielectric layer, the high-resistivity dielectric layer, the lower interlayer dielectric layer and the contact etch stop layer, and is electrically in contact with the source region; A drain contact plug is formed in the upper interlayer dielectric layer, the high-resistivity dielectric layer, the lower interlayer dielectric layer and the contact etch stop layer, and is electrically in contact with the drain region; as well as High-voltage component contact plugs are formed in the upper interlayer dielectric layer and make electrical contact with the high-resistivity field plate. The high-voltage component contact plug and the drain contact plug are electrically connected by a metal layer.

17. The method for forming a semiconductor element as claimed in claim 12, further comprising: An upper interlayer dielectric layer is formed on the high-resistivity dielectric layer and the high-resistivity field plate; A source contact plug is formed in the upper interlayer dielectric layer, the high-resistivity dielectric layer, the lower interlayer dielectric layer and the contact etch stop layer, and is electrically in contact with the source region; A drain contact plug is formed in the upper interlayer dielectric layer, the high-resistivity dielectric layer, the lower interlayer dielectric layer and the contact etch stop layer, and is electrically in contact with the drain region; as well as High-voltage component contact plugs are formed in the upper interlayer dielectric layer and make electrical contact with the high-resistivity field plate. The high-voltage component contact plug and the source contact plug are electrically connected by a metal layer.

18. The method for forming a semiconductor element as claimed in claim 12, further comprising: An upper interlayer dielectric layer is formed on the high-resistivity dielectric layer and the high-resistivity field plate; A source contact plug is formed in the upper interlayer dielectric layer, the high-resistivity dielectric layer, the lower interlayer dielectric layer and the contact etch stop layer, and is electrically in contact with the source region; as well as A drain contact plug is formed in the upper interlayer dielectric layer, the high-resistivity dielectric layer, the lower interlayer dielectric layer, and the contact etch stop layer, and makes electrical contact with the drain region. The high-resistivity field plate is not electrically connected to the source contact plug or the drain contact plug.

19. The method of forming a semiconductor device as claimed in claim 12, wherein the gate structure comprises a metal gate.

20. The method of forming a semiconductor element as claimed in claim 12, wherein the high-resistivity field plate comprises titanium nitride (TiN).

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