Semiconductor device and method of manufacturing the same

Abstract

Embodiments of the present application disclose a semiconductor device and a manufacturing method thereof. The semiconductor device comprises a substrate, a channel layer on the substrate, a barrier layer on the channel layer, a two-dimensional electron gas generated at an interface between the channel layer and the barrier layer, a gate structure on the barrier layer, an insulating structure covering the gate structure and covering an upper surface of the barrier layer adjacent to the gate structure, a barrier layer comprising a first part covering the insulating structure and a second part at least partially covering the exposed upper surface of the barrier layer, and a source structure and a drain structure on two sides of the gate structure.

Description

Technical Field

[0001] This application relates to the field of semiconductor device technology, specifically to a semiconductor device and a method for manufacturing a semiconductor device. Background Technology

[0002] High electron mobility transistors (HEMTs), especially AlGaN / GaN HEMTs based on gallium nitride (GaN) wide bandgap semiconductor materials, have become the mainstream choice for next-generation high-frequency, high-efficiency power switching devices due to their advantages such as high breakdown electric field, high electron mobility and high two-dimensional electron gas (2DEG) concentration. They are widely used in consumer electronics fast charging, server power supplies, electric vehicle on-board chargers and industrial power supplies.

[0003] In practical applications of power HEMT devices, the switching speed and voltage levels are constantly increasing, which places higher demands on the reliability and anti-interference capabilities of the devices. However, in the layout design of existing HEMT devices, there is a problem that has not been given sufficient attention and seriously affects the reliability of the devices: the parasitic coupling effect of the high-voltage metal trace above the gate to the gate.

[0004] How to effectively suppress the parasitic coupling effect of the high-voltage metal trace above the gate to the gate and reduce the risk of gate voltage overshoot has become a technical problem that urgently needs to be solved by those skilled in the art. Summary of the Invention

[0005] This invention provides a semiconductor device and a method for manufacturing the same, in order to solve the problems existing in the prior art.

[0006] According to a first aspect of the present invention, a semiconductor device is provided, comprising: a substrate; a channel layer located on the substrate; a barrier layer located on the channel layer, wherein a two-dimensional electron gas is generated at the interface between the channel layer and the barrier layer; a gate structure located on the barrier layer; an insulating structure covering the gate structure and covering an upper surface of the barrier layer adjacent to the gate structure; a barrier layer including a first portion covering the insulating structure and a second portion at least partially covering the exposed upper surface of the barrier layer; and a source structure and a drain structure located on opposite sides of the gate structure.

[0007] Preferably, the bandgap width of the barrier layer is greater than the bandgap width of the channel layer.

[0008] Preferably, the material of the barrier layer is a group III-V compound.

[0009] Preferably, the barrier layer is configured as a continuous, integral structure.

[0010] Preferably, the first and second portions of the barrier layer are made of different materials.

[0011] Preferably, the insulating structure comprises at least one material.

[0012] Preferably, the insulating structure comprises alternating layers of silicon oxide and silicon nitride.

[0013] Preferably, the thickness of the insulating structure located above the top surface of the gate structure is set to 0.1-1 μm.

[0014] Preferably, the width of the insulating structure located on one side of the gate structure and covering the barrier layer is set to 10-100 nm.

[0015] Preferably, the barrier layer is separated from both the source structure and the drain structure.

[0016] Preferably, the barrier layer is in contact with the source structure and the drain structure.

[0017] Preferably, the edge of the insulating structure near the drain structure includes a transition region.

[0018] Preferably, the transition region has one of the following shapes: stepped, inclined, inner arc, or outer arc.

[0019] Preferably, the materials of the channel layer and the barrier layer are set as group III nitrides.

[0020] Preferably, the source-drain structure extends into the channel layer.

[0021] According to a second aspect of the present invention, a method for manufacturing a semiconductor device is provided, comprising: providing a substrate; forming a channel layer on the substrate; forming a barrier layer on the channel layer and generating a two-dimensional electron gas at the interface between the channel layer and the barrier layer; forming a gate structure on the barrier layer; forming an insulating structure that covers the gate structure and covers an upper surface of the barrier layer adjacent to the gate structure; forming a barrier layer that includes a first portion covering the insulating structure and a second portion at least partially covering the exposed upper surface of the barrier layer; and forming a source structure and a drain structure on both sides of the gate structure.

[0022] Preferably, the barrier layer is formed by a one-step deposition process.

[0023] Preferably, the barrier layer is formed by a two-step deposition process, wherein the first and second parts of the barrier layer are made of different materials.

[0024] Preferably, the bandgap width of the barrier layer is greater than the bandgap width of the channel layer.

[0025] Preferably, the insulating structure comprises at least one material.

[0026] Preferably, the insulating structure comprises alternating layers of silicon oxide and silicon nitride.

[0027] Preferably, the edge of the insulating structure near the drain structure includes a transition region.

[0028] The semiconductor device provided in this application, by providing a barrier layer that covers the gate structure and at least partially covers the exposed barrier layer, can adjust the two-dimensional electron gas concentration between the gate and drain to reduce the on-resistance, while also improving the dielectric strength around the gate to prevent the gate from being affected by the high-voltage metal traces above, and can also improve the gate's withstand voltage capability at the same time.

[0029] The semiconductor device manufacturing method provided in this application forms the barrier layer through a one-step deposition process, which not only simplifies the process and reduces process costs, but also achieves the effects of protecting the gate structure and regulating the channel electron concentration. Attached Figure Description

[0030] The above and other objects, features, and advantages of this application will become clearer from the following description of embodiments with reference to the accompanying drawings, in which:

[0031] Figure 1 This is a cross-sectional schematic diagram of the semiconductor device according to Embodiment 1 of this application;

[0032] Figure 2 This is a cross-sectional schematic diagram of the semiconductor device according to Embodiment 2 of this application;

[0033] Figure 3 This is a cross-sectional schematic diagram of the semiconductor device according to Embodiment 3 of this application;

[0034] Figure 4 This is a cross-sectional schematic diagram of the semiconductor device according to Embodiment 4 of this application;

[0035] Figures 5a-5c This is a cross-sectional schematic diagram corresponding to certain steps of the method for forming a semiconductor device according to an embodiment of this application. Detailed Implementation

[0036] The present application is described below based on embodiments, but it is not limited to these embodiments. In the detailed description of the present application below, certain specific details are described in detail. Those skilled in the art can fully understand the present application without these details. To avoid obscuring the substance of the present application, well-known methods, processes, flows, elements, and circuits are not described in detail.

[0037] Those skilled in the art will understand that the accompanying drawings provided herein are for illustrative purposes and are not necessarily drawn to scale.

[0038] Figure 1 This is a cross-sectional schematic diagram of a semiconductor device according to Embodiment 1 of this application. The semiconductor device includes: a substrate 100; a channel layer 300 on the substrate 100; a barrier layer 400 on the channel layer 300; a gate structure G on the barrier layer 400; an insulating structure 800 covering the upper surface and side surfaces of the gate structure G and a portion of the upper surface of the barrier layer 400 adjacent to the gate structure G; a barrier layer 500 including a first portion covering the insulating structure 800 and a second portion at least partially covering the exposed upper surface of the barrier layer; and a source structure 710 and a drain structure 720 located on both sides of the gate structure G.

[0039] In an optional embodiment, a buffer layer 200 may be further included between the substrate 100 and the channel layer 300. The buffer layer 200 is used to release stress between the epitaxially grown heterostructure and the semiconductor substrate 101 caused by lattice mismatch and thermal mismatch.

[0040] The substrate 100 can be made of materials such as Si, SiC, AlN, Al2O3, or sapphire. The buffer layer 200 can be made of III-V group semiconductor materials, such as GaN or GaAs. The channel layer 300 can be made of the same material as the buffer layer 200. The processes for forming the buffer layer 200 on the substrate 100 and the channel layer 300 on the buffer layer 200 include, for example, epitaxy, chemical vapor deposition (CVD), physical vapor deposition (PVD), and atomic layer deposition (ALD). Examples of chemical vapor deposition include metal-organic chemical vapor deposition (MOCVD) and plasma-enhanced chemical vapor deposition (PECVD).

[0041] The channel layer 300 and the barrier layer 400 are made of group III semiconductor materials, such as GaN or GaAs for the channel layer 300, and AlGaN, InGaN, InAlGaN, or AlN for the barrier layer 400. The barrier layer 400 and the channel layer 300 form a heterojunction. The barrier layer 400 generates a two-dimensional electron gas (2DEG) near the upper surface of the channel layer 300 below it through a polarization effect.

[0042] In some embodiments, the gate structure G includes a first layer 910 and a second layer 920, wherein the first layer 910 is formed on the barrier layer 400, and the second layer 920 is formed on the first layer 910. The first layer 910 is a doped III-V semiconductor layer, and the second layer 920 is a gate metal layer. For example, the first layer 910 is a P-GaN layer, and the second layer 920 is a TiN layer or a Ti layer. The P-GaN layer is, for example, a Mg-doped GaN layer. Another example is that the first layer 910 is a gate dielectric layer, and the second layer 920 is a metal layer. By applying a voltage to the second layer 920, the concentration of the two-dimensional electron gas in the channel layer 300 below it can be controlled, thereby controlling the on-resistance of the device. In some embodiments, in the channel length direction of the semiconductor device, the two sides of the second layer 920 are recessed relative to the two sides of the first layer 910, wherein the channel length direction is the drain-source direction.

[0043] An insulating structure 800 covers the gate structure G (i.e., the upper and side surfaces of the gate structure G) and the upper surface of the barrier layer 400 adjacent to the gate structure G. The thickness d1 of the insulating structure 800 above the top surface of the gate structure presents a trade-off: too thick a thickness weakens the voltage withstand capability at the gate structure edge, while too thin a thickness introduces significant parasitic capacitance Cgs. In this invention, the thickness d1 of the insulating structure 800 above the top surface of the gate structure is set to 0.1-1 μm. Similarly, the width L1 of the insulating structure located on both sides of the gate structure and covering the barrier layer also requires a trade-off: if L1 is too short, it will lead to electric field concentration near the gate structure; if L1 is too long, it will weaken the barrier layer's ability to regulate the two-dimensional electron gas concentration. In this invention, the width L1 of the insulating structure located on both sides of the gate structure and covering the barrier layer is set to 10-100 nm.

[0044] In this embodiment, the insulating structure 800 includes a single layer, and the material of the insulating structure 800 may be silicon dioxide or the like. In other embodiments, such as Figure 2As shown, the insulating structure 800 includes a two-layer structure, comprising a first insulating layer 801 covering the gate structure G and a second insulating layer 802 covering the first insulating layer 801. Optionally, the first insulating layer 801 covers the gate structure G and the upper surface of a portion of the barrier layer 400 adjacent to the gate structure G, and the second insulating layer 802 covers the upper surface and side surface of the first insulating layer 801. The material of the first insulating layer 801 may be silicon oxide, and the material of the second insulating layer 802 may be silicon nitride. In optional embodiments, the insulating structure 800 may also employ a multilayer structure with alternating stacks of silicon oxide and silicon nitride.

[0045] The barrier layer 500 is made of a III-V group semiconductor material, such as AlGaN, InGaN, InAlGaN, AlN, etc. The bandgap of the barrier layer 500 is greater than the bandgap of the channel layer 400. The material of the barrier layer 500 and the barrier layer 400 can be the same or different. The barrier layer 500, located above and to the side of the gate structure G, has a higher dielectric constant, which helps prevent signal coupling interference from the interconnect metal layer traces above the gate structure during high-frequency operation, improving device reliability. Furthermore, because the bandgap of the barrier layer is greater than that of the insulating layer (e.g., silicon nitride) covering the gate structure in the prior art, it increases the withstand voltage between the gate structure and the high-voltage metal. The barrier layer located on the upper surface of the barrier layer can enhance the polarization effect of the barrier layer 400 on the channel layer 300, resulting in more two-dimensional electron gas near the upper surface of the channel layer 300. In this embodiment, the barrier layer 500 is a monolithic structural layer that can be formed in a single step. In an alternative embodiment, the first and second portions of the barrier layer 500 may also be made of different materials and formed in two steps.

[0046] In this embodiment, the barrier layer 500 can be configured to contact both the drain and source structures, respectively. Furthermore, the barrier layer can cover the entire upper surface of the exposed barrier layer. This configuration allows for one-step deposition, simplifying the device fabrication process and eliminating the need for complex processes such as etching. In other embodiments, such as... Figure 3 As shown, the barrier layer 500 can also be configured to be separate from the drain structure 710 and the source structure 720, respectively. In the subsequent formation of the drain structure 710 and the source structure 720, similar to existing technologies, there is no need to separately etch the barrier layer. Furthermore, the etching of the trenches in both the source and drain regions can be completed simultaneously through the same etching process, reducing process complexity and improving efficiency. Of course, in other embodiments, the barrier layer can be configured to contact the drain structure and be separate from the source structure, or vice versa, depending on the specific requirements of the device and process; no limitations are imposed here.

[0047] In an optional embodiment, the thickness of the barrier layer 400 directly covered by the barrier layer 500 is less than the thickness of the barrier layer 400 in other areas. This application eliminates surface damage by etching portions of the barrier layer 400, providing a good growth interface for the barrier layer subsequently formed on its surface. Of course, in other embodiments, the entire barrier layer can also be configured to have a uniform thickness, i.e., the unetched portions of the barrier layer, to reduce the number of process steps.

[0048] The semiconductor device further includes an interlayer dielectric layer 600 covering the barrier layer 500, and contact vias extending through the interlayer dielectric layer 600, the barrier layer 500, the barrier layer 400, and into the channel layer 300. The source structure 710 and drain structure 720 fill the contact vias and are partially located on the upper surface of the interlayer dielectric layer 600. The source structure 710 and drain structure 720 are groove-shaped. Optionally, as an implementation, the interlayer dielectric layer 600 can be made of silicon dioxide (SiO2), silicon nitride (SiN), silicon oxynitride (SiON), or aluminum oxide (Al2O3). The source structure 710 and drain structure 720 can be ohmic contact structures, and their materials can be metals such as titanium (Ti), aluminum (Al), nickel (Ni), and / or gold (Au).

[0049] Figure 4 This is a cross-sectional schematic diagram of the semiconductor device according to Embodiment 4 of this application. In Embodiment 1, the insulating structure of the semiconductor device lacks a transition region on the side near the drain structure, causing an electric field to easily accumulate in this area, thus affecting the device's withstand voltage performance. Therefore, in this embodiment, a transition region 510 is provided at the edge of the insulating structure 800 near the drain structure 720. The transition region 510 can be any shape, such as stepped, inclined, inner arc, or outer arc. Correspondingly, the barrier layer covering the transition region also includes a corresponding transition structure. In an optional embodiment, a transition region 520 can also be provided at the edge of the insulating structure 800 near the source structure 710, and the two transition regions 510 and 520 can be symmetrically arranged about the gate structure G.

[0050] Due to the transition region of the insulating structure, the thickness of the barrier layer above it gradually decreases as it extends from the insulating structure to the barrier layer, resulting in a gradual increase in the concentration of the two-dimensional electron gas below it. This helps to reduce the electric field near the gate structure and also facilitates a more uniform distribution of the electric field within the device.

[0051] The present invention also provides a method for forming a semiconductor device, which can form the semiconductor device described above. For example... Figures 5a-5c As shown, the semiconductor device formation method may specifically include the following steps:

[0052] S100: Provides substrate 100;

[0053] S200: A trench layer 300 is formed on the substrate 100;

[0054] S300: A barrier layer 400 is formed on the channel layer 300.

[0055] like Figure 5a As shown, substrate 100 is located at the bottom layer of the semiconductor device. Substrate 100 can serve as a carrier to provide necessary physical support for the semiconductor device during and after device formation. The substrate material can be Si, SiC, AlN, Al2O3, sapphire, etc.

[0056] Optionally, the thermal expansion coefficients between the substrate 100 and the channel layer 300 typically differ significantly, making the formation process of the channel layer 300 prone to substrate cracking. Therefore, a buffer layer 200 can also be formed on the substrate. The buffer layer 200 can be located between the substrate 100 and the channel layer 300. The buffer layer 200 can be used to isolate the substrate 100 from the channel layer 300, preventing the formation process of the channel layer 300 from affecting the substrate 100. The buffer layer 300 can be made of aluminum nitride (AlN) and / or aluminum gallium nitride (AlGaN).

[0057] Alternatively, as a formation method, this embodiment may first provide a substrate, and then sequentially deposit or grow corresponding material layers (i.e., buffer layer, channel layer and barrier layer) on the substrate.

[0058] The channel layer 300 can be made of gallium nitride (GaN). The barrier layer 400 can be made of group III nitrides (e.g., aluminum nitride (AlN) or aluminum gallium nitride (AlGaN).

[0059] S400: Forming a gate structure G on the barrier layer 400;

[0060] like Figure 5aAs shown, the gate structure G includes a first layer 910 and a second layer 920. The first layer 910 is formed on the barrier layer 400, and the second layer 920 is formed on the first layer 910. The first layer 910 is a doped III-V semiconductor layer, and the second layer 920 is a gate metal layer. The gate metal is, for example, titanium (Ti) or titanium nitride (TiN). For example, the first layer 910 is a P-GaN layer, and the second layer 920 is a TiN layer or a Ti layer. The P-GaN layer is, for example, a magnesium (Mg) doped GaN layer. Another example is that the first layer 910 is a gate dielectric layer, and the second layer 920 is a metal layer. By applying a voltage to the second layer 920, the concentration of the two-dimensional electron gas in the channel layer 300 below it can be controlled, thereby controlling the on-resistance of the device. In some embodiments, in the channel length direction of the semiconductor device, the two sides of the second layer 920 are recessed relative to the two sides of the first layer 910, wherein the channel length direction is the drain-source direction.

[0061] Specifically, the method for forming the gate structure includes: first forming a first material layer on the barrier layer 400; then forming a second material layer on the first material layer; forming a patterned mask on the second material layer; and sequentially etching the second material layer and the first material layer to form the first layer and the second layer, i.e., the gate structure G.

[0062] S500: An insulating structure 800 is formed, the insulating structure 800 covering the gate structure G and the upper surface of the barrier layer 400 adjacent to the gate structure G;

[0063] like Figure 5b As shown, specifically, the method for forming the insulating structure includes: forming an insulating material layer covering the upper surface and side surface of the gate structure and the upper surface of the barrier layer; forming a patterned mask layer on the insulating material layer, wherein the patterned mask layer is located at least above the gate structure G; and etching the insulating material layer to form the insulating structure 800.

[0064] The insulating material layer may consist of only one material layer, such as a silicon oxide material layer; or it may consist of at least two stacked material layers, wherein the first material layer may be silicon oxide and the second material layer may be silicon nitride; or it may be a multilayer material structure layer with alternating stacks of silicon oxide and silicon nitride.

[0065] When the insulating structure includes a transition region, the insulating structure located on the barrier layer also needs to undergo corresponding etching and other processing.

[0066] S600: Forming a barrier layer 500, including a first portion covering the insulating structure 800 and a second portion at least partially covering the upper surface of the exposed barrier layer;

[0067] Specifically, such as Figure 5c As shown, the barrier layer 500 is formed on the upper surface of the insulating structure and the barrier layer through a one-step deposition process. The barrier layer 500 is configured as a III-V group semiconductor material, such as AlGaN, InGaN, InAlGaN, AlN, etc. If the barrier layer is to be in contact with the subsequently formed source and drain structures, a mask layer needs to be formed in advance at the locations of the subsequently formed source and drain structures, and removed after the barrier layer is deposited. Forming the barrier layer through a one-step deposition process not only simplifies the process but also simultaneously achieves the effects of protecting the gate structure and controlling the channel electron concentration.

[0068] In other embodiments, the first and second portions of the barrier layer 500 may be made of different materials. The process steps may include: using the insulating structure 800 as a mask, depositing a first barrier layer on the upper surface of the barrier layer, then removing the first barrier layer from the insulating structure, and finally forming a second barrier layer covering the insulating structure.

[0069] S700: Form source and drain structures located on both sides of the gate structure.

[0070] like Figure 1 As shown, in this embodiment, an interlayer dielectric layer 600 can be deposited on the barrier layer 500. After forming the interlayer dielectric layer 600, selective etching can be performed on both sides of the gate structure 26 to form source contact vias and drain contact vias extending from the interlayer dielectric layer 600 to the channel layer 300, respectively. Furthermore, in this embodiment, metal materials can be filled into the source contact vias and drain contact vias to form source structure 710 and drain structure 720. Optionally, as an implementation, the material of the interlayer dielectric layer 600 can be silicon dioxide (SiO2), silicon nitride (SiN), silicon oxynitride (SiON), and aluminum oxide (Al2O3), etc. The source structure 710 and drain structure 720 can be ohmic contact structures, and their materials can be titanium (Ti), aluminum (Al), nickel (Ni), and / or gold (Au), etc.

[0071] It should be noted that, in the embodiments of the present invention, all material layers or corresponding layer structures involved can be formed using existing semiconductor deposition processes, including but not limited to Chemical Vapor Deposition (CVD), Physical Vapor Deposition (PVD), Atomic Layer Deposition (ALD), Molecular Beam Epitaxy (MBE), and Liquid-Phase Deposition (LPD), etc., and this application does not impose any limitations on these processes. The groove structures involved can all be formed using existing semiconductor etching processes, including but not limited to wet etching, dry etching, and ion beam etching (IBE), etc., and this application does not impose any limitations on these processes. Furthermore, although not explicitly stated, in actual process flows, to ensure that the formed material layers meet design requirements, this embodiment may also include other operations, such as planarization operations, and this application does not impose any limitations on these operations.

[0072] The above description is merely a preferred embodiment of this application and is not intended to limit this application. Various modifications and variations can be made to this application by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the protection scope of this application.

Claims

1. A semiconductor device, comprising: Substrate; A channel layer, wherein the channel layer is located on the substrate; A barrier layer is located on the channel layer, and a two-dimensional electron gas is generated at the interface between the channel layer and the barrier layer; A gate structure, wherein the gate structure is located on the barrier layer; An insulating structure that encloses the gate structure and covers the upper surface of the barrier layer adjacent to the gate structure; The barrier layer includes a first portion covering the insulating structure and a second portion at least partially covering the upper surface of the exposed barrier layer. The source structure and drain structure are located on both sides of the gate structure.

2. The semiconductor device according to claim 1, wherein, The bandgap width of the barrier layer is greater than the bandgap width of the channel layer.

3. The semiconductor device according to claim 1, wherein, The barrier layer is made of a group III-V compound.

4. The semiconductor device according to claim 1, wherein, The barrier layer is configured as a continuous, monolithic structure.

5. The semiconductor device according to claim 1, wherein, The first and second parts of the barrier layer are made of different materials.

6. The semiconductor device according to claim 1, wherein, The insulating structure includes at least one material.

7. The semiconductor device according to claim 1, wherein, The insulating structure comprises alternating layers of silicon oxide and silicon nitride.

8. The semiconductor device according to claim 1, wherein, The thickness of the insulating structure located above the top surface of the gate structure is set to 0.1-1 μm.

9. The semiconductor device according to claim 1, wherein, The width of the insulating structure located on one side of the gate structure and covering the barrier layer is set to 10-100 nm.

10. The semiconductor device according to claim 1, wherein, The barrier layer is separated from both the source structure and the drain structure.

11. The semiconductor device according to claim 1, wherein, The barrier layer is in contact with the source structure and the drain structure.

12. The semiconductor device according to claim 1, wherein, The edge of the insulating structure near the drain structure includes a transition region.

13. The semiconductor device according to claim 12, wherein, The transition region is in one of the following shapes: stepped, inclined, inwardly curved, or outwardly curved.

14. The semiconductor device according to claim 1, wherein, The materials of the channel layer and the barrier layer are set to group III nitrides.

15. The semiconductor device according to claim 1, wherein, The source-drain structure extends into the channel layer.

16. A method for manufacturing a semiconductor device, comprising: Provide substrate, Form a channel layer on the substrate; A barrier layer is formed on the channel layer, and a two-dimensional electron gas is generated at the interface between the channel layer and the barrier layer; A gate structure is formed on the barrier layer; An insulating structure is formed, the insulating structure covering the gate structure and the upper surface of the barrier layer adjacent to the gate structure; A barrier layer is formed, the barrier layer comprising a first portion covering the insulating structure and a second portion at least partially covering the upper surface of the exposed barrier layer, and Source and drain structures are formed on both sides of the gate structure.

17. The method according to claim 16, wherein, The barrier layer is formed by a one-step deposition process.

18. The method according to claim 16, wherein, The barrier layer is formed by a two-step deposition process, and the first and second parts of the barrier layer are made of different materials.

19. The method of claim 16, wherein, The bandgap width of the barrier layer is greater than the bandgap width of the channel layer.

20. The method of claim 16, wherein, The insulating structure includes at least one material.

21. The method according to claim 16, wherein, The insulating structure comprises alternating layers of silicon oxide and silicon nitride.

22. The method according to claim 16, wherein, The edge of the insulating structure near the drain structure includes a transition region.

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