Assembled structure and manufacturing method for manufacturing an assembled structure

Abstract

An assembly structure includes a first electronic device, a second electronic device, a conductive portion, and a dielectric structure. The second electronic device is disposed above the first electronic device. The conductive portion connects the first electronic device and the second electronic device. The dielectric structure encapsulates the conductive portion and extends beyond side surfaces of the first electronic device and side surfaces of the second electronic device.

Description

[0001] Cross-references to related applications

[0002] This application claims the benefit of U.S. Provisional Application No. 63 / 749,463, filed January 24, 2025, the contents of which are incorporated herein by reference in their entirety. Technical Field

[0003] This disclosure relates to an assembly structure and a method for manufacturing the assembly structure, and further relates to an assembly structure comprising a dielectric structure and a method for manufacturing the assembly structure. Background Technology

[0004] In existing semiconductor electronic packaging structures, multiple electronic devices can be stacked one on top of the other. Due to the numerous high-temperature thermal cycles involved in the manufacturing process, significant warping of electronic devices and solder cracking between them can occur in semiconductor packaging. Therefore, the manufacturing yield and long-term reliability of semiconductor electronic packaging can be adversely affected. Summary of the Invention

[0005] In some embodiments, an assembly structure includes a first electronic device, a second electronic device, a conductive portion, and a dielectric structure. The second electronic device is disposed above the first electronic device. The conductive portion connects the first electronic device and the second electronic device. The dielectric structure encapsulates the conductive portion and extends beyond the side surfaces of the first electronic device and the second electronic device.

[0006] In some embodiments, a manufacturing method includes: forming a first dielectric layer on a first electronic device to cover an end surface of a first reflowable material on the first electronic device, wherein the first dielectric layer comprises an organic material; removing a portion of the first dielectric layer to expose the first reflowable material; forming a second dielectric layer on a second electronic device to cover an end surface of a second reflowable material on the second electronic device, wherein the second dielectric layer comprises an organic material; removing a portion of the second dielectric layer to expose the second reflowable material; bonding the first dielectric layer and the second dielectric layer together to jointly form a dielectric structure; and fusing the first reflowable material and the second reflowable material together to jointly form a solder structure.

[0007] In some embodiments, a manufacturing method includes: providing a first electronic device, the first electronic device including a first pad embedded in and exposed by a first conductive structure of the first electronic device, wherein the first conductive structure comprises an inorganic material; forming a second dielectric layer on the second electronic device, wherein the second dielectric layer exposes a second reflowable material and comprises an organic material; bonding the first conductive structure and the second dielectric layer; and bonding the first pad and the second reflowable material. Attached Figure Description

[0008] In relation to Figure 1 Some aspects of embodiments of this disclosure will be readily understood from the following detailed description. It should be noted that the various structures may not be drawn to scale, and the dimensions of the various structures may be arbitrarily increased or decreased for clarity of discussion.

[0009] Figure 1 A cross-sectional view of an assembly structure according to some embodiments of the present disclosure is shown.

[0010] Figure 2 A cross-sectional view of an assembly structure according to some embodiments of the present disclosure is shown.

[0011] Figures 3 to 11 A manufacturing method for manufacturing an assembly structure according to some embodiments of the present disclosure is shown.

[0012] Figure 12 A cross-sectional view of an assembly structure according to some embodiments of the present disclosure is shown.

[0013] Figure 13 Show Figure 12 A magnified view of area "A".

[0014] Figures 14 to 31 A manufacturing method for manufacturing an assembly structure according to some embodiments of the present disclosure is shown.

[0015] Figure 32 A cross-sectional view of an assembly structure according to some embodiments of the present disclosure is shown.

[0016] Figure 33 A cross-sectional view of an assembly structure according to some embodiments of the present disclosure is shown.

[0017] Figure 34 Show Figure 33 A magnified view of area "B".

[0018] Figures 35 to 49 A manufacturing method for manufacturing an assembly structure according to some embodiments of the present disclosure is shown.

[0019] Figure 50A cross-sectional view of an assembly structure according to some embodiments of the present disclosure is shown.

[0020] Figure 51 A cross-sectional view of an assembly structure according to some embodiments of the present disclosure is shown. Detailed Implementation

[0021] Common reference numerals are used throughout the drawings and detailed description to indicate the same or similar components. Embodiments of this disclosure will be readily understood from the following detailed description taken in conjunction with the accompanying drawings.

[0022] The following disclosure provides numerous different embodiments or instances for implementing various features of the provided subject matter. Specific examples of components and arrangements are described below to explain certain aspects of this disclosure. Of course, these are merely examples and are not intended to be limiting. For example, in the following description, embodiments in which a first feature is formed over or on a second feature may include instances where the first and second features are formed or disposed in direct contact, and embodiments in which additional features may be formed or disposed between the first and second features such that the first and second features do not directly contact each other. Furthermore, reference numerals and / or letters may be repeated in various instances of this disclosure. Such repetition is for the purpose of simplicity and clarity and does not in itself define the relationship between the various embodiments and / or configurations discussed.

[0023] Figure 1 A cross-sectional view of an assembly structure 1 according to some embodiments of the present disclosure is shown. The assembly structure 1 may be a combined structure, an electronic package structure, a semiconductor package structure, an electronic structure, an electronic device, a semiconductor device, or a three-dimensional form factor device. The assembly structure 1 may include a first electronic device 12, a second electronic device 14, at least one conductive portion 11, and a dielectric structure 19. The assembly structure 1 can be used in a voltage regulator. The voltage regulator may include control logic and redundant control logic, and can perform steps of engaging and disengaging the redundant control logic.

[0024] The first electronic device 12 may be a substrate, a semiconductor die, a semiconductor chip, or an integrated circuit die. In some embodiments, the first electronic device 12 may be a logic device, such as a logic die or a logic chip. In some embodiments, the first electronic device 12 may include an application-specific integrated circuit (ASIC) chip. Alternatively, the first electronic device 12 may include a memory device, such as high bandwidth memory (HBM).

[0025] The first electronic device 12 may have a top surface 121 (e.g., an upper surface, a first surface, or a first outer surface), a bottom surface 122 (e.g., a lower surface, a second surface, or a second outer surface) opposite the top surface 121, and a side surface 123 extending between the top surface 121 and the bottom surface 122. The first electronic device 12 may include a main portion 120, a conductive structure 124, and a plurality of through vias 125.

[0026] The main portion 120 may be a semiconductor substrate and may contain, for example, silicon (Si) or other semiconductor materials. The main portion 120 may have a top surface 1201 (e.g., an active surface) and a bottom surface 1202 (e.g., a back surface) opposite the top surface 1201. The bottom surface 1202 of the main portion 120 may be the bottom surface 122 of the first electronic device 12. A via 125 may extend through the main portion 120 and may also be referred to as a "through silicon via (TSV)". The via 125 may be formed outside of stress concentration areas in the main portion 120.

[0027] Conductive structure 124 may be disposed on the top surface 1201 of main portion 120. Conductive structure 124 may also be referred to as an "outer structure," "addition structure," "stacked structure," or "built-up structure." The top surface of conductive structure 124 may be the top surface 121 of the first electronic device 12. In some embodiments, conductive structure 124 may include multiple front-end-of-line (FEOL) devices, such as resistors, capacitors, inductors, and / or transistors. In some embodiments, conductive structure 124 may further include at least one back-end-of-line (BEOL) interconnect pattern electrically connected to the front-end (FEOL) devices, such as multiple patterned circuit layers. Conductive structure 124 may include a dielectric structure, multiple circuit layers (including multiple traces and multiple pads) embedded in the dielectric structure, and multiple internal vias. The dielectric structure may be a multilayer film stack deposited on main portion 120. An internal via can be disposed within the dielectric structure and can connect to the circuit layer. The circuit layer of the conductive structure 124 can be electrically connected to the via 125. The dielectric structure of the conductive structure 124 can contain inorganic or organic materials.

[0028] The second electronic device 14 may be disposed above the first electronic device 12. The second electronic device 14 may be a substrate, a semiconductor die, a semiconductor chip, or an integrated circuit die. In some embodiments, the second electronic device 14 may be a logic device, such as a logic die or a logic chip. In some embodiments, the second electronic device 14 may include an application-specific integrated circuit (ASIC) chip. Alternatively, the second electronic device 14 may include a memory device, such as high-bandwidth memory (HBM).

[0029] The second electronic device 14 may have a top surface 141 (e.g., an upper surface, a first surface, or a first outer surface), a bottom surface 142 (e.g., a lower surface, a second surface, or a second outer surface) opposite the top surface 141, and a side surface 143 extending between the top surface 141 and the bottom surface 142. The bottom surface 142 of the second electronic device 14 may have a general trend that is substantially parallel to the top surface 121 of the first electronic device 12. The second electronic device 14 may include a main portion 140, a conductive structure 144, and a plurality of through holes 145.

[0030] The main portion 140 may be a semiconductor substrate and may contain, for example, silicon (Si) or other semiconductor materials. The main portion 140 may have a bottom surface 1401 (e.g., an active surface) and a top surface 1402 (e.g., a back surface) opposite the bottom surface 1401. The top surface 1402 of the main portion 140 may be the top surface 141 of the second electronic device 14. A via 145 may extend through the main portion 140 and may also be referred to as a "through-silicon via (TSV)".

[0031] Conductive structure 144 may be disposed on the bottom surface 1401 of the main portion 140. The bottom surface of conductive structure 144 may be the bottom surface 142 of the second electronic device 14. In some embodiments, conductive structure 144 may include a plurality of front-end process (FEOL) devices, such as resistors, capacitors, inductors, and / or transistors. In some embodiments, conductive structure 144 may further include at least one back-end process (BEOL) interconnect pattern electrically connected to the front-end process (FEOL) devices, such as a plurality of patterned circuit layers. Conductive structure 144 may include a dielectric structure, a plurality of circuit layers (including a plurality of traces and a plurality of pads) embedded in the dielectric structure, and a plurality of internal vias. The dielectric structure may be a multilayer film stack deposited on the main portion 140. Internal vias may be disposed in the dielectric structure and may connect the circuit layers. The circuit layers of conductive structure 144 may be electrically connected to vias 145. The dielectric structure of conductive structure 144 may contain inorganic or organic materials.

[0032] At least one conductive portion 11 may comprise a plurality of conductive portions 11 spaced apart from each other. The conductive portion 11 may be disposed between and connect the first electronic device 12 and the second electronic device 14. The conductive portion 11 may include a first connector 129, a second connector 149, and a solder structure 13. The conductive portion 11 may be a bonding structure, a metallic portion, or a support structure. The first connector 129 may extend beyond the top surface 121 of the first electronic device 12. The first connector 129 may include a first bump 126 and a first barrier layer 127. The first bump 126 may be disposed on the conductive structure 124 and may comprise copper (Cu). The first bump 126 may generally suppress van der Waals force stiction associated with quality inspection. The first barrier layer 127 may be disposed on the first bump 126 and may comprise nickel (Ni). The first barrier layer 127 may be a transition element conformally to the first bump 126.

[0033] The second connector 149 may extend beyond the bottom surface 142 of the second electronic device 14. The second connector 149 may include a second bump 146 and a second barrier layer 147. The second bump 146 may be disposed on the conductive structure 144 and may contain copper (Cu). The second barrier layer 147 may be disposed on the second bump 146 and may contain nickel (Ni). A solder structure 13 may be disposed between the first barrier layer 127 of the first connector 129 and the second barrier layer 147 of the second connector 149 and contact the first barrier layer 127 of the first connector 129 and the second barrier layer 147 of the second connector 149. For example, the end surfaces of the first barrier layer 127 and the second barrier layer 147 may be solder areas. The solder structure 13 may contain, for example, a Sn / Ag alloy solder material or a reflowable material, or may be formed of, for example, a Sn / Ag alloy solder material or a reflowable material. The side surface 133 of the solder structure 13 may be a convex surface. Solder structure 13 may be a single-layer or monolithic structure filled with intermetallic compound (IMC). Solder structure 13 may be a full IMC structure with a single IMC or multiple IMCs. A portion of solder structure 13 may contact the side surface of the first barrier layer 127 of the first connector 129 and the side surface of the second barrier layer 147 of the second connector 149. Solder structure 13 may be a self-aligned structure.

[0034] The dielectric structure 19 may encapsulate the conductive portions 11 and fill the spaces between the conductive portions 11. The dielectric structure 19 may comprise, or be formed from, an organic material such as polyimide (PI), benzocyclobutene (BCB), or polybenzoxazoles (PBO). The dielectric structure 19 may not contain fillers. The dielectric structure 19 may be disposed between the conductive structure 124 of the first electronic device 12 and the conductive structure 144 of the second electronic device 14, and may contact both the conductive structure 124 of the first electronic device 12 and the conductive structure 144 of the second electronic device 14. The bottom surface of the dielectric structure 19 may contact the conductive structure 124 of the first electronic device 12. The top surface of the dielectric structure 19 may contact the conductive structure 144 of the second electronic device 14. The dielectric structure 19 may cover and contact the first connector 129 (e.g., the first bump 126 and the first barrier layer 127), the second connector 149 (e.g., the second bump 146 and the second barrier layer 147), and the solder structure 13. The dielectric structure 19 may be a continuous internal stress-relief structure. The dielectric structure 19 may function as a retainer. The dielectric structure 19 may have a loss tangent of less than about 0.01. The materials of the first connector 129 and the second connector 149 may have greater ductility than the material of the dielectric structure 19. The dielectric structure 19 may be a strain layer configured to reduce thermal stress on the assembly structure 1 during thermal cycling.

[0035] The dielectric structure 19 may extend beyond the side surface 123 of the first electronic device 12 and the side surface 143 of the second electronic device 14. The side surface 193 of the dielectric structure 19 may be a convex surface. The curvature of the side surface 133 of the solder structure 13 may be the same as or different from the curvature of the side surface 193 of the dielectric structure 19. The dielectric structure 19 may be a single-layer or monomeric structure filled with a cured organic material. The dielectric structure 19 may not have horizontal interfaces therein. In some embodiments, the dielectric structure 19 may have a glass transition temperature (Tg) in the range of 150°C to 250°C. The Mohs hardness of the dielectric structure 19 may be in the range of about 2.0 to about 4.0, for example, 3.0. The Young's modulus of the dielectric structure 19 may be in the range of about 1.5 GPa to about 2.0 GPa, for example, 1.8 GPa.

[0036] In contrast, dielectric structure 19 differs from molding compound (or underfill). Molding compound may contain epoxy resin with silica filler. Molding compound may have a glass transition temperature (Tg) in the range of 95°C to 115°C. Molding compound may have a Young's modulus in the range of about 7.0 GPa to 18.0 GPa.

[0037] In contrast, the dielectric structure 19 differs from conventional inorganic bonding materials such as SiO2, SiCN, and SiN. For example, SiO2 can have a Young's modulus of 73 GPa and a Mohs hardness of 7.0. SiCN can have a Young's modulus in the range of 190 GPa to 300 GPa and a Mohs hardness of 9.0. SiN can have a Young's modulus of 290 GPa and a Mohs hardness of 7.0.

[0038] In contrast, the dielectric structure 19 differs from the dielectric structures of the conductive structures 124 and 144. For example, the dielectric structures of the conductive structures 124 and 144 may have a Young's modulus greater than 2.2 GPa. Furthermore, the dielectric structures of the conductive structures 124 and 144 are not used for bonding. The ratio of the Young's modulus of the dielectric structure 19 to the Young's modulus of the dielectric structures of the conductive structures 124 and 144 may be from 0.68 to 0.81.

[0039] During the manufacturing process, the dielectric structure 19 can be formed at a low temperature, for example, not exceeding 150°C. Therefore, warpage of the first electronic device 12 and the second electronic device 14 can be reduced. For example, the warpage of the first electronic device 12 and the second electronic device 14 can be less than 10 μm. Furthermore, not much IMC is formed in the solder structure 13. Therefore, the solder structure 13 is protected against cracking. The yield of the assembled structure 1 can be improved. The first electronic device 12 can be securely bonded to the second electronic device 14 through the cooperative operation of the dielectric structure 19 and the solder structure 13.

[0040] Figure 2 A cross-sectional view of an assembly structure 1a according to some embodiments of the present disclosure is shown. Figure 2 The assembly structure 1a is similar to Figure 1 The assembly structure 1, except for the side surface 133 of the solder structure 13 and the side surface 193 of the dielectric structure 19. Figure 2 The side surface 133 of the solder structure 13 of the assembly structure 1a may be a substantially flat surface and may be substantially aligned with the side surface of the first connector 129 and the side surface of the second connector 149. Figure 2The side surface 193 of the dielectric structure 19 of the assembly structure 1a may be a substantially flat surface and may be substantially aligned with the side surface 123 of the first electronic device 12 and the side surface 143 of the second electronic device 14. In some embodiments, Figure 2 The side surface 193 of the dielectric structure 19 in the assembly structure 1a may be a convex surface. The curvature of the side surface 133 of the solder structure 13 may be different from the curvature of the side surface 193 of the dielectric structure 19.

[0041] Figures 3 to 11 A manufacturing method for manufacturing an assembly structure according to some embodiments of the present disclosure is illustrated. In some embodiments, the method is used to manufacture... Figure 1 The assembly structure 1 shown is illustrated.

[0042] refer to Figure 3 A first electronic device 12' may be provided. The first electronic device 12' may be similar to Figure 1 The first electronic device 12' may be a substrate or a semiconductor structure. In some embodiments, the first electronic device 12' may be a panel type (or panel structure) or a wafer type (or wafer structure).

[0043] The first electronic device 12' may have a top surface 121 and a bottom surface 122. The first electronic device 12' may include a main portion 120, a conductive structure 124, and a plurality of through holes 125. The main portion 120 may have a top surface 1201 and a bottom surface 1202. The through holes 125 may extend through the main portion 120. The conductive structure 124 may be disposed on the top surface 1201 of the main portion 120. In some embodiments, Figure 3 The conductive structure 124 can be with Figure 1 The conductive structure is the same as that of 124.

[0044] Then, a first bump 126 may be formed on or disposed on the conductive structure 124 of the first electronic device 12' by plating, and may contact the conductive structure 124 of the first electronic device 12'. The first bump 126 may be formed on or disposed on the top surface 121 of the first electronic device 12'. The first bump 126 may comprise copper (Cu). Then, a first barrier layer 127 may be formed on or disposed on the first bump 126 by plating. The first barrier layer 127 may comprise nickel (Ni). The first bump 126 and the first barrier layer 127 may together form the first connector 129. Then, a first resolderable material 128 may be formed on or disposed on the first barrier layer 127 on the first bump 126. The first resolderable material 128 may comprise a solder material, such as a Sn / Ag alloy.

[0045] The first dielectric layer 16 can then be coated onto the top surface 121 of the first electronic device 12' to cover the first connector 129 (e.g., the first bump 126 and the first barrier layer 127) and the top surface 1281 (e.g., the end surface) of the first reflowable material 128 on the first electronic device 12'. The amount of the first dielectric layer 16 can be determined by multiple threshold levels corresponding to multiple measured widths of the first reflowable material 128. The first dielectric layer 16 may contain organic materials such as polyimide (PI), benzocyclobutene (BCB), or polybenzoxazole (PBO). The first dielectric layer 16 may not contain fillers. The top surface 161 (e.g., the outer surface) of the first dielectric layer 16 may be higher than the top surface 1281 (e.g., the end surface) of the first reflowable material 128. The first dielectric layer 16 can then be pre-cured, for example, at a temperature of 140°C for 30 minutes, such that the first dielectric layer 16 is in a stage B state.

[0046] refer to Figure 4 and Figure 5 ,in Figure 5 Show Figure 4A top view shows that a fly-cutting process can be performed on the top surface 161 of the first dielectric layer 16. Therefore, the upper portion of the first dielectric layer 16 and the upper portion of the first reflowable material 128 can be removed simultaneously using a diamond drill bit. After the fly-cutting process, the first dielectric layer 16 exposes the first reflowable material 128. That is, the top surface 1281 (e.g., end surface) of the first reflowable material 128 can be exposed by the top surface 161 (e.g., outer surface) of the first dielectric layer 16. In some embodiments, the top surface 1281 (e.g., end surface) of the first reflowable material 128 can be substantially aligned with the top surface 161 (e.g., outer surface) of the first dielectric layer 16. The total thickness variation (TTV) of the top surface 1281 (e.g., end surface) of the first reflowable material 128 and the top surface 161 (e.g., outer surface) of the first dielectric layer 16 can be less than 1 μm. In some embodiments, the removal rate of the first reflowable material 128 is higher than the removal rate of the first dielectric layer 16. Therefore, the top surface 1281 (e.g., the end surface) of the first reflowable material 128 may be dished. For example, the top surface 1281 (e.g., the end surface) of the first reflowable material 128 may be recessed about 100 nm from the top surface 161 (e.g., the outer surface) of the first dielectric layer 16. In some embodiments, the recess between the top surface 1281 (e.g., the end surface) of the first reflowable material 128 and the top surface 161 (e.g., the outer surface) of the first dielectric layer 16 may be a trench recess.

[0047] refer to Figure 5 After the fly-cut process, the top surface 1281 (e.g., the end surface) of the first reflowable material 128 may have a plurality of machining marks 1282 and may have a wavy profile. The machining marks 1282 may be curves spaced apart from each other. The machining marks 1282 may have equal curvature. The first reflowable material 128 may have a first thickness T1.

[0048] refer to Figure 4 Then, a single-cutting process can be performed to form a plurality of first electronic devices 12. In some embodiments, a single-cutting process may not have been performed.

[0049] refer to Figure 6 A second electronic device 14' may be provided. The second electronic device 14' may be similar to... Figure 1 The second electronic device 14' may be a substrate or a semiconductor structure. In some embodiments, the second electronic device 14' may be a panel type (or panel structure) or a wafer type (or wafer structure).

[0050] The second electronic device 14' may have a top surface 141 and a bottom surface 142. The second electronic device 14' may include a main portion 140, a conductive structure 144, and a plurality of through holes 145. The main portion 140 may have a top surface 1402 and a bottom surface 1401. The through holes 145 may extend through the main portion 140. The conductive structure 144 may be disposed on the bottom surface 1401 of the main portion 140. In some embodiments, Figure 6 The conductive structure 144 can be with Figure 1 The conductive structure is the same as that of 144.

[0051] Then, a second bump 146 may be formed on or disposed on the conductive structure 144 of the second electronic device 14' by plating, and may contact the conductive structure 144 of the second electronic device 14'. The second bump 146 may be formed on or disposed on the bottom surface 142 of the second electronic device 14'. The second bump 146 may comprise copper (Cu). Then, a second barrier layer 147 may be formed on or disposed on the second bump 146 by plating. The second barrier layer 147 may comprise nickel (Ni). The second bump 146 and the second barrier layer 147 may together form the second connector 149. Then, a second resolderable material 148 may be formed on or disposed on the second barrier layer 147 on the second bump 146. The second resolderable material 148 may comprise a solder material, such as a Sn / Ag alloy.

[0052] The second dielectric layer 18 can then be coated onto the bottom surface 142 of the second electronic device 14' to cover the second connector 149 (e.g., the second bump 146 and the second barrier layer 147) and the bottom surface 1482 (e.g., the end surface) of the second reflowable material 148 on the second electronic device 14'. The second dielectric layer 18 may contain organic materials such as polyimide (PI), benzocyclobutene (BCB), or polybenzoxazole (PBO). The second dielectric layer 18 may not contain fillers. The bottom surface 182 (e.g., the outer surface) of the second dielectric layer 18 may be lower than the bottom surface 1482 (e.g., the end surface) of the second reflowable material 148. The second dielectric layer 18 can then be pre-cured, for example, at a temperature of 140°C for 30 minutes, such that the second dielectric layer 18 is in a stage B state.

[0053] refer to Figure 7A fly-cutting process can be performed on the bottom surface 182 of the second dielectric layer 18. Therefore, the lower portion of the second dielectric layer 18 and the lower portion of the second reflowable material 148 can be removed simultaneously using a diamond drill bit. After the fly-cutting process, the second dielectric layer 18 exposes the second reflowable material 148. That is, the bottom surface 1482 (e.g., end surface) of the second reflowable material 148 can be exposed by the bottom surface 182 (e.g., outer surface) of the second dielectric layer 18. In some embodiments, the bottom surface 1482 (e.g., end surface) of the second reflowable material 148 can be substantially aligned with the bottom surface 182 (e.g., outer surface) of the second dielectric layer 18. The total thickness variation (TTV) of the bottom surface 1482 (e.g., end surface) of the second reflowable material 148 and the bottom surface 182 (e.g., outer surface) of the second dielectric layer 18 can be less than 1 μm. In some embodiments, the bottom surface 1482 (e.g., end surface) of the second resolderable material 148 may be recessed. For example, the bottom surface 1482 (e.g., end surface) of the second resolderable material 148 may be recessed about 100 nm from the bottom surface 182 (e.g., outer surface) of the second dielectric layer 18.

[0054] refer to Figure 8 and Figure 9 The second dielectric layer 18 can be etched or thinned by descumming, allowing the second reflowable material 148 to protrude from the bottom surface 182 (e.g., the outer surface) of the second dielectric layer 18. In some embodiments, descum gas 15 (comprising argon (Ar) and oxygen (O2)) can be applied to or supplied to the bottom surface 182 (e.g., the outer surface) of the second dielectric layer 18 to remove only a portion of the second dielectric layer 18. The bottom surface 1482 (e.g., the end surface) of the second reflowable material 148 may protrude less than 1 μm from the bottom surface 182 (e.g., the outer surface) of the second dielectric layer 18. The second reflowable material 148 may extend less than 1 μm beyond the bottom surface 182 (e.g., the outer surface) of the second dielectric layer 18. The second reflowable material 148 may have a second thickness T2. The second thickness T2 of the second reflowable material 148 may be substantially equal to the first thickness T1 of the first reflowable material 128. Alternatively, the second thickness T2 of the second reflowable material 148 may be less than or greater than the first thickness T1 of the first reflowable material 128.

[0055] Then, a single-cut process can be performed to form a plurality of second electronic devices 14. In some embodiments, a single-cut process may not have been performed.

[0056] refer to Figure 10 can Figure 4 Structure and Figure 9The structure is placed in a reducing atmosphere, such as a formic acid atmosphere, to remove the oxide layer on the bottom surface 1482 (e.g., end surface) of the second reflowable material 148 and the oxide layer on the top surface 1281 (e.g., end surface) of the first reflowable material 128. Formic acid is systematically named methanoic acid and is the simplest carboxylic acid, having the chemical formula HCOOH and the structure HC(=O)-OH.

[0057] refer to Figure 11 The second electronic device 14 and the first electronic device 12 can move toward each other. Therefore, the second reflowable material 148 can contact the first reflowable material 128. The second dielectric layer 18 can contact the first dielectric layer 16. Then, tack bonding can be performed between the second dielectric layer 18 and the first dielectric layer 16 in a reducing atmosphere at a temperature between 130°C and 170°C (e.g., at 150°C). Such a temperature can be the glass transition temperature (Tg) of the second dielectric layer 18 and the first dielectric layer 16. Therefore, the first dielectric layer 16 and the second dielectric layer 18 can be bonded together in a reducing atmosphere at a temperature between 130°C and 170°C (e.g., at 150°C) to jointly form the dielectric structure 19. It should be noted that the dielectric structure 19 is still in the B-stage state. Additionally, a portion of the first dielectric layer 16 (or dielectric structure 19) may extend into the space between the bottom surface 1482 (e.g., end surface) of the second reflowable material 148 and the top surface 1281 (e.g., end surface) of the first reflowable material 128.

[0058] Then, a reflow process can be performed for 15 minutes at a temperature between 240°C and 260°C to fuse the first reflowable material 128 and the second reflowable material 148 together to form a common structure. Figure 1 The solder structure 13 is shown. At the same time, the dielectric structure 19 can be partially cured.

[0059] Then, a full curing process can be performed at approximately 200°C for up to 2 hours to fully cure the dielectric structure 19, such as... Figure 1 As shown. Simultaneously, forming Figure 1 The assembly structure shown is 1.

[0060] In the method shown, the bonding between the first dielectric layer 16 and the second dielectric layer 18 can be formed at a temperature lower than that of the reflow process. For example, this bonding temperature may not exceed 150°C. Therefore, warpage of the first electronic device 12 and the second electronic device 14 can be reduced. For example, the warpage of the first electronic device 12 and the second electronic device 14 may be less than 10 μm. Furthermore, not much IMC is formed in the solder structure 13. Therefore, the solder structure 13 is protected against cracking. In addition, the method can improve the void problem during the bonding process. For example, the top surface 121 of the first electronic device 12 can be a void-free interface. Therefore, the yield of the assembled structure 1 can be improved.

[0061] Figure 12 A cross-sectional view of an assembly structure 2 according to some embodiments of the present disclosure is shown. Figure 13 Show Figure 12 An enlarged view of region "A". Assembly structure 2 may be an electronic package structure, a semiconductor package structure, an electronic structure, an electronic device, or a semiconductor device. Assembly structure 2 may also be referred to as a "three-dimensional form factor device". Assembly structure 2 may be a high-bandwidth memory (HBM). Assembly structure 2 may include a bottom portion 3, a first electronic device 4, a second electronic device 4a, a third electronic device 4b, a top electronic device 4t, a lower solder structure 52, a first solder structure 54, a second solder structure 56, a third solder structure 58, a lower dielectric structure 51, a first dielectric structure 53, a second dielectric structure 55, a third dielectric structure 57, an encapsulant 29, and multiple external connectors 50.

[0062] The bottom portion 3 may be a substrate, a semiconductor die, a semiconductor chip, or an integrated circuit die. The bottom portion 3 may also be referred to as a "first electronic device." In some embodiments, the bottom portion 3 may be a logic device, such as a logic die or a logic chip. In some embodiments, the bottom portion 3 (e.g., a logic device) may include an application-specific integrated circuit (ASIC) chip. The bottom portion 3 may be a controller chip, such as an application processor (AP) chip. The bottom portion 3 may be disposed below the first electronic device 4 and may be electrically connected to the first electronic device 4. The bottom portion 3 (or the logic device or the ASIC chip) may have a top surface 31, a bottom surface 32 opposite to the top surface 31, and a side surface 33 extending between the top surface 31 and the bottom surface 32. The bottom portion 3 (or the logic device or the ASIC chip) may include a main portion 30, an upper conductive structure 34, a lower conductive structure 35, a plurality of through-holes 36, a plurality of upper connectors 37, and a plurality of lower connectors 38.

[0063] The main portion 30 may be a semiconductor substrate and may contain, for example, silicon (Si) or other semiconductor materials. The main portion 30 may have a top surface 301 (e.g., an active surface or a back surface) and a bottom surface 302 (e.g., an active surface or a back surface) opposite the top surface 301.

[0064] The upper conductive structure 34 may be disposed on the top surface 301 of the main portion 30. The top surface of the upper conductive structure 34 may be the top surface 31 of the bottom portion 3. In some embodiments, the upper conductive structure 34 may include multiple front-end process (FEOL) devices, such as resistors, capacitors, inductors, and / or transistors. In some embodiments, the upper conductive structure 34 may further include at least one back-end process (BEOL) interconnect pattern, such as multiple patterned circuit layers, electrically connected to the front-end process (FEOL) devices. The upper conductive structure 34 may include a dielectric structure, multiple circuit layers (including multiple traces and multiple pads) embedded in the dielectric structure, and multiple internal vias. The dielectric structure may be a multilayer film stack deposited on the main portion 30. The internal vias may be disposed in the dielectric structure and may connect the circuit layers. The dielectric structure of the upper conductive structure 34 may contain inorganic or organic materials. In some embodiments, the upper conductive structure 34 may be or may include a single dielectric layer.

[0065] The upper connector 37 (e.g., an upper gasket) may be disposed on or protrude from the upper conductive structure 34. The upper connector 37 may be disposed on or protrude from the top surface 31 of the bottom portion 3. The upper connector 37 may extend beyond the top surface 31 of the bottom portion 3. The upper connector 37 may be part of a circuit layer.

[0066] A lower conductive structure 35 may be disposed on the bottom surface 302 of the main portion 30. The bottom surface of the lower conductive structure 35 may be the bottom surface 32 of the bottom portion 3. In some embodiments, the lower conductive structure 35 may include a plurality of front-end process (FEOL) devices and at least one back-end process (BEOL) interconnect pattern. The lower conductive structure 35 may include a dielectric structure, a plurality of circuit layers (including a plurality of traces and a plurality of pads) embedded in the dielectric structure, and a plurality of internal vias. The dielectric structure may be a multilayer film stack deposited on the main portion 30. The internal vias may be disposed in the dielectric structure and may connect the circuit layers. The dielectric structure of the lower conductive structure 35 may contain inorganic or organic materials. In some embodiments, the lower conductive structure 35 may be or may include a single dielectric layer.

[0067] The lower connector 38 (e.g., a lower gasket) may be disposed on or protrude from the lower conductive structure 35. The lower connector 38 may be disposed on or protrude from the bottom surface 32 of the bottom portion 3. The lower connector 38 may extend beyond the bottom surface 32 of the bottom portion 3. The lower connector 38 may be part of a circuit layer.

[0068] The via 36 extends through (through) the main portion 30, the upper conductive structure 34, and the lower conductive structure 35. The via 36 may also be referred to as a "through-silicon via (TSV)". The via 36 provides a physical and electrical connection between the upper connector 37 and the lower connector 38. Therefore, the upper connector 37 can be electrically connected to the lower connector 38 via the via 36.

[0069] The first electronic device 4 may be disposed above the bottom portion 3. The first electronic device 4 may also be referred to as the "second electronic device". The first electronic device 4 may be or may contain a semiconductor chip, such as a memory chip. The first electronic device 4 may be or may contain a dynamic random access memory (DRAM) chip.

[0070] refer to Figure 13 The first electronic device 4 may have a top surface 41, a bottom surface 42 opposite to the top surface 41, and a side surface 43 extending between the top surface 41 and the bottom surface 42. The first electronic device 4 may include a first main portion 40, a first upper conductive structure 44, a first lower conductive structure 45, a plurality of first through holes 46, a plurality of first upper connectors 47, and a plurality of first lower connectors 48.

[0071] The first main portion 40 may be a semiconductor substrate and may contain, for example, silicon (Si) or other semiconductor materials. The first main portion 40 may have a top surface 401 (e.g., an active surface or a back surface) and a bottom surface 402 (e.g., an active surface or a back surface) opposite to the top surface 401.

[0072] A first upper conductive structure 44 may be disposed on the top surface 401 of the first main portion 40. The top surface of the first upper conductive structure 44 may be the top surface 41 of the first electronic device 4. In some embodiments, the first upper conductive structure 44 may include a plurality of front-end process (FEOL) devices and at least one back-end process (BEOL) interconnect pattern. The first upper conductive structure 44 may include a dielectric structure, a plurality of circuit layers (including a plurality of traces and a plurality of pads) embedded in the dielectric structure, and a plurality of internal vias. The dielectric structure may be a multilayer film stack deposited on the main portion 40. The internal vias may be disposed in the dielectric structure and may connect the circuit layers. The dielectric structure of the first upper conductive structure 44 may contain inorganic or organic materials. In some embodiments, the first upper conductive structure 44 may be or may include a single dielectric layer.

[0073] A first upper connector 47 (e.g., a first upper gasket) may be disposed on or protrude from the first upper conductive structure 44. The first upper connector 47 may be disposed on or protrude from the top surface 41 of the first electronic device 4. The first upper connector 47 may extend beyond the top surface 41 of the first electronic device 4. The first upper connector 47 may be part of a circuit layer.

[0074] A first lower conductive structure 45 may be disposed on the bottom surface 402 of the first main portion 40. The bottom surface of the first lower conductive structure 45 may be the bottom surface 42 of the first electronic device 4. In some embodiments, the first lower conductive structure 45 may include a plurality of front-end process (FEOL) devices and at least one back-end process (BEOL) interconnect pattern. The first lower conductive structure 45 may include a dielectric structure, a plurality of circuit layers (including a plurality of traces and a plurality of pads) embedded in the dielectric structure, and a plurality of internal vias. The dielectric structure may be a multilayer film stack deposited on the main portion 40. The internal vias may be disposed in the dielectric structure and may connect the circuit layers. The dielectric structure of the first lower conductive structure 45 may contain inorganic or organic materials. In some embodiments, the first lower conductive structure 45 may be or may include a single dielectric layer.

[0075] A first lower connector 48 (e.g., a lower gasket) may be disposed on or protrude from a first lower conductive structure 45. The first lower connector 48 may be disposed on or protrude from the bottom surface 42 of the first electronic device 4. The first lower connector 48 may extend beyond the bottom surface 42 of the first electronic device 4. The first lower connector 48 may be part of a circuit layer.

[0076] The first via 46 extends through the first main portion 40, the first upper conductive structure 44, and the first lower conductive structure 45. The first via 46 may also be referred to as a "through-silicon via (TSV)". The first via 46 physically connects and electrically connects the first upper connector 47 and the first lower connector 48. Therefore, the first upper connector 47 can be electrically connected to the first lower connector 48 through the first via 46.

[0077] The first lower connector 48 of the first electronic device 4 is electrically connected to the upper connector 37 of the bottom portion 3 via a lower solder structure 52 to jointly form a lower conductive portion 20a (e.g., a bonding structure). The lower conductive portion 20a may include the first lower connector 48 (e.g., a lower pad), the lower solder structure 52, and the upper connector 37 (e.g., an upper pad). The lower conductive portion 20a may connect the first electronic device 4 and the bottom portion 3 (or a logic device). The lower solder structure 52 may contain, for example, a solder material of Sn / Ag alloy or a reflowable material, or may be formed from, for example, a solder material of Sn / Ag alloy or a reflowable material. The side surfaces of the lower solder structure 52 may be substantially flat surfaces. The lower solder structure 52 may be a single-layer or monolithic structure filled with an intermetallic compound (IMC). The lower solder structure 52 may be a full IMC structure having a single IMC or multiple IMCs.

[0078] The lower dielectric structure 51 may encapsulate the lower conductive portion 20a. The lower dielectric structure 51 may comprise, or be formed from, an organic material such as polyimide (PI), benzocyclobutene (BCB), or polybenzoxazole (PBO). The lower dielectric structure 51 may not contain filler. The lower dielectric structure 51 may be disposed between the first lower conductive structure 45 of the first electronic device 4 and the upper conductive structure 34 of the bottom portion 3 (or logic device), and may contact the first lower conductive structure 45 of the first electronic device 4 and the upper conductive structure 34 of the bottom portion 3 (or logic device).

[0079] The lower dielectric structure 51 may extend beyond the side surface 43 of the first electronic device 4. The lower dielectric structure 51 may include a main portion 514 and an extension portion 515 extending from the main portion 514. The side surface 513 of the main portion 514 may be a curved surface. The main portion 514 may be a raised feature relative to the extension portion 515. The extension portion 515 may be disposed between the encapsulation 29 and the top surface 31 of the bottom portion 3. The top surface 511 of the extension portion 515 may be substantially parallel to the top surface 31 of the bottom portion 3. From a top view, the extension portion 515 may have a wrinkled top surface 511. The side surfaces of the extension portion 515 may be substantially aligned with the side surface 33 of the bottom portion 3 (or logic device) and the side surface 293 of the encapsulation 29.

[0080] The second electronic device 4a, the third electronic device 4b, and the top electronic device 4t may be disposed above or stacked on the first electronic device 4. Each of the second electronic device 4a, the third electronic device 4b, and the top electronic device 4t may be or may contain a semiconductor chip, such as a memory chip. Each of the second electronic device 4a, the third electronic device 4b, and the top electronic device 4t may be or may contain a dynamic random access memory (DRAM) chip.

[0081] The structure of the second electronic device 4a may be the same as that of the first electronic device 4. The second electronic device 4a may have a top surface 41, a bottom surface 42 opposite to the top surface 41, and a side surface 43 extending between the top surface 41 and the bottom surface 42. The second electronic device 4a may include a second main part 40, a second upper conductive structure 44, a second lower conductive structure 45, a plurality of second through holes 46, a plurality of second upper connectors 47, and a plurality of second lower connectors 48.

[0082] The second main portion 40 may have a top surface 401 (e.g., an active surface or a back surface) and a bottom surface 402 (e.g., an active surface or a back surface) opposite the top surface 401. A second upper conductive structure 44 may be disposed on the top surface 401 of the second main portion 40. In some embodiments, the second upper conductive structure 44 may be the same as the first upper conductive structure 44. A second upper connector 47 (e.g., a second upper gasket) may be disposed on or protrude from the second upper conductive structure 44.

[0083] A second lower conductive structure 45 may be disposed on the bottom surface 402 of the second main portion 40. In some embodiments, the second lower conductive structure 45 may be identical to the first lower conductive structure 45. A second lower connector 48 (e.g., a lower gasket) may be disposed on or protrude from the second lower conductive structure 45. A second through-hole 46 may extend through the second main portion 40, the second upper conductive structure 44, and the second lower conductive structure 45. The second through-hole 46 may physically connect and electrically connect the second upper connector 47 and the second lower connector 48.

[0084] The second lower connector 48 of the second electronic device 4a is electrically connected to the first upper connector 47 of the first electronic device 4 via the first solder structure 54 to jointly form the first conductive portion 20 (e.g., a bonding structure). The first conductive portion 20 may include the second lower connector 48 (e.g., a lower pad), the first solder structure 54, and the first upper connector 47 (e.g., an upper pad). The first conductive portion 20 may connect the second electronic device 4a and the first electronic device 4. The first solder structure 54 may be the same as the lower solder structure 52.

[0085] The first dielectric structure 53 may encapsulate the first conductive portion 20. The first dielectric structure 53 may comprise, or be formed from, an organic material such as polyimide (PI), benzocyclobutene (BCB), or polybenzoxazole (PBO). The first dielectric structure 53 may not contain fillers. The first dielectric structure 53 may be disposed between the second lower conductive structure 45 of the second electronic device 4a and the first upper conductive structure 44 of the first electronic device 4, and may contact the second lower conductive structure 45 of the second electronic device 4a and the first upper conductive structure 44 of the first electronic device 4.

[0086] The first dielectric structure 53 may extend beyond the side surface 43 of the first electronic device 4 and the side surface 43 of the second electronic device 4a. The side surface 533 of the first dielectric structure 53 may be a convex surface. The first dielectric structure 53 may be a single-layer or monomeric structure filled with cured organic material. The shape and curvature of the side surface 513 of the lower dielectric structure 51 may be different from the shape and curvature of the side surface 533 of the first dielectric structure 53.

[0087] The third electronic device 4b may be disposed above or stacked on the second electronic device 4a. The structure of the third electronic device 4b may be the same as that of the second electronic device 4a. The third electronic device 4b may be electrically connected to the second electronic device 4a via the second solder structure 56. The second dielectric structure 55 may encapsulate the second conductive portion, which includes the third lower connector 48 of the third electronic device 4b, the second solder structure 56, and the second upper connector 47 of the second electronic device 4a. The side surface 553 of the second dielectric structure 55 may be a convex surface.

[0088] The top electronic device 4t may be positioned above or stacked on the third electronic device 4b. The structure of the top electronic device 4t may be similar to that of the third electronic device 4b, except that the top electronic device 4t does not include an upper conductive structure, through-holes, and an upper connector. The top electronic device 4t may be electrically connected to the third electronic device 4b via a third solder structure 58. A third dielectric structure 57 may encapsulate a third conductive portion, which includes a fourth lower connector of the top electronic device 4t, the third solder structure 58, and a third upper connector of the third electronic device 4b. The side surface 573 of the third dielectric structure 57 may be a convex surface.

[0089] Encapsulation 29 can be a molding material with or without filler. Encapsulation 29 can encapsulate the bottom portion 3, the first electronic device 4, the second electronic device 4a, the third electronic device 4b, the top electronic device 4t, the lower dielectric structure 51, the first dielectric structure 53, the second dielectric structure 55, and the third dielectric structure 57. Encapsulation 29 can be separated from the bottom portion 3 through the extension 515 of the lower dielectric structure 51.

[0090] External connectors 50 may be formed on or disposed on the lower connector 38 (e.g., lower gasket) of the bottom portion 3. Each of the external connectors 50 may be solder material, solder bump, conductive connector, resolderable connector, or resolderable material. External connectors 50 may include controlled collapse chip connectors.

[0091] Figures 14 to 31 A manufacturing method for manufacturing an assembly structure according to some embodiments of the present disclosure is illustrated. In some embodiments, the method is used to manufacture... Figure 12 Assembly structure 2 is shown in the figure.

[0092] refer to Figure 14 A carrier 90 may be provided, and a release layer 92 may be formed on or disposed on the surface of the carrier 90. The carrier 90 may be a glass substrate or an FR4 substrate. The carrier 90 may be a panel type (or panel structure) or a wafer type (or wafer structure). Then, a bottom portion 3' may be formed on or disposed on the release layer 92 on the carrier 90. Figure 14 The bottom part 3' can be with Figure 12 The bottom portion 3' is identical to the top portion 3'. The lower connector 38 (e.g., lower gasket) and the outer connector 50 of the bottom portion 3' can be embedded in the release layer 92. The dielectric layer 21 can then be coated onto or disposed on the top surface 31 of the bottom portion 3' to cover the upper connector 37 (e.g., upper gasket). The dielectric layer 21 may comprise an organic material such as polyimide (PI), benzocyclobutene (BCB), or polybenzoxazole (PBO). The top surface 211 (e.g., outer surface) of the dielectric layer 21 may be higher than the top surface 371 (e.g., end surface) of the upper connector 37 (e.g., upper gasket). The dielectric layer 21 can then be pre-cured, for example, at a temperature of 140°C for 30 minutes, such that the dielectric layer 21 is in a stage B state.

[0093] refer to Figure 15 A polishing process (e.g., chemical mechanical polishing (CMP)) can be performed on the top surface 211 of the dielectric layer 21. Therefore, the upper portion of the dielectric layer 21 and the upper portion of the upper connector 37 can be removed simultaneously. After the polishing process, the top surface 371 (e.g., end surface) of the upper connector 37 can be substantially aligned with the top surface 211 (e.g., outer surface) of the dielectric layer 21. The upper connector 37 can be embedded in the dielectric layer 21. The top surface 371 (e.g., end surface) of the upper connector 37 can be exposed by the top surface 211 (e.g., outer surface) of the dielectric layer 21.

[0094] refer to Figure 16 A carrier 96 may be provided, and a release layer 94 may be formed on or disposed on the surface of the carrier 96. The carrier 96 may be a glass substrate or an FR4 substrate. The carrier 96 may be a panel type (or panel structure) or a wafer type (or wafer structure). Then, a first electronic device 4' may be formed on or disposed on the release layer 94 on the carrier 96. Figure 16 The first electronic device 4' can be connected with Figure 12 The first electronic device 4 is the same.

[0095] A first upper connector 47 (e.g., upper gasket) of the first electronic device 4' may be embedded in a release layer 94. A plurality of lower resolderable materials 52 may then be formed on or disposed on the first lower connector 48 (e.g., lower gasket). A first lower dielectric layer 22 may then be coated onto a bottom surface 42 of the first electronic device 4' to cover the lower resolderable materials 52. The first lower dielectric layer 22 may comprise an organic material such as polyimide (PI), benzocyclobutene (BCB), or polybenzoxazole (PBO). The bottom surface 222 (e.g., outer surface) of the first lower dielectric layer 22 may be lower than the bottom surface 522 (e.g., end surface) of the lower resolderable materials 52. The first lower dielectric layer 22 may then be pre-cured, for example, at a temperature of 140°C for 30 minutes, such that the first lower dielectric layer 22 is in a stage B state.

[0096] refer to Figure 17 A fly-cut process can be performed on the bottom surface 222 (e.g., outer surface) of the first lower dielectric layer 22. After the fly-cut process, the bottom surface 522 (e.g., end surface) of the lower resoldable material 52 can be exposed from the bottom surface 222 (e.g., outer surface) of the first lower dielectric layer 22. In some embodiments, the bottom surface 522 (e.g., end surface) of the lower resoldable material 52 can be recessed from the bottom surface 222 (e.g., outer surface) of the first lower dielectric layer 22 by about 100 nm.

[0097] refer to Figure 18 The first lower dielectric layer 22 can be etched or thinned by removing slag, so that the lower resolderable material 52 can protrude less than 1 μm from the bottom surface 222 (e.g., the outer surface) of the first lower dielectric layer 22.

[0098] refer to Figure 19 The first electronic device 4' and the first lower dielectric layer 22 can be placed on the release layer 98 on the carrier 99. Then, the release layer 94 and the carrier 96 can be removed.

[0099] refer to Figure 20The first upper dielectric layer 23 can be coated onto or disposed on the top surface 41 of the first electronic device 4' to cover the first upper connector 47 (e.g., upper gasket). The first upper dielectric layer 23 may contain an organic material such as polyimide (PI), benzocyclobutene (BCB), or polybenzoxazole (PBO). The top surface 231 (e.g., outer surface) of the first upper dielectric layer 23 may be higher than the top surface 471 (e.g., end surface) of the first upper connector 47 (e.g., upper gasket). The first upper dielectric layer 23 can then be pre-cured, for example, at a temperature of 140°C for 30 minutes, such that the first upper dielectric layer 23 is in a stage B state.

[0100] refer to Figure 21 A polishing process (e.g., chemical mechanical polishing (CMP)) can be performed on the top surface 231 of the first upper dielectric layer 23. After the polishing process, the top surface 471 (e.g., end surface) of the first upper connector 47 can be substantially aligned with the top surface 231 (e.g., outer surface) of the first upper dielectric layer 23. The first upper connector 47 can be embedded in the first upper dielectric layer 23. The top surface 471 (e.g., end surface) of the first upper connector 47 can be exposed by the top surface 231 (e.g., outer surface) of the first upper dielectric layer 23.

[0101] refer to Figure 22 A single-cut process can be performed along the cutting line 49 to form multiple first electronic devices 4.

[0102] The second electronic device 4a and the third electronic device 4b can be manufactured using the same methods used to manufacture the first electronic device 4.

[0103] refer to Figure 23 It can provide a top electronic device of 4t'. Figure 23 The top electronic device 4t' can be connected with Figure 12 The top electronic device 4t is identical to the top electronic device 4t. Then, a dielectric layer 22 can be coated onto or disposed on the bottom surface 42 of the top electronic device 4t' to cover the third reflowable material 58. The dielectric layer 22 may contain organic materials such as polyimide (PI), benzocyclobutene (BCB), or polybenzoxazole (PBO). The bottom surface 222 (e.g., the outer surface) of the dielectric layer 22 may be lower than the bottom surface 582 (e.g., the end surface) of the third reflowable material 58. The dielectric layer 22 can then be pre-cured, for example, at a temperature of 140°C for 30 minutes, so that the dielectric layer 22 is in a stage B state.

[0104] refer to Figure 24A fly-cut process can be performed on the bottom surface 222 (e.g., the outer surface) of the dielectric layer 22. After the fly-cut process, the bottom surface 582 (e.g., the end surface) of the third reflowable material 58 can be exposed from the bottom surface 222 (e.g., the outer surface) of the dielectric layer 22. In some embodiments, the bottom surface 582 (e.g., the end surface) of the third reflowable material 58 can be recessed from the bottom surface 222 (e.g., the outer surface) of the dielectric layer 22 by about 100 nm.

[0105] refer to Figure 25 The dielectric layer 22 can be etched or thinned by removing slag, so that the third resolderable material 58 can protrude less than 1 μm from the bottom surface 222 (e.g., the outer surface) of the dielectric layer 22.

[0106] refer to Figure 26 A single-cut process can be performed along the cutting line 49 to form multiple top electronic devices 4t.

[0107] refer to Figure 27 , Figure 22 The first electronic device 4 can be coupled to Figure 15 The bottom portion 3'. For example, bonding can be performed between dielectric layer 21 and first lower dielectric layer 22 in a reducing atmosphere at a temperature between 130°C and 170°C (e.g., at 150°C). Thus, dielectric layer 21 and first lower dielectric layer 22 can be bonded together to jointly form lower dielectric structure 51. Note that lower dielectric structure 51 is still in stage B. Then, a reflow process can be performed at a temperature between 240°C and 260°C for 15 minutes to bond lower reflowable material 52 to upper connector 37 to form lower solder structure 52. Then, a full curing process can be performed at a temperature of about 200°C for 2 hours to fully cure lower dielectric structure 51.

[0108] refer to Figure 28 The second electronic device 4a can be coupled to the first electronic device 4. The third electronic device 4b can be coupled to the second electronic device 4a.

[0109] refer to Figure 29 The top electronic device 4t can be coupled to the third electronic device 4b.

[0110] refer to Figure 30 Encapsulant 29 may be formed on the side surface 513 of the main portion 514 of the lower dielectric structure 51 and the top surface 511 of the extension portion 515 of the lower dielectric structure 51 on the top surface 31 of the bottom portion 3' to encapsulate and cover the first electronic device 4, the second electronic device 4a, the third electronic device 4b and the top electronic device 4t.

[0111] refer to Figure 31It can remove the release layer 92 and the carrier 90.

[0112] Then, a single-cut process can be performed to form Figure 1 The multiple assembly structures 1 shown.

[0113] Figure 32 A cross-sectional view of an assembly structure 2a according to some embodiments of the present disclosure is shown. Figure 32 The assembly structure 2a is similar to Figure 12 The assembly structure 2, except that the second electronic device 4a may be misaligned with the first electronic device 4, the third electronic device 4b may be misaligned with the second electronic device 4a, and the top electronic device 4t may be misaligned with the third electronic device 4b. The first main portion 40 of the first electronic device 4 and the second main portion 40 of the second electronic device 4a may form a stepped configuration. The first solder structure 54, the second solder structure 56, and the third solder structure 58 may have inclined sidewalls.

[0114] Figure 33 A cross-sectional view of an assembly structure 6 according to some embodiments of the present disclosure is shown. Figure 34 Show Figure 33 A magnified view of area "B". Figure 33 and Figure 34 The assembly structure 6 is similar to Figure 12 and Figure 13 Assembly structure 2. Assembly structure 6 may include a bottom portion 7, a first electronic device 8, a second electronic device 8a, a third electronic device 8b, a top electronic device 8t, a lower solder structure 52, a first solder structure 54, a second solder structure 56, a third solder structure 58, a lower dielectric structure 62, a first dielectric structure 64, a second dielectric structure 66, a third dielectric structure 68, an encapsulation 69, and a plurality of external connectors 50.

[0115] Figure 33 and Figure 34 The bottom part 7 is similar to Figure 12 and Figure 13 The bottom portion 3. The bottom portion 7 may have a top surface 71, a bottom surface 72 opposite to the top surface 71, and a side surface 73 extending between the top surface 71 and the bottom surface 72. The bottom portion 7 may include a main portion 70, an upper conductive structure 74, a lower conductive structure 75, a plurality of through holes 76, a plurality of upper connectors 77, and a plurality of lower connectors 78.

[0116] The main portion 70 may have a top surface 701 and a bottom surface 702 opposite to the top surface 701. An upper conductive structure 74 may be disposed on the top surface 701 of the main portion 70. The top surface of the upper conductive structure 74 may be the top surface 71 of the bottom portion 7. In some embodiments, the upper conductive structure 74 may include a plurality of front-end process (FEOL) devices and at least one back-end process (BEOL) interconnect pattern. The upper conductive structure 74 may include a dielectric structure, a plurality of circuit layers (including a plurality of traces and a plurality of pads) embedded in the dielectric structure, and a plurality of internal vias. The dielectric structure may be a multilayer film stack deposited on the main portion 70. The internal vias may be disposed in the dielectric structure and may connect the circuit layers. The dielectric structure of the upper conductive structure 74 may contain inorganic or organic materials. In some embodiments, the upper conductive structure 74 may be or may include a single dielectric layer.

[0117] An upper connector 77 (e.g., an upper gasket) may be disposed on the top surface 701 of the main portion 70. The upper connector 77 may be embedded in the upper conductive structure 74 of the bottom portion 7 and may be exposed by the top surface 71 of the bottom portion 7. The top surface 771 of the upper connector 77 is substantially aligned with the top surface 71 of the bottom portion 7.

[0118] A lower conductive structure 75 may be disposed on the bottom surface 702 of the main portion 70. In some embodiments, the lower conductive structure 75 may include a plurality of front-end process (FEOL) devices and at least one back-end process (BEOL) interconnect pattern. The lower conductive structure 75 may include a dielectric structure, a plurality of circuit layers (including a plurality of traces and a plurality of pads) embedded in the dielectric structure, and a plurality of internal vias. The dielectric structure may be a multilayer film stack deposited on the main portion 70. The internal vias may be disposed in the dielectric structure and may connect the circuit layers. The dielectric structure of the lower conductive structure 75 may comprise inorganic or organic materials. In some embodiments, the lower conductive structure 75 may be or may comprise a single dielectric layer.

[0119] The lower connector 78 (e.g., a lower gasket) may be disposed on or protrude from the lower conductive structure 75. The lower connector 78 may be disposed on or protrude from the bottom surface 72 of the bottom portion 7. The lower connector 78 may extend beyond the bottom surface 72 of the bottom portion 7. The upper connector 77 may be electrically connected to the lower connector 78 through a through-hole 76.

[0120] The first electronic device 8 may be disposed above the bottom portion 7. The first electronic device 7 may also be referred to as the "second electronic device". The first electronic device 8 may be or may contain a semiconductor chip, such as a memory chip. The first electronic device 8 may be or may contain a dynamic random access memory (DRAM) chip.

[0121] refer to Figure 34 The first electronic device 8 may have a top surface 81, a bottom surface 82 opposite to the top surface 81, and a side surface 83 extending between the top surface 81 and the bottom surface 82. The first electronic device 8 may include a first main portion 80, a first upper conductive structure 84, a first lower conductive structure 85, a plurality of first through holes 86, a plurality of first upper connectors 87, and a plurality of first lower connectors 88.

[0122] The first main portion 80 may be a semiconductor substrate and may contain, for example, silicon (Si) or other semiconductor materials. The first main portion 80 may have a top surface 801 and a bottom surface 802 opposite to the top surface 801.

[0123] A first upper conductive structure 84 may be disposed on the top surface 801 of the first main portion 80. The top surface of the first upper conductive structure 84 may be the top surface 81 of the first electronic device 8. In some embodiments, the first upper conductive structure 84 may include a plurality of front-end process (FEOL) devices and at least one back-end process (BEOL) interconnect pattern. The first upper conductive structure 84 may include a dielectric structure, a plurality of circuit layers (including a plurality of traces and a plurality of pads) embedded in the dielectric structure, and a plurality of internal vias. The dielectric structure may be a multilayer film stack deposited on the main portion 80. The internal vias may be disposed in the dielectric structure and may connect the circuit layers. The dielectric structure of the first upper conductive structure 84 may contain inorganic or organic materials. In some embodiments, the first upper conductive structure 84 may be or may include a single dielectric layer.

[0124] A first upper connector 87 (e.g., a first upper gasket) may be disposed on the top surface 801 of the first main portion 80. The first upper connector 87 may be embedded in the first upper conductive structure 84 of the first electronic device 8 and may be exposed by the top surface 81 of the first electronic device 8. The top surface 871 of the first upper connector 87 is substantially aligned with the top surface 81 of the first electronic device 8 (i.e., the top surface 841 of the first upper conductive structure 84).

[0125] A first lower conductive structure 85 may be disposed on the bottom surface 802 of the first main portion 80. The bottom surface of the first lower conductive structure 85 may be the bottom surface 82 of the first electronic device 8. In some embodiments, the first lower conductive structure 85 may include a plurality of front-end process (FEOL) devices and at least one back-end process (BEOL) interconnect pattern. In some embodiments, the first lower conductive structure 85 may be or may include a single dielectric layer.

[0126] A first lower connector 88 (e.g., a lower gasket) may be disposed on or protrude from a first lower conductive structure 85. The first lower connector 88 may be disposed on or protrude from the bottom surface 82 of the first electronic device 8. The first lower connector 88 may extend beyond the bottom surface 82 of the first electronic device 8. A first upper connector 87 may be electrically connected to the first lower connector 88 through a first through-hole 86.

[0127] A first lower connector 88 of the first electronic device 8 is electrically connected to an upper connector 77 of the bottom portion 7 via a lower solder structure 52 to jointly form a lower conductive portion 60a (e.g., a bonding structure). The lower conductive portion 60a may include the first lower connector 88 (e.g., a lower pad), the lower solder structure 52, and the upper connector 77 (e.g., an upper pad). The lower conductive portion 60a may connect the first electronic device 8 and the bottom portion 7.

[0128] The lower dielectric structure 62 may encapsulate the lower conductive portion 60a. The lower dielectric structure 62 may comprise, or be formed from, an organic material such as polyimide (PI), benzocyclobutene (BCB), or polybenzoxazole (PBO). The lower dielectric structure 62 may not contain filler. The lower dielectric structure 62 may be disposed between the first lower conductive structure 85 of the first electronic device 8 and the upper conductive structure 74 of the bottom portion 7, and may contact both the first lower conductive structure 85 and the upper conductive structure 74 of the bottom portion 7.

[0129] The lower dielectric structure 62 may extend beyond the side surface 83 of the first electronic device 8. The side surface 623 of the lower dielectric structure 62 may be a convex surface.

[0130] The second electronic device 8a, the third electronic device 8b, and the top electronic device 8t may be disposed above or stacked on the first electronic device 8. Each of the second electronic device 8a, the third electronic device 8b, and the top electronic device 8t may be or may contain a semiconductor chip, such as a memory chip. Each of the second electronic device 8a, the third electronic device 8b, and the top electronic device 8t may be or may contain a dynamic random access memory (DRAM) chip.

[0131] The structure of the second electronic device 8a may be the same as that of the first electronic device 8. The second electronic device 8a may have a top surface 81, a bottom surface 82 opposite to the top surface 81, and a side surface 83 extending between the top surface 81 and the bottom surface 82. The second electronic device 8a may include a second main part 80, a second upper conductive structure 84, a second lower conductive structure 85, a plurality of second through holes 86, a plurality of second upper connectors 87, and a plurality of second lower connectors 88.

[0132] The second main portion 80 may have a top surface 801 and a bottom surface 802 opposite to the top surface 801. A second upper conductive structure 84 may be disposed on the top surface 801 of the second main portion 80. In some embodiments, the second upper conductive structure 84 may be the same as the first upper conductive structure 84. A second upper connector 87 may be embedded in the second upper conductive structure 84. The top surface of the second upper connector 87 is substantially aligned with the top surface 81 of the second electronic device 8a.

[0133] The second lower conductive structure 85 may be disposed on the bottom surface 802 of the second main portion 80. The second lower connector 88 (e.g., a lower gasket) may be disposed on or protrude from the second lower conductive structure 85. The second through hole 86 may physically connect and electrically connect the second upper connector 87 and the second lower connector 88.

[0134] The second lower connector 88 of the second electronic device 8a is electrically connected to the first upper connector 87 of the first electronic device 8a via the first solder structure 54 to jointly form the first conductive portion 60 (e.g., a bonding structure). The first conductive portion 60 may include the second lower connector 88, the first solder structure 54, and the first upper connector 77.

[0135] The first dielectric structure 64 may encapsulate the first conductive portion 60. The first dielectric structure 64 may be disposed between the second lower conductive structure 85 of the second electronic device 8a and the first upper conductive structure 84 of the first electronic device 4, and may contact the second lower conductive structure 85 of the second electronic device 8a and the first upper conductive structure 84 of the first electronic device 4. The first dielectric structure 64 may extend beyond the side surface 83 of the first electronic device 8a and the side surface 83 of the second electronic device 8a. The side surface 643 of the first dielectric structure 64 may be a convex surface. The first dielectric structure 64 may be a single-layer or monomeric structure filled with cured organic material. The shape and curvature of the side surface 623 of the lower dielectric structure 62 may be the same as the shape and curvature of the side surface 643 of the first dielectric structure 64.

[0136] The third electronic device 8b may be disposed above or stacked on the second electronic device 8a. The structure of the third electronic device 8b may be the same as that of the second electronic device 8a. The third electronic device 8b may be electrically connected to the second electronic device 8a via the second solder structure 56. The second dielectric structure 66 may encapsulate the second conductive portion, which includes the third lower connector 88 of the third electronic device 8b, the second solder structure 56, and the second upper connector 87 of the second electronic device 8a. The side surface 663 of the second dielectric structure 66 may be a convex surface.

[0137] The top electronic device 8t may be positioned above or stacked on the third electronic device 8b. The structure of the top electronic device 8t may be similar to that of the third electronic device 8b, except that the top electronic device 8t does not include an upper conductive structure, through-holes, or an upper connector. The top electronic device 8t may be electrically connected to the third electronic device 8b via a third solder structure 58. A third dielectric structure 68 may encapsulate a third conductive portion, which includes a fourth lower connector of the top electronic device 8t, the third solder structure 58, and a third upper connector of the third electronic device 8b. The side surface 683 of the third dielectric structure 68 may be a convex surface.

[0138] Encapsulation 69 may be a molding material with or without fillers. Encapsulation 69 may encapsulate the bottom portion 7, the first electronic device 8, the second electronic device 8a, the third electronic device 8b, the top electronic device 8t, the lower dielectric structure 62, the first dielectric structure 64, the second dielectric structure 66, and the third dielectric structure 68. Encapsulation 69 may contact the upper conductive structure 74 of the bottom portion 7 to form an inorganic-to-inorganic bond. Encapsulation 69 may contact the top surface 71 of the bottom portion 7.

[0139] External connectors 50 may be formed on or disposed on the lower connector 78 of the bottom portion 7. Each of the external connectors 50 may be solder material, solder bump, conductive connector, resolderable connector, or resolderable material.

[0140] Figures 35 to 49 A manufacturing method for manufacturing an assembly structure according to some embodiments of the present disclosure is illustrated. In some embodiments, the method is used to manufacture... Figure 33 The assembly structure 6 shown is illustrated.

[0141] refer to Figure 35 A bottom portion 7' ​​may be provided, and the bottom portion 7' ​​may be formed on or disposed on a release layer 92 on a carrier 90. Figure 35 The bottom part 7' can be with Figure 33 The bottom portion 7' ​​is the same. The lower connector 78 (e.g., lower pad) and the outer connector 50 of the bottom portion 7' ​​can be embedded in the release layer 92.

[0142] The top surface 771 of the upper connector 77 of the bottom portion 7' ​​is substantially aligned with the top surface 71 of the bottom portion 7'.

[0143] refer to Figure 36 The first electronic device 8' may be formed on or disposed on the release layer 94 on the carrier 96. Figure 36 The first electronic device 8' can be connected with Figure 33The first electronic device 8 is identical to the first upper connector 87. The top surface 871 of the first upper connector 87 is substantially aligned with the top surface 81 of the first electronic device 8 (i.e., the top surface 841 of the first upper conductive structure 84). Then, a first lower dielectric layer 62 can be coated onto or disposed on the bottom surface 82 of the first electronic device 8' to cover the lower resolderable material 52. The first lower dielectric layer 62 may contain organic materials such as polyimide (PI), benzocyclobutene (BCB), or polybenzoxazole (PBO). The bottom surface 622 of the first lower dielectric layer 62 may be lower than the bottom surface 522 of the lower resolderable material 52. The first lower dielectric layer 62 can then be pre-cured, for example, at a temperature of 140°C for 30 minutes, such that the first lower dielectric layer 62 is in a stage B state.

[0144] refer to Figure 37 A fly-cut process can be performed on the bottom surface 622 of the first lower dielectric layer 62. After the fly-cut process, the bottom surface 522 of the lower resoldable material 52 can be exposed from the bottom surface 622 of the first lower dielectric layer 62. In some embodiments, the bottom surface 522 of the lower resoldable material 52 can be recessed from the bottom surface 622 of the first lower dielectric layer 62 by about 100 nm.

[0145] refer to Figure 38 The first lower dielectric layer 62 can be etched or thinned by removing slag, so that the lower resolderable material 52 can protrude less than 1 μm from the bottom surface 622 of the first lower dielectric layer 62.

[0146] refer to Figure 39 The first electronic device 8' and the first lower dielectric layer 62 can be disposed on the release layer 98 on the carrier 99. Then, the release layer 94 and the carrier 96 can be removed.

[0147] refer to Figure 40 The release layer 98 and the carrier 99 can then be removed. A single-cut process can then be performed along the cutting line 89 to form multiple first electronic devices 8.

[0148] The second electronic device 8a and the third electronic device 8b can be manufactured using the same methods used to manufacture the first electronic device 8.

[0149] refer to Figure 41 It can provide top electronic devices 8t'. Figure 41 The top electronic device 8t' can be connected with Figure 33The top electronic device 8t is identical to the top electronic device 8t. Then, a dielectric layer 68 can be coated onto or disposed on the bottom surface 82 of the top electronic device 8t' to cover the third reflowable material 58. The dielectric layer 68 may contain organic materials such as polyimide (PI), benzocyclobutene (BCB), or polybenzoxazole (PBO). The bottom surface 682 (e.g., the outer surface) of the dielectric layer 68 may be lower than the bottom surface 582 of the third reflowable material 58. The dielectric layer 68 can then be pre-cured, for example, at a temperature of 140°C for 30 minutes, so that the dielectric layer 68 is in stage B.

[0150] refer to Figure 42 A fly-cut process can be performed on the bottom surface 682 of the dielectric layer 68. After the fly-cut process, the bottom surface 582 of the third reflowable material 58 can be exposed from the bottom surface 682 of the dielectric layer 68. In some embodiments, the bottom surface 582 of the third reflowable material 58 can be recessed from the bottom surface 682 of the dielectric layer 68 by about 100 nm.

[0151] refer to Figure 43 The dielectric layer 68 can be etched or thinned by removing slag, so that the third resolderable material 58 can protrude less than 1 μm from the bottom surface 682 of the dielectric layer 68.

[0152] refer to Figure 44 A single-cut process can be performed along the cutting line 89 to form multiple top electronic devices 8t.

[0153] refer to Figure 45 , Figure 40 The first electronic device 8 can be coupled to Figure 35 The bottom portion 7'. For example, the first lower dielectric layer 62 can be bonded to the upper conductive structure 74 of the bottom portion 7' ​​in a reducing atmosphere at a temperature between 130°C and 170°C (e.g., at 150°C). Thus, the first lower dielectric layer 62 can be used to form the lower dielectric structure 62. Note that the lower dielectric structure 62 is still in the B-stage state. Then, a reflow process can be performed at a temperature between 240°C and 260°C for 15 minutes to bond the lower reflowable material 52 to the upper connector 77 to form the lower solder structure 52. Then, a full curing process can be performed at a temperature of about 200°C for 2 hours to fully cure the lower dielectric structure 62.

[0154] refer to Figure 46 The second electronic device 8a can be coupled to the first electronic device 8. The third electronic device 8b can be coupled to the second electronic device 8a.

[0155] refer to Figure 47 The top electronic device 8t can be connected to the third electronic device 8b.

[0156] refer to Figure 48 Encapsulant 29 may be formed on the top surface 71 of the bottom portion 7' ​​to encapsulate and cover the first electronic device 8, the second electronic device 8a, the third electronic device 8b and the top electronic device 8t.

[0157] refer to Figure 49 It can remove the release layer 92 and the carrier 90.

[0158] Then, a single-cut process can be performed to form Figure 33 The multiple assembly structures shown are 6.

[0159] Figure 50 A cross-sectional view of an assembly structure 6a according to some embodiments of the present disclosure is shown. Figure 50 The assembly structure 6a is similar to Figure 33 The assembly structure 6, except that the second electronic device 8a may be misaligned with the first electronic device 8, the third electronic device 8b may be misaligned with the second electronic device 8a, and the top electronic device 8t may be misaligned with the third electronic device 8bb.

[0160] Figure 51 A cross-sectional view of an assembly structure 2b according to some embodiments of the present disclosure is shown. Figure 51 The assembly structure 2b is similar to Figure 12 The assembly structure 2 is described below, with the following differences: The fourth electronic device 4c can be coupled to the third electronic device 4b. The fifth electronic device 4d can be coupled to the fourth electronic device 4c. The sixth electronic device 4e can be coupled to the fifth electronic device 4d. The seventh electronic device 4f can be coupled to the sixth electronic device 4e. The top electronic device 4t can be coupled to the seventh electronic device 4f. The lower dielectric structure 51, the first dielectric structure 53, and the second dielectric structure 55 can be omitted. The third dielectric structure 57 can be disposed between the fourth electronic device 4c and the third electronic device 4b.

[0161] Unless otherwise specified, spatial descriptions such as “above,” “below,” “up,” “left,” “right,” “lower,” “top,” “bottom,” “vertical,” “horizontal,” “side surface,” “above,” “below,” “upper part,” “above,” and “below” are relative to the orientation shown in the figures. It should be understood that the spatial descriptions used herein are for illustrative purposes only, and embodiments of the structures described herein can be arranged in space in any orientation or manner, provided that the advantages of the embodiments of this disclosure are not compromised by such arrangement.

[0162] As used herein, the terms “approximately,” “generally,” “roughly,” “about,” and “approximately” are used to describe and explain minor variations. When used in conjunction with an event or situation, these terms may refer to examples where the event or situation occurred precisely or very approximately. For example, when used in conjunction with a numerical value, these terms may refer to a range of variation less than or equal to ±10% of the stated value, such as less than or equal to ±5%, less than or equal to ±4%, less than or equal to ±3%, less than or equal to ±2%, less than or equal to ±1%, less than or equal to ±0.5%, less than or equal to ±0.1%, or less than or equal to ±0.05%. For example, if a first value is within a range of variation less than or equal to ±10% of a second value, such as less than or equal to ±5%, less than or equal to ±4%, less than or equal to ±3%, less than or equal to ±2%, less than or equal to ±1%, less than or equal to ±0.5%, less than or equal to ±0.1%, or less than or equal to ±0.05%, then the first value may be considered “generally” the same as or equal to the second value.

[0163] If the displacement between two surfaces is no greater than 5 µm, 2 µm, 1 µm, or 0.5 µm, then the two surfaces are considered coplanar or substantially coplanar. If the displacement between the highest and lowest points of a surface is no greater than 5 µm, 2 µm, 1 µm, or 0.5 µm, then the surface is considered substantially flat.

[0164] As used herein, unless the context clearly indicates otherwise, the singular forms “a / an” and “the” may contain a plural or multiple indicators.

[0165] As used herein, the terms “conductive,” “electrically conductive,” and “conductivity” refer to the ability to conduct electric current. Conductive materials are those that offer little or no resistance to the flow of electric current. A unit of measurement for conductivity is Siemens per meter (S / m). Typically, conductive materials have a conductivity greater than approximately 10. 4 S / m, for example, at least 10 5 S / m or at least 10 6 A material with conductivity of S / m. The conductivity of a material can sometimes vary with temperature. Unless otherwise specified, the conductivity of a material is measured at room temperature.

[0166] In addition, quantities, ratios, and other numerical values ​​are sometimes presented in range format in this document. It should be understood that such range format is used for convenience and brevity, and should be flexibly interpreted as including not only the numerical values ​​explicitly specified as the limits of the range, but also all individual numerical values ​​or subranges covered within the range, as if each numerical value and subrange were explicitly specified.

[0167] While this disclosure has been described and illustrated with reference to specific embodiments thereof, such descriptions and illustrations are not limiting. Those skilled in the art will understand that various changes and alternative equivalents may be made without departing from the true spirit and scope of this disclosure as defined by the appended claims. Illustrations may not be drawn to scale. Due to manufacturing processes and tolerances, the process reproduction in this disclosure may differ from actual equipment. Other embodiments may exist that are not specifically described in this disclosure. The description and drawings should be considered illustrative rather than limiting. Modifications may be made to suit particular circumstances, materials, compositions, methods, or processes to the objectives, spirit, and scope of this disclosure. All such modifications are considered to be included within the scope of the appended claims. Although the disclosed methods have been described herein with reference to specific operations performed in a particular order, it should be understood that these operations may be combined, subdivided, or reordered to form equivalent methods without departing from the teachings of this disclosure. Therefore, unless specifically indicated herein, the order and grouping of operations are not limitations of this disclosure.

Claims

1. An assembly structure comprising: First electronic device; A second electronic device is disposed above the first electronic device; A conductive portion that connects the first electronic device and the second electronic device; as well as A dielectric structure that encapsulates the conductive portion and extends beyond the side surfaces of the first electronic device and the second electronic device.

2. The assembly structure according to claim 1, wherein each of the first electronic device and the second electronic device is a semiconductor chip or semiconductor die, and wherein the dielectric structure comprises an organic material.

3. The assembly structure according to claim 1, wherein the conductive portion comprises: A first connector extends beyond the top surface of the first electronic device; A second connector extends beyond the bottom surface of the second electronic device; as well as A solder structure is disposed between the first connector and the second connector.

4. The assembly structure according to claim 3, wherein the side surface of the solder structure is a convex surface, and the curvature of the side surface of the solder structure is different from the curvature of the side surface of the dielectric structure.

5. The assembly structure according to claim 1, wherein the conductive portion comprises: A first connector is embedded in the first electronic device and exposed by the top surface of the first electronic device; A second connector extends beyond the bottom surface of the second electronic device; as well as Solder material, which is placed between the first connector and the second connector.

6. The assembly structure according to claim 1, wherein the first electronic device includes a first conductive structure comprising an inorganic material, the second electronic device includes a second conductive structure comprising an inorganic material, and the dielectric structure contacts the first conductive structure and the second conductive structure.

7. The assembly structure according to claim 1, further comprising: A logic device disposed below the first electronic device and electrically connected to the first electronic device; as well as An encapsulation material that encapsulates the first electronic device and the second electronic device.

8. The assembly structure according to claim 7, further comprising: The lower conductive portion connects the first electronic device and the logic device; as well as A lower dielectric structure encapsulates the lower conductive portion and extends beyond the side surface of the first electronic device, wherein the lower dielectric structure comprises an organic material, and a portion of the lower dielectric structure lies between the encapsulation and the top surface of the logic device.

9. The assembly structure according to claim 8, wherein the curvature of the side surface of the lower dielectric structure is different from the curvature of the side surface of the dielectric structure.

10. A manufacturing method, comprising: A first dielectric layer is formed on a first electronic device to cover the end surface of a first reflowable material on the first electronic device, wherein the first dielectric layer comprises an organic material; Remove a portion of the first dielectric layer to expose the first resolderable material; A second dielectric layer is formed on a second electronic device to cover the end surface of a second resolderable material on the second electronic device, wherein the second dielectric layer comprises an organic material; Remove a portion of the second dielectric layer to expose the second resolderable material; The first dielectric layer and the second dielectric layer are bonded together to form a dielectric structure. as well as The first reflowable material and the second reflowable material are fused together to form a solder structure.

11. The manufacturing method according to claim 10, further comprising: The first dielectric layer is pre-cured so that the first dielectric layer is in stage B state; as well as The second dielectric layer is pre-cured, so that the second dielectric layer is in stage B state.

12. The manufacturing method of claim 10, wherein removing the portion of the first dielectric layer comprises: Remove the portion of the first dielectric layer and a portion of the first reflowable material, wherein the first reflowable material is recessed from the outer surface of the first dielectric layer.

13. The manufacturing method of claim 10, wherein removing the portion of the second dielectric layer to expose the second reflowable material comprises: Remove the portion of the second dielectric layer and a portion of the second reflowable material, wherein the second reflowable material is recessed from the outer surface of the second dielectric layer; and This causes the second resolderable material to protrude from the outer surface of the second dielectric layer.

14. The manufacturing method according to claim 13, further comprising: A second upper dielectric layer is formed on the top surface of the second electronic device to cover the end surface of the second upper pad protruding from the second upper conductive structure of the second electronic device, wherein the second upper dielectric layer comprises an organic material; and The second upper pad is exposed.

15. The manufacturing method according to claim 10, further comprising: The dielectric structure is completely solidified.

16. A manufacturing method comprising: A first electronic device is provided, the first electronic device including a first pad, the first pad being embedded in and exposed by a first conductive structure of the first electronic device, wherein the first conductive structure comprises an inorganic material; A second dielectric layer is formed on a second electronic device, wherein the second dielectric layer exposes a second reflowable material and comprises an organic material; The first conductive structure and the second dielectric layer are joined together; as well as Join the first pad and the second resolderable material.

17. The manufacturing method according to claim 16, further comprising: The second dielectric layer is pre-cured, so that the second dielectric layer is in stage B state.

18. The manufacturing method of claim 16, wherein forming the second dielectric layer on the second electronic device comprises: The second dielectric layer is formed on the second electronic device to cover the end surface of the second resolderable material on the second electronic device; Remove a portion of the second dielectric layer and a portion of the second reflowable material, wherein the second reflowable material is recessed from the outer surface of the second dielectric layer; as well as This causes the second resolderable material to protrude from the outer surface of the second dielectric layer.

19. The manufacturing method according to claim 16, wherein the bonding of the first conductive structure and the second dielectric layer is performed in a reducing atmosphere at a temperature between 130°C and 170°C.

20. The manufacturing method according to claim 16, further comprising: The second dielectric layer is completely cured.

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