A microelectronic system and integration method

Abstract

The application discloses a kind of micro electronic systems and integrated method. Specifically related to the field of semiconductor three-dimensional integrated packaging technology, the method comprises the following steps: S1, provide a semiconductor substrate, the semiconductor substrate surface is equipped with first linear strip I / O pin solder pad array and second linear strip I / O pin solder pad array;S2, provide a memory stack core particle, the memory stack core particle surface is equipped with third linear strip I / O pin solder pad array with the first linear strip I / O pin solder pad array is oppositely arranged;S3, provide a logic processor core particle, the logic processor core particle surface is equipped with fourth linear strip I / O pin solder pad array with the second linear strip I / O pin solder pad array is oppositely arranged.The application will be mechanically fixed and electrically decoupled, with low parasitic capacitance, good heat dissipation, easy repair, small stress, simple process, compatible high bandwidth memory and graphic processor thickness gap and other advantages.

Description

Technical Field

[0001] This invention relates to the field of semiconductor three-dimensional integrated packaging technology, and in particular to a microelectronic system and integration method suitable for heterogeneous integration (such as HBM and GPU). Background Technology

[0002] With the rapid development of applications such as artificial intelligence and high-performance computing, the data bandwidth between the processor and memory has become a key bottleneck in system performance. 2.5D packaging technology (such as TSMC's CoWoS-S) horizontally integrates HBM memory and GPU processor through silicon interposers, becoming the mainstream solution.

[0003] The existing CoWoS-S solution uses thermocompression bonding (TCB) to achieve electrical interconnection through microbumps, and then uses underfill to fill the gaps under the entire chip, encapsulating each microbump. However, this solution has the following problems: 1. High parasitic capacitance: The dielectric constant (ε≈3-4) of the bottom filler increases the parasitic capacitance of the interconnect, limiting signal speed; 2. Poor heat dissipation: The bottom filler adhesive has a low thermal conductivity (0.3-0.5 W / m·K), thus becoming a thermal resistance layer; 3. Difficult to repair: Once the bottom filler has cured, the chip is almost impossible to remove without damage; 4. High thermal stress: The difference in CTE (coefficient of thermal expansion) between the bottom filler and the silicone leads to thermal cycling stress; 5. Complex process: It requires precise dispensing, capillary filling, and thermosetting, which poses a risk of voids.

[0004] In particular, in heterogeneous integration scenarios of HBM and GPU, the finished HBM stack thickness is 750-775μm (which cannot be reduced), while the GPU can be reduced to 30μm. This thickness gap makes hybrid bonding impossible to mass-produce. Although TCB can accommodate the thickness difference, the above problems still exist. Summary of the Invention

[0005] The present invention aims to provide a method and structure for integrating microelectronic systems with fixed and electrically decoupled components, thereby solving problems such as high parasitic capacitance, poor heat dissipation, difficulty in rework, high stress, and complex processes in the prior art.

[0006] To achieve the above objectives, the present invention provides the following technical solution.

[0007] An integration method for a microelectronic system includes the following steps: S1. A semiconductor substrate is provided, wherein a first linear strip-shaped I / O pin solder pad array and a second linear strip-shaped I / O pin solder pad array are provided on the surface of the semiconductor substrate; S2. A memory stack core is provided, wherein the surface of the memory stack core is provided with a third linear strip I / O pin pad array disposed opposite to the first linear strip I / O pin pad array; S3. A logic processor chip is provided, wherein the surface of the logic processor chip is provided with a fourth linear strip I / O pin pad array disposed opposite to the second linear strip I / O pin pad array; S4. A temporary adhesion layer covering the entire surface is formed on the bonding surface of the semiconductor substrate and / or the memory stack core and / or the logic processor core. S5. A protruding adhesive sheet is provided on the bonding surface of the semiconductor substrate and / or the memory stack core and / or the logic processor core; S6. Simultaneously attach the memory stack chip and the logic processor chip to the semiconductor substrate, and temporarily fix them by adhering the adhesive sheet to the temporary adhesive layer, so that the third linear strip I / O pin solder pad array is perpendicular to the first linear strip I / O pin solder pad array, and the fourth linear strip I / O pin solder pad array is opposite to the second linear strip I / O pin solder pad array. S7. Selectively remove the temporary adhesion layer from the surfaces of the first linear strip I / O pin solder pad array, the second linear strip I / O pin solder pad array, the third linear strip I / O pin solder pad array, and the fourth linear strip I / O pin solder pad array. S8. A first metal interconnect is formed between the first and third linear strip I / O pin pads and a second metal interconnect is formed between the second and fourth linear strip I / O pin pads using a selective deposition process. The first and second metal interconnects are separated from the adhesive sheet in the horizontal direction, and the metal interconnects are surrounded by an air gap.

[0008] Preferably, the material of the temporary adhesion layer is selected from a self-assembled monolayer formed by hexamethyldisilazane, trimethylsilyldiethylamine, or silane coupling agent, or from a liquid-phase spin-coating type temporary bonding adhesive, or from a vapor-deposited thin film of hydrogenated amorphous carbon; the temporary adhesion layer is a material that can be completely ashed and removed by oxygen plasma.

[0009] Preferably, the bonding sheet is a raised dielectric or metallic structure, and the material is selected from one or a combination of silicon dioxide, silicon nitride, polyimide, aluminum nitride, aluminum, cobalt, copper, nickel, and gold, with a height of 10 μm to 100 μm, used to control the spacing between the memory stack chip, the logic processor chip, and the semiconductor substrate.

[0010] Preferably, in step S7, the method for selectively removing the temporary adhesion layer includes one or a combination of laser ashing, oxygen plasma ashing, ultraviolet ozone treatment, Piranha solution wet etching, and atomic layer etching.

[0011] Preferably, in step S8, the selective deposition process includes one or a combination of electroless plating, electroplating, chemical vapor deposition, atomic layer deposition, and plasma-enhanced atomic layer deposition, and the deposited metal is selected from one or an alloy of copper, nickel, gold, aluminum, cobalt, silver, tin, and tungsten.

[0012] Preferably, the semiconductor substrate further includes a redistribution layer and / or through-silicon vias and / or deep trench capacitors. The redistribution layer is used to electrically connect the first metal interconnect to the second metal interconnect. The through-silicon vias are used to lead signals upward or downward. The deep trench capacitors are used to provide local decoupling capacitance for the memory stack chip and / or logic processor chip.

[0013] Preferably, the through-silicon vias and the deep trench capacitors are formed simultaneously in the same etching process. By adjusting the etching depth and / or etching pattern, through-silicon vias that penetrate the substrate and deep trench capacitors that do not penetrate the substrate are formed simultaneously in the same substrate.

[0014] The present invention also provides a microelectronic system, which is integrated using the above method, comprising: A semiconductor substrate having a first linear strip-shaped I / O pin pad and a second linear strip-shaped I / O pin pad on its surface; The memory stack core is fixed to the semiconductor substrate by an outwardly protruding adhesive sheet and electrically connected to the first linear I / O pin pad through a first metal interconnect. The logic processor chip is fixed to the semiconductor substrate by an outwardly protruding adhesive sheet and electrically connected to the second linear I / O pin pads by a second metal interconnect. The bonding sheet is separated from the first and second metal interconnects in the horizontal direction; the gap between the semiconductor substrate and the memory stack chip and the logic processor chip is an air gap.

[0015] Preferably, the thickness of the memory stack core is greater than the thickness of the logic processor core, and the thickness difference between the two is ≥650μm.

[0016] Preferably, the semiconductor substrate has a redistribution layer, through-silicon vias (TSVs), and deep trench capacitors. The redistribution layer electrically connects the first linear I / O pin pads to the second linear I / O pin pads, forming a data path between the memory stack chip and the logic processor chip. The TSVs are used to lead signals upwards or downwards to the system surface. The deep trench capacitors are electrically connected between the power network and ground of the semiconductor substrate, providing local decoupling capacitance for the memory stack chip and / or the logic processor chip.

[0017] The beneficial effects of the technical solution of this invention are as follows: 1. This invention spatially separates the mechanical fixing function (performed by discrete adhesive sheets) from the electrical interconnect function (performed by selectively deposited metal interconnects). Compared to the coupling design of TSMC's silicon interposer solution, which uses bottom filler to wrap bumps, this invention features an air gap around the metal interconnects, without any material covering, completely eliminating thermal stress caused by thermal expansion coefficient mismatch. This design allows 760-micron-thick high-bandwidth memory and 30-micron-thick graphics processors to be directly integrated onto the same substrate without bottom filler buffering, achieving natural compatibility with thickness differences ≥650 microns.

[0018] 2. The dielectric constant of the air gap in this invention is ε≈1, which is much lower than that of the bottom filler adhesive, ε≈3-4. The reduction in parasitic capacitance directly leads to an increase in signal transmission speed, a decrease in power consumption, and a reduction in crosstalk, providing significant performance advantages for high-speed data interfaces between high-bandwidth memory and graphics processors.

[0019] 3. The air gap of this invention has no thermal resistance and can be directly used as a flow channel for the cooling medium. Compared with the bottom filler adhesive (thermal conductivity of only 0.3-0.5 W / m·Kelvin), this invention can reduce the junction temperature by 10-20 degrees Celsius, improving system reliability and lifespan.

[0020] 4. Easy to repair: There is no underfill around the interconnect, which can be selectively removed by laser or chemical methods.

[0021] 5. The substrate integrates a redistribution layer, through-silicon vias (TSVs), and deep trench capacitors simultaneously. The redistribution layer provides inter-chip data paths, TSVs enable three-dimensional vertical routing, and deep trench capacitors provide local decoupling. TSVs and deep trench capacitors can be formed simultaneously in the same etching process, reducing the number of photolithography and etching steps. Atomic layer deposition of the seed layer ensures conformal filling of the high aspect ratio structure. Attached Figure Description

[0022] Figure 1 This is a schematic diagram of the steps of the microelectronic system integration method of the present invention.

[0023] Figure 2This is a schematic diagram of the microelectronic system of the present invention.

[0024] In the diagram: 100 - Semiconductor substrate; 101 - Through-silicon via (TSV); 102 - Rewiring layer; 110 - First linear I / O pin array; 120 - Second linear I / O pin array; 200 - Memory stack core; 210 - Third linear I / O pin array; 300 - Logic processor core; 310 - Fourth linear I / O pin array; 400 - Temporary adhesion layer; 500 - Adhesive sheet; 610 - First metal interconnect; 620 - Second metal interconnect; 900 - Deep trench capacitor. Specific Implementation

[0026] The technical solutions in the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of them. Based on the embodiments in this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application. In the absence of conflict, the following embodiments and their technical features can be combined with each other.

[0027] Example 1

[0028] like Figure 1 As shown, this embodiment provides an integration method for a microelectronic system. It includes the following steps: S1. A semiconductor substrate 100 is provided, wherein a first linear strip-shaped I / O pin solder pad array 110 and a second linear strip-shaped I / O pin solder pad array 120 are provided on the surface of the semiconductor substrate 100. S2. A memory stack core 200 is provided, wherein the surface of the memory stack core 200 is provided with a third linear strip I / O pin pad array 210 disposed opposite to the first linear strip I / O pin pad array 110. S3. A logic processor chip 300 is provided, wherein a fourth linear strip I / O pin pad array 310 is provided on the surface of the logic processor chip 300, which is disposed opposite to the second linear strip I / O pin pad array 120. S4. A temporary adhesion layer covering the entire surface is formed on the bonding surfaces of the semiconductor substrate 100 and / or the memory stack core 200 and / or the logic processor core 300. S5. On the bonding surfaces of the semiconductor substrate 100 and / or the memory stack core 200 and / or the logic processor core 300, a protruding adhesive sheet 500 is provided. S6. The memory stack chip 200 and the logic processor chip 300 are simultaneously attached to the semiconductor substrate 100. Temporary fixation is achieved by the adhesion of the adhesive sheet 500 to the temporary adhesive layer, so that the third linear strip I / O pin solder array 210 is perpendicular to the first linear strip I / O pin solder array 110 and the fourth linear strip I / O pin solder array 310 is opposite to the second linear strip I / O pin solder array 120. S7. Selectively remove the temporary adhesion layer from the surfaces of the first linear strip I / O pin solder pad array 110, the second linear strip I / O pin solder pad array 120, the third linear strip I / O pin solder pad array 210, and the fourth linear strip I / O pin solder pad array 310. S8. A first metal interconnect 610 is formed between the first and third linear strip I / O pin pads and a second metal interconnect 620 is formed between the second and fourth linear strip I / O pin pads by selective deposition process. The first metal interconnect 610 and the second metal interconnect 620 are separated from the adhesive sheet 500 in the horizontal direction, and the metal interconnects are surrounded by an air gap.

[0029] The following is combined Figure 2 The following is a detailed explanation using silicon-based processes as an example.

[0030] First, a silicon substrate 100 with a thickness of 100-150 μm is provided, containing TSV (Through Silicon Via) 101, RDL (Rewiring Layer) 102, and deep trench capacitors 900. The surface of the silicon substrate 100 has a first linear I / O pin array 110 (for connecting memory) and a second linear I / O pin array 120 (for connecting processor). The pads are made of copper, 10 μm wide, 500 μm long, and spaced 20 μm apart, arranged in a linear strip pattern. Other passive and active devices can be formed in the silicon substrate, depending on the process requirements.

[0031] Next, an HBM memory stack die 200 is provided, which is a 12-layer or 16-layer DRAM (Dynamic Random Access Memory) stack with a total thickness of 760 μm. A third linear I / O pin array 210 is provided on the lower surface of the memory, corresponding in position and matching in size to the first linear I / O pin array 110 on the substrate. The lower surface of the memory is a passivation layer, not polished by CMP (Chemical Mechanical Polishing), with a surface roughness Ra≈5-10 nm.

[0032] Next, a logic processor chip 300 (such as a GPU) is provided, with an original thickness of 780 μm, which is thinned to 30 μm through temporary bonding, thinning, and debonding processes. The lower surface of the logic processor chip 300 has a fourth linear strip-shaped I / O pin pad array 310, which corresponds in position and matches in size to the second linear strip-shaped I / O pin pad array 120 on the silicon substrate. The thinned logic processor chip 300 is flexible and can adapt to the undulations of the substrate surface.

[0033] Next, a temporary adhesion layer 400 is formed on the entire upper surface of the semiconductor substrate 100. In this embodiment, HMDS (hexamethyldisilazane) vapor phase treatment is used: the substrate is placed in a vacuum oven at 120°C for dehydration for 30 minutes, then evacuated to 0.5 Torr, and HMDS vapor is introduced for a reaction for 10 minutes, forming a monolayer self-assembled film with a thickness of approximately 1 nm on the substrate surface. After treatment, the surface water contact angle increases from <10° to >65°, exhibiting a hydrophobic state. This temporary adhesion layer is made of a material that can be completely removed by oxygen plasma ashing.

[0034] In other embodiments, the temporary adhesion layer may also employ a liquid-phase spin-coated temporary bonding adhesive (such as 3MLC3200, TOK THB, Sekisui SELFA, Dow silicone, Henkel Ablestik, Shanghai Xinyang, Huahai Chengke, etc.), with a thickness of 5-20 μm; or a vapor-deposited hydrogenated amorphous carbon film (AMAT APF), with a thickness of 50-200 nm. These materials are all oxygen plasma-electrodegradable systems, free of metals and flame-retardant inorganic fillers, and are completely oxidized to CO2 (carbon dioxide), H2O (water), and a small amount of SiO2 (silicon dioxide) under high-temperature O2 (oxygen) conditions.

[0035] Next, multiple protruding bonding pads 500 are fabricated on the surfaces of the HBM memory stack die 200 and the logic processor die 300, respectively. The bonding pads are silicon dioxide dielectric pillars, formed by depositing a 5μm silicon dioxide layer via PECVD (plasma-enhanced chemical vapor deposition), followed by photolithography and RIE etching. They are 30μm high, 50μm in diameter, and discretely distributed. The height of the bonding pads is precisely controlled to maintain a 30μm gap between subsequent solder pads.

[0036] In other embodiments, the adhesive sheet may also be disposed on the core surface (instead of the substrate surface), and the material may be silicon dinitride, silicon oxide, polyimide, copper, nickel, gold, cobalt, aluminum, aluminum nitride, etc., with a height range of 10-100 μm.

[0037] The adhesive sheet, as an independent mechanical fixing structure, is spatially separated from the subsequently formed metal interconnect, thus decoupling the fixing function from the electrical function.

[0038] Next, the memory stack chip 200 and the logic processor chip 300 are simultaneously picked up, flipped, and aligned with the semiconductor substrate 100. A multi-pickup high-precision bonding machine is used to align the third linear I / O pin pad 210 with the first linear I / O pin pad 110, and the fourth linear I / O pin pad 310 with the second linear I / O pin pad 120. A pressure of 0.2N is applied to bring the lower surface of the chip into contact with the bonding sheet 500 on the substrate. Since the lower surface of the chip is not coated with an adhesive layer (in this embodiment, the adhesive layer is on the substrate), and the bonding sheet contacts the HMDS adhesive layer on the substrate surface, temporary fixation is achieved through van der Waals forces on the hydrophobic surface. The bonding sheet height is 30μm to precisely control the gap between the bonding sheets.

[0039] At this point, the HBM memory is 760 μm thick, and the GPU is 30 μm thick, with a thickness difference of 730 μm. Because the bonded sheets are discretely distributed with air gaps and no underfill, this thickness difference does not generate additional thermal stress.

[0040] Through the above steps, multiple cores can be mounted simultaneously, reducing the number of bonding operations; the air gap is naturally compatible with large thickness differences, eliminating the need for underfill buffering.

[0041] Next, a laser ashing process was used to selectively remove the HMDS adhesion layer from the surfaces of the first linear I / O pin solder pad 110 and the second linear I / O pin solder pad 120. An excimer laser with a wavelength of 248 nm was used, incident obliquely from the edge of the core (incident angle 30°), allowing laser energy to enter the 30 μm gap between the core and the substrate, irradiating the solder pad area. The energy density was 150 mJ / cm², and the irradiation time was 2 seconds. The HMDS on the solder pad surface was removed by photothermal ashing, and the solder pad returned to its hydrophilic state (contact angle <10°). HMDS in other areas below the bonded sheet and below the core was retained.

[0042] In other embodiments, the selective removal method may also employ one or a combination of oxygen plasma ashing (using a core particle as a mask), ultraviolet ozone treatment, Piranha solution (a mixture of H2SO4 + H2O2 sulfuric acid and hydrogen peroxide) wet etching, and atomic layer etching (ALE).

[0043] After selective removal, the solder pad surface is clean and free of residue, providing a good growth interface for subsequent metal deposition; no additional cleaning steps are required.

[0044] Next, the stacked structure is immersed in a chemical copper plating solution, and copper is selectively deposited on the exposed solder pad surfaces. After 30 minutes of deposition, the 30μm gap between the solder pads is completely filled with copper, forming a first metal interconnect 610 (connecting the memory to the substrate) and a second metal interconnect 620 (connecting the processor to the substrate). The interconnects are linear strips, 10μm wide, 500μm long, and 30μm high. The first metal interconnect 610 and the second metal interconnect 620 are electrically connected through a redistribution layer, thereby directly forming a data path between the memory stack chip and the logic processor chip inside the substrate. Compared to conventional interconnection methods that use external circuit boards or long-distance traces, the redistribution layer of this invention significantly shortens the signal transmission path, reduces interconnect resistance and parasitic inductance, significantly improves signal integrity and data transmission bandwidth, and reduces system power consumption.

[0045] In other embodiments, the selective deposition process may also employ electroplating, chemical vapor deposition (CVD), atomic layer deposition (ALD), plasma-enhanced atomic layer deposition (PEALD), etc. The deposited metal may be selected from one or an alloy of copper, nickel, gold, silver, tin, tungsten, aluminum, and cobalt.

[0046] Deep trench capacitors, with a depth of 50-80μm, are placed inside a semiconductor substrate. They do not penetrate the substrate but are electrically connected between the power network and ground of the substrate. They provide local decoupling capacitance for memory stack chips and / or logic processor chips. Deep trench capacitors utilize the vertical depth of the substrate to form high-density capacitors without occupying additional surface area. Multiple discrete decoupling capacitors can be integrated into the substrate, thereby reducing the number of external components, simplifying the packaging process, and reducing system costs.

[0047] Through-silicon vias (TSVs) are formed inside the semiconductor substrate to guide signals upwards or downwards to the system surface. TSVs provide the shortest vertical interconnect paths, breaking the planar limitations of traditional two-dimensional packaging and enabling true three-dimensional integration. Through TSVs, the microelectronic system of this invention can be easily stacked and connected vertically with other chips, substrates, or heat sinks, significantly improving I / O density and system integration, and providing a scalable architectural foundation for future heterogeneous integration with higher bandwidth and density.

[0048] Through-silicon vias (TSVs) and deep trench capacitors are formed simultaneously in the same etching process. By performing one photolithography and one deep reactive ion etching process, through-silicon vias that penetrate the substrate and deep trench capacitors that do not penetrate the substrate can be formed simultaneously within the same substrate. This eliminates the need for two separate photolithography and etching processes, significantly reducing process steps, manufacturing costs, and the number of photomasks required. It also reduces the risk of defects introduced by multiple processes, which is beneficial for improving mass production yield and production efficiency.

[0049] Since interconnects are formed by deposition without relying on mechanical contact, there are no special requirements for the surface flatness of the core particles (compatible with HBM surfaces with Ra≈5-10nm); linear strip interconnects have lower resistance and better signal integrity compared to dot bumps.

[0050] The resulting microelectronic system includes: A semiconductor substrate having a first linear strip-shaped I / O pin pad and a second linear strip-shaped I / O pin pad on its surface; The memory stack core is fixed to the semiconductor substrate by an outwardly protruding adhesive sheet and electrically connected to the first linear I / O pin pad through a first metal interconnect. The logic processor chip is fixed to the semiconductor substrate by an outwardly protruding adhesive sheet and electrically connected to the second linear I / O pin pads by a second metal interconnect. Wherein, the bonding sheet is separated from the first and second metal interconnects in the horizontal direction; the gap between the semiconductor substrate and the memory stack chip and the logic processor chip is an air gap; the preparation of the first and second metal interconnects includes an atomic layer deposition process step.

[0051] In this embodiment, the first metal interconnect 610 and the second metal interconnect 620 are separated from the bonding sheet 500 in the horizontal direction. The metal interconnects are surrounded by air gaps and are not encased in any material. The gaps between the semiconductor substrate 100 and the memory stack chip 200 and logic processor chip 300 are primarily air gaps. The advantages of this structure are: fixed and mutually decoupled, low parasitic capacitance (air ε≈1 vs underfill ε≈3-4), good heat dissipation, easy repair, and low stress.

[0052] Preferably, in this embodiment, the semiconductor substrate 100 further includes: Redistribution layer (RDL) 102: Located below the upper surface of the substrate, the first linear strip I / O pin pad array 110 and the second linear strip I / O pin pad array 120 are electrically connected to form a data path between the memory and the processor. The RDL is a multilayer copper wiring with a line width / spacing of 2μm / 2μm.

[0053] Through-Silicon Via (TSV) 101: Penetrates the substrate 100, with a depth of 100-150 μm and a diameter of 5 μm. Used to bring signals up or down to the system surface. The TSV is filled with copper and has an insulating layer and a barrier layer on the outside.

[0054] Deep trench capacitor 900: Formed inside the substrate, with a depth of 50-80μm, and does not penetrate the substrate. The deep trench capacitor is electrically connected between the power network and ground of the substrate, providing local decoupling capacitance for the memory and processor, and suppressing power supply noise.

[0055] In one embodiment, the TSV and deep trench capacitor are formed simultaneously: the through-silicon via 101 and the deep trench capacitor 102 are formed simultaneously in the same etching process. Specifically, the TSV region and the deep trench capacitor region are defined by a single photolithography step, and a Bosch deep reactive ion etching (DRIE) process is used, with SF6 / C4F8 (a mixture of sulfur hexafluoride and octafluorocyclobutane) as the etching gas. Because the TSV region has a larger opening (5 μm in diameter) and the deep trench capacitor region has a smaller opening (1-2 μm in diameter), under the same etching conditions, the etching rate of the smaller opening is slower. Therefore, a TSV penetrating the substrate (100-150 μm depth) and a non-penetrating deep trench capacitor (50-80 μm depth) are formed simultaneously. After etching, the metal filling of the TSV and deep trench capacitor is prepared using atomic layer deposition (ALD) to create a seed layer (depositing a 5 nm copper seed), followed by electroplating or electroless plating to complete the overall copper filling.

[0056] TSV and deep trench capacitors are formed in the same etching process, reducing process steps and manufacturing costs; the deep trench capacitors are close to the TSV, providing local decoupling for the signals transmitted by the TSV; the ALD (atomic layer deposition) seed layer has good shape preservation, ensuring the complete filling of the high aspect ratio structure.

[0057] Example 2

[0058] This embodiment is essentially the same as Embodiment 1, except that: a temporary adhesion layer is formed on the lower surface of the memory stack chip and the logic processor chip (rather than the substrate surface), and the adhesive sheet is disposed on the substrate surface. The entire lower surface of the chip is coated with HMDS, and a silicon dioxide adhesive sheet is pre-formed on the substrate surface. During bonding, the HMDS on the lower surface of the chip contacts and is fixed to the adhesive sheet on the substrate. For selective removal, a laser is incident from the substrate side or obliquely incident from the edge of the chip to remove the HMDS on the surface of the chip solder pad.

[0059] This embodiment places a temporary adhesion layer on the lower surface of the core and an adhesive sheet on the substrate surface, which has the following advantages: the temporary adhesion layer on the core surface can be pre-coated at the wafer level, simplifying the substrate pretreatment process; the adhesive sheet is precisely prefabricated on the substrate surface, ensuring alignment accuracy; reliable temporary fixation is achieved by relying on the van der Waals forces of HMDS during bonding; during selective removal, the laser can be incident from the substrate side or the edge of the core, allowing for flexible optical path selection; this arrangement provides optional process solutions for different production line conditions, enhancing industrial applicability.

[0060] Example 3

[0061] This embodiment is essentially the same as Embodiment 1, except that: no protruding adhesive sheet is used, and the gap between the core and the substrate is naturally formed by the surface micro-roughness (0.5-2 μm). The temporary adhesion layer is an AMAT APF (Advanced Patterning Film) film (100 nm thick), deposited by PECVD (Plasma Enhanced Chemical Vapor Deposition). Selective removal is performed using an ultrashort pulse laser (355 nm, 10 ps), which enters the ultrathin gap through edge diffraction. After interconnection, all APF is removed by overall ashing with oxygen plasma, forming a pure air gap structure.

[0062] This embodiment eliminates the fabrication step of the protruding bonding sheet. The gap between the core and the substrate is naturally formed by the surface micro-roughness (0.5-2 μm), simplifying the process and reducing costs. The temporary adhesion layer uses an advanced amorphous carbon thin film (100 nm thick) formed by plasma-enhanced chemical vapor deposition. For selective removal, an ultrashort pulse laser (355 nm wavelength, 10 picosecond pulse width) is used. The edge diffraction effect allows the laser to enter the ultrathin gap, precisely removing the adhesion layer on the solder pad surface. After interconnection, all residual film is removed by overall ashing with oxygen plasma, forming a pure air gap structure. The advantages of this embodiment are: eliminating the bonding sheet fabrication step, reducing mask costs; minimal thermal impact of the ultrashort pulse laser, without damaging the solder pad; and final overall ashing ensures no solid residue in the gap, minimizing parasitic capacitance.

[0063] Example 4

[0064] This embodiment is basically the same as Embodiment 1, except that: the temporary adhesion layer uses TOK THB-1000 liquid-phase spin-coating adhesive with a thickness of 10μm. After spin-coating, it undergoes three stages of baking: 100℃ / 2min soft baking → 150℃ / 10min medium baking → cooling to room temperature to reach B-stage (semi-cured state). The Q-time (process waiting time) is controlled to complete bonding within 45 minutes. Selective removal is performed using oxygen plasma ashing (500W, 1μm / min), using the core particle as a mask to remove the TOK adhesive from the exposed areas.

[0065] This embodiment uses a liquid-phase spin-coating temporary bonding adhesive (THB-1000 series from Tokyo Ohka Kogyo Co., Ltd.). A three-stage baking process (100°C soft baking, 150°C medium baking, and cooling to room temperature) is employed to achieve a semi-cured state, with the process waiting time controlled within 45 minutes. Selective removal utilizes oxygen plasma ashing (500W power, removal rate approximately 1 micrometer / minute), using the core particle itself as a mask to remove the adhesive from exposed areas. The advantages of this embodiment are: the use of a mature commercial temporary bonding material, a wide process window, and ease of integration into production lines; the three-stage baking and semi-cured state control ensure moderate adhesion strength, meeting both fixation requirements and preventing permanent bonding; the clearly defined process waiting time provides quantifiable parameters for mass production; oxygen plasma ashing uses the core particle as a mask, eliminating the need for additional photolithography alignment steps; and the removal rate of approximately 1 micrometer / minute allows for completion of a 10-micrometer thick adhesive layer within 10-15 minutes, demonstrating good mass production efficiency.

[0066] Benefiting from the teachings presented in the foregoing description and the accompanying drawings, those skilled in the art will conceive of many modifications and other embodiments of the invention set forth herein. Therefore, it should be understood that the invention is not limited to the specific embodiments disclosed, and that modifications and other embodiments are intended to be included within the scope of the appended claims. Although specific terminology is used herein, it is used only in a general and descriptive sense and is not intended to be limiting.

Claims

1. A method for integrating a microelectronic system, characterized in that, Includes the following steps: S1. A semiconductor substrate is provided, wherein a first linear strip-shaped I / O pin solder pad array and a second linear strip-shaped I / O pin solder pad array are provided on the surface of the semiconductor substrate; S2. A memory stack core is provided, wherein the surface of the memory stack core is provided with a third linear strip I / O pin pad array disposed opposite to the first linear strip I / O pin pad array; S3. A logic processor chip is provided, wherein the surface of the logic processor chip is provided with a fourth linear strip I / O pin pad array disposed opposite to the second linear strip I / O pin pad array; S4. A temporary adhesion layer covering the entire surface is formed on the bonding surface of the semiconductor substrate and / or the memory stack core and / or the logic processor core. S5. A protruding adhesive sheet is provided on the bonding surface of the semiconductor substrate and / or the memory stack core and / or the logic processor core; S6. Simultaneously attach the memory stack chip and the logic processor chip to the semiconductor substrate, and temporarily fix them by adhering the adhesive sheet to the temporary adhesive layer, so that the third linear strip I / O pin solder pad array is perpendicular to the first linear strip I / O pin solder pad array, and the fourth linear strip I / O pin solder pad array is opposite to the second linear strip I / O pin solder pad array. S7. Selectively remove the temporary adhesion layer from the surfaces of the first linear strip I / O pin solder pad array, the second linear strip I / O pin solder pad array, the third linear strip I / O pin solder pad array, and the fourth linear strip I / O pin solder pad array. S8. A first metal interconnect is formed between the first and third linear strip I / O pin pads and a second metal interconnect is formed between the second and fourth linear strip I / O pin pads using a selective deposition process. The first and second metal interconnects are separated from the adhesive sheet in the horizontal direction, and the metal interconnects are surrounded by an air gap.

2. The integration method according to claim 1, characterized in that, The material of the temporary adhesion layer is selected from self-assembled monolayers formed by hexamethyldisilazane, trimethylsilyldiethylamine, and silane coupling agents, or from liquid-phase spin-coating temporary bonding adhesives, or from vapor-deposited thin films of hydrogenated amorphous carbon; the temporary adhesion layer is a material that can be completely ashed and removed by oxygen plasma.

3. The integration method according to claim 1, characterized in that, The bonding sheet is a raised dielectric or metallic structure, and the material is selected from one or a combination of silicon dioxide, silicon nitride, polyimide, aluminum nitride, aluminum, cobalt, copper, nickel, and gold. The height is 10μm to 100μm, and it is used to control the spacing between the memory stack chip, the logic processor chip and the semiconductor substrate.

4. The integration method according to claim 1, characterized in that, In step S7, the method for selectively removing the temporary adhesion layer includes one or a combination of laser ashing, oxygen plasma ashing, ultraviolet ozone treatment, Piranha solution wet etching, and atomic layer etching.

5. The integration method according to claim 1, characterized in that, In step S8, the selective deposition process includes one or a combination of electroless plating, electroplating, chemical vapor deposition, atomic layer deposition, and plasma-enhanced atomic layer deposition, and the deposited metal is selected from one or an alloy of copper, nickel, gold, aluminum, cobalt, silver, tin, and tungsten.

6. The integration method according to claim 1, characterized in that, The semiconductor substrate is further provided with a redistribution layer and / or through-silicon vias and / or deep trench capacitors. The redistribution layer is used to electrically connect the first metal interconnect to the second metal interconnect. The through-silicon vias are used to lead signals up or down. The deep trench capacitors are used to provide local decoupling capacitance for the memory stack chip and / or logic processor chip.

7. The integration method according to claim 6, characterized in that, The through-silicon vias and the deep trench capacitors are formed simultaneously in the same etching process. By adjusting the etching depth and / or etching pattern, through-silicon vias that penetrate the substrate and deep trench capacitors that do not penetrate the substrate are formed simultaneously in the same substrate.

8. A microelectronic system, characterized in that, include: A semiconductor substrate having a first linear strip-shaped I / O pin pad and a second linear strip-shaped I / O pin pad on its surface; The memory stack core is fixed to the semiconductor substrate by an outwardly protruding adhesive sheet and electrically connected to the first linear I / O pin pad through a first metal interconnect. The logic processor chip is fixed to the semiconductor substrate by an outwardly protruding adhesive sheet and electrically connected to the second linear I / O pin pads by a second metal interconnect. The bonding sheet is separated from the first metal interconnect and the second metal interconnect in the horizontal direction; the gap between the semiconductor substrate and the memory stack chip and the logic processor chip is an air gap.

9. The microelectronic system according to claim 8, characterized in that, The thickness of the memory stack core is greater than the thickness of the logic processor core, and the thickness difference between the two is ≥650μm.

10. The microelectronic system according to claim 8, characterized in that, The semiconductor substrate has a redistribution layer, through-silicon vias (TSVs), and deep trench capacitors. The redistribution layer electrically connects the first linear I / O pin pads to the second linear I / O pin pads, forming a data path between the memory stack chip and the logic processor chip. The TSVs are used to lead signals upwards or downwards to the system surface. The deep trench capacitors are electrically connected between the power network and ground of the semiconductor substrate, providing local decoupling capacitance for the memory stack chip and / or the logic processor chip.

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