A parasitic capacitance-aware standard cell interconnect method
Patent Information
- Application Number
- CN202610917390.1
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2026-06-24
- Publication Date
- 2026-09-25
AI Technical Summary
[0006]本发明的目的是提供一种寄生电容感知的标准单元内布线方法，以克服现有标准单元版图综合技术过度依赖几何代理指标、难以直接优化电学性能的问题
[0026]本发明提供一种寄生电容感知的标准单元内布线方法，通过策略模型生成软提示并行引导求解器、求解器冲突修复得到合法布线解；再将合法布线解编码为二维多通道密度图并进行寄生电容代理评估，得到归一化电容代价；以合法布线解作为伪标签，并根据归一化电容代价进行代价加权策略更新；并进行最终候选筛选和验证。本发明不再将总线长等几何指标作为唯一优化目标，而是直接将关键线网的寄生电容作为布线优化依据，能够更准确地反映先进工艺节点下标准单元版图的真实电学性能趋势。本发明保留了约束求解器在满足设计规则方面的严格性，并通过软提示注入和冲突修复机制保证所有采样结果均为合法版图，因此兼顾了优化质量与制造可行性。同时，本发明通过并行求解和代理模型评估实现大规模候选拓扑的快速搜索，避免在每一次搜索迭代中调用高成本寄生提取与电路仿真，克服现有标准单元版图综合技术过度依赖几何代理指标、难以直接优化电学性能的缺陷，从而显著提升了标准单元版图综合效率。
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Abstract
Description
Technical Field
[0001] This invention belongs to the field of integrated circuit design automation technology, and relates to standard cell routing technology for generating standard cell layouts of digital integrated circuits. Specifically, it relates to a parasitic capacitance sensing standard cell routing method to improve the performance of layout synthesis results. Background Technology
[0002] Standard cells are the fundamental building blocks of digital integrated circuit design, and their layout quality directly affects the chip's power consumption, performance, and area. As process nodes advance to more advanced stages, the rules for standard cell layout design become increasingly complex. Manual layout design is costly and time-consuming, making automated synthesis technology for standard cells an important means of improving the efficiency of standard cell development.
[0003] Existing automatic synthesis methods for standard cell layouts typically employ Satisfiability Modulo Theories (SMT) for modeling to complete transistor placement and routing within standard cells while satisfying complex design rules. To facilitate searching, these methods generally use geometric parameters such as area and half-perimeter wire length (HPWL) estimated bus length as optimization targets or surrogate targets. However, at advanced process nodes, the actual electrical performance of standard cells is increasingly affected by parasitic effects, especially parasitic capacitance and coupling capacitance. Relying solely on geometric parameters is no longer sufficient to accurately reflect true timing and power consumption performance.
[0004] For different layout designs using the same standard cell, there may be cases where the bus length is the same or similar, but the parasitic capacitance and timing performance differ significantly. If the routing search is still guided by geometric surrogate indices, the solver will struggle to find solutions with better electrical performance. On the other hand, if parasitic parameter extraction and circuit simulation are directly invoked during the search process, the computational cost is too high, making it difficult to iterate across a large number of candidate layouts and failing to meet the efficiency requirements of automatic synthesis of standard cell layouts.
[0005] Therefore, there is an urgent need for a technical solution that can introduce parasitic capacitance, an electrical parameter, into the standard cell layout synthesis process while strictly meeting design rules, so as to improve the performance of the layout synthesis results without increasing unacceptable computational costs. Summary of the Invention
[0006] The purpose of this invention is to provide a standard cell routing method with parasitic capacitance sensing, so as to overcome the problem that existing standard cell layout synthesis technology relies too much on geometric proxy indicators and is difficult to directly optimize electrical performance.
[0007] This invention combines the solver's constraint satisfaction capability, parallel sampling capability, and parasitic capacitance proxy evaluation capability to ensure that the layout meets design rules while guiding the routing topology to search for low parasitic capacitance, thereby obtaining a standard cell layout with better performance.
[0008] The core of this invention lies in constructing the standard cell routing problem under a given transistor layout as a multi-commodity flow constraint satisfaction problem based on a mesh graph. A strategy model is used to generate candidate usage probabilities for each routing edge, and sampling hints are injected into multiple solver threads in parallel to guide the solver in generating multiple combination routing solutions while satisfying design rules. A multi-channel geometric representation, i.e., a two-dimensional multi-channel density map, representing the distribution of metal layers and via layers is extracted from each valid routing solution and input into a convolutional neural network surrogate model to obtain the parasitic capacitance prediction value of the critical wire mesh of the transistor routing. The normalized capacitance cost of each candidate routing solution is calculated based on the parasitic capacitance prediction value. After each round of parallel routing, the valid routing solution repaired by the solver is used as a pseudo-label, and the strategy model is iteratively updated based on its normalized capacitance cost. In the initial stage of iteration, a cost-weighted imitation update prioritizing low-capacitance candidates is used, and in subsequent stages, a reinforcement update based on the advantage value is used to simultaneously improve search stability and optimization capability. During the iterative parallel routing and optimization process, the layout with parasitic capacitance prediction values is recorded, and parasitic parameters are extracted and the circuit is simulated on the candidate layouts to obtain the final standard cell layout with optimal performance.
[0009] The technical solution of this invention is:
[0010] A standard cell routing method for parasitic capacitance sensing integrates policy model soft hints, parasitic capacitance proxy evaluation, and cost-weighted policy updates into a closed-loop routing optimization process; specifically, it includes the following steps:
[0011] A. Parallel routing sampling: Based on the strategy model, a parallel guide solver is generated with hints, and the solver conflicts are resolved to obtain a valid routing solution;
[0012] The wiring region within a standard cell under a fixed transistor layout is discretized into a three-dimensional mesh, and a multi-commodity flow constraint model is established. A probability distribution of candidate occupancy states is generated for each edge in the three-dimensional mesh using a strategy model. Multiple sets of sampling prompts are obtained through parallel sampling based on the probability distribution, and each set is injected into multiple solver threads as soft decision directions. Under the premise of satisfying connectivity, mutual exclusion occupancy, and design rule constraints, each solver thread covers or repairs the conflict prompts and outputs multiple combination method wiring solutions.
[0013] Given a transistor layout, the routing region within a standard cell is discretized into a 3D mesh, where vertices represent available routing locations and edges represent adjacent available routing resources. For each edge, a candidate state is defined, indicating whether it can be occupied by a net or remain unoccupied. A policy model is used to output the probability distribution of candidate states for each edge, and a roulette wheel sampling method is employed to select a candidate state for each edge based on the probability distribution, thus forming a set of sampling hints. Multiple sets of sampling hints are generated in parallel and assigned to multiple solver threads. A decision callback mechanism is registered in each solver thread. When the solver needs to make a branch decision for a Boolean variable, it prioritizes the edge occupancy state corresponding to the sampling hint as the decision direction, thereby guiding the solver search to the vicinity of the routing topology preferred by the policy model. The sampling hints are soft hints rather than hard constraints. When the edge occupancy state corresponding to the sampling hint causes short circuits, spacing conflicts, connectivity disruptions, or other design rule conflicts, the solver uses conflict analysis, backtracking, and clause learning mechanisms to cover and repair the hint, ultimately outputting a valid routing solution that satisfies all design rules.
[0014] B. Decode the legal wiring into a two-dimensional multi-channel density map and perform parasitic capacitance proxy evaluation to obtain the normalized capacitance cost;
[0015] The parasitic capacitance of critical nets in transistor wiring is predicted by proxy, and the total parasitic capacitance of each critical net is predicted, and the normalized capacitance cost is obtained; including:
[0016] B1) For each valid routing solution, extract the geometric distribution information of the key transistor nets on each metal layer and via layer, and construct a two-dimensional multi-channel density map representation. The two-dimensional multi-channel density map representation is composed of the geometric distribution of metal layers and via layers in the valid routing solution, with different metal layers and different via layers corresponding to different channels. Different metal layers and different via layers occupy different channels to characterize in-layer coupling and cross-layer coupling features. Key nets include nets corresponding to input / output pins, internal cascaded nets, or a set of nets to be optimized specified by the user.
[0017] B2) Input the two-dimensional multi-channel density map into the pre-trained convolutional neural network surrogate model to predict the total parasitic capacitance of each key network.
[0018] Parasitic capacitance surrogate models can employ convolutional neural networks or residual convolutional networks.
[0019] (B3) To avoid the imbalance caused by differences in net length and capacitance levels in the optimization process, the predicted capacitance of each candidate wiring solution is normalized based on the parasitic capacitance of the critical net corresponding to the initial layout, thus obtaining the normalized capacitance cost. The smaller the normalized capacitance cost, the better the parasitic capacitance performance of the candidate wiring solution.
[0020] C. Normalized capacitance cost weighting strategy update: The valid wiring solution after solver repair is used as a pseudo-label, and a two-stage cost weighting strategy update is performed based on the normalized capacitance cost;
[0021] The valid wiring solutions obtained through parallel wiring sampling (with conflict resolution performed on each parallel solver thread in step A) are used as the supervision targets of the policy model. The occupancy state of each edge in a valid wiring solution is used as a pseudo-label to construct the loss function of the policy model, and an entropy regularization term is added to maintain search diversity. In the warm-up phase, several candidate wiring solutions with the lowest normalized capacitance cost are selected from a batch of valid wiring solutions as elite samples. Weights are assigned based on the difference between their costs and the global optimum, allowing low-capacity candidates to contribute more to policy updates, thus quickly establishing an initial search distribution biased towards superior topologies. In the stable optimization phase, the advantage value of each candidate wiring solution is calculated based on the average capacitance cost and standard deviation of a batch of valid wiring solutions. Positive weights are assigned to candidate wiring solutions that are better than the batch mean, and positive weights are also assigned to candidate wiring solutions with normalized capacitance costs lower than the current batch's average normalized capacitance cost, to increase their generation probability. Negative weights are assigned to candidate wiring solutions that are worse than the batch mean to suppress their generation probability, thereby further driving the search process out of local optima and continuously converging towards lower parasitic capacitance.
[0022] Repeat steps A to C until the set number of iterations is reached, no better candidate is generated for several consecutive rounds, or other termination conditions are met, and the candidate wiring solution is obtained through iteration.
[0023] D. Candidate map output and precise filtering
[0024] From the final iteration process, several candidate layouts (candidate routing solutions) with the lowest normalized capacitance cost are selected to form a candidate layout library. Accurate parasitic parameter extraction and circuit simulation are performed on the candidate layouts, and the final layout is selected based on delay, power consumption, switching time, or a weighted combination thereof. The final layout, while maintaining the same placement area and satisfying design rules, exhibits superior electrical performance compared to routing schemes solely guided by line length.
[0025] Compared with the prior art, the beneficial effects of the present invention are as follows:
[0026] This invention provides a standard cell routing method with parasitic capacitance awareness. It generates soft hints through a strategy model to guide the solver in parallel, and resolves solver conflicts to obtain valid routing solutions. These valid solutions are then encoded into a two-dimensional multi-channel density map and subjected to parasitic capacitance proxy evaluation to obtain a normalized capacitance cost. Valid routing solutions are used as pseudo-labels, and a cost-weighted strategy is updated based on the normalized capacitance cost. Finally, candidate selection and verification are performed. This invention no longer uses geometric parameters such as bus length as the sole optimization objective, but directly uses the parasitic capacitance of critical nets as the basis for routing optimization, which can more accurately reflect the true electrical performance trend of standard cell layouts under advanced process nodes. This invention retains the strictness of the constraint solver in satisfying design rules and ensures that all sampling results are valid layouts through soft hint injection and conflict resolution mechanisms, thus balancing optimization quality and manufacturing feasibility. Meanwhile, this invention achieves rapid search for large-scale candidate topologies through parallel solving and surrogate model evaluation, avoiding the need to call high-cost parasitic extraction and circuit simulation in each search iteration. It overcomes the shortcomings of existing standard cell layout synthesis technology, which relies too much on geometric surrogate indicators and is difficult to directly optimize electrical performance, thereby significantly improving the efficiency of standard cell layout synthesis. Attached Figure Description
[0027] Figure 1 This is a flowchart of the method of the present invention.
[0028] Figure 2 A schematic diagram of the parallel routing sampling and cost-weighted strategy update process. Detailed Implementation
[0029] The present invention will be further illustrated below with reference to the accompanying drawings and embodiments.
[0030] This invention provides a standard cell routing method for parasitic capacitance sensing. This method addresses the problem in automated synthesis of standard cell layouts using advanced processes where "geometric parameters fail to reflect true electrical performance." While ensuring design rules are met, it incorporates the parasitic capacitance of critical nets into the routing search closed loop. The method includes the following steps: parallel routing sampling, parasitic capacitance proxy evaluation, cost-weighted strategy updating, and candidate layout output and precise screening, such as... Figure 1 As shown. The parallel routing sampling and cost-weighted strategy update process is as follows. Figure 2 As shown. The specific steps are as follows:
[0031] A. Parallel routing sampling
[0032] Under fixed placement, the wiring-accessible area within a standard cell is discretized into a three-dimensional mesh, denoted as . ,in For the set of vertices that can be wired, For a set of wireable edges, For the set of nets to be wired, For each edge, there is a set of candidate occupancy states. This indicates that the edge is not occupied by any network.
[0033] Online On the side The commodity flow variable on the above is denoted as , online Does it occupy an edge? The binary variable is denoted as opposite side The variable indicating whether a metal exists is denoted as Except for the source and sink, for any intermediate vertex Satisfying the commodity flow conservation constraint:
[0034]
[0035] in Represents the vertex The set of adjacent vertices.
[0036] For any edge Satisfying the exclusive constraint:
[0037]
[0038] And satisfy the metal presence relation:
[0039]
[0040] Design rules and constraints are directly applied to metallic variables. The above is used to characterize short circuits, spacing, through-hole connections, and other manufacturing constraints.
[0041] Building a strategy model For each edge Output candidate set probability distribution on ,satisfy Subsequently, roulette wheel sampling is performed independently on each edge to obtain parallel solver threads. On the side Candidate states on:
[0042]
[0043] in, This represents the candidate occupancy state of edge e in the k-th sampling prompt, and its value belongs to the set of candidate occupancy states. ;when When, it indicates that the sampling hints of the k-th solver thread tend to cause the net n to occupy edge e; when When, it indicates that the sampling hints tend to prevent edge e from being occupied by any net; k is the number of the sampling hint or parallel solver thread (sampling hints and threads correspond one-to-one); This indicates that the candidate occupancy state probability distribution output by edge e is classified and sampled according to the policy model; the sampling results of all edges are combined into a set of sampling hints. To improve search throughput, generate one at a time. Group sampling prompts were sent separately. One parallel solver thread.
[0044] On the solver side, sampling hints are embedded as preferred branch directions into the solution process via a user propagator or decision callback mechanism. (If Boolean variables...) Indicates "network" Does it occupy an edge? Then the optimal decision function can be written as:
[0045]
[0046]
[0047] If the suggested assignment does not conflict with existing constraints, the solver continues searching in that direction. If the suggested assignment induces a conflict, the solver automatically covers the error message through conflict analysis, backtracking, and clause learning, and searches for new feasible assignments. Therefore, the sampling hints only serve a guiding role and do not compromise the solver's ability to strictly satisfy design rules. Ultimately, each thread outputs a valid wiring solution that satisfies connectivity constraints, mutual exclusion constraints, and all design rule constraints. .
[0048] B. Parasitic Capacitance Substitute Evaluation
[0049] For each valid routing solution obtained in step A, the metal geometry and via geometry related to the critical mesh are extracted. Considering the compact internal space and significant cross-layer coupling of the standard cell, this embodiment encodes different metal layers and different via layers into different channels, forming a two-dimensional multi-channel density map. The pixel value in each channel is used to characterize the occupancy intensity, length density, or geometric coverage relationship of the metal or via at the corresponding location.
[0050] A two-dimensional multi-channel density map is input into a pre-trained convolutional neural network surrogate model. The surrogate model can employ a residual convolutional network structure to learn the nonlinear mapping relationship between complex wiring topologies and parasitic capacitances. The model output is the predicted total parasitic capacitance for each critical wire network.
[0051] To establish a comparable and unified optimization objective across multiple key network lines, starting with the initial layout... Using the parasitic capacitance of the corresponding critical net as a benchmark, candidate layouts are analyzed. The predicted capacitance is normalized. Let the critical line network set be denoted as . Proxy model for online networks The predicted total parasitic capacitance is denoted as Initial map with wire mesh The reference capacitor is denoted as The normalized capacitance cost of the candidate layout is then defined as:
[0052]
[0053] in, Candidate map Normalized capacitance cost;
[0054] The lower the normalized capacitance cost, the more significant the improvement in critical net parasitic capacitance of the candidate layout compared to the initial layout. Preferably, input / output pin nets and internal cascade nets in multi-level logic can be included together. .
[0055] C. Cost-weighted strategy update
[0056] In this embodiment, the valid routing solution obtained after repair by the solver in step A is regarded as the target topology that the current policy model should learn. Let the set of valid routing solutions collected in the current batch be... Map Sample On the side The final candidate state is denoted as Then the loss function of the policy model (log-likelihood loss) The preferred definition is:
[0057]
[0058] in, for The weight, For entropy regularization, The regularization coefficient is used. This is the k-th valid wiring solution in the current batch B after solver conflict repair.
[0059] In the initial iterations, the policy model is unstable and prone to generating hints that are detrimental to low capacitance optimization. Therefore, during the warm-up phase, elite samples with the lowest cost are selected from all legitimate candidates, and their cost is compared to the globally optimal cost. The differences between the topologies are assigned exponential weights, allowing the better topology to contribute more to policy updates. The optimal weights for the warm-up phase are defined as follows:
[0060]
[0061] in, This refers to the temperature parameter; I represents the first stage, i.e., the preheating stage. for The normalized capacitance cost. This stage is essentially a cost-weighted imitation learning stage, which helps to quickly establish a prior distribution biased towards high-quality solutions.
[0062] In this invention, advantage weights are defined based on the mean and standard deviation of the normalized capacitance cost of the current batch, and are used for updating low parasitic capacitance routing strategies. Once the strategy model has a relatively stable ability to generate valid solutions, it enters a stable optimization phase. Let the average cost of the current batch be... The standard deviation is Then the sample The optimal value is defined as:
[0063]
[0064] in, To avoid tiny positive numbers with a denominator of zero, candidates better than the batch mean are given positive weights to increase the generation probability of the corresponding edge state combination; candidates worse than the batch mean are given negative weights to reduce their generation probability. The absolute value of the weight is proportional to the difference between the sample and the batch mean and is normalized by the batch standard deviation. This stage can actively suppress poor solutions, thereby overcoming the local optimum limitation caused by merely imitating high-quality solutions. Parallel sampling, surrogate evaluation, and policy update are repeated until the termination condition is met.
[0065] D. Candidate map output and precise filtering
[0066] After the iteration terminates, several candidate layouts with the lowest normalized capacitance cost are selected as the final candidate set. Precise parasitic parameter extraction and circuit simulation are performed on the candidate set to obtain electrical performance indicators such as delay, power consumption, and switching time. The final layout is then selected according to preset evaluation criteria.
[0067] It should be noted that the purpose of disclosing the embodiments is to help further understand the present invention. However, those skilled in the art will understand that various substitutions and modifications are possible without departing from the scope of the present invention and the appended claims. Therefore, the present invention should not be limited to the content disclosed in the embodiments, and the scope of protection of the present invention is defined by the scope of the claims.
Claims
1. A standard cell wiring method for parasitic capacitance sensing, characterized in that, The steps include the following: A. Perform parallel routing sampling, generate sampling prompts through the strategy model to guide the solver in parallel, and obtain a valid routing solution by solving the solver conflict repair; B. Decode the valid wiring into a two-dimensional multi-channel density map; The parasitic capacitance of critical nets in transistor wiring is estimated and predicted by proxy to obtain the total parasitic capacitance of each critical net and the normalized capacitance cost; including: B1. For each valid wiring solution, extract the geometric distribution information of the key wire mesh of the transistor wiring on each metal layer and via layer, and construct a two-dimensional multi-channel density map representation; wherein, different metal layers and different via layers occupy different channels to characterize the coupling characteristics of the same layer and cross-layer coupling. B2. Input the two-dimensional multi-channel density map into a pre-trained convolutional neural network surrogate model to predict the total parasitic capacitance of each key network; B3. Based on the parasitic capacitance of the critical net corresponding to the initial layout, normalize the predicted capacitance of each candidate wiring solution to obtain the normalized capacitance cost. C. Normalized Capacitor Cost Weighted Strategy Update: Use the valid wiring solution as a pseudo-label and update the cost weighted strategy according to the normalized capacitor cost; Repeat steps A through C for iteration until candidate wiring solutions are obtained.
2. The standard cell wiring method for parasitic capacitance sensing as described in claim 1, characterized in that, Step A involves parallel routing sampling, including: The wiring area within a standard cell under a fixed transistor layout is discretized into a three-dimensional mesh diagram, and a multi-commodity flow constraint model is established. A policy model is used to generate a probability distribution of candidate occupancy states for each edge in a 3D mesh graph; Multiple sampling prompts are obtained through parallel sampling based on probability distribution, and each is injected into multiple solver threads as soft decision directions. Each solver thread, under the premise of satisfying connectivity, mutual exclusion and design rule constraints, overwrites or repairs conflict prompts and outputs multi-combination method wiring solutions.
3. The standard cell wiring method for parasitic capacitance sensing as described in claim 2, characterized in that, In the 3D mesh graph, vertices represent available routing locations, and edges represent adjacent available routing resources. For each edge, a candidate state is defined, which can be occupied by a certain mesh or remain unoccupied. The probability distribution of the candidate states for each edge is output using a policy model, and a candidate state is selected for each edge using a roulette wheel sampling method based on the probability distribution, thus forming a set of sampling hints. The sampling hints are soft hints. Multiple sets of sampling hints are generated in parallel and assigned to multiple solver threads respectively.
4. The standard cell wiring method for parasitic capacitance sensing as described in claim 3, characterized in that, A decision callback mechanism is registered in each solver thread. When the solver needs to make a branch decision for a Boolean variable, the edge occupancy state corresponding to the sampling hint is used as the decision direction first, thereby guiding the solver search to the vicinity of the wiring topology preferred by the policy model.
5. The standard cell wiring method for parasitic capacitance sensing as described in claim 1, characterized in that, In step B3, the smaller the normalized capacitance cost, the better the parasitic capacitance performance of the candidate wiring solution.
6. The standard cell wiring method for parasitic capacitance sensing as described in claim 1, characterized in that, The cost-weighted strategy is updated based on the normalized capacitance cost, including the following process: The valid routing solutions obtained by parallel routing sampling are used as the supervision targets of the policy model; Using the occupancy state of the valid wiring solution on each edge as pseudo-labels, the loss function of the policy model is constructed, and an entropy regularization term is added to maintain search diversity. During the warm-up phase, multiple candidate routing solutions with the lowest normalized capacitance cost are selected from the legal routing solutions as elite samples, and weights are assigned according to the difference between their costs and the global optimal cost, so that low-capacity candidates contribute more to the policy update, thereby quickly establishing an initial search distribution biased towards high-quality topologies. During the stable optimization phase, the advantage value of each candidate routing solution is calculated based on the average capacitance cost and standard deviation of the legal routing solutions. Positive weights are assigned to candidate wiring solutions whose normalized capacitance cost is lower than the current average normalized capacitance cost. Otherwise, negative weights are assigned; this drives the search process out of local optima and continuously converges towards lower parasitic capacitance.
7. The standard cell wiring method for parasitic capacitance sensing as described in claim 6, characterized in that, Let the currently collected set of valid wiring solutions be... Map Sample On the side The final candidate state is denoted as Then the loss function of the strategy model The definition is expressed as: in, for The weight, For entropy regularization, The regularization coefficient is used. This is the k-th valid wiring solution in the current batch B after solver conflict repair.
8. The standard cell wiring method for parasitic capacitance sensing as described in claim 7, characterized in that, The weights for the preheating phase are defined as follows: in, Here is the temperature parameter; I represents the preheating stage; For the sample The cost of normalized capacitance.
9. The standard cell wiring method for parasitic capacitance sensing as described in claim 8, characterized in that, sample The advantage value is defined as follows: The average cost of the current batch is The standard deviation is ; To avoid tiny positive numbers with a denominator of zero.
10. The standard cell wiring method for parasitic capacitance sensing as described in claim 1, characterized in that, Multiple candidate layouts with the lowest normalized capacitance cost are selected as candidate routing solutions during the iteration process to form a candidate layout library; precise parasitic parameter extraction and circuit simulation are performed on the candidate layouts, and the final layout is selected based on delay, power consumption, switching time or their weighted combination.