Chip packaging structure

Abstract

A chip packaging structure comprises a substrate which is provided with a first surface and a second surface which are oppositely arranged in a first direction, at least one bonding wire window which penetrates through the substrate in the first direction, a grounding circuit is arranged in the substrate, and two ends of the grounding circuit are located on the second surface of the substrate; the chip is provided with a third surface, a fourth surface and a chip side surface, the third surface and the fourth surface are oppositely arranged in the first direction, the chip side surface is perpendicular to the third surface and the fourth surface, the third surface of the chip is mounted on the first surface of the substrate, a grounding welding pad of the third surface of the chip is exposed to the welding wire window, at least one silicon through hole penetrates through the chip in the first direction, and the silicon through hole is connected with the grounding welding pad; the grounding welding wire is respectively connected with the grounding welding pad and one end of the grounding circuit through the welding wire window; the plastic package body coats the first surface of the substrate, the side surface of the chip and the grounding welding wire, and fills the welding wire window; and the shielding layer at least covers the fourth surface of the chip and the plastic package body above the first surface of the substrate, and is electrically connected with the through silicon via. The technical scheme can increase the grounding area of the shielding layer and improve the electromagnetic shielding interference effect.

Description

Technical Field

[0001] The utility model relates to the field of chip packaging, in particular to a chip packaging structure. Background Art

[0002] Electromagnetic interference is a serious and challenging problem for most electronic products or systems. Since electromagnetic interference often interrupts, hinders, reduces or limits the performance of electronic devices or overall circuit systems, effective electromagnetic interference shielding is required to ensure the efficiency and safe operation of electronic devices or systems. In general, in order to avoid electromagnetic interference, an electromagnetic interference shielding layer is usually covered on the outer side of the semiconductor package. In order to ground the shielding layer, it is necessary to add a corresponding grounding line to the side of the semiconductor package or substrate, which will increase the production cost. In addition, the electromagnetic interference shielding layer is used to connect the grounding line on the side of the substrate. The exposed end face of the grounding line on the side of the substrate is limited and narrow, so the contact area with the electromagnetic interference shielding layer is a point connection, which can easily cause poor contact of the grounding line and cause electromagnetic shielding failure.

[0003] Therefore, how to achieve good grounding of the shielding layer and improve the electromagnetic interference shielding effect of the package is a problem that needs to be solved at present. Summary of the invention

[0004] The technical problem to be solved by the utility model is how to achieve good grounding of the shielding layer, improve the electromagnetic interference shielding effect of the package, and provide a chip packaging structure.

[0005] In order to solve the above problems, the utility model provides a chip packaging structure, comprising: a substrate, having a first surface and a second surface arranged opposite to each other in a first direction, at least one welding wire window penetrating the substrate in the first direction, the substrate also having a grounding circuit, and the two ends of the grounding circuit are located on the second surface of the substrate; a chip, having a third surface and a fourth surface arranged opposite to each other in the first direction, and a chip side surface perpendicular to the third surface and the fourth surface, the third surface of the chip is mounted on the first surface of the substrate, and a grounding pad on the third surface of the chip is exposed to the welding wire window, at least one silicon through hole penetrating the chip in the first direction, and the silicon through hole is connected to the grounding pad; a grounding wire, connected to the grounding pad and one end of the grounding circuit respectively through the welding wire window; a plastic package body covering the first surface of the substrate, the chip side surface, the grounding wire, and filling the welding wire window; a shielding layer covering at least the fourth surface of the chip and the plastic package body above the first surface of the substrate, and electrically connected to the silicon through hole.

[0006] The above technical solution uses a substrate with a welding wire window and sets a silicon through hole penetrating the third surface and the fourth surface in the chip, and connects to the grounding line of the substrate through the grounding welding wire, so that the shielding layer located on the fourth surface of the chip can be grounded through the silicon through hole inside the chip, so that the contact area of ​​the shielding layer is changed from point-like connection to surface-like connection, which greatly increases the grounding area of ​​the shielding layer, realizes good grounding of the shielding layer, avoids electromagnetic shielding failure caused by poor contact of the grounding line, and improves the electromagnetic interference shielding effect of the packaging structure; at the same time, the packaging thickness is reduced, the double-sided plastic sealing is performed at one time, and no special design circuit of the substrate is required, the process is simple, and the operation is convenient.

[0007] It should be understood that the above general description and the detailed description below are only exemplary and explanatory and cannot limit the present invention. The techniques, methods and devices known to ordinary technicians in the relevant field may not be discussed in detail, but in appropriate cases, the techniques, methods and devices should be considered as part of the authorization specification. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] In order to more clearly illustrate the technical solutions in the specific implementation of the utility model, the following is a brief introduction to the drawings required for the description of the specific implementation. Obviously, the drawings described below are only some specific implementations of the utility model. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0009] Figure 1 It is a structural schematic diagram of the first embodiment of the chip packaging structure of the present invention.

[0010] Figure 2 It is a structural schematic diagram of the second embodiment of the chip packaging structure of the present invention.

[0011] Figure 3 It is a structural schematic diagram of the third embodiment of the chip packaging structure of the present invention. DETAILED DESCRIPTION

[0012] The technical scheme in the embodiment of the utility model will be described clearly and completely below in conjunction with the accompanying drawings. Obviously, the described embodiment is only a part of the embodiment of the utility model, not all of the embodiments. Based on the embodiment of the utility model, all other embodiments obtained by those skilled in the art without creative work are within the scope of protection of the utility model.

[0013] See also Figure 1 , which is a schematic diagram of the structure of the first embodiment of the chip packaging structure of the utility model. Figure 1As shown, the chip packaging structure includes: a substrate 11, a chip 12, a grounding wire 151, a plastic package 13, and a shielding layer 14. The substrate 11 has a first surface S1 and a second surface S2 arranged opposite to each other in a first direction D1, at least one wire bonding window 16 penetrates the substrate 11 in the first direction, and the substrate 11 also has a grounding circuit 111, and the two ends of the grounding circuit 111 are located on the second surface S2 of the substrate 11. The chip 12 has a third surface S3 and a fourth surface S4 arranged opposite to each other in the first direction D1, and a chip side surface 120 perpendicular to the third surface S3 and the fourth surface S4, the third surface S3 of the chip 12 is mounted on the first surface S1 of the substrate 11, and the grounding pad 121 of the third surface S3 of the chip 12 is exposed to the wire bonding window 16, at least one silicon through hole 17 penetrates the chip 12, and the silicon through hole 17 is connected to the grounding pad 121. The grounding wire 151 is connected to the grounding pad 121 and one end of the grounding line 111 through the wire window 16. The plastic package 13 covers the first surface S1 of the substrate 11, the chip side 120, the grounding wire 151, and fills the wire window 16. The shielding layer 14 at least covers the fourth surface S4 of the chip 12 and the plastic package 13 above the first surface S1 of the substrate 11, and is electrically connected to the through silicon via 17.

[0014] The above technical solution uses a substrate with a welding wire window and sets a silicon through hole penetrating the third surface and the fourth surface in the chip, and connects to the grounding line of the substrate through the grounding welding wire, so that the shielding layer located on the fourth surface of the chip can be grounded through the silicon through hole inside the chip, so that the contact area of ​​the shielding layer is changed from point-like connection to surface-like connection, which greatly increases the grounding area of ​​the shielding layer, realizes good grounding of the shielding layer, avoids electromagnetic shielding failure caused by poor contact of the grounding line, and improves the electromagnetic interference shielding effect of the packaging structure; at the same time, the packaging thickness is reduced, the double-sided plastic sealing is performed at one time, and no special design circuit of the substrate is required, the process is simple, and the operation is convenient.

[0015] like Figure 1 As shown, in this embodiment, the plastic package 13 also covers a portion of the second surface S2 of the substrate 11. In some embodiments, the shielding layer 14 also covers the plastic package 13 covering the second surface S2 of the substrate 11 to further enhance the shielding effect.

[0016] In some embodiments, a metal layer 141 is disposed on the fourth surface S4 of the chip 12, the metal layer 141 is in contact with the through silicon via 17, and the shielding layer 14 is in contact with the metal layer 141. Providing the metal layer 141 can increase the contact area with the shielding layer 14, and using a good conductor as the metal layer 141 can increase the conductivity between the shielding layer 14 and the through silicon via 17, improve the grounding effect of the shielding layer 14, and further improve the electromagnetic interference shielding effect of the package.

[0017] In some embodiments, the cross-sectional area of ​​the through silicon via 17 close to the fourth surface S4 of the chip 12 is larger than the cross-sectional area of ​​the through silicon via 17 close to the third surface S3 of the chip 12, while ensuring that the contact area between the through silicon via 17 and the shielding layer 14 is large enough, while avoiding occupying the area of ​​the functional surface of the chip 12 (i.e., the third surface S3).

[0018] In some embodiments, the chip 12 is mounted on the first surface S1 of the substrate 11 through a non-conductive adhesive 190 .

[0019] In some embodiments, the shielding layer 14 is one or more metal layers. In this embodiment, the shielding layer 14 is a three-layer metal layer structure, the first metal layer is made of stainless steel, the second metal layer in the middle is made of copper, and the third metal layer is made of stainless steel. In some embodiments, the shielding layer 14 can be formed by physical vapor deposition, or by other methods such as ion plating, spraying, evaporation or chemical vapor deposition.

[0020] In some embodiments, the second surface S2 of the substrate 11 is further provided with a grounding solder ball 181, and the grounding solder ball 181 is electrically connected to the other end of the grounding line 111. The grounding solder ball 181 serves as an external terminal for electrically connecting to an external circuit. At this point, the shielding layer 14 is connected to the silicon through-via 17 inside the chip 12 and the grounding pad 121 on the third surface S3 of the chip 12 through the metal layer 141 on the fourth surface S4 of the chip 12, and is connected to the grounding line 111 inside the substrate 11 through the grounding wire 151, and finally connected to the grounding solder ball 181, so as to realize the grounding function of the shielding layer 14. Compared with the traditional grounding method, the chip packaging structure proposed in the utility model can change the contact area of ​​the shielding layer from point-like connection to surface-like connection, greatly increase the grounding area of ​​the shielding layer, realize good grounding of the shielding layer, avoid electromagnetic shielding failure caused by poor contact of the grounding line, and improve the electromagnetic interference shielding effect of the package.

[0021] In some embodiments, the third surface S3 of the chip 12 further includes a plurality of functional pads 122. The substrate 11 further includes a plurality of functional circuits 112, and both ends of the functional circuits 112 are located on the second surface S2 of the substrate 11. The chip packaging structure further includes a plurality of functional bonding wires 152, and the functional bonding wires 152 are connected to the functional pads 122 and the other ends of the functional circuits 112 through the bonding wire windows 16.

[0022] In some embodiments, the chip packaging structure further includes a plurality of functional solder balls 182 , which are located on the second surface S2 of the substrate 11 and electrically connected to one end of the functional circuit 112 , thereby electrically connecting the functional pad 122 to the functional solder ball 182 .

[0023] The chip packaging structure of the first embodiment of the present invention completes the connection between the ground circuit and the functional circuit through the wire bonding window 16. However, within the limited space of the wire bonding window 16, interference may occur between the ground bonding wire 151 and the functional bonding wire 152. In order to avoid interference between the ground bonding wire 151 and the functional bonding wire 152, the second embodiment of the present invention provides a chip packaging structure.

[0024] See also Figure 2 , which is a schematic diagram of the structure of the second embodiment of the chip packaging structure of the utility model. Figure 2 As shown, Figure 1 The difference from the embodiment shown is that in this embodiment, a plurality of the wire bonding windows 26 penetrate the substrate 21 in the first direction D1, and the wire bonding windows 26 further include at least one grounding window 261 and at least one functional window 262. The grounding wire 251 is electrically connected to the grounding pad 221 and the grounding circuit 211 through the grounding window 261, and the functional wire 252 is electrically connected to the functional pad 222 and the functional circuit 212 through the functional window 262. The plurality of grounding windows 261 and the functional window 262 are respectively provided, so that the grounding circuit and the functional circuit can be functionally partitioned, the possibility of interference between the grounding wire 251 and the functional wire 252 is reduced, and the grounding wire 251 and the functional wire 252 are prevented from short-circuiting, and the process complexity is reduced; at the same time, the plurality of wire bonding windows 26 can also disperse the stress borne by the chip packaging structure and enhance the strength of the chip packaging structure.

[0025] like Figure 2 As shown, in this embodiment, the plastic package 23 also covers a portion of the second surface S2 of the substrate 21. In some embodiments, the shielding layer 24 also covers the plastic package 23 covering the second surface S2 of the substrate 21 to further enhance the shielding effect.

[0026] Specifically, the ground pad 221 is exposed to the ground window 261 , and the through silicon via 27 is electrically connected to one of the ground pads 221 ; the functional pad 222 is exposed to the functional wire bonding window 262 .

[0027] In this embodiment, the plastic package body 23 further covers the third surface S3 of the chip 22 and a portion of the second surface S2 of the substrate 21 and fills the wire bonding window 26 .

[0028] In this embodiment, the fourth surface S4 of the chip 22 is in direct contact with the shielding layer 24 , which not only achieves electromagnetic shielding but also helps to dissipate heat.

[0029] The above technical solution uses a substrate with multiple welding wire windows and sets a silicon through hole penetrating the third surface and the fourth surface in the chip, and connects to the grounding line of the substrate through the grounding welding wire, so that the shielding layer located on the fourth surface of the chip can be grounded through the silicon through hole inside the chip, so that the contact area of ​​the shielding layer is changed from point-like connection to surface-like connection, which greatly increases the grounding area of ​​the shielding layer, realizes good grounding of the shielding layer, avoids electromagnetic shielding failure caused by poor contact of the grounding line, and improves the electromagnetic interference shielding effect of the packaging structure; the grounding welding wire and the functional welding wire are distributed in different welding wire windows, and the functions are divided to reduce the possibility of mutual interference or short circuit; at the same time, the packaging thickness is reduced, the double-sided plastic sealing is performed at one time, and no special circuit design of the substrate is required, the process is simple, and the operation is convenient.

[0030] See also Figure 3 , which is a schematic diagram of the structure of the third embodiment of the chip packaging structure of the utility model. Figure 3 As shown, Figure 2 The embodiment shown is different in that, when there are multiple wire bonding windows 36, there is a gap between the plastic encapsulation bodies 33 filling the adjacent wire bonding windows 36 on the second surface S2 of the substrate 31. Specifically, the plastic encapsulation body 33 fills the wire bonding windows 36, covers the portion of the third surface S3 of the chip 32 exposed to the wire bonding windows 36, and covers the portion of the second surface S2 of the substrate 31 located near the wire bonding windows 36. There is a gap between the plastic encapsulation bodies 33 filling the adjacent wire bonding windows 36, and the second surface S2 of the substrate 31 of the gap portion is exposed, so as to disperse the stress borne by the chip packaging structure and enhance the strength of the chip packaging structure.

[0031] In this embodiment, the plastic package 33 (eg, Figure 3The portion indicated by reference numeral 330 is used to enhance the strength of the chip package structure and prevent the chip package structure from cracking at the corners, warping of the substrate, and damage to the internal chip during the surface mounting process.

[0032] like Figure 3 As shown, in this embodiment, the plastic package 33 also covers a portion of the second surface S2 of the substrate 31. In some embodiments, the shielding layer 34 also covers the plastic package 33 covering the second surface S2 of the substrate 31 to further enhance the shielding effect.

[0033] In this embodiment, the fourth surface S4 of the chip 32 is in direct contact with the shielding layer 34 , which not only achieves electromagnetic shielding but also helps to dissipate heat.

[0034] The above technical solution uses a substrate with multiple welding wire windows and sets a silicon through hole penetrating the third surface and the fourth surface in the chip, and connects to the grounding line of the substrate through the grounding welding wire, so that the shielding layer located on the fourth surface of the chip can be grounded through the silicon through hole inside the chip, so that the contact area of ​​the shielding layer is changed from point-like connection to surface-like connection, which greatly increases the grounding area of ​​the shielding layer, realizes good grounding of the shielding layer, avoids electromagnetic shielding failure caused by poor contact of the grounding line, and improves the electromagnetic interference shielding effect of the packaging structure; distributes the grounding welding wire and the functional welding wire in different welding wire windows, and divides the functions to reduce the possibility of mutual interference or short circuit; and further adopts a plastic packaging body with intervals between adjacent welding wire windows to reduce the stress of the chip packaging structure and enhance the strength of the chip packaging structure; at the same time, the packaging thickness is reduced, the double-sided plastic packaging is performed at one time, and no special circuit design of the substrate is required, the process is simple, and the operation is convenient.

[0035] It should be noted that references in the specification to "an embodiment", "an embodiment", "an exemplary embodiment", "some embodiments", etc. indicate that the described embodiment may include a particular feature, structure, or characteristic, but every embodiment may not necessarily include the particular feature, structure, or characteristic. Moreover, such phrases do not necessarily refer to the same embodiment. In addition, when a particular feature, structure, or characteristic is described in conjunction with an embodiment, whether or not explicitly described, it is within the knowledge of a technician in the relevant art to implement such feature, structure, or characteristic in conjunction with other embodiments.

[0036] Typically, a term can be understood at least in part from usage in context. For example, the term "one or more" as used herein depends at least in part on the context and can be used to describe any feature, structure or characteristic in a singular sense, or can be used to describe a combination of features, structures or features in a plural sense. Similarly, terms such as "one", "a" or "the" can also be understood to express singular usage or to express plural usage, depending at least in part on the context. In addition, the term "based on" can be understood to not necessarily be intended to express a set of exclusive factors, but can alternatively, also at least in part depending on the context, allow for the presence of other factors that are not necessarily explicitly described. It should also be noted in this specification that "connected / coupled" refers not only to the direct coupling of one component to another component, but also to the indirect coupling of one component to another component through an intermediate component.

[0037] It should be noted that the terms "including" and "having" and their variations involved in the documents of the present utility model are intended to cover non-exclusive inclusions. The terms "first", "second", etc. are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. Unless the context clearly indicates otherwise, it should be understood that the data used in this way can be interchanged under appropriate circumstances. In addition, the embodiments of the present utility model and the features in the embodiments can be combined with each other unless there is a conflict. In addition, in the above description, the description of well-known components and technologies is omitted to avoid unnecessary confusion of the concepts of the present utility model. In the above-mentioned embodiments, each embodiment focuses on the differences from other embodiments, and the same / similar parts between the embodiments can be referred to each other.

[0038] The above is only a preferred embodiment of the present invention. It should be pointed out that ordinary technicians in this technical field can make several improvements and modifications without departing from the principle of the present invention. These improvements and modifications should also be regarded as the protection scope of the present invention.

Claims

1. A chip packaging structure, characterized in that: include: A substrate having a first surface and a second surface arranged opposite to each other in a first direction, at least one welding wire window penetrating the substrate in the first direction, a grounding circuit in the substrate, and two ends of the grounding circuit are located on the second surface of the substrate; A chip having a third surface and a fourth surface arranged opposite to each other in the first direction, and a chip side surface perpendicular to the third surface and the fourth surface, the third surface of the chip being mounted on the first surface of the substrate, and a grounding pad on the third surface of the chip being exposed to the wire bonding window, at least one through silicon via penetrating the chip in the first direction, and the through silicon via being connected to the grounding pad; A grounding wire, connected to the grounding pad and one end of the grounding line respectively through the wire window; A plastic package body, covering the first surface of the substrate, the side surface of the chip, the grounding wire, and filling the wire window; The shielding layer at least covers the fourth surface of the chip and the plastic package above the first surface of the substrate, and is electrically connected to the through silicon via.

2. The chip packaging structure according to claim 1, characterized in that: A metal layer is disposed on the fourth surface of the chip, the metal layer is in contact with the through silicon via, and the shielding layer is in contact with the metal layer.

3. The chip packaging structure according to claim 1, characterized in that: The shielding layer is one or more metal layers.

4. The chip packaging structure according to claim 1, characterized in that: The chip is mounted on the first surface of the substrate by means of non-conductive adhesive.

5. The chip packaging structure according to claim 1, characterized in that: A grounding solder ball is also disposed on the second surface of the substrate, and the grounding solder ball is electrically connected to the other end of the grounding circuit.

6. The chip packaging structure according to claim 1, characterized in that: The third surface of the chip also includes a plurality of functional pads; The substrate also includes a plurality of functional circuits, and the two ends of the functional circuits are located on the second surface of the substrate; the chip packaging structure also includes a plurality of functional welding wires, and the functional welding wires are respectively connected to the functional pads and the other end of the functional circuits through the welding wire windows.

7. The chip packaging structure according to claim 6, characterized in that: A plurality of welding wire windows penetrate the substrate in the first direction, and the welding wire windows further include at least one grounding window and at least one functional window; the grounding welding wires are respectively connected to the grounding pads and the grounding circuits through the grounding windows, and the functional welding wires are respectively connected to the functional welding pads and the functional circuits through the functional windows.

8. The chip packaging structure according to any one of claims 1 to 7, characterized in that: The plastic package body also covers the third surface of the chip and a portion of the second surface of the substrate and fills the wire bonding window.

9. The chip packaging structure according to claim 8, characterized in that: The shielding layer also covers the plastic package body covered on the second surface of the substrate.

10. The chip packaging structure according to claim 8, characterized in that: When there are a plurality of the wire bonding windows, there are intervals between the plastic packaging bodies filling adjacent wire bonding windows on the second surface of the substrate.

11. The chip packaging structure according to claim 1, characterized in that: The plastic packaging body is also arranged at the edge of the second surface of the substrate.

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