Charging circuit of equipment seat charger with strong anti-interference capability

Abstract

The utility model discloses a charging circuit of an equipment seat charger with strong anti-interference capability, which is provided with a power supply input module, an LDO (Low Dropout Regulator) step-down module and a step-up module which are connected with the output end of the power supply input module, a singlechip processing module connected with the output end of the LDO step-down module, and a charging control module connected with the output end of the step-up module, the single-chip microcomputer processing module is connected with the charging control module, and a power supply filtering module used for reducing common-mode noise is arranged between the power supply input module and the boost module and between the power supply input module and the LDO step-down module. According to the utility model, the power supply filtering module is additionally arranged at the output end of the power supply input module to filter the input power supply, so that common-mode noise is reduced, electromagnetic interference is reduced from the source, conducted interference and radiated interference are filtered out, the anti-interference capability of equipment is improved, and the requirement of an electromagnetic compatibility test standard is met. The utility model also has the characteristics of simple structure, low cost, high reliability and the like.

Description

Technical Field

[0001] The utility model relates to a charging circuit technology, in particular to a charging circuit for a device charger with strong anti-interference capability. Background Art

[0002] Handheld medical devices are widely used in hospitals. Among them, in the current mainstream handheld medical devices, the seat charger is an essential component. For the seat charger of handheld medical devices, electromagnetic compatibility testing is an important indicator for testing product quality. Among them, the radiation emission (RE) test must meet the radiation standard of GB18268.26: <30dB and <37dB. However, the RE test of the existing seat charger of handheld medical devices exceeds the standard. The main reason is that the radiation is too high due to the boost IC power supply or ground noise. In order to reduce radiation, the existing solution is to add a shielding cover to the seat charger, but this will take up a large structural space. At the same time, it will increase the cost and mold opening fee. The most important thing is that the problem is not solved from the source. Therefore, how to provide a low-cost, reliable, and fundamentally solve the problem of excessive radiation of the seat charger has become an objective need. Utility Model Content

[0003] The utility model provides a charging circuit for a device charger with strong anti-interference capability, which is used to solve the problems that the existing handheld medical device charger does not meet the requirements of electromagnetic compatibility test standards and has high cost and complex structure.

[0004] To achieve the purpose of the utility model, the utility model provides a charging circuit for a device charger with strong anti-interference ability. The charging circuit is provided with a power input module, an LDO buck module and a boost module connected to the output end of the power input module, a single-chip microcomputer processing module connected to the output end of the LDO buck module, and a charging control module connected to the output end of the boost module. The single-chip microcomputer processing module is connected to the charging control module, and a power filter module for reducing common mode noise is provided between the power input module and the boost module and the LDO buck module.

[0005] Furthermore, the power supply filter module includes a first capacitor C1, a second capacitor C2, a first magnetic bead RL1, a second magnetic bead RL2 and a common mode filter LF1, one end of the first capacitor C1 is connected to the power end of the power input module, and the other end thereof is connected to the ground end of the power input module, one end of the second capacitor C2 is connected to one end of the first magnetic bead RL1, and the other end thereof is connected to one end of the second magnetic bead RL2, the other end of the first magnetic bead RL1 is connected to the first power supply VDD1, and the other end of the second magnetic bead RL2 is grounded, and the common mode filter LF1 is arranged between the first capacitor C1 and the second capacitor C2.

[0006] Preferably, the first capacitor C1 and the second capacitor C2 are chip capacitors with a model number of 0805-1010uF (106) / 16V, and the first magnetic bead RL1 and the second magnetic bead RL2 are chip magnetic beads with a model number of B2012-301 / 3A.

[0007] Preferably, the common mode filter LF1 is a low pass filter of model SHB7060-701.

[0008] Furthermore, the boost module includes a second chip U2 and a peripheral circuit connected thereto, the first pin of the second chip U2 is grounded through a fifth resistor R5 and a seventh capacitor C7, the first pin of the second chip U2 is connected to the second power supply VDD2 via a first diode D1 and a third magnetic bead RL3, the first pin of the second chip U2 is connected to the first power supply VDD1 via a first inductor L1, the fourth pin and the fifth pin of the second chip U2 are respectively connected to the first power supply VDD1, and the first diode D1 is connected in parallel with a twentieth resistor R20 and a fifteenth capacitor C15.

[0009] Further, the peripheral circuit includes a fifth capacitor C5, a sixth capacitor C6, an eighth capacitor C8, a ninth capacitor C9, a third resistor R3, a fourth resistor R4 and a sixth resistor R6, one end of the fifth capacitor C5 is connected to the first power supply VDD1, and the other end thereof is grounded, one end of the sixth capacitor C6 is connected to the first power supply VDD1, and the other end thereof is grounded, one end of the third resistor R3 is connected to the sixth pin of the second chip U2, and the other end thereof is grounded, one end of the sixth resistor R6 is respectively connected to the cathode of the first diode D1 and one end of the eighth capacitor C8, and the other end thereof is respectively connected to the third pin of the second chip U2 and one end of the fourth resistor R4, one end of the ninth capacitor C9 is connected to the second power supply VDD2, and the other end of the fourth resistor R4, the other end of the eighth capacitor C8 and the other end of the ninth capacitor C9 are respectively grounded.

[0010] Preferably, the fifth resistor R5 is a chip resistor with a model number of 0603-2.0R, the seventh capacitor C7 is a chip capacitor with a model number of 0603-3.3nF / 25V, the twentieth resistor R20 is a chip resistor with a model number of 0805-10R±5%, the fifteenth capacitor C15 is a chip capacitor with a model number of 0805-1nF(102) / 50V, the first inductor L1 is a chip inductor with a model number of SHC0603-3R3, and the third magnetic bead RL3 is a chip magnetic bead with a model number of PB2012-301 / 3A.

[0011] Furthermore, the LDO step-down module includes a first chip U1, a third capacitor C3 and a fourth capacitor C4, the first pin of the first chip U1 is respectively connected to one end of the third capacitor C3 and the first power supply VDD1, the third pin is respectively connected to one end of the fourth capacitor C4 and the third power supply VDD3, and the second pin, the other end of the third capacitor C3 and the other end of the fourth capacitor C4 are respectively grounded.

[0012] Furthermore, the single-chip processing module includes a third chip U3, a tenth capacitor C10, an eleventh capacitor C11, a twelfth capacitor C12, a fourteenth capacitor C14, a tenth resistor R10 and a first light-emitting diode LD1. The first pin of the third chip U3 is respectively connected to one end of the fourteenth capacitor C14 and the third power supply VDD3, the seventh pin thereof is grounded via the tenth resistor R10 and the first light-emitting diode LD1, the ninth pin thereof is grounded via the tenth capacitor C10, the tenth pin thereof is grounded via the eleventh capacitor C11, the twelfth pin thereof is grounded via the twelfth capacitor C12, the fourteenth pin thereof and the other end of the fourteenth capacitor C14 are grounded, and the sixth pin, the ninth pin, the tenth pin, the eleventh pin and the twelfth pin thereof are respectively connected to the charging control module.

[0013] Further, the charging control module includes a transistor Q1, a MOS tube Q2, a seventh resistor R7, an eighth resistor R8, a ninth resistor R9, an eleventh resistor R11, a twelfth resistor R12, a thirteenth resistor R13, a fourteenth resistor R14, a fifteenth resistor R15, a sixteenth resistor R16, a seventeenth resistor R17, an eighteenth resistor R18, a nineteenth resistor R19, a thirteenth capacitor C13, a third diode D3 and a second plug J2, the source of the MOS tube Q2 is respectively connected to one end of the fifteenth resistor R15, one end of the sixteenth resistor R16, one end of the nineteenth resistor R19, one end of the thirteenth capacitor C13 and the second power supply VDD2, its gate is respectively connected to the other end of the sixteenth resistor R16 and the collector of the transistor Q1, its drain, the other end of the nineteenth resistor R19, one end of the seventeenth resistor R17, one end of the eighteenth resistor R18, one end of the third diode D3 and The first pin of the second plug J2 is connected, the other end of the fifteenth resistor R15, one end of the ninth resistor R9, one end of the eighth resistor R8, the other end of the seventeenth resistor R17, the other end of the eighteenth resistor R18, one end of the thirteenth resistor R13 and one end of the fourteenth resistor R14 are respectively connected to the third chip U3 of the single-chip processing module 50, the other end of the eighth resistor R8 is respectively connected to one end of the seventh resistor R7 and the base of the transistor Q1, the other end of the fourteenth resistor R14 is respectively connected to one end of the eleventh resistor R11, one end of the twelfth resistor R12 and the second pin of the second plug J2, the other end of the ninth resistor R9, the other end of the seventh resistor R7, the emitter of the transistor Q1, the other end of the thirteenth capacitor C13, the other end of the thirteenth resistor R13, the other end of the eleventh resistor R11, the other end of the twelfth resistor R12 and the other end of the third diode D3 are respectively grounded.

[0014] The beneficial effects of the utility model are as follows: the charging circuit of the device charger with strong anti-interference ability of the utility model filters the input power by adding a power filter module at the output end of the power input module, thereby reducing common mode noise. On the other hand, by selecting suitable chip resistors, chip capacitors, chip inductors and chip magnetic beads in the boost module, the clutter noise caused by spikes can be reduced and the differential mode radiation can be reduced, thereby reducing the generation of electromagnetic interference from the source, filtering out conducted interference and radiated interference, and improving the anti-interference ability of the equipment to meet the requirements of electromagnetic compatibility test standards. The utility model also has the characteristics of simple structure, low cost, high reliability, etc. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] Figure 1 It is a structural frame diagram of the utility model.

[0016] Figure 2The utility model is a circuit diagram of a power input module, a power filter module, a boost module and an LDO buck module.

[0017] Figure 3 It is a circuit diagram of the single chip microcomputer processing module of the utility model.

[0018] Figure 4 It is a circuit diagram of a charging control module of the utility model. DETAILED DESCRIPTION

[0019] The technical solution of the utility model will be described clearly and completely below in conjunction with the accompanying drawings and specific embodiments. Obviously, the described embodiments are only part of the embodiments of the utility model, not all of them. Based on the embodiments of the utility model, all other embodiments obtained by those skilled in the art without creative work are within the scope of protection of the utility model.

[0020] like Figure 1 As shown, the charging circuit of the device charger with strong anti-interference ability of the utility model is provided with a power input module 10, a power filter module 20, a boost module 30, an LDO buck module 40, a single-chip processing module 50 and a charging control module 60, wherein the output end of the power input module 10 is connected to the input end of the power filter module 20, the output end of the power filter module 20 is respectively connected to the boost module 30 and the LDO buck module 40, the output end of the boost module 30 is connected to the charging control module 60, the output end of the LDO buck module 40 is connected to the single-chip processing module 50, and the single-chip processing module 50 is connected to the charging control module 60. The input end of the charging circuit is connected to an external power supply, and the output end thereof is connected to a handheld medical device, for powering the handheld medical device, and meets the requirements of the electromagnetic compatibility test standard.

[0021] like Figure 1 As shown, the input end of the power input module 10 is connected to an external power source, which is used to access the power source. Figure 2 As shown, the power input module 10 is an input interface J1, specifically a TYPE-C 16pin plug, which is connected to the mains through a power adapter.

[0022] like Figure 1 As shown, the output end of the power input module 10 is connected to a power filter module 20, and the power filter module 20 is used to reduce the common mode noise of the input power to meet the electromagnetic compatibility test standard. Figure 2As shown, the power filter module 20 includes a first capacitor C1, a second capacitor C2, a first magnetic bead RL1, a second magnetic bead RL2 and a common mode filter LF1, wherein one end of the first capacitor C1 is connected to the power end of the power input module 10, and the other end thereof is connected to the ground end of the power input module 10, one end of the second capacitor C2 is connected to one end of the first magnetic bead RL1, and the other end thereof is connected to one end of the second magnetic bead RL2, the other end of the first magnetic bead RL1 is connected to the first power supply VDD1, and the other end of the second magnetic bead RL2 is grounded, and the common mode filter LF1 is arranged between the first capacitor C1 and the second capacitor C2. In this embodiment, the first power supply VDD1 is a 5V power supply, the first capacitor C1 and the second capacitor C2 are both chip capacitors with a model of 0805-1010uF (106) / 16V, the first magnetic bead RL1 and the second magnetic bead RL2 are both chip magnetic beads with a model of B2012-301 / 3A, and the common mode filter LF1 is a low-pass filter with a model of SHB7060-701. By setting the first capacitor C1 and the second capacitor C2 as chip capacitors, the first magnetic bead RL1 and the second magnetic bead RL2 as chip magnetic beads, and using a low-pass filter for the common-mode filter LF1, the common-mode noise of the input power supply can be reduced and the electromagnetic compatibility test standard can be met.

[0023] like Figure 1 As shown, the output end of the power filter module 20 is connected to the boost module 30 and the LDO buck module 40 respectively. The boost module 30 is used to generate the second power supply VDD2 to supply power to the charging control module 60. Specifically, Figure 2As shown, the boost module 30 includes a second chip U2 and a peripheral circuit connected thereto, wherein the first pin of the second chip U2 is grounded through a fifth resistor R5 and a seventh capacitor C7, the first pin of the second chip U2 is connected to the second power supply VDD2 through a first diode D1 and a third magnetic bead RL3, and the first pin of the second chip U2 is connected to the first power supply VDD1 through a first inductor L1, the fourth pin and the fifth pin of the second chip U2 are respectively connected to the first power supply VDD1, and the first diode D1 is connected in parallel with a twentieth resistor R20 and a fifteenth capacitor C15. In this embodiment, the second power supply VDD2 is a 5.5V power supply. The second chip U2 is a boost chip. The fifth resistor R5 is a chip resistor with a model number of 0603-2.0R, the seventh capacitor C7 is a chip capacitor with a model number of 0603-3.3nF / 25V, and the first pin of the first chip U1 is grounded through the fifth resistor R5 and the seventh capacitor C7, which can reduce the clutter noise caused by the spike. The twentieth resistor R20 is a chip resistor of model 0805-10R±5%, the fifteenth capacitor C15 is a chip capacitor of model 0805-1nF(102) / 50V, the first inductor L1 is a chip inductor of model SHC0603-3R3, and the third magnetic bead RL3 is a chip magnetic bead of model PB2012-301 / 3A. By setting the third chip magnetic bead RL3, the fifteenth chip capacitor C15 and the twentieth chip resistor R20, the differential mode radiation can be reduced to meet the electromagnetic compatibility test standard.

[0024] like Figure 2 As shown, the peripheral circuit includes a fifth capacitor C5, a sixth capacitor C6, an eighth capacitor C8, a ninth capacitor C9, a third resistor R3, a fourth resistor R4 and a sixth resistor R6. Among them, one end of the fifth capacitor C5 is connected to the first power supply VDD1, and the other end thereof is grounded; one end of the sixth capacitor C6 is connected to the first power supply VDD1, and the other end thereof is grounded; one end of the third resistor R3 is connected to the sixth pin of the second chip U2, and the other end thereof is grounded; one end of the sixth resistor R6 is respectively connected to the cathode of the first diode D1 and one end of the eighth capacitor C8, and the other end thereof is respectively connected to the third pin of the second chip U2 and one end of the fourth resistor R4; one end of the ninth capacitor C9 is connected to the second power supply VDD2, and the other end of the fourth resistor R4, the other end of the eighth capacitor C8 and the other end of the ninth capacitor C9 are respectively grounded.

[0025] like Figure 2As shown, in the peripheral circuit, the fourth resistor R4 and the sixth resistor R6 form an output voltage feedback resistor. When the built-in switch tube of the second chip U2 is turned on, the first power supply VDD1 forms a loop through the inductor L1 and the built-in switch tube of the second chip U2. The inductor L1 stores energy and is connected in series with the input voltage to increase the voltage. When the built-in switch tube of the second chip U2 is disconnected, since the current of the inductor L1 cannot change suddenly, the inductor L1 releases the stored energy. At this time, the output voltage = input voltage * (1 + D) / (1-D), where D is the output duty cycle of the built-in switch tube of the second chip U2. The second chip U2 samples the output voltage through the voltage feedback pin and adjusts the output duty cycle of its built-in switch tube so that the output voltage VDD2 is greater than the input voltage VDD1.

[0026] like Figure 2 As shown, the LDO buck module 40 is used to generate a third power supply VDD3 to power the single-chip processing module. Specifically, the LDO buck module 40 includes a first chip U1, a third capacitor C3 and a fourth capacitor C4, wherein the first pin of the first chip U1 is respectively connected to one end of the third capacitor C3 and the first power supply VDD1, the third pin thereof is respectively connected to one end of the fourth capacitor C4 and the third power supply VDD3, and the second pin thereof, the other end of the third capacitor C3 and the other end of the fourth capacitor C4 are respectively grounded. In this embodiment, the first chip U1 is a voltage regulator of model HT7533-1 / SOT89. The voltage of the third power supply VDD 3 is 3.3V.

[0027] like Figure 1 As shown, the output end of the LDO buck module 40 is connected to the single-chip processing module 50, which is used to detect the current and voltage data of the charging control module 60 and control whether the charging control module 60 is working. Figure 3 As shown, the single-chip processing module 50 includes a third chip U3, a tenth capacitor C10, an eleventh capacitor C11, a twelfth capacitor C12, a fourteenth capacitor C14, a tenth resistor R10 and a first light-emitting diode LD1. Among them, the first pin of the third chip U3 is respectively connected to one end of the fourteenth capacitor C14 and the third power supply VDD3, its seventh pin is grounded through the tenth resistor R10 and the first light-emitting diode LD1, its ninth pin is grounded through the tenth capacitor C10, its tenth pin is grounded through the eleventh capacitor C11, its twelfth pin is grounded through the twelfth capacitor C12, its fourteenth pin and the other end of the fourteenth capacitor C14 are grounded, and its sixth pin, ninth pin, tenth pin, eleventh pin, and twelfth pin are respectively connected to the charging control module 60. In this embodiment, the third chip U3 is a single-chip microcomputer of model NX6P80A / SOP14. The first light-emitting diode LD1 is used to display the working status of the charging circuit.

[0028] like Figure 1As shown, the output end of the boost module 30 is provided with a charging control module 60, which is connected to the single-chip processing module 50 and outputs voltage under the control of the single-chip output module 50. Specifically, Figure 4 As shown, the charging control module 60 includes a transistor Q1, a MOS transistor Q2, a seventh resistor R7, an eighth resistor R8, a ninth resistor R9, an eleventh resistor R11, a twelfth resistor R12, a thirteenth resistor R13, a fourteenth resistor R14, a fifteenth resistor R15, a sixteenth resistor R16, a seventeenth resistor R17, an eighteenth resistor R18, a nineteenth resistor R19, a thirteenth capacitor C13, a third diode D3 and a second plug J2. The source of the MOS tube Q2 is respectively connected to one end of the fifteenth resistor R15, one end of the sixteenth resistor R16, one end of the nineteenth resistor R19, one end of the thirteenth capacitor C13 and the second power supply VDD2, the gate thereof is respectively connected to the other end of the sixteenth resistor R16 and the collector of the transistor Q1, the drain thereof, the other end of the nineteenth resistor R19, one end of the seventeenth resistor R17, one end of the eighteenth resistor R18, one end of the third diode D3 and the first pin of the second plug J2, the other end of the fifteenth resistor R15, one end of the ninth resistor R9, one end of the eighth resistor R8, the other end of the seventeenth resistor R17, the other end of the eighteenth resistor R18, One end of the thirteenth resistor R13 and one end of the fourteenth resistor R14 are respectively connected to the third chip U3 of the single-chip processing module 50, the other end of the eighth resistor R8 is respectively connected to one end of the seventh resistor R7 and the base of the transistor Q1, the other end of the fourteenth resistor R14 is respectively connected to one end of the eleventh resistor R11, one end of the twelfth resistor R12 and the second pin of the plug J2, the other end of the ninth resistor R9, the other end of the seventh resistor R7, the emitter of the transistor Q1, the other end of the thirteenth capacitor C13, the other end of the thirteenth resistor R13, the other end of the eleventh resistor R11, the other end of the twelfth resistor R12 and the other end of the third diode D3 are respectively grounded. Among them, the ninth resistor R9 and the fifteenth resistor R15 form a voltage divider circuit for the single-chip processing module 50 to detect the voltage of the second power supply VDD2. The eighteenth resistor R18 and the thirteenth resistor R13 form a voltage divider circuit for the single-chip processing module 50 to detect the voltage of the output power supply of the charging control module 60. The eleventh resistor R11 and the twelfth resistor R12 form a current sampling circuit, which is used by the single-chip processing module 50 to detect the charging current of the charging control module 60. In this embodiment, the transistor Q1 is an NPN transistor, the MOS transistor Q2 is a P-channel MOS transistor, and its model is AP9435GM. The second interface J2 can select an existing power output interface.

[0029] like Figure 3 , Figure 4As shown, when the sixth pin of the third chip U3 outputs a high level, the transistor Q1 is turned on, and the MOS tube Q2 is turned on. At this time, the second power supply VDD2 outputs a voltage through the MOS tube Q2 via the second plug J2 to supply power to the handheld medical device. When the third chip U3 detects an abnormal signal, the sixth pin of the third chip U3 outputs a low level, the transistor Q1 is turned off, and the MOS tube Q2 is turned off. At this time, the second power supply VDD2 cannot output a voltage through the MOS tube Q2. Specifically, when the third chip U3 detects the second power supply VDD2 voltage through the voltage-dividing resistors 15th resistor R15 and 9th resistor R9, detects the output power supply voltage through the voltage-dividing resistors 18th resistor R18 and 13th resistor R13, or detects any abnormality in the charging current through the current sampling resistors 11th resistor R11 and 12th resistor R12, the sixth pin of the third chip U3 outputs a low level. At the same time, the third chip U3 displays an abnormal signal through the first light-emitting diode LD1 to remind the staff to repair.

[0030] like Figure 2 , Figure 3 and Figure 4 As shown, the working process of the charging circuit of the device charger with strong anti-interference ability of the utility model is: the power input module 10 filters the input power through the power filter module 20 and outputs the first power VDD1, and then generates the second power VDD2 through the boost module 30 to supply power to the charging control module 60; at the same time, the first power VDD1 generates the third power VDD3 through the LDO buck module 40 to supply power to the single-chip microcomputer processing module 50, and the single-chip microcomputer processing module 50 detects whether the input voltage, output voltage and output current parameters of the charging control module 60 are normal. If normal, the charging control module 60 is controlled to output voltage to the outside to power the handheld medical device; if abnormal, the charging control module 60 is controlled not to output voltage to the outside, and the working status is indicated by the first light-emitting diode LD1.

[0031] The charging circuit of the device charger with strong anti-interference ability of the utility model adds a power filter module 20 at the output end of the power input module 10 to filter the input power, thereby reducing common mode noise. On the other hand, by selecting suitable chip resistors, chip capacitors, chip inductors and chip magnetic beads in the boost module 30, the clutter noise caused by spikes can be reduced and the differential mode radiation can be reduced, thereby reducing the generation of electromagnetic interference from the source, filtering out conducted interference and radiated interference, and improving the anti-interference ability of the equipment to meet the requirements of electromagnetic compatibility test standards. The utility model also has the characteristics of simple structure, low cost, high reliability, etc.

[0032] Although the present invention is disclosed through the above embodiments, the protection scope of the present invention is not limited thereto. Without departing from the concept of the present invention, any deformation, replacement, etc. made to the above components shall fall within the scope of the claims of the present invention.

Claims

1. A charging circuit for a device charger with strong anti-interference capability, characterized in that: The charging circuit is provided with a power input module, an LDO buck module and a boost module connected to the output end of the power input module, a single-chip microcomputer processing module connected to the output end of the LDO buck module, and a charging control module connected to the output end of the boost module. The single-chip microcomputer processing module is connected to the charging control module, and a power filter module for reducing common mode noise is provided between the power input module and the boost module and the LDO buck module.

2. The charging circuit according to claim 1, characterized in that: The power supply filter module includes a first capacitor C1, a second capacitor C2, a first magnetic bead RL1, a second magnetic bead RL2 and a common mode filter LF1. One end of the first capacitor C1 is connected to the power end of the power input module, and the other end thereof is connected to the ground end of the power input module. One end of the second capacitor C2 is connected to one end of the first magnetic bead RL1, and the other end thereof is connected to one end of the second magnetic bead RL2. The other end of the first magnetic bead RL1 is connected to the first power supply VDD1, and the other end of the second magnetic bead RL2 is grounded. The common mode filter LF1 is arranged between the first capacitor C1 and the second capacitor C2.

3. The charging circuit according to claim 2, characterized in that: The first capacitor C1 and the second capacitor C2 are chip capacitors with a model number of 0805-1010uF (106) / 16V, and the first magnetic bead RL1 and the second magnetic bead RL2 are chip magnetic beads with a model number of B2012-301 / 3A.

4. The charging circuit according to claim 2, characterized in that: The common mode filter LF1 is a low pass filter of model SHB7060-701.

5. The charging circuit according to claim 2, characterized in that: The boost module includes a second chip U2 and a peripheral circuit connected thereto, the first pin of the second chip U2 is grounded through a fifth resistor R5 and a seventh capacitor C7, the first pin of the second chip U2 is connected to the second power supply VDD2 via a first diode D1 and a third magnetic bead RL3, the first pin of the second chip U2 is connected to the first power supply VDD1 via a first inductor L1, the fourth pin and the fifth pin of the second chip U2 are respectively connected to the first power supply VDD1, and the first diode D1 is connected in parallel with a twentieth resistor R20 and a fifteenth capacitor C15.

6. The charging circuit according to claim 5, characterized in that: The peripheral circuit includes a fifth capacitor C5, a sixth capacitor C6, an eighth capacitor C8, a ninth capacitor C9, a third resistor R3, a fourth resistor R4 and a sixth resistor R6, one end of the fifth capacitor C5 is connected to the first power supply VDD1, and the other end thereof is grounded, one end of the sixth capacitor C6 is connected to the first power supply VDD1, and the other end thereof is grounded, one end of the third resistor R3 is connected to the sixth pin of the second chip U2, and the other end thereof is grounded, one end of the sixth resistor R6 is respectively connected to the cathode of the first diode D1 and one end of the eighth capacitor C8, and the other end thereof is respectively connected to the third pin of the second chip U2 and one end of the fourth resistor R4, one end of the ninth capacitor C9 is connected to the second power supply VDD2, and the other ends of the fourth resistor R4, the eighth capacitor C8 and the ninth capacitor C9 are respectively grounded.

7. The charging circuit according to claim 5, characterized in that: The fifth resistor R5 is a chip resistor with a model number of 0603-2.0R, the seventh capacitor C7 is a chip capacitor with a model number of 0603-3.3nF / 25V, the twentieth resistor R20 is a chip resistor with a model number of 0805-10R±5%, the fifteenth capacitor C15 is a chip capacitor with a model number of 0805-1nF(102) / 50V, the first inductor L1 is a chip inductor with a model number of SHC0603-3R3, and the third magnetic bead RL3 is a chip magnetic bead with a model number of PB2012-301 / 3A.

8. The charging circuit according to claim 1, characterized in that: The LDO step-down module includes a first chip U1, a third capacitor C3 and a fourth capacitor C4. The first pin of the first chip U1 is respectively connected to one end of the third capacitor C3 and the first power supply VDD1, the third pin is respectively connected to one end of the fourth capacitor C4 and the third power supply VDD3, and the second pin, the other end of the third capacitor C3 and the other end of the fourth capacitor C4 are respectively grounded.

9. The charging circuit according to claim 1, characterized in that: The single-chip processing module includes a third chip U3, a tenth capacitor C10, an eleventh capacitor C11, a twelfth capacitor C12, a fourteenth capacitor C14, a tenth resistor R10 and a first light-emitting diode LD1. The first pin of the third chip U3 is respectively connected to one end of the fourteenth capacitor C14 and the third power supply VDD3, the seventh pin is grounded via the tenth resistor R10 and the first light-emitting diode LD1, the ninth pin is grounded via the tenth capacitor C10, the tenth pin is grounded via the eleventh capacitor C11, the twelfth pin is grounded via the twelfth capacitor C12, the fourteenth pin and the other end of the fourteenth capacitor C14 are grounded, and the sixth pin, the ninth pin, the tenth pin, the eleventh pin and the twelfth pin are respectively connected to the charging control module.

10. The charging circuit according to claim 1, characterized in that: The charging control module includes a transistor Q1, a MOS transistor Q2, a seventh resistor R7, an eighth resistor R8, a ninth resistor R9, an eleventh resistor R11, a twelfth resistor R12, a thirteenth resistor R13, a fourteenth resistor R14, a fifteenth resistor R15, a sixteenth resistor R16, a seventeenth resistor R17, an eighteenth resistor R18, a nineteenth resistor R19, a thirteenth capacitor C13, a third diode D3 and a second plug J2. The source of the MOS transistor Q2 is respectively connected to one end of the fifteenth resistor R15, one end of the sixteenth resistor R16, one end of the nineteenth resistor R19, one end of the thirteenth capacitor C13 and the second power supply VDD2, and its gate is respectively connected to the other end of the sixteenth resistor R16 and the collector of the transistor Q1, and its drain, the other end of the nineteenth resistor R19, one end of the seventeenth resistor R17, one end of the eighteenth resistor R18, one end of the third diode D3 and the second power supply VDD2. The first pin of the plug J2 is connected, the other end of the fifteenth resistor R15, one end of the ninth resistor R9, one end of the eighth resistor R8, the other end of the seventeenth resistor R17, the other end of the eighteenth resistor R18, one end of the thirteenth resistor R13 and one end of the fourteenth resistor R14 are respectively connected to the third chip U3 of the single-chip processing module 50, the other end of the eighth resistor R8 is respectively connected to one end of the seventh resistor R7 and the base of the transistor Q1, the other end of the fourteenth resistor R14 is respectively connected to one end of the eleventh resistor R11, one end of the twelfth resistor R12 and the second pin of the second plug J2, the other end of the ninth resistor R9, the other end of the seventh resistor R7, the emitter of the transistor Q1, the other end of the thirteenth capacitor C13, the other end of the thirteenth resistor R13, the other end of the eleventh resistor R11, the other end of the twelfth resistor R12 and the other end of the third diode D3 are respectively grounded.

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