Low-noise amplifier with high-performance bypass mode
By using a T-shaped structure bypass circuit composed of multiple switch tubes in a low-noise amplifier and adding a new bypass input, the problem of poor isolation of bypass circuits in traditional designs is solved, stability and impedance matching are improved, and insertion loss is reduced.
Patent Information
- Application Number
- CN202420252742.2
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2024-01-31
- Publication Date
- 2025-03-07
- Estimated Expiration
- 2034-01-31
AI Technical Summary
Traditional low-noise amplifiers with bypass mode have poor isolation of bypass circuit switch tubes, resulting in low gain and poor stability of main paths, and poor impedance matching in bypass mode and large insertion loss.
A T-shaped structure composed of multiple switch tubes is used as a bypass circuit, replacing the traditional single switch tube bypass circuit, and a new bypass input is added to the LNA to improve impedance matching.
Achieve higher stability and isolation, improve gain and impedance matching of the main path, and reduce insertion loss in bypass mode.
Smart Images
Figure CN222582395U_ABST
Abstract
Description
Technical Field
[0001] The present disclosure relates to low noise amplifiers (LNAs) in integrated circuit design, and more particularly, to low noise amplifiers with high performance bypass modes. Background Art
[0002] In the RF receiving link, the low noise amplifier is at the forefront of the entire link, and its performance directly affects the performance of the entire receiver. Generally speaking, LNA has two working modes, high gain mode and bypass mode. In high gain mode, LNA is required to have high gain, low noise, and good impedance matching; while in bypass mode, it is required to have low insertion loss, high linearity, good impedance matching and other performance characteristics. In addition, it is also expected that the two modes will not affect each other's performance as much as possible.
[0003] Traditional low-noise amplifiers with bypass mode basically have a switch connected in parallel to the main path of the LNA for bypass mode. Such traditional design solutions have the problem of poor isolation of the switch tube in the bypass circuit, which causes low gain and poor stability when the main path is working due to poor reverse isolation, and even has the risk of oscillation. In addition, when this traditional design solution works in bypass mode, the main path is closed, but the input matching inductor is still included in the bypass. In this case, the impedance matching in the bypass mode will be very poor due to the presence of the matching inductor, which will lead to large insertion loss. Utility Model Content
[0004] The present disclosure provides a low noise amplifier (LNA), comprising: a matching circuit, which is configured outside a tube core; a low noise amplification circuit; a bypass circuit, which is connected in parallel with the low noise amplification circuit; and a control circuit, which is configured to control the LNA to switch between the low noise amplification circuit and the bypass circuit; and is characterized in that the bypass circuit includes a T-type structure composed of transistors.
[0005] In one example, the transistor includes an N-type metal oxide semiconductor (NMOS).
[0006] In one example, the T-type structure includes a fifth NMOS, a sixth NMOS, and a seventh NMOS, wherein a gate terminal of the fifth NMOS and a gate terminal of the sixth NMOS are connected to a fourth input port of the control circuit, a drain terminal of the fifth NMOS is connected to a source terminal of the sixth NMOS and a drain terminal of the seventh NMOS, a drain terminal of the sixth NMOS is connected to an output port of the LNA, and a source terminal of the seventh NMOS is connected to ground.
[0007] In one example, a source terminal of the fifth NMOS is connected to an output terminal of the matching circuit.
[0008] In one example, a source terminal of the fifth NMOS is connected to the first input port of the LNA.
[0009] In one example, a low-noise amplifier circuit includes a first NMOS, a second NMOS, a first capacitor, a second capacitor, a first inductor, a second inductor, and a resistor, wherein a first end of the second inductor is connected to a sixth input port of the low-noise amplifier circuit, a second end of the second inductor is connected to a first end of the second capacitor and a drain terminal of the second NMOS, a gate terminal of the second NMOS is connected to the second input port of the low-noise amplifier circuit, a source terminal of the second NMOS is connected to a drain terminal of the first NMOS, a gate terminal of the first NMOS is connected to a first end of the resistor and a second end of the first capacitor, a second end of the resistor is connected to a third input port of the low-noise amplifier circuit, a second end of the first capacitor is connected to a first end of the resistor and a gate terminal of the first NMOS, a source terminal of the first NMOS is connected to one end of the first inductor, and a second end of the first inductor is grounded.
[0010] In one example, the control circuit includes a third NMOS, a fourth NMOS, and an inverter, wherein a drain terminal of the third NMOS is connected to the output terminal of the matching circuit, a gate terminal of the third NMOS is connected to the input terminal of the inverter and the gate terminal of the seventh NMOS, a source terminal of the third NMOS is connected to the first end of the first capacitor, a gate terminal of the fourth NMOS is connected to the output terminal of the inverter, a source terminal of the fourth NMOS is connected to the output port of the LNA, a drain of the fourth NMOS is connected to the second end of the second capacitor, and an input terminal of the inverter is connected to the fourth input port.
[0011] In one example, the matching circuit includes a matching inductor.
[0012] In one example, the control circuit receives a control signal for the LNA to switch between the low noise amplification circuit and the bypass circuit through the fourth input port.
[0013] In one example, controlling the LNA to switch between the low noise amplification circuit and the bypass circuit includes:
[0014] When the control signal is logic low, the inverted control signal output to the gate terminal of the fourth NMOS and the gate terminal of the seventh NMOS after inversion is logic high, and the control signal input to the gate terminals of the fifth NMOS and the sixth NMOS is logic low, so that the fourth NMOS and the seventh NMOS are turned on, the fifth NMOS and the sixth NMOS are turned off, and the low-noise amplifier circuit works; when the control signal is logic high, the inverted control signal output to the gate terminal of the fourth NMOS and the gate terminal of the seventh NMOS after inversion is logic low, and the control signal input to the gate terminals of the fifth NMOS and the sixth NMOS is logic high, so that the fourth NMOS and the seventh NMOS are turned off, the fifth NMOS and the sixth NMOS are turned on, and the bypass circuit works.
[0015] In one example, the sixth input port is used to receive a power supply voltage for driving the LNA.
[0016] The present disclosure proposes an LNA design with a high-performance bypass mode, which replaces the bypass switch tube in the traditional design with a T-type structure including multiple switch tubes, thereby achieving better stability and high isolation; in addition, the improved LNA design proposed in the present disclosure can also use a newly added bypass input to achieve better impedance matching and lower insertion loss. BRIEF DESCRIPTION OF THE DRAWINGS
[0017] Figure 1 An implementation of a low noise amplifier 10 with a bypass mode is shown;
[0018] Figure 2 Shows Figure 1 The simulation results of the main path in the low noise amplifier circuit 102 of the low noise amplifier 10 are shown;
[0019] Figure 3 Shows Figure 1 The simulation results of bypass in the bypass circuit 104 of the low noise amplifier 10 are shown;
[0020] Figure 4 A low noise amplifier 40 according to an embodiment of the present disclosure is shown;
[0021] Figure 5 The embodiment according to the present disclosure is shown Figure 4 A simulation scheme of the low noise amplifier 40 shown;
[0022] Figure 6 Shows Figure 4 The simulation results of the main path in the low noise amplifier circuit 402 of the low noise amplifier 40 shown;
[0023] Figure 7 Shows Figure 4The simulation results of bypass in the bypass circuit 404 of the low noise amplifier 40 are shown. DETAILED DESCRIPTION
[0024] Hereinafter, embodiments of the present disclosure will be described in detail with reference to the accompanying drawings. It should be noted that in the accompanying drawings, identical or similar elements are represented by identical or similar reference numerals as much as possible. In addition, detailed descriptions of known functions or configurations that may make the subject matter of the present disclosure unclear will be omitted.
[0025] When describing the embodiments of the present disclosure, descriptions related to technical contents that are well known in the art and not directly related to the present disclosure will be omitted. Such omission of unnecessary descriptions is to prevent the main idea of the present disclosure from being obscured and to convey the main idea more clearly.
[0026] For the same reason, in the accompanying drawings, some elements may be enlarged, omitted or schematically shown. In addition, the size of each element does not fully reflect the actual size. In the accompanying drawings, the same or corresponding elements have the same reference numerals.
[0027] By referring to the embodiments described in detail below in conjunction with the accompanying drawings, the advantages and features of the present disclosure and the ways to achieve them will become clear. However, the present disclosure is not limited to the embodiments set forth below, but can be implemented in various different forms. The following embodiments are provided only to fully disclose the present disclosure and inform those skilled in the art of the scope of the present disclosure, and the present disclosure is limited only by the scope of the attached claims. Throughout the specification, the same or similar reference numerals represent the same or similar elements.
[0028] The following will take the LNA operating in the N77 frequency band (3.3 GHz-4.2 GHz) as an example to specifically describe the LNA design scheme and the improved LNA circuit structure described in various embodiments of the present application.
[0029] As the first-stage active module of the RF receiving chain, LNA has an important impact on the performance of the receiver system. The performance of LNA is measured by various parameters, including noise figure (NF), gain, input and output matching, linearity, reverse isolation and stability.
[0030] Noise figure is often used to measure the amount of noise inside a circuit or system, and it increases as temperature rises.
[0031] Generally, LNA is expected to have a large gain to better amplify the signal input to LNA. In actual RF systems, the previous stage of LNA can be an off-chip RF filter, whose output port is connected to the input port of LNA, and input-output impedance matching is generally required to achieve high-power transmission; if the impedance is not matched, power reflection will occur, affecting the power of the signal received by LNA, and deteriorating the performance of the previous stage RF filter, thereby deteriorating the performance of the entire system.
[0032] The actual LNA is not an ideal LNA and is not ideally linear, that is, as the input power increases, the output power may not increase linearly. The degree to which the output power increases linearly with the increase in input power is characterized by the linearity of the LNA.
[0033] Reverse isolation characterizes the reverse isolation performance between the input port and the output port of the LNA. It is numerically defined as the attenuation value of the signal from the output port to the input port, usually represented by S12 in the scattering (S) parameter. The S parameter is a network parameter based on the relationship between the incident wave and the reflected wave. For a two-port network, it includes the input return loss coefficient S11, the output return loss coefficient S22, the reverse isolation coefficient S12, and the forward isolation coefficient S21.
[0034] Stability is generally reflected by the stability coefficient (Kf). When the stability coefficient Kf>1, the low noise amplifier is considered to be stable.
[0035] In the design of LNA, it is expected that LNA has low noise, sufficient gain, can suppress the noise of subsequent circuits, and has good linearity and reverse isolation. However, the design of LNA is not just the optimization of a certain indicator, but a compromise among multiple indicators, including gain, noise figure, input and output impedance matching, linearity, power consumption and reverse isolation.
[0036] Figure 1 FIG. 1 shows an implementation of a low noise amplifier 10 with a bypass mode. Figure 1 As shown in FIG. 1 , as shown by the dotted line, the LNA 10 includes a matching inductor L1 101, a low noise amplifier circuit (main circuit) 102, a control circuit 103 and a bypass circuit 104. One end of the matching inductor L1 101 is the first input port rfin of the LNA 10. In addition, Figure 1 The matching inductor L1 101 shown in FIG. 1 can be replaced by a more complex matching circuit 101. Figure 1 As shown, the matching inductor L1101 is located outside the DIE, while the remainder of the LNA 10 is located inside the DIE. Figure 1The switch tubes M1, M2, M3, M4 and M5 are shown by taking N-type metal oxide semiconductor (NMOS) as an example, but the present application is not limited thereto, and any other suitable switch tubes or transistors are also applicable to various embodiments of the present disclosure.
[0037] like Figure 1 As shown, the low noise amplifier circuit 102 adopts a cascode structure, which is a circuit composed of a mirror current tube and an amplifier tube to improve linearity, and specifically includes switch tubes M1 and M2, capacitors C1 and C2, inductors L2 and L3, and resistor R1. One end of L3 is connected to the power supply voltage VDD (which is input from the sixth input port of LNA 10), and the other end thereof is connected to one end of C2 and the drain terminal of M2. The other end of C2 is connected to the drain terminal of M4 in the control circuit 103. The gate terminal of M2 is connected to the second input port, through which the voltage vb2 for turning on or off M2 is received. The source terminal of M2 is connected to the drain terminal of M1. The gate terminal of M1 is connected to one end of R1, and the other end of R1 is connected to the third input port providing the voltage vb1. One end of C1 is connected to the source terminal of M3 in the control circuit 103, and the other end thereof is connected to one end of R1 and the gate terminal of M1. The source terminal of M1 is connected to one end of the inductor L2, and the other end of L2 is grounded GND. The low noise amplifier circuit 102 composed of M1, M2, C1, C2, L2, L3 and R1 provides the main path in the LNA. Figure 1 The low-noise amplifier circuit 102 is illustrated by taking a cascode structure as an example, but the present application is not limited thereto, and any other suitable low-noise amplifier circuit structure is also applicable to various embodiments of the present disclosure.
[0038] like Figure 1 As shown, the control circuit 103 includes switch tubes M3 and M4 and an inverter INV. The drain terminal of M3 is connected to the source terminal of M5 in the bypass circuit 104 and the other end of the matching inductor L1 101, the source terminal of M3 is connected to one end of C1 in the low noise amplifier circuit 102, and the gate terminal of M3 is connected to the output terminal of INV and the gate terminal of M4. The input terminal of INV is connected to the fourth input port receiving the control signal en_BY for the control circuit 103 and the bypass circuit 104 and the gate terminal of the switch tube M5 in the bypass circuit 104. The drain terminal of M4 is connected to the other end of the capacitor C2 in the low noise amplifier circuit 102, and the source terminal of M4 is connected to the output port rfout of LNA10 and the drain terminal of M5 in the bypass circuit 104.
[0039] like Figure 1As shown, the bypass circuit 104 includes a switch tube M5. As described above with reference to the low noise amplifier circuit 102 and the control circuit 103, the gate terminal of M5 is connected to the fourth input port and the input terminal of INV in the control circuit 103, the source terminal of M5 is connected to the drain terminal of M3 in the control circuit and the other end of the matching inductor L1 101, and the drain terminal of M5 is connected to the source terminal of M4 and the output port rfout of the LNA 10. The bypass circuit 104 composed of M5 provides bypass in the LNA.
[0040] The control circuit 104 controls the LNA 10 to switch between the low noise amplifier circuit 102 and the bypass circuit 104 based on the control signal en_BY received from the fourth input port, that is, controls the LNA 10 to switch between the high gain mode provided by the low noise amplifier circuit 102 and the bypass mode provided by the bypass circuit 104 . Specifically, when the control signal en_BY received from the fourth input port is logic low, the control signal inverted and output to the gate terminal of M4 through INV is logic high, so that M4 is turned on, and the control signal en_BY directly input to the gate terminal of M5 is logic low, so that M5 is turned off, so the low noise amplifier circuit 102 of the LNA 10 works, and the bypass circuit 104 does not work; on the contrary, when the control signal en_BY received from the fourth input port is logic high, the control signal inverted and output to the gate terminal of M4 through INV is logic low, so that M4 is turned off, and the control signal en_BY directly input to the gate terminal of M5 is logic high, so that M5 is turned on, so the low noise amplifier circuit 102 of the LNA 10 does not work, but the bypass circuit 104 works. In this way, the control circuit 104 controls the LNA 10 to switch between the low noise amplifier circuit 102 (main path) and the bypass circuit 104 (bypass) based on the control signal en_BY received from the fourth input port.
[0041] However, Figure 1 The LNA design shown has the problem of poor isolation of the switch tube M5 in the bypass circuit 104, which causes the main path of the low-noise amplifier circuit 102 of the LNA 10 to have low gain and poor stability due to poor reverse isolation, and even a risk of oscillation when working. Figure 2 Shows Figure 1 The simulation results of the main path in the low noise amplifier circuit 102 of the LNA 10 are shown, wherein the horizontal axis represents the frequency, the vertical axis represents the value of the S parameter (S11, S22, S21 and S12), and V1-V2 represents the N77 frequency band. Figure 2 As shown, Figure 1The main path of the LNA 10 shown has a reverse isolation coefficient S12 of only about 25 dB at worst in the N77 band due to the low isolation of M5 in the bypass, resulting in a gain (S21) of only about 17 dB, poor impedance matching (S11 and S22), and a stability coefficient Kf of less than 1 at V2 (4.2 GHz), which cannot achieve absolute stability and has an oscillation risk.
[0042] In addition, when Figure 1 When the LNA 10 shown works in the bypass mode, although the main path is closed, the matching inductor L1 is still included in the bypass. In this case, the impedance matching of the LNA 10 in the bypass mode is very poor due to the presence of the matching inductor L1, which leads to a large insertion loss. Figure 3 Shows Figure 1 The simulation results of bypass in the bypass circuit 103 of the LNA 10 are shown, wherein the horizontal axis represents the frequency, the vertical axis represents the value of the S parameter (S11, S22 and S21), and V1-V2 represents the N77 frequency band. Figure 3 As shown, due to Figure 1 The LNA 10 shown in the bypass mode passes through the matching inductor L1, that is, Figure 1 The bypass of the LNA 10 shown includes a matching inductor L1, so the inductor L1 pulls the impedance to the inductive region of the upper half plane of the Smith chart, resulting in S11 and S22 being very poor in the N77 band, above -10 dB, and the insertion loss (forward isolation coefficient) S21 being greater than 1.5 dB, which is also very poor.
[0043] The following will refer to Figure 4 and Figure 5 An LNA structure according to an embodiment of the present disclosure that can solve the above-mentioned problems is described.
[0044] Figure 4 FIG. 4 shows a circuit 40 including a low noise amplifier 40 according to an embodiment of the present disclosure. As shown by the dashed line, similar to Figure 1 The LNA 10 shown, Figure 4 The circuit 40 shown includes an LNA 40 including a matching inductor L1 401, a low noise amplifier circuit 402, a control circuit 403 and a bypass circuit 404. One end of the matching inductor L1 401 is a first input port rfin of the LNA 40. Figure 1 Similarly as shown, the matching inductor L1 401 is located off-die, while the remainder of the LNA 40 is located on-die. Figure 4 Detailed description is given in the figure using NMOS as an example to illustrate the switch tubes M1, M2, M3, M4, M5, M6 and M7, but the present application is not limited thereto, and any other suitable switch tubes are also applicable to the various embodiments of the present disclosure.
[0045] like Figure 4 As shown, similar to Figure 1 The low noise amplifier circuit 402 uses a cascode structure, which is a circuit for improving linearity composed of a mirror current tube and an amplifier tube, specifically including switch tubes M1 and M2, capacitors C1 and C2, inductors L2 and L3, and resistor R1. One end of L3 is connected to the power supply voltage VDD (which is input from the sixth input port of LNA 40), and the other end is connected to one end of C2 and the drain terminal of M2. The other end of C2 is connected to the drain terminal of M4 in the control circuit 403. The gate terminal of M2 is connected to the second input port, through which the voltage vb2 for turning on or off M2 is received. The source terminal of M2 is connected to the drain terminal of M1. The gate terminal of M1 is connected to one end of R1, and the other end of R1 is connected to the third input port providing the voltage vb1. One end of C1 is connected to the source terminal of M3 in the control circuit 403 and the other end is connected to one end of R1 and the gate terminal of M1. The source terminal of M1 is connected to one end of inductor L2, and the other end of L2 is grounded GND. The low noise amplifier circuit 402 composed of M1, M2, C1, C2, L2, L3 and R1 provides the main path in LNA 40. Figure 4 The low-noise amplifier circuit 402 is illustrated by taking a cascode structure as an example, but the present application is not limited thereto, and any other suitable low-noise amplifier circuit structure is also applicable to various embodiments of the present disclosure.
[0046] like Figure 4 As shown, similar to Figure 1 , the control circuit 403 includes switch tubes M3 and M4 and an inverter INV. The drain terminal of M3 is connected to the other end of the matching inductor L1 401, the source terminal of M3 is connected to one end of C1 in the low noise amplifier circuit 102, and the gate terminal of M3 is connected to the output terminal of INV and the gate terminal of M4. The input terminal of INV is connected to the fourth input port receiving the control signal en_BY for the control circuit 403 and the bypass circuit 404 and the gate terminals of the switch tubes M5 and M6 in the bypass circuit 404. The drain terminal of M4 is connected to the other end of the capacitor C2 in the low noise amplifier circuit 402, and the source terminal of M4 is connected to the output port rfout of LNA 40 and the drain terminal of M6 in the bypass circuit 404.
[0047] like Figure 4 As shown, Figure 1Unlike the bypass circuit 104 in the LNA 40, the bypass circuit 404 includes switch tubes M5, M6 and M7. The source terminal of M5 is connected to the fifth input port rfin_BY of the LNA 40, and the fifth input port rfin_BY is connected to one end of the matching inductor L1. The drain terminal of M7 is connected to the drain terminal of M5 and the source terminal of M7, the source terminal of M7 is grounded GND, and the gate terminal of M7 is connected to the output terminal of INV in the control circuit 403 and the gate terminal of M4. Through such a connection method, the bypass circuit 404 in the LNA 40 is formed into a T-type structure. The bypass circuit 404 composed of M5-M7 provides a bypass in the LNA 40.
[0048] The control circuit 404 controls the LNA 40 to switch between the low noise amplifier circuit 402 and the bypass circuit 404 based on the control signal en_BY received from the fourth input port, that is, controls the LNA 40 to switch between the high gain mode provided by the low noise amplifier circuit 402 and the bypass mode provided by the bypass circuit 404. Specifically, when the control signal en_BY received from the fourth input port is logic low, the control signal inverted and output to the gate terminal of M4 and the gate terminal of M7 through INV is logic high, so that M4 and M7 are turned on, and the control signal en_BY directly input to the gate terminals of M5 and M6 is logic low, so that M5 and M6 are turned off, so the low noise amplifier circuit 402 of LNA 40 works, and the bypass circuit 404 does not work; conversely, when the control signal en_BY received from the fourth input port is logic high, the control signal inverted and output to the gate terminal of M4 and the gate terminal of M7 through INV is logic low, so that M4 and M7 are turned off, and the control signal en_BY directly input to the gate terminals of M5 and M6 is logic high, so that M5 and M6 are turned on, so the low noise amplifier circuit 402 of LNA 40 does not work, and the bypass circuit 404 works. In this way, the control circuit 404 controls the LNA 40 to switch between the low noise amplifier circuit 402 (main path) and the bypass circuit 404 (bypass) based on the control signal en_BY received from the fourth input port.
[0049] Figure 4 The LNA 40 shown is replaced by a bypass circuit 404 of a T-type structure. Figure 1 The single switch bypass circuit 104 in the LNA 10 shown in the figure can solve the problems existing in the above LNA 10. Specifically, the bypass circuit 404 with a T-shaped structure can bring better isolation (high isolation). Figure 4As shown, by using the bypass circuit 404 of the T-type structure, when the control signal en_BY received from the fourth input port is logic low, the main path of the LNA 40 works, M4 and M7 are turned on, and M5 and M6 are turned off, so that M7 guides the RF signal leaked through the parasitic capacitors of M5 and M6 to the ground GND, so that the main path can maintain a very high reverse isolation, thereby improving the stability and gain of the main path.
[0050] In addition, in order to further improve the performance of LNA 40 in bypass mode, a bypass fifth input port rfin_BY is added on the basis of only one input port (rfin_DIE) in the tube core (DIE) of LNA 10, and the newly added fifth input port rfin_BY is directly connected to the first input port rfin, so that when LNA 40 works in bypass mode, the RF signal does not pass through the matching inductor L1401, thereby achieving better overall input-output impedance matching and lower insertion loss. However, the present application is not limited to this, similar to Figure 1 The case where the drain terminal of M3 is directly connected to the source terminal of M5 in the bypass circuit 403, that is, the case where the new fifth input port rfin_BY is not added, is also applicable. Figure 4 In addition, as shown in the LNA40 Figure 1 As mentioned above, the matching inductor L1 shown in the drawings can be replaced by a more complex matching circuit.
[0051] Figure 5 The embodiment according to the present disclosure is shown Figure 4 The simulation scheme of the low noise amplifier 40 shown in FIG. Figure 5 As shown, add 50 ohm port0 to the input port rfin of LNA40, and add 50 ohm port1 to the output port rfout. Apply 1.2V DC power supply VDD, ground the GND port, set the control signal en_BY to logic low when the main path is working, and set the control signal en_BY to logic high when the bypass is working. Figure 2 and Figure 3 and Figure 6 and Figure 7 It can be seen from the comparison of the simulation results that, regardless of whether it is working in the main path or the bypass path, the various performances of the LNA 40 according to the embodiment of the present disclosure are greatly improved. Figure 6 and Figure 7 The performance improvement of the LNA 40 when operating in the main path and the bypass path according to the embodiments of the present disclosure is described in detail.
[0052] Figure 6 Shows Figure 4The simulation results of the main path in the low noise amplifier circuit 402 of the low noise amplifier 40 shown in the figure, wherein the horizontal axis represents the frequency, the vertical axis represents the value of the S parameter (S11, S22, S21 and S12), and V1-V2 represents the N77 frequency band; Figure 7 Shows Figure 4 The simulation results of bypass in the bypass circuit 404 of the low noise amplifier 40 are shown, wherein the horizontal axis represents the frequency, the vertical axis represents the value of the S parameter (S11, S22 and S21), and V1-V2 represents the N77 frequency band. Figure 6 As shown, the reverse isolation coefficient S12 of LNA40 according to the embodiment of the present disclosure when working in the main path is greater than 30dB. The stability coefficient Kf is above 1.3 and greater than 1 in the entire N77 band, so it has absolute stability. The impedance matching (S11 and S22) is lower than -13dB in the entire N77 band, and the gain (S21) is as high as 23dB, and its performance is better than LNA 10 in all aspects. Figure 7 As shown, the impedance matching (S11 and S22) of the LNA40 in the bypass mode according to the embodiment of the present disclosure is both below -18 dB, the insertion loss (S21) is less than 1 dB, and the bandwidth is also very wide, and its performance is better than that of the LNA10 in all aspects.
[0053] Various embodiments described in the present disclosure and various examples in the embodiments may be changed and combined in any appropriate forms.
[0054] The description set forth herein, in conjunction with the accompanying drawings, describes example configurations, methods, and apparatuses and does not represent all examples that may be implemented or within the scope of the claims. The detailed description includes specific details for the purpose of providing an understanding of the described techniques. However, these techniques may be practiced without these specific details. In some cases, well-known structures and devices are shown in block diagram form to avoid obscuring the concepts of the described examples.
[0055] Although this specification contains a plurality of specific implementation details, these should not be interpreted as limitations on any utility model or the scope of the claimed protection, but rather as descriptions of the specific features of the specific embodiments of the specific utility model. Certain features described in the context of a separate embodiment in this specification may also be implemented in combination in a single embodiment. On the contrary, the various features described in the context of a single embodiment may also be implemented separately in multiple embodiments or in any suitable sub-combination. In addition, although features may be described above as working in certain combinations, and even initially claimed as such, in some cases, one or more features from the claimed combination may be deleted from the combination, and the claimed combination may be directed to a sub-combination or a variation of the sub-combination.
[0056] It should be understood that the specific order or hierarchy of steps in the method of the present disclosure is an illustration of an exemplary process. Based on design preferences, it is understood that the specific order or hierarchy of steps in the method can be rearranged to achieve the functions and effects disclosed in the present disclosure. The attached method claims present the elements of various steps in an example order, and are not meant to be limited to the specific order or hierarchy presented, unless otherwise specifically stated. In addition, although elements can be described or claimed in singular form, the plural number is also contemplated unless a limitation to the singular is explicitly stated. Therefore, the present disclosure is not limited to the examples shown, and any device for performing the functions described herein is included in the various aspects of the present disclosure.
[0057] The text and drawings are provided as examples only to help readers understand the present disclosure. They are not intended and should not be interpreted as limiting the scope of the present disclosure in any way. Although certain embodiments and examples have been provided, it is obvious to those skilled in the art based on what is disclosed herein that the embodiments and examples shown may be changed without departing from the scope of the present disclosure.
Claims
1. A low noise amplifier with a high performance bypass mode, comprising: A matching circuit, wherein the matching circuit is configured outside the die; Low noise amplifier circuit; A bypass circuit connected in parallel with the low-noise amplifier circuit; as well as a control circuit configured to control the low noise amplifier to switch between the low noise amplifier circuit and the bypass circuit; and It is characterized in that the bypass circuit includes a T-type structure composed of transistors.
2. A low noise amplifier with a high performance bypass mode according to claim 1, characterized in that: The transistor includes an N-type metal oxide semiconductor (NMOS).
3. A low noise amplifier with a high performance bypass mode according to claim 2, characterized in that: The T-type structure includes a fifth NMOS, a sixth NMOS and a seventh NMOS, wherein the gate terminal of the fifth NMOS and the gate terminal of the sixth NMOS are connected to the fourth input port of the control circuit, the drain terminal of the fifth NMOS is connected to the source terminal of the sixth NMOS and the drain terminal of the seventh NMOS, the drain terminal of the sixth NMOS is connected to the output port of the low noise amplifier, and the source terminal of the seventh NMOS is connected to the ground.
4. A low noise amplifier with a high performance bypass mode according to claim 3, characterized in that: A source terminal of the fifth NMOS is connected to the output terminal of the matching circuit.
5. A low noise amplifier with a high performance bypass mode according to claim 3, characterized in that: A source terminal of the fifth NMOS is connected to the first input port of the low noise amplifier.
6. A low noise amplifier with a high performance bypass mode according to claim 4 or 5, characterized in that: The low-noise amplifier circuit includes a first NMOS, a second NMOS, a first capacitor, a second capacitor, a first inductor, a second inductor and a resistor, wherein a first end of the second inductor is connected to a sixth input port of the low-noise amplifier circuit, a second end of the second inductor is connected to a first end of the second capacitor and a drain terminal of the second NMOS, a gate terminal of the second NMOS is connected to the second input port of the low-noise amplifier circuit, a source terminal of the second NMOS is connected to a drain terminal of the first NMOS, a gate terminal of the first NMOS is connected to a first end of the resistor and a second end of the first capacitor, a second end of the resistor is connected to a third input port of the low-noise amplifier circuit, a second end of the first capacitor is connected to a first end of the resistor and a gate terminal of the first NMOS, a source terminal of the first NMOS is connected to one end of the first inductor, and a second end of the first inductor is grounded.
7. A low noise amplifier with a high performance bypass mode according to claim 6, characterized in that: The control circuit includes a third NMOS, a fourth NMOS and an inverter, wherein a drain terminal of the third NMOS is connected to the output terminal of the matching circuit, a gate terminal of the third NMOS is connected to the input terminal of the inverter and the gate terminal of the seventh NMOS, a source terminal of the third NMOS is connected to the first end of the first capacitor, a gate terminal of the fourth NMOS is connected to the output terminal of the inverter, a source terminal of the fourth NMOS is connected to the output port of the low noise amplifier, a drain of the fourth NMOS is connected to the second end of the second capacitor, and the input terminal of the inverter is connected to the fourth input port.
8. A low noise amplifier with a high performance bypass mode according to claim 1, characterized in that: The matching circuit includes a matching inductor.
9. A low noise amplifier with a high performance bypass mode according to claim 7, characterized in that: The control circuit receives a control signal for switching the low noise amplifier between the low noise amplifier circuit and the bypass circuit through a fourth input port.
10. A low noise amplifier with a high performance bypass mode according to claim 9, characterized in that: Controlling the low noise amplifier to switch between the low noise amplifier circuit and the bypass circuit includes: When the control signal is logic low, the inverted control signal output to the gate terminal of the fourth NMOS and the gate terminal of the seventh NMOS through the inversion is logic high, and the control signal input to the gate terminal of the fifth NMOS and the sixth NMOS is logic low, so that the fourth NMOS and the seventh NMOS are turned on, the fifth NMOS and the sixth NMOS are turned off, and the low noise amplifier circuit works; When the control signal is logic high, the inverted control signal output to the gate terminal of the fourth NMOS and the gate terminal of the seventh NMOS through the inversion is logic low, and the control signal input to the gate terminals of the fifth NMOS and the sixth NMOS is logic this, so that the fourth NMOS and the seventh NMOS are turned off, the fifth NMOS and the sixth NMOS are turned on, and the bypass circuit works.
11. A low noise amplifier with a high performance bypass mode according to claim 6, characterized in that: The sixth input port is used to receive a power supply voltage for driving the low noise amplifier.